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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f0xx_ll_i2c.h
  4.   * @author  MCD Application Team
  5.   * @brief   Header file of I2C LL module.
  6.   ******************************************************************************
  7.   * @attention
  8.   *
  9.   * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
  10.   * All rights reserved.</center></h2>
  11.   *
  12.   * This software component is licensed by ST under BSD 3-Clause license,
  13.   * the "License"; You may not use this file except in compliance with the
  14.   * License. You may obtain a copy of the License at:
  15.   *                        opensource.org/licenses/BSD-3-Clause
  16.   *
  17.   ******************************************************************************
  18.   */
  19.  
  20. /* Define to prevent recursive inclusion -------------------------------------*/
  21. #ifndef STM32F0xx_LL_I2C_H
  22. #define STM32F0xx_LL_I2C_H
  23.  
  24. #ifdef __cplusplus
  25. extern "C" {
  26. #endif
  27.  
  28. /* Includes ------------------------------------------------------------------*/
  29. #include "stm32f0xx.h"
  30.  
  31. /** @addtogroup STM32F0xx_LL_Driver
  32.   * @{
  33.   */
  34.  
  35. #if defined (I2C1) || defined (I2C2)
  36.  
  37. /** @defgroup I2C_LL I2C
  38.   * @{
  39.   */
  40.  
  41. /* Private types -------------------------------------------------------------*/
  42. /* Private variables ---------------------------------------------------------*/
  43.  
  44. /* Private constants ---------------------------------------------------------*/
  45. /** @defgroup I2C_LL_Private_Constants I2C Private Constants
  46.   * @{
  47.   */
  48. /**
  49.   * @}
  50.   */
  51.  
  52. /* Private macros ------------------------------------------------------------*/
  53. #if defined(USE_FULL_LL_DRIVER)
  54. /** @defgroup I2C_LL_Private_Macros I2C Private Macros
  55.   * @{
  56.   */
  57. /**
  58.   * @}
  59.   */
  60. #endif /*USE_FULL_LL_DRIVER*/
  61.  
  62. /* Exported types ------------------------------------------------------------*/
  63. #if defined(USE_FULL_LL_DRIVER)
  64. /** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
  65.   * @{
  66.   */
  67. typedef struct
  68. {
  69.   uint32_t PeripheralMode;      /*!< Specifies the peripheral mode.
  70.                                      This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE.
  71.  
  72.                                      This feature can be modified afterwards using unitary function
  73.                                      @ref LL_I2C_SetMode(). */
  74.  
  75.   uint32_t Timing;              /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
  76.                                      This parameter must be set by referring to the STM32CubeMX Tool and
  77.                                      the helper macro @ref __LL_I2C_CONVERT_TIMINGS().
  78.  
  79.                                      This feature can be modified afterwards using unitary function
  80.                                      @ref LL_I2C_SetTiming(). */
  81.  
  82.   uint32_t AnalogFilter;        /*!< Enables or disables analog noise filter.
  83.                                      This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION.
  84.  
  85.                                      This feature can be modified afterwards using unitary functions
  86.                                      @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
  87.  
  88.   uint32_t DigitalFilter;       /*!< Configures the digital noise filter.
  89.                                      This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F.
  90.  
  91.                                      This feature can be modified afterwards using unitary function
  92.                                      @ref LL_I2C_SetDigitalFilter(). */
  93.  
  94.   uint32_t OwnAddress1;         /*!< Specifies the device own address 1.
  95.                                      This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF.
  96.  
  97.                                      This feature can be modified afterwards using unitary function
  98.                                      @ref LL_I2C_SetOwnAddress1(). */
  99.  
  100.   uint32_t TypeAcknowledge;     /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive
  101.                                      match code or next received byte.
  102.                                      This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE.
  103.  
  104.                                      This feature can be modified afterwards using unitary function
  105.                                      @ref LL_I2C_AcknowledgeNextData(). */
  106.  
  107.   uint32_t OwnAddrSize;         /*!< Specifies the device own address 1 size (7-bit or 10-bit).
  108.                                      This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1.
  109.  
  110.                                      This feature can be modified afterwards using unitary function
  111.                                      @ref LL_I2C_SetOwnAddress1(). */
  112. } LL_I2C_InitTypeDef;
  113. /**
  114.   * @}
  115.   */
  116. #endif /*USE_FULL_LL_DRIVER*/
  117.  
  118. /* Exported constants --------------------------------------------------------*/
  119. /** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
  120.   * @{
  121.   */
  122.  
  123. /** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
  124.   * @brief    Flags defines which can be used with LL_I2C_WriteReg function
  125.   * @{
  126.   */
  127. #define LL_I2C_ICR_ADDRCF                   I2C_ICR_ADDRCF          /*!< Address Matched flag   */
  128. #define LL_I2C_ICR_NACKCF                   I2C_ICR_NACKCF          /*!< Not Acknowledge flag   */
  129. #define LL_I2C_ICR_STOPCF                   I2C_ICR_STOPCF          /*!< Stop detection flag    */
  130. #define LL_I2C_ICR_BERRCF                   I2C_ICR_BERRCF          /*!< Bus error flag         */
  131. #define LL_I2C_ICR_ARLOCF                   I2C_ICR_ARLOCF          /*!< Arbitration Lost flag  */
  132. #define LL_I2C_ICR_OVRCF                    I2C_ICR_OVRCF           /*!< Overrun/Underrun flag  */
  133. #define LL_I2C_ICR_PECCF                    I2C_ICR_PECCF           /*!< PEC error flag         */
  134. #define LL_I2C_ICR_TIMOUTCF                 I2C_ICR_TIMOUTCF        /*!< Timeout detection flag */
  135. #define LL_I2C_ICR_ALERTCF                  I2C_ICR_ALERTCF         /*!< Alert flag             */
  136. /**
  137.   * @}
  138.   */
  139.  
  140. /** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
  141.   * @brief    Flags defines which can be used with LL_I2C_ReadReg function
  142.   * @{
  143.   */
  144. #define LL_I2C_ISR_TXE                      I2C_ISR_TXE             /*!< Transmit data register empty        */
  145. #define LL_I2C_ISR_TXIS                     I2C_ISR_TXIS            /*!< Transmit interrupt status           */
  146. #define LL_I2C_ISR_RXNE                     I2C_ISR_RXNE            /*!< Receive data register not empty     */
  147. #define LL_I2C_ISR_ADDR                     I2C_ISR_ADDR            /*!< Address matched (slave mode)        */
  148. #define LL_I2C_ISR_NACKF                    I2C_ISR_NACKF           /*!< Not Acknowledge received flag       */
  149. #define LL_I2C_ISR_STOPF                    I2C_ISR_STOPF           /*!< Stop detection flag                 */
  150. #define LL_I2C_ISR_TC                       I2C_ISR_TC              /*!< Transfer Complete (master mode)     */
  151. #define LL_I2C_ISR_TCR                      I2C_ISR_TCR             /*!< Transfer Complete Reload            */
  152. #define LL_I2C_ISR_BERR                     I2C_ISR_BERR            /*!< Bus error                           */
  153. #define LL_I2C_ISR_ARLO                     I2C_ISR_ARLO            /*!< Arbitration lost                    */
  154. #define LL_I2C_ISR_OVR                      I2C_ISR_OVR             /*!< Overrun/Underrun (slave mode)       */
  155. #define LL_I2C_ISR_PECERR                   I2C_ISR_PECERR          /*!< PEC Error in reception (SMBus mode) */
  156. #define LL_I2C_ISR_TIMEOUT                  I2C_ISR_TIMEOUT         /*!< Timeout detection flag (SMBus mode) */
  157. #define LL_I2C_ISR_ALERT                    I2C_ISR_ALERT           /*!< SMBus alert (SMBus mode)            */
  158. #define LL_I2C_ISR_BUSY                     I2C_ISR_BUSY            /*!< Bus busy                            */
  159. /**
  160.   * @}
  161.   */
  162.  
  163. /** @defgroup I2C_LL_EC_IT IT Defines
  164.   * @brief    IT defines which can be used with LL_I2C_ReadReg and  LL_I2C_WriteReg functions
  165.   * @{
  166.   */
  167. #define LL_I2C_CR1_TXIE                     I2C_CR1_TXIE            /*!< TX Interrupt enable                         */
  168. #define LL_I2C_CR1_RXIE                     I2C_CR1_RXIE            /*!< RX Interrupt enable                         */
  169. #define LL_I2C_CR1_ADDRIE                   I2C_CR1_ADDRIE          /*!< Address match Interrupt enable (slave only) */
  170. #define LL_I2C_CR1_NACKIE                   I2C_CR1_NACKIE          /*!< Not acknowledge received Interrupt enable   */
  171. #define LL_I2C_CR1_STOPIE                   I2C_CR1_STOPIE          /*!< STOP detection Interrupt enable             */
  172. #define LL_I2C_CR1_TCIE                     I2C_CR1_TCIE            /*!< Transfer Complete interrupt enable          */
  173. #define LL_I2C_CR1_ERRIE                    I2C_CR1_ERRIE           /*!< Error interrupts enable                     */
  174. /**
  175.   * @}
  176.   */
  177.  
  178. /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
  179.   * @{
  180.   */
  181. #define LL_I2C_MODE_I2C                    0x00000000U              /*!< I2C Master or Slave mode                 */
  182. #define LL_I2C_MODE_SMBUS_HOST             I2C_CR1_SMBHEN           /*!< SMBus Host address acknowledge           */
  183. #define LL_I2C_MODE_SMBUS_DEVICE           0x00000000U              /*!< SMBus Device default mode
  184.                                                                          (Default address not acknowledge)        */
  185. #define LL_I2C_MODE_SMBUS_DEVICE_ARP       I2C_CR1_SMBDEN           /*!< SMBus Device Default address acknowledge */
  186. /**
  187.   * @}
  188.   */
  189.  
  190. /** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
  191.   * @{
  192.   */
  193. #define LL_I2C_ANALOGFILTER_ENABLE          0x00000000U             /*!< Analog filter is enabled.  */
  194. #define LL_I2C_ANALOGFILTER_DISABLE         I2C_CR1_ANFOFF          /*!< Analog filter is disabled. */
  195. /**
  196.   * @}
  197.   */
  198.  
  199. /** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
  200.   * @{
  201.   */
  202. #define LL_I2C_ADDRESSING_MODE_7BIT         0x00000000U              /*!< Master operates in 7-bit addressing mode. */
  203. #define LL_I2C_ADDRESSING_MODE_10BIT        I2C_CR2_ADD10            /*!< Master operates in 10-bit addressing mode.*/
  204. /**
  205.   * @}
  206.   */
  207.  
  208. /** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
  209.   * @{
  210.   */
  211. #define LL_I2C_OWNADDRESS1_7BIT             0x00000000U             /*!< Own address 1 is a 7-bit address. */
  212. #define LL_I2C_OWNADDRESS1_10BIT            I2C_OAR1_OA1MODE        /*!< Own address 1 is a 10-bit address.*/
  213. /**
  214.   * @}
  215.   */
  216.  
  217. /** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
  218.   * @{
  219.   */
  220. #define LL_I2C_OWNADDRESS2_NOMASK           I2C_OAR2_OA2NOMASK      /*!< Own Address2 No mask.                 */
  221. #define LL_I2C_OWNADDRESS2_MASK01           I2C_OAR2_OA2MASK01      /*!< Only Address2 bits[7:2] are compared. */
  222. #define LL_I2C_OWNADDRESS2_MASK02           I2C_OAR2_OA2MASK02      /*!< Only Address2 bits[7:3] are compared. */
  223. #define LL_I2C_OWNADDRESS2_MASK03           I2C_OAR2_OA2MASK03      /*!< Only Address2 bits[7:4] are compared. */
  224. #define LL_I2C_OWNADDRESS2_MASK04           I2C_OAR2_OA2MASK04      /*!< Only Address2 bits[7:5] are compared. */
  225. #define LL_I2C_OWNADDRESS2_MASK05           I2C_OAR2_OA2MASK05      /*!< Only Address2 bits[7:6] are compared. */
  226. #define LL_I2C_OWNADDRESS2_MASK06           I2C_OAR2_OA2MASK06      /*!< Only Address2 bits[7] are compared.   */
  227. #define LL_I2C_OWNADDRESS2_MASK07           I2C_OAR2_OA2MASK07      /*!< No comparison is done.
  228.                                                                          All Address2 are acknowledged.        */
  229. /**
  230.   * @}
  231.   */
  232.  
  233. /** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
  234.   * @{
  235.   */
  236. #define LL_I2C_ACK                          0x00000000U              /*!< ACK is sent after current received byte. */
  237. #define LL_I2C_NACK                         I2C_CR2_NACK             /*!< NACK is sent after current received byte.*/
  238. /**
  239.   * @}
  240.   */
  241.  
  242. /** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
  243.   * @{
  244.   */
  245. #define LL_I2C_ADDRSLAVE_7BIT               0x00000000U              /*!< Slave Address in 7-bit. */
  246. #define LL_I2C_ADDRSLAVE_10BIT              I2C_CR2_ADD10            /*!< Slave Address in 10-bit.*/
  247. /**
  248.   * @}
  249.   */
  250.  
  251. /** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
  252.   * @{
  253.   */
  254. #define LL_I2C_REQUEST_WRITE                0x00000000U              /*!< Master request a write transfer. */
  255. #define LL_I2C_REQUEST_READ                 I2C_CR2_RD_WRN           /*!< Master request a read transfer.  */
  256. /**
  257.   * @}
  258.   */
  259.  
  260. /** @defgroup I2C_LL_EC_MODE Transfer End Mode
  261.   * @{
  262.   */
  263. #define LL_I2C_MODE_RELOAD                  I2C_CR2_RELOAD           /*!< Enable I2C Reload mode.     */
  264. #define LL_I2C_MODE_AUTOEND                 I2C_CR2_AUTOEND          /*!< Enable I2C Automatic end mode
  265.                                                                           with no HW PEC comparison.  */
  266. #define LL_I2C_MODE_SOFTEND                 0x00000000U              /*!< Enable I2C Software end mode
  267.                                                                           with no HW PEC comparison.  */
  268. #define LL_I2C_MODE_SMBUS_RELOAD            LL_I2C_MODE_RELOAD       /*!< Enable SMBUS Automatic end mode
  269.                                                                           with HW PEC comparison.     */
  270. #define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC    LL_I2C_MODE_AUTOEND      /*!< Enable SMBUS Automatic end mode
  271.                                                                           with HW PEC comparison.     */
  272. #define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC    LL_I2C_MODE_SOFTEND      /*!< Enable SMBUS Software end mode
  273.                                                                           with HW PEC comparison.     */
  274. #define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)
  275. /*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */
  276. #define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)
  277. /*!< Enable SMBUS Software end mode with HW PEC comparison.    */
  278. /**
  279.   * @}
  280.   */
  281.  
  282. /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
  283.   * @{
  284.   */
  285. #define LL_I2C_GENERATE_NOSTARTSTOP         0x00000000U
  286. /*!< Don't Generate Stop and Start condition. */
  287. #define LL_I2C_GENERATE_STOP                (uint32_t)(0x80000000U | I2C_CR2_STOP)
  288. /*!< Generate Stop condition (Size should be set to 0).      */
  289. #define LL_I2C_GENERATE_START_READ          (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
  290. /*!< Generate Start for read request. */
  291. #define LL_I2C_GENERATE_START_WRITE         (uint32_t)(0x80000000U | I2C_CR2_START)
  292. /*!< Generate Start for write request. */
  293. #define LL_I2C_GENERATE_RESTART_7BIT_READ   (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
  294. /*!< Generate Restart for read request, slave 7Bit address.  */
  295. #define LL_I2C_GENERATE_RESTART_7BIT_WRITE  (uint32_t)(0x80000000U | I2C_CR2_START)
  296. /*!< Generate Restart for write request, slave 7Bit address. */
  297. #define LL_I2C_GENERATE_RESTART_10BIT_READ  (uint32_t)(0x80000000U | I2C_CR2_START | \
  298.                                                        I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)
  299. /*!< Generate Restart for read request, slave 10Bit address. */
  300. #define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
  301. /*!< Generate Restart for write request, slave 10Bit address.*/
  302. /**
  303.   * @}
  304.   */
  305.  
  306. /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
  307.   * @{
  308.   */
  309. #define LL_I2C_DIRECTION_WRITE              0x00000000U              /*!< Write transfer request by master,
  310.                                                                           slave enters receiver mode.  */
  311. #define LL_I2C_DIRECTION_READ               I2C_ISR_DIR              /*!< Read transfer request by master,
  312.                                                                           slave enters transmitter mode.*/
  313. /**
  314.   * @}
  315.   */
  316.  
  317. /** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
  318.   * @{
  319.   */
  320. #define LL_I2C_DMA_REG_DATA_TRANSMIT        0x00000000U              /*!< Get address of data register used for
  321.                                                                           transmission */
  322. #define LL_I2C_DMA_REG_DATA_RECEIVE         0x00000001U              /*!< Get address of data register used for
  323.                                                                           reception */
  324. /**
  325.   * @}
  326.   */
  327.  
  328. /** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
  329.   * @{
  330.   */
  331. #define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW      0x00000000U          /*!< TimeoutA is used to detect
  332.                                                                           SCL low level timeout.              */
  333. #define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE   /*!< TimeoutA is used to detect
  334.                                                                           both SCL and SDA high level timeout.*/
  335. /**
  336.   * @}
  337.   */
  338.  
  339. /** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
  340.   * @{
  341.   */
  342. #define LL_I2C_SMBUS_TIMEOUTA               I2C_TIMEOUTR_TIMOUTEN                 /*!< TimeoutA enable bit          */
  343. #define LL_I2C_SMBUS_TIMEOUTB               I2C_TIMEOUTR_TEXTEN                   /*!< TimeoutB (extended clock)
  344.                                                                                        enable bit                   */
  345. #define LL_I2C_SMBUS_ALL_TIMEOUT            (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | \
  346.                                                        I2C_TIMEOUTR_TEXTEN)       /*!< TimeoutA and TimeoutB
  347. (extended clock) enable bits */
  348. /**
  349.   * @}
  350.   */
  351.  
  352. /**
  353.   * @}
  354.   */
  355.  
  356. /* Exported macro ------------------------------------------------------------*/
  357. /** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
  358.   * @{
  359.   */
  360.  
  361. /** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
  362.   * @{
  363.   */
  364.  
  365. /**
  366.   * @brief  Write a value in I2C register
  367.   * @param  __INSTANCE__ I2C Instance
  368.   * @param  __REG__ Register to be written
  369.   * @param  __VALUE__ Value to be written in the register
  370.   * @retval None
  371.   */
  372. #define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
  373.  
  374. /**
  375.   * @brief  Read a value in I2C register
  376.   * @param  __INSTANCE__ I2C Instance
  377.   * @param  __REG__ Register to be read
  378.   * @retval Register value
  379.   */
  380. #define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
  381. /**
  382.   * @}
  383.   */
  384.  
  385. /** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
  386.   * @{
  387.   */
  388. /**
  389.   * @brief  Configure the SDA setup, hold time and the SCL high, low period.
  390.   * @param  __PRESCALER__ This parameter must be a value between  Min_Data=0 and Max_Data=0xF.
  391.   * @param  __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
  392.                            (tscldel = (SCLDEL+1)xtpresc)
  393.   * @param  __HOLD_TIME__  This parameter must be a value between Min_Data=0 and Max_Data=0xF.
  394.                            (tsdadel = SDADELxtpresc)
  395.   * @param  __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
  396.                             (tsclh = (SCLH+1)xtpresc)
  397.   * @param  __SCLL_PERIOD__ This parameter must be a value between  Min_Data=0 and Max_Data=0xFF.
  398.                             (tscll = (SCLL+1)xtpresc)
  399.   * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
  400.   */
  401. #define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \
  402.   ((((uint32_t)(__PRESCALER__)    << I2C_TIMINGR_PRESC_Pos)  & I2C_TIMINGR_PRESC)   | \
  403.    (((uint32_t)(__SETUP_TIME__)   << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL)  | \
  404.    (((uint32_t)(__HOLD_TIME__)    << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL)  | \
  405.    (((uint32_t)(__SCLH_PERIOD__)  << I2C_TIMINGR_SCLH_Pos)   & I2C_TIMINGR_SCLH)    | \
  406.    (((uint32_t)(__SCLL_PERIOD__)  << I2C_TIMINGR_SCLL_Pos)   & I2C_TIMINGR_SCLL))
  407. /**
  408.   * @}
  409.   */
  410.  
  411. /**
  412.   * @}
  413.   */
  414.  
  415. /* Exported functions --------------------------------------------------------*/
  416. /** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
  417.   * @{
  418.   */
  419.  
  420. /** @defgroup I2C_LL_EF_Configuration Configuration
  421.   * @{
  422.   */
  423.  
  424. /**
  425.   * @brief  Enable I2C peripheral (PE = 1).
  426.   * @rmtoll CR1          PE            LL_I2C_Enable
  427.   * @param  I2Cx I2C Instance.
  428.   * @retval None
  429.   */
  430. __STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
  431. {
  432.   SET_BIT(I2Cx->CR1, I2C_CR1_PE);
  433. }
  434.  
  435. /**
  436.   * @brief  Disable I2C peripheral (PE = 0).
  437.   * @note   When PE = 0, the I2C SCL and SDA lines are released.
  438.   *         Internal state machines and status bits are put back to their reset value.
  439.   *         When cleared, PE must be kept low for at least 3 APB clock cycles.
  440.   * @rmtoll CR1          PE            LL_I2C_Disable
  441.   * @param  I2Cx I2C Instance.
  442.   * @retval None
  443.   */
  444. __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
  445. {
  446.   CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
  447. }
  448.  
  449. /**
  450.   * @brief  Check if the I2C peripheral is enabled or disabled.
  451.   * @rmtoll CR1          PE            LL_I2C_IsEnabled
  452.   * @param  I2Cx I2C Instance.
  453.   * @retval State of bit (1 or 0).
  454.   */
  455. __STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
  456. {
  457.   return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL);
  458. }
  459.  
  460. /**
  461.   * @brief  Configure Noise Filters (Analog and Digital).
  462.   * @note   If the analog filter is also enabled, the digital filter is added to analog filter.
  463.   *         The filters can only be programmed when the I2C is disabled (PE = 0).
  464.   * @rmtoll CR1          ANFOFF        LL_I2C_ConfigFilters\n
  465.   *         CR1          DNF           LL_I2C_ConfigFilters
  466.   * @param  I2Cx I2C Instance.
  467.   * @param  AnalogFilter This parameter can be one of the following values:
  468.   *         @arg @ref LL_I2C_ANALOGFILTER_ENABLE
  469.   *         @arg @ref LL_I2C_ANALOGFILTER_DISABLE
  470.   * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
  471.                           and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
  472.   *         This parameter is used to configure the digital noise filter on SDA and SCL input.
  473.   *         The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
  474.   * @retval None
  475.   */
  476. __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
  477. {
  478.   MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos));
  479. }
  480.  
  481. /**
  482.   * @brief  Configure Digital Noise Filter.
  483.   * @note   If the analog filter is also enabled, the digital filter is added to analog filter.
  484.   *         This filter can only be programmed when the I2C is disabled (PE = 0).
  485.   * @rmtoll CR1          DNF           LL_I2C_SetDigitalFilter
  486.   * @param  I2Cx I2C Instance.
  487.   * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
  488.                           and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
  489.   *         This parameter is used to configure the digital noise filter on SDA and SCL input.
  490.   *         The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
  491.   * @retval None
  492.   */
  493. __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
  494. {
  495.   MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);
  496. }
  497.  
  498. /**
  499.   * @brief  Get the current Digital Noise Filter configuration.
  500.   * @rmtoll CR1          DNF           LL_I2C_GetDigitalFilter
  501.   * @param  I2Cx I2C Instance.
  502.   * @retval Value between Min_Data=0x0 and Max_Data=0xF
  503.   */
  504. __STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
  505. {
  506.   return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
  507. }
  508.  
  509. /**
  510.   * @brief  Enable Analog Noise Filter.
  511.   * @note   This filter can only be programmed when the I2C is disabled (PE = 0).
  512.   * @rmtoll CR1          ANFOFF        LL_I2C_EnableAnalogFilter
  513.   * @param  I2Cx I2C Instance.
  514.   * @retval None
  515.   */
  516. __STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
  517. {
  518.   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
  519. }
  520.  
  521. /**
  522.   * @brief  Disable Analog Noise Filter.
  523.   * @note   This filter can only be programmed when the I2C is disabled (PE = 0).
  524.   * @rmtoll CR1          ANFOFF        LL_I2C_DisableAnalogFilter
  525.   * @param  I2Cx I2C Instance.
  526.   * @retval None
  527.   */
  528. __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
  529. {
  530.   SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
  531. }
  532.  
  533. /**
  534.   * @brief  Check if Analog Noise Filter is enabled or disabled.
  535.   * @rmtoll CR1          ANFOFF        LL_I2C_IsEnabledAnalogFilter
  536.   * @param  I2Cx I2C Instance.
  537.   * @retval State of bit (1 or 0).
  538.   */
  539. __STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
  540. {
  541.   return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL);
  542. }
  543.  
  544. /**
  545.   * @brief  Enable DMA transmission requests.
  546.   * @rmtoll CR1          TXDMAEN       LL_I2C_EnableDMAReq_TX
  547.   * @param  I2Cx I2C Instance.
  548.   * @retval None
  549.   */
  550. __STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
  551. {
  552.   SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
  553. }
  554.  
  555. /**
  556.   * @brief  Disable DMA transmission requests.
  557.   * @rmtoll CR1          TXDMAEN       LL_I2C_DisableDMAReq_TX
  558.   * @param  I2Cx I2C Instance.
  559.   * @retval None
  560.   */
  561. __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
  562. {
  563.   CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
  564. }
  565.  
  566. /**
  567.   * @brief  Check if DMA transmission requests are enabled or disabled.
  568.   * @rmtoll CR1          TXDMAEN       LL_I2C_IsEnabledDMAReq_TX
  569.   * @param  I2Cx I2C Instance.
  570.   * @retval State of bit (1 or 0).
  571.   */
  572. __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
  573. {
  574.   return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL);
  575. }
  576.  
  577. /**
  578.   * @brief  Enable DMA reception requests.
  579.   * @rmtoll CR1          RXDMAEN       LL_I2C_EnableDMAReq_RX
  580.   * @param  I2Cx I2C Instance.
  581.   * @retval None
  582.   */
  583. __STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
  584. {
  585.   SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
  586. }
  587.  
  588. /**
  589.   * @brief  Disable DMA reception requests.
  590.   * @rmtoll CR1          RXDMAEN       LL_I2C_DisableDMAReq_RX
  591.   * @param  I2Cx I2C Instance.
  592.   * @retval None
  593.   */
  594. __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
  595. {
  596.   CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
  597. }
  598.  
  599. /**
  600.   * @brief  Check if DMA reception requests are enabled or disabled.
  601.   * @rmtoll CR1          RXDMAEN       LL_I2C_IsEnabledDMAReq_RX
  602.   * @param  I2Cx I2C Instance.
  603.   * @retval State of bit (1 or 0).
  604.   */
  605. __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
  606. {
  607.   return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL);
  608. }
  609.  
  610. /**
  611.   * @brief  Get the data register address used for DMA transfer
  612.   * @rmtoll TXDR         TXDATA        LL_I2C_DMA_GetRegAddr\n
  613.   *         RXDR         RXDATA        LL_I2C_DMA_GetRegAddr
  614.   * @param  I2Cx I2C Instance
  615.   * @param  Direction This parameter can be one of the following values:
  616.   *         @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
  617.   *         @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
  618.   * @retval Address of data register
  619.   */
  620. __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
  621. {
  622.   uint32_t data_reg_addr;
  623.  
  624.   if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
  625.   {
  626.     /* return address of TXDR register */
  627.     data_reg_addr = (uint32_t) &(I2Cx->TXDR);
  628.   }
  629.   else
  630.   {
  631.     /* return address of RXDR register */
  632.     data_reg_addr = (uint32_t) &(I2Cx->RXDR);
  633.   }
  634.  
  635.   return data_reg_addr;
  636. }
  637.  
  638. /**
  639.   * @brief  Enable Clock stretching.
  640.   * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
  641.   * @rmtoll CR1          NOSTRETCH     LL_I2C_EnableClockStretching
  642.   * @param  I2Cx I2C Instance.
  643.   * @retval None
  644.   */
  645. __STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
  646. {
  647.   CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
  648. }
  649.  
  650. /**
  651.   * @brief  Disable Clock stretching.
  652.   * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
  653.   * @rmtoll CR1          NOSTRETCH     LL_I2C_DisableClockStretching
  654.   * @param  I2Cx I2C Instance.
  655.   * @retval None
  656.   */
  657. __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
  658. {
  659.   SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
  660. }
  661.  
  662. /**
  663.   * @brief  Check if Clock stretching is enabled or disabled.
  664.   * @rmtoll CR1          NOSTRETCH     LL_I2C_IsEnabledClockStretching
  665.   * @param  I2Cx I2C Instance.
  666.   * @retval State of bit (1 or 0).
  667.   */
  668. __STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
  669. {
  670.   return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
  671. }
  672.  
  673. /**
  674.   * @brief  Enable hardware byte control in slave mode.
  675.   * @rmtoll CR1          SBC           LL_I2C_EnableSlaveByteControl
  676.   * @param  I2Cx I2C Instance.
  677.   * @retval None
  678.   */
  679. __STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
  680. {
  681.   SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
  682. }
  683.  
  684. /**
  685.   * @brief  Disable hardware byte control in slave mode.
  686.   * @rmtoll CR1          SBC           LL_I2C_DisableSlaveByteControl
  687.   * @param  I2Cx I2C Instance.
  688.   * @retval None
  689.   */
  690. __STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
  691. {
  692.   CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
  693. }
  694.  
  695. /**
  696.   * @brief  Check if hardware byte control in slave mode is enabled or disabled.
  697.   * @rmtoll CR1          SBC           LL_I2C_IsEnabledSlaveByteControl
  698.   * @param  I2Cx I2C Instance.
  699.   * @retval State of bit (1 or 0).
  700.   */
  701. __STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
  702. {
  703.   return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL);
  704. }
  705.  
  706. #if defined(I2C_CR1_WUPEN)
  707. /**
  708.   * @brief  Enable Wakeup from STOP.
  709.   * @note   The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
  710.   *         WakeUpFromStop feature is supported by the I2Cx Instance.
  711.   * @note   This bit can only be programmed when Digital Filter is disabled.
  712.   * @rmtoll CR1          WUPEN         LL_I2C_EnableWakeUpFromStop
  713.   * @param  I2Cx I2C Instance.
  714.   * @retval None
  715.   */
  716. __STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
  717. {
  718.   SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
  719. }
  720.  
  721. /**
  722.   * @brief  Disable Wakeup from STOP.
  723.   * @note   The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
  724.   *         WakeUpFromStop feature is supported by the I2Cx Instance.
  725.   * @rmtoll CR1          WUPEN         LL_I2C_DisableWakeUpFromStop
  726.   * @param  I2Cx I2C Instance.
  727.   * @retval None
  728.   */
  729. __STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
  730. {
  731.   CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
  732. }
  733.  
  734. /**
  735.   * @brief  Check if Wakeup from STOP is enabled or disabled.
  736.   * @note   The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
  737.   *         WakeUpFromStop feature is supported by the I2Cx Instance.
  738.   * @rmtoll CR1          WUPEN         LL_I2C_IsEnabledWakeUpFromStop
  739.   * @param  I2Cx I2C Instance.
  740.   * @retval State of bit (1 or 0).
  741.   */
  742. __STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx)
  743. {
  744.   return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL);
  745. }
  746.  
  747. #endif /* I2C_CR1_WUPEN */
  748. /**
  749.   * @brief  Enable General Call.
  750.   * @note   When enabled the Address 0x00 is ACKed.
  751.   * @rmtoll CR1          GCEN          LL_I2C_EnableGeneralCall
  752.   * @param  I2Cx I2C Instance.
  753.   * @retval None
  754.   */
  755. __STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
  756. {
  757.   SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
  758. }
  759.  
  760. /**
  761.   * @brief  Disable General Call.
  762.   * @note   When disabled the Address 0x00 is NACKed.
  763.   * @rmtoll CR1          GCEN          LL_I2C_DisableGeneralCall
  764.   * @param  I2Cx I2C Instance.
  765.   * @retval None
  766.   */
  767. __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
  768. {
  769.   CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
  770. }
  771.  
  772. /**
  773.   * @brief  Check if General Call is enabled or disabled.
  774.   * @rmtoll CR1          GCEN          LL_I2C_IsEnabledGeneralCall
  775.   * @param  I2Cx I2C Instance.
  776.   * @retval State of bit (1 or 0).
  777.   */
  778. __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
  779. {
  780.   return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);
  781. }
  782.  
  783. /**
  784.   * @brief  Configure the Master to operate in 7-bit or 10-bit addressing mode.
  785.   * @note   Changing this bit is not allowed, when the START bit is set.
  786.   * @rmtoll CR2          ADD10         LL_I2C_SetMasterAddressingMode
  787.   * @param  I2Cx I2C Instance.
  788.   * @param  AddressingMode This parameter can be one of the following values:
  789.   *         @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
  790.   *         @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
  791.   * @retval None
  792.   */
  793. __STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
  794. {
  795.   MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
  796. }
  797.  
  798. /**
  799.   * @brief  Get the Master addressing mode.
  800.   * @rmtoll CR2          ADD10         LL_I2C_GetMasterAddressingMode
  801.   * @param  I2Cx I2C Instance.
  802.   * @retval Returned value can be one of the following values:
  803.   *         @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
  804.   *         @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
  805.   */
  806. __STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
  807. {
  808.   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
  809. }
  810.  
  811. /**
  812.   * @brief  Set the Own Address1.
  813.   * @rmtoll OAR1         OA1           LL_I2C_SetOwnAddress1\n
  814.   *         OAR1         OA1MODE       LL_I2C_SetOwnAddress1
  815.   * @param  I2Cx I2C Instance.
  816.   * @param  OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
  817.   * @param  OwnAddrSize This parameter can be one of the following values:
  818.   *         @arg @ref LL_I2C_OWNADDRESS1_7BIT
  819.   *         @arg @ref LL_I2C_OWNADDRESS1_10BIT
  820.   * @retval None
  821.   */
  822. __STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
  823. {
  824.   MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
  825. }
  826.  
  827. /**
  828.   * @brief  Enable acknowledge on Own Address1 match address.
  829.   * @rmtoll OAR1         OA1EN         LL_I2C_EnableOwnAddress1
  830.   * @param  I2Cx I2C Instance.
  831.   * @retval None
  832.   */
  833. __STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
  834. {
  835.   SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
  836. }
  837.  
  838. /**
  839.   * @brief  Disable acknowledge on Own Address1 match address.
  840.   * @rmtoll OAR1         OA1EN         LL_I2C_DisableOwnAddress1
  841.   * @param  I2Cx I2C Instance.
  842.   * @retval None
  843.   */
  844. __STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
  845. {
  846.   CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
  847. }
  848.  
  849. /**
  850.   * @brief  Check if Own Address1 acknowledge is enabled or disabled.
  851.   * @rmtoll OAR1         OA1EN         LL_I2C_IsEnabledOwnAddress1
  852.   * @param  I2Cx I2C Instance.
  853.   * @retval State of bit (1 or 0).
  854.   */
  855. __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
  856. {
  857.   return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL);
  858. }
  859.  
  860. /**
  861.   * @brief  Set the 7bits Own Address2.
  862.   * @note   This action has no effect if own address2 is enabled.
  863.   * @rmtoll OAR2         OA2           LL_I2C_SetOwnAddress2\n
  864.   *         OAR2         OA2MSK        LL_I2C_SetOwnAddress2
  865.   * @param  I2Cx I2C Instance.
  866.   * @param  OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
  867.   * @param  OwnAddrMask This parameter can be one of the following values:
  868.   *         @arg @ref LL_I2C_OWNADDRESS2_NOMASK
  869.   *         @arg @ref LL_I2C_OWNADDRESS2_MASK01
  870.   *         @arg @ref LL_I2C_OWNADDRESS2_MASK02
  871.   *         @arg @ref LL_I2C_OWNADDRESS2_MASK03
  872.   *         @arg @ref LL_I2C_OWNADDRESS2_MASK04
  873.   *         @arg @ref LL_I2C_OWNADDRESS2_MASK05
  874.   *         @arg @ref LL_I2C_OWNADDRESS2_MASK06
  875.   *         @arg @ref LL_I2C_OWNADDRESS2_MASK07
  876.   * @retval None
  877.   */
  878. __STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
  879. {
  880.   MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
  881. }
  882.  
  883. /**
  884.   * @brief  Enable acknowledge on Own Address2 match address.
  885.   * @rmtoll OAR2         OA2EN         LL_I2C_EnableOwnAddress2
  886.   * @param  I2Cx I2C Instance.
  887.   * @retval None
  888.   */
  889. __STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
  890. {
  891.   SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
  892. }
  893.  
  894. /**
  895.   * @brief  Disable  acknowledge on Own Address2 match address.
  896.   * @rmtoll OAR2         OA2EN         LL_I2C_DisableOwnAddress2
  897.   * @param  I2Cx I2C Instance.
  898.   * @retval None
  899.   */
  900. __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
  901. {
  902.   CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
  903. }
  904.  
  905. /**
  906.   * @brief  Check if Own Address1 acknowledge is enabled or disabled.
  907.   * @rmtoll OAR2         OA2EN         LL_I2C_IsEnabledOwnAddress2
  908.   * @param  I2Cx I2C Instance.
  909.   * @retval State of bit (1 or 0).
  910.   */
  911. __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
  912. {
  913.   return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL);
  914. }
  915.  
  916. /**
  917.   * @brief  Configure the SDA setup, hold time and the SCL high, low period.
  918.   * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
  919.   * @rmtoll TIMINGR      TIMINGR       LL_I2C_SetTiming
  920.   * @param  I2Cx I2C Instance.
  921.   * @param  Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
  922.   * @note   This parameter is computed with the STM32CubeMX Tool.
  923.   * @retval None
  924.   */
  925. __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
  926. {
  927.   WRITE_REG(I2Cx->TIMINGR, Timing);
  928. }
  929.  
  930. /**
  931.   * @brief  Get the Timing Prescaler setting.
  932.   * @rmtoll TIMINGR      PRESC         LL_I2C_GetTimingPrescaler
  933.   * @param  I2Cx I2C Instance.
  934.   * @retval Value between Min_Data=0x0 and Max_Data=0xF
  935.   */
  936. __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
  937. {
  938.   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
  939. }
  940.  
  941. /**
  942.   * @brief  Get the SCL low period setting.
  943.   * @rmtoll TIMINGR      SCLL          LL_I2C_GetClockLowPeriod
  944.   * @param  I2Cx I2C Instance.
  945.   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
  946.   */
  947. __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
  948. {
  949.   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
  950. }
  951.  
  952. /**
  953.   * @brief  Get the SCL high period setting.
  954.   * @rmtoll TIMINGR      SCLH          LL_I2C_GetClockHighPeriod
  955.   * @param  I2Cx I2C Instance.
  956.   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
  957.   */
  958. __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
  959. {
  960.   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
  961. }
  962.  
  963. /**
  964.   * @brief  Get the SDA hold time.
  965.   * @rmtoll TIMINGR      SDADEL        LL_I2C_GetDataHoldTime
  966.   * @param  I2Cx I2C Instance.
  967.   * @retval Value between Min_Data=0x0 and Max_Data=0xF
  968.   */
  969. __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
  970. {
  971.   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
  972. }
  973.  
  974. /**
  975.   * @brief  Get the SDA setup time.
  976.   * @rmtoll TIMINGR      SCLDEL        LL_I2C_GetDataSetupTime
  977.   * @param  I2Cx I2C Instance.
  978.   * @retval Value between Min_Data=0x0 and Max_Data=0xF
  979.   */
  980. __STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
  981. {
  982.   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
  983. }
  984.  
  985. /**
  986.   * @brief  Configure peripheral mode.
  987.   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
  988.   *         SMBus feature is supported by the I2Cx Instance.
  989.   * @rmtoll CR1          SMBHEN        LL_I2C_SetMode\n
  990.   *         CR1          SMBDEN        LL_I2C_SetMode
  991.   * @param  I2Cx I2C Instance.
  992.   * @param  PeripheralMode This parameter can be one of the following values:
  993.   *         @arg @ref LL_I2C_MODE_I2C
  994.   *         @arg @ref LL_I2C_MODE_SMBUS_HOST
  995.   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
  996.   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
  997.   * @retval None
  998.   */
  999. __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
  1000. {
  1001.   MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode);
  1002. }
  1003.  
  1004. /**
  1005.   * @brief  Get peripheral mode.
  1006.   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
  1007.   *         SMBus feature is supported by the I2Cx Instance.
  1008.   * @rmtoll CR1          SMBHEN        LL_I2C_GetMode\n
  1009.   *         CR1          SMBDEN        LL_I2C_GetMode
  1010.   * @param  I2Cx I2C Instance.
  1011.   * @retval Returned value can be one of the following values:
  1012.   *         @arg @ref LL_I2C_MODE_I2C
  1013.   *         @arg @ref LL_I2C_MODE_SMBUS_HOST
  1014.   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
  1015.   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
  1016.   */
  1017. __STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
  1018. {
  1019.   return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
  1020. }
  1021.  
  1022. /**
  1023.   * @brief  Enable SMBus alert (Host or Device mode)
  1024.   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
  1025.   *         SMBus feature is supported by the I2Cx Instance.
  1026.   * @note   SMBus Device mode:
  1027.   *         - SMBus Alert pin is drived low and
  1028.   *           Alert Response Address Header acknowledge is enabled.
  1029.   *         SMBus Host mode:
  1030.   *         - SMBus Alert pin management is supported.
  1031.   * @rmtoll CR1          ALERTEN       LL_I2C_EnableSMBusAlert
  1032.   * @param  I2Cx I2C Instance.
  1033.   * @retval None
  1034.   */
  1035. __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
  1036. {
  1037.   SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
  1038. }
  1039.  
  1040. /**
  1041.   * @brief  Disable SMBus alert (Host or Device mode)
  1042.   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
  1043.   *         SMBus feature is supported by the I2Cx Instance.
  1044.   * @note   SMBus Device mode:
  1045.   *         - SMBus Alert pin is not drived (can be used as a standard GPIO) and
  1046.   *           Alert Response Address Header acknowledge is disabled.
  1047.   *         SMBus Host mode:
  1048.   *         - SMBus Alert pin management is not supported.
  1049.   * @rmtoll CR1          ALERTEN       LL_I2C_DisableSMBusAlert
  1050.   * @param  I2Cx I2C Instance.
  1051.   * @retval None
  1052.   */
  1053. __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
  1054. {
  1055.   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
  1056. }
  1057.  
  1058. /**
  1059.   * @brief  Check if SMBus alert (Host or Device mode) is enabled or disabled.
  1060.   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
  1061.   *         SMBus feature is supported by the I2Cx Instance.
  1062.   * @rmtoll CR1          ALERTEN       LL_I2C_IsEnabledSMBusAlert
  1063.   * @param  I2Cx I2C Instance.
  1064.   * @retval State of bit (1 or 0).
  1065.   */
  1066. __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
  1067. {
  1068.   return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL);
  1069. }
  1070.  
  1071. /**
  1072.   * @brief  Enable SMBus Packet Error Calculation (PEC).
  1073.   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
  1074.   *         SMBus feature is supported by the I2Cx Instance.
  1075.   * @rmtoll CR1          PECEN         LL_I2C_EnableSMBusPEC
  1076.   * @param  I2Cx I2C Instance.
  1077.   * @retval None
  1078.   */
  1079. __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
  1080. {
  1081.   SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
  1082. }
  1083.  
  1084. /**
  1085.   * @brief  Disable SMBus Packet Error Calculation (PEC).
  1086.   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
  1087.   *         SMBus feature is supported by the I2Cx Instance.
  1088.   * @rmtoll CR1          PECEN         LL_I2C_DisableSMBusPEC
  1089.   * @param  I2Cx I2C Instance.
  1090.   * @retval None
  1091.   */
  1092. __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
  1093. {
  1094.   CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
  1095. }
  1096.  
  1097. /**
  1098.   * @brief  Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
  1099.   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
  1100.   *         SMBus feature is supported by the I2Cx Instance.
  1101.   * @rmtoll CR1          PECEN         LL_I2C_IsEnabledSMBusPEC
  1102.   * @param  I2Cx I2C Instance.
  1103.   * @retval State of bit (1 or 0).
  1104.   */
  1105. __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
  1106. {
  1107.   return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL);
  1108. }
  1109.  
  1110. /**
  1111.   * @brief  Configure the SMBus Clock Timeout.
  1112.   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
  1113.   *         SMBus feature is supported by the I2Cx Instance.
  1114.   * @note   This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
  1115.   * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_ConfigSMBusTimeout\n
  1116.   *         TIMEOUTR     TIDLE         LL_I2C_ConfigSMBusTimeout\n
  1117.   *         TIMEOUTR     TIMEOUTB      LL_I2C_ConfigSMBusTimeout
  1118.   * @param  I2Cx I2C Instance.
  1119.   * @param  TimeoutA This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
  1120.   * @param  TimeoutAMode This parameter can be one of the following values:
  1121.   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
  1122.   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
  1123.   * @param  TimeoutB
  1124.   * @retval None
  1125.   */
  1126. __STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
  1127.                                                uint32_t TimeoutB)
  1128. {
  1129.   MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB,
  1130.              TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));
  1131. }
  1132.  
  1133. /**
  1134.   * @brief  Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
  1135.   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
  1136.   *         SMBus feature is supported by the I2Cx Instance.
  1137.   * @note   These bits can only be programmed when TimeoutA is disabled.
  1138.   * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_SetSMBusTimeoutA
  1139.   * @param  I2Cx I2C Instance.
  1140.   * @param  TimeoutA This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
  1141.   * @retval None
  1142.   */
  1143. __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
  1144. {
  1145.   WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
  1146. }
  1147.  
  1148. /**
  1149.   * @brief  Get the SMBus Clock TimeoutA setting.
  1150.   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
  1151.   *         SMBus feature is supported by the I2Cx Instance.
  1152.   * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_GetSMBusTimeoutA
  1153.   * @param  I2Cx I2C Instance.
  1154.   * @retval Value between Min_Data=0 and Max_Data=0xFFF
  1155.   */
  1156. __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
  1157. {
  1158.   return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
  1159. }
  1160.  
  1161. /**
  1162.   * @brief  Set the SMBus Clock TimeoutA mode.
  1163.   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
  1164.   *         SMBus feature is supported by the I2Cx Instance.
  1165.   * @note   This bit can only be programmed when TimeoutA is disabled.
  1166.   * @rmtoll TIMEOUTR     TIDLE         LL_I2C_SetSMBusTimeoutAMode
  1167.   * @param  I2Cx I2C Instance.
  1168.   * @param  TimeoutAMode This parameter can be one of the following values:
  1169.   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
  1170.   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
  1171.   * @retval None
  1172.   */
  1173. __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
  1174. {
  1175.   WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
  1176. }
  1177.  
  1178. /**
  1179.   * @brief  Get the SMBus Clock TimeoutA mode.
  1180.   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
  1181.   *         SMBus feature is supported by the I2Cx Instance.
  1182.   * @rmtoll TIMEOUTR     TIDLE         LL_I2C_GetSMBusTimeoutAMode
  1183.   * @param  I2Cx I2C Instance.
  1184.   * @retval Returned value can be one of the following values:
  1185.   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
  1186.   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
  1187.   */
  1188. __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
  1189. {
  1190.   return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
  1191. }
  1192.  
  1193. /**
  1194.   * @brief  Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
  1195.   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
  1196.   *         SMBus feature is supported by the I2Cx Instance.
  1197.   * @note   These bits can only be programmed when TimeoutB is disabled.
  1198.   * @rmtoll TIMEOUTR     TIMEOUTB      LL_I2C_SetSMBusTimeoutB
  1199.   * @param  I2Cx I2C Instance.
  1200.   * @param  TimeoutB This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
  1201.   * @retval None
  1202.   */
  1203. __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
  1204. {
  1205.   WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos);
  1206. }
  1207.  
  1208. /**
  1209.   * @brief  Get the SMBus Extended Cumulative Clock TimeoutB setting.
  1210.   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
  1211.   *         SMBus feature is supported by the I2Cx Instance.
  1212.   * @rmtoll TIMEOUTR     TIMEOUTB      LL_I2C_GetSMBusTimeoutB
  1213.   * @param  I2Cx I2C Instance.
  1214.   * @retval Value between Min_Data=0 and Max_Data=0xFFF
  1215.   */
  1216. __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
  1217. {
  1218.   return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
  1219. }
  1220.  
  1221. /**
  1222.   * @brief  Enable the SMBus Clock Timeout.
  1223.   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
  1224.   *         SMBus feature is supported by the I2Cx Instance.
  1225.   * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_EnableSMBusTimeout\n
  1226.   *         TIMEOUTR     TEXTEN        LL_I2C_EnableSMBusTimeout
  1227.   * @param  I2Cx I2C Instance.
  1228.   * @param  ClockTimeout This parameter can be one of the following values:
  1229.   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
  1230.   *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
  1231.   *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
  1232.   * @retval None
  1233.   */
  1234. __STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
  1235. {
  1236.   SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
  1237. }
  1238.  
  1239. /**
  1240.   * @brief  Disable the SMBus Clock Timeout.
  1241.   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
  1242.   *         SMBus feature is supported by the I2Cx Instance.
  1243.   * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_DisableSMBusTimeout\n
  1244.   *         TIMEOUTR     TEXTEN        LL_I2C_DisableSMBusTimeout
  1245.   * @param  I2Cx I2C Instance.
  1246.   * @param  ClockTimeout This parameter can be one of the following values:
  1247.   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
  1248.   *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
  1249.   *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
  1250.   * @retval None
  1251.   */
  1252. __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
  1253. {
  1254.   CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
  1255. }
  1256.  
  1257. /**
  1258.   * @brief  Check if the SMBus Clock Timeout is enabled or disabled.
  1259.   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
  1260.   *         SMBus feature is supported by the I2Cx Instance.
  1261.   * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_IsEnabledSMBusTimeout\n
  1262.   *         TIMEOUTR     TEXTEN        LL_I2C_IsEnabledSMBusTimeout
  1263.   * @param  I2Cx I2C Instance.
  1264.   * @param  ClockTimeout This parameter can be one of the following values:
  1265.   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
  1266.   *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
  1267.   *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
  1268.   * @retval State of bit (1 or 0).
  1269.   */
  1270. __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
  1271. {
  1272.   return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \
  1273.            (ClockTimeout)) ? 1UL : 0UL);
  1274. }
  1275.  
  1276. /**
  1277.   * @}
  1278.   */
  1279.  
  1280. /** @defgroup I2C_LL_EF_IT_Management IT_Management
  1281.   * @{
  1282.   */
  1283.  
  1284. /**
  1285.   * @brief  Enable TXIS interrupt.
  1286.   * @rmtoll CR1          TXIE          LL_I2C_EnableIT_TX
  1287.   * @param  I2Cx I2C Instance.
  1288.   * @retval None
  1289.   */
  1290. __STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
  1291. {
  1292.   SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
  1293. }
  1294.  
  1295. /**
  1296.   * @brief  Disable TXIS interrupt.
  1297.   * @rmtoll CR1          TXIE          LL_I2C_DisableIT_TX
  1298.   * @param  I2Cx I2C Instance.
  1299.   * @retval None
  1300.   */
  1301. __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
  1302. {
  1303.   CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
  1304. }
  1305.  
  1306. /**
  1307.   * @brief  Check if the TXIS Interrupt is enabled or disabled.
  1308.   * @rmtoll CR1          TXIE          LL_I2C_IsEnabledIT_TX
  1309.   * @param  I2Cx I2C Instance.
  1310.   * @retval State of bit (1 or 0).
  1311.   */
  1312. __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
  1313. {
  1314.   return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL);
  1315. }
  1316.  
  1317. /**
  1318.   * @brief  Enable RXNE interrupt.
  1319.   * @rmtoll CR1          RXIE          LL_I2C_EnableIT_RX
  1320.   * @param  I2Cx I2C Instance.
  1321.   * @retval None
  1322.   */
  1323. __STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
  1324. {
  1325.   SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
  1326. }
  1327.  
  1328. /**
  1329.   * @brief  Disable RXNE interrupt.
  1330.   * @rmtoll CR1          RXIE          LL_I2C_DisableIT_RX
  1331.   * @param  I2Cx I2C Instance.
  1332.   * @retval None
  1333.   */
  1334. __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
  1335. {
  1336.   CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
  1337. }
  1338.  
  1339. /**
  1340.   * @brief  Check if the RXNE Interrupt is enabled or disabled.
  1341.   * @rmtoll CR1          RXIE          LL_I2C_IsEnabledIT_RX
  1342.   * @param  I2Cx I2C Instance.
  1343.   * @retval State of bit (1 or 0).
  1344.   */
  1345. __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
  1346. {
  1347.   return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL);
  1348. }
  1349.  
  1350. /**
  1351.   * @brief  Enable Address match interrupt (slave mode only).
  1352.   * @rmtoll CR1          ADDRIE        LL_I2C_EnableIT_ADDR
  1353.   * @param  I2Cx I2C Instance.
  1354.   * @retval None
  1355.   */
  1356. __STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
  1357. {
  1358.   SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
  1359. }
  1360.  
  1361. /**
  1362.   * @brief  Disable Address match interrupt (slave mode only).
  1363.   * @rmtoll CR1          ADDRIE        LL_I2C_DisableIT_ADDR
  1364.   * @param  I2Cx I2C Instance.
  1365.   * @retval None
  1366.   */
  1367. __STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
  1368. {
  1369.   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
  1370. }
  1371.  
  1372. /**
  1373.   * @brief  Check if Address match interrupt is enabled or disabled.
  1374.   * @rmtoll CR1          ADDRIE        LL_I2C_IsEnabledIT_ADDR
  1375.   * @param  I2Cx I2C Instance.
  1376.   * @retval State of bit (1 or 0).
  1377.   */
  1378. __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
  1379. {
  1380.   return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL);
  1381. }
  1382.  
  1383. /**
  1384.   * @brief  Enable Not acknowledge received interrupt.
  1385.   * @rmtoll CR1          NACKIE        LL_I2C_EnableIT_NACK
  1386.   * @param  I2Cx I2C Instance.
  1387.   * @retval None
  1388.   */
  1389. __STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
  1390. {
  1391.   SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
  1392. }
  1393.  
  1394. /**
  1395.   * @brief  Disable Not acknowledge received interrupt.
  1396.   * @rmtoll CR1          NACKIE        LL_I2C_DisableIT_NACK
  1397.   * @param  I2Cx I2C Instance.
  1398.   * @retval None
  1399.   */
  1400. __STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
  1401. {
  1402.   CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
  1403. }
  1404.  
  1405. /**
  1406.   * @brief  Check if Not acknowledge received interrupt is enabled or disabled.
  1407.   * @rmtoll CR1          NACKIE        LL_I2C_IsEnabledIT_NACK
  1408.   * @param  I2Cx I2C Instance.
  1409.   * @retval State of bit (1 or 0).
  1410.   */
  1411. __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
  1412. {
  1413.   return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL);
  1414. }
  1415.  
  1416. /**
  1417.   * @brief  Enable STOP detection interrupt.
  1418.   * @rmtoll CR1          STOPIE        LL_I2C_EnableIT_STOP
  1419.   * @param  I2Cx I2C Instance.
  1420.   * @retval None
  1421.   */
  1422. __STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
  1423. {
  1424.   SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
  1425. }
  1426.  
  1427. /**
  1428.   * @brief  Disable STOP detection interrupt.
  1429.   * @rmtoll CR1          STOPIE        LL_I2C_DisableIT_STOP
  1430.   * @param  I2Cx I2C Instance.
  1431.   * @retval None
  1432.   */
  1433. __STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
  1434. {
  1435.   CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
  1436. }
  1437.  
  1438. /**
  1439.   * @brief  Check if STOP detection interrupt is enabled or disabled.
  1440.   * @rmtoll CR1          STOPIE        LL_I2C_IsEnabledIT_STOP
  1441.   * @param  I2Cx I2C Instance.
  1442.   * @retval State of bit (1 or 0).
  1443.   */
  1444. __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
  1445. {
  1446.   return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL);
  1447. }
  1448.  
  1449. /**
  1450.   * @brief  Enable Transfer Complete interrupt.
  1451.   * @note   Any of these events will generate interrupt :
  1452.   *         Transfer Complete (TC)
  1453.   *         Transfer Complete Reload (TCR)
  1454.   * @rmtoll CR1          TCIE          LL_I2C_EnableIT_TC
  1455.   * @param  I2Cx I2C Instance.
  1456.   * @retval None
  1457.   */
  1458. __STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
  1459. {
  1460.   SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
  1461. }
  1462.  
  1463. /**
  1464.   * @brief  Disable Transfer Complete interrupt.
  1465.   * @note   Any of these events will generate interrupt :
  1466.   *         Transfer Complete (TC)
  1467.   *         Transfer Complete Reload (TCR)
  1468.   * @rmtoll CR1          TCIE          LL_I2C_DisableIT_TC
  1469.   * @param  I2Cx I2C Instance.
  1470.   * @retval None
  1471.   */
  1472. __STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
  1473. {
  1474.   CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
  1475. }
  1476.  
  1477. /**
  1478.   * @brief  Check if Transfer Complete interrupt is enabled or disabled.
  1479.   * @rmtoll CR1          TCIE          LL_I2C_IsEnabledIT_TC
  1480.   * @param  I2Cx I2C Instance.
  1481.   * @retval State of bit (1 or 0).
  1482.   */
  1483. __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
  1484. {
  1485.   return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL);
  1486. }
  1487.  
  1488. /**
  1489.   * @brief  Enable Error interrupts.
  1490.   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
  1491.   *         SMBus feature is supported by the I2Cx Instance.
  1492.   * @note   Any of these errors will generate interrupt :
  1493.   *         Arbitration Loss (ARLO)
  1494.   *         Bus Error detection (BERR)
  1495.   *         Overrun/Underrun (OVR)
  1496.   *         SMBus Timeout detection (TIMEOUT)
  1497.   *         SMBus PEC error detection (PECERR)
  1498.   *         SMBus Alert pin event detection (ALERT)
  1499.   * @rmtoll CR1          ERRIE         LL_I2C_EnableIT_ERR
  1500.   * @param  I2Cx I2C Instance.
  1501.   * @retval None
  1502.   */
  1503. __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
  1504. {
  1505.   SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
  1506. }
  1507.  
  1508. /**
  1509.   * @brief  Disable Error interrupts.
  1510.   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
  1511.   *         SMBus feature is supported by the I2Cx Instance.
  1512.   * @note   Any of these errors will generate interrupt :
  1513.   *         Arbitration Loss (ARLO)
  1514.   *         Bus Error detection (BERR)
  1515.   *         Overrun/Underrun (OVR)
  1516.   *         SMBus Timeout detection (TIMEOUT)
  1517.   *         SMBus PEC error detection (PECERR)
  1518.   *         SMBus Alert pin event detection (ALERT)
  1519.   * @rmtoll CR1          ERRIE         LL_I2C_DisableIT_ERR
  1520.   * @param  I2Cx I2C Instance.
  1521.   * @retval None
  1522.   */
  1523. __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
  1524. {
  1525.   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
  1526. }
  1527.  
  1528. /**
  1529.   * @brief  Check if Error interrupts are enabled or disabled.
  1530.   * @rmtoll CR1          ERRIE         LL_I2C_IsEnabledIT_ERR
  1531.   * @param  I2Cx I2C Instance.
  1532.   * @retval State of bit (1 or 0).
  1533.   */
  1534. __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
  1535. {
  1536.   return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL);
  1537. }
  1538.  
  1539. /**
  1540.   * @}
  1541.   */
  1542.  
  1543. /** @defgroup I2C_LL_EF_FLAG_management FLAG_management
  1544.   * @{
  1545.   */
  1546.  
  1547. /**
  1548.   * @brief  Indicate the status of Transmit data register empty flag.
  1549.   * @note   RESET: When next data is written in Transmit data register.
  1550.   *         SET: When Transmit data register is empty.
  1551.   * @rmtoll ISR          TXE           LL_I2C_IsActiveFlag_TXE
  1552.   * @param  I2Cx I2C Instance.
  1553.   * @retval State of bit (1 or 0).
  1554.   */
  1555. __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
  1556. {
  1557.   return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);
  1558. }
  1559.  
  1560. /**
  1561.   * @brief  Indicate the status of Transmit interrupt flag.
  1562.   * @note   RESET: When next data is written in Transmit data register.
  1563.   *         SET: When Transmit data register is empty.
  1564.   * @rmtoll ISR          TXIS          LL_I2C_IsActiveFlag_TXIS
  1565.   * @param  I2Cx I2C Instance.
  1566.   * @retval State of bit (1 or 0).
  1567.   */
  1568. __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
  1569. {
  1570.   return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL);
  1571. }
  1572.  
  1573. /**
  1574.   * @brief  Indicate the status of Receive data register not empty flag.
  1575.   * @note   RESET: When Receive data register is read.
  1576.   *         SET: When the received data is copied in Receive data register.
  1577.   * @rmtoll ISR          RXNE          LL_I2C_IsActiveFlag_RXNE
  1578.   * @param  I2Cx I2C Instance.
  1579.   * @retval State of bit (1 or 0).
  1580.   */
  1581. __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
  1582. {
  1583.   return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);
  1584. }
  1585.  
  1586. /**
  1587.   * @brief  Indicate the status of Address matched flag (slave mode).
  1588.   * @note   RESET: Clear default value.
  1589.   *         SET: When the received slave address matched with one of the enabled slave address.
  1590.   * @rmtoll ISR          ADDR          LL_I2C_IsActiveFlag_ADDR
  1591.   * @param  I2Cx I2C Instance.
  1592.   * @retval State of bit (1 or 0).
  1593.   */
  1594. __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
  1595. {
  1596.   return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL);
  1597. }
  1598.  
  1599. /**
  1600.   * @brief  Indicate the status of Not Acknowledge received flag.
  1601.   * @note   RESET: Clear default value.
  1602.   *         SET: When a NACK is received after a byte transmission.
  1603.   * @rmtoll ISR          NACKF         LL_I2C_IsActiveFlag_NACK
  1604.   * @param  I2Cx I2C Instance.
  1605.   * @retval State of bit (1 or 0).
  1606.   */
  1607. __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
  1608. {
  1609.   return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL);
  1610. }
  1611.  
  1612. /**
  1613.   * @brief  Indicate the status of Stop detection flag.
  1614.   * @note   RESET: Clear default value.
  1615.   *         SET: When a Stop condition is detected.
  1616.   * @rmtoll ISR          STOPF         LL_I2C_IsActiveFlag_STOP
  1617.   * @param  I2Cx I2C Instance.
  1618.   * @retval State of bit (1 or 0).
  1619.   */
  1620. __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
  1621. {
  1622.   return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
  1623. }
  1624.  
  1625. /**
  1626.   * @brief  Indicate the status of Transfer complete flag (master mode).
  1627.   * @note   RESET: Clear default value.
  1628.   *         SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
  1629.   * @rmtoll ISR          TC            LL_I2C_IsActiveFlag_TC
  1630.   * @param  I2Cx I2C Instance.
  1631.   * @retval State of bit (1 or 0).
  1632.   */
  1633. __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
  1634. {
  1635.   return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL);
  1636. }
  1637.  
  1638. /**
  1639.   * @brief  Indicate the status of Transfer complete flag (master mode).
  1640.   * @note   RESET: Clear default value.
  1641.   *         SET: When RELOAD=1 and NBYTES date have been transferred.
  1642.   * @rmtoll ISR          TCR           LL_I2C_IsActiveFlag_TCR
  1643.   * @param  I2Cx I2C Instance.
  1644.   * @retval State of bit (1 or 0).
  1645.   */
  1646. __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
  1647. {
  1648.   return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL);
  1649. }
  1650.  
  1651. /**
  1652.   * @brief  Indicate the status of Bus error flag.
  1653.   * @note   RESET: Clear default value.
  1654.   *         SET: When a misplaced Start or Stop condition is detected.
  1655.   * @rmtoll ISR          BERR          LL_I2C_IsActiveFlag_BERR
  1656.   * @param  I2Cx I2C Instance.
  1657.   * @retval State of bit (1 or 0).
  1658.   */
  1659. __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
  1660. {
  1661.   return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL);
  1662. }
  1663.  
  1664. /**
  1665.   * @brief  Indicate the status of Arbitration lost flag.
  1666.   * @note   RESET: Clear default value.
  1667.   *         SET: When arbitration lost.
  1668.   * @rmtoll ISR          ARLO          LL_I2C_IsActiveFlag_ARLO
  1669.   * @param  I2Cx I2C Instance.
  1670.   * @retval State of bit (1 or 0).
  1671.   */
  1672. __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
  1673. {
  1674.   return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL);
  1675. }
  1676.  
  1677. /**
  1678.   * @brief  Indicate the status of Overrun/Underrun flag (slave mode).
  1679.   * @note   RESET: Clear default value.
  1680.   *         SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
  1681.   * @rmtoll ISR          OVR           LL_I2C_IsActiveFlag_OVR
  1682.   * @param  I2Cx I2C Instance.
  1683.   * @retval State of bit (1 or 0).
  1684.   */
  1685. __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
  1686. {
  1687.   return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL);
  1688. }
  1689.  
  1690. /**
  1691.   * @brief  Indicate the status of SMBus PEC error flag in reception.
  1692.   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
  1693.   *         SMBus feature is supported by the I2Cx Instance.
  1694.   * @note   RESET: Clear default value.
  1695.   *         SET: When the received PEC does not match with the PEC register content.
  1696.   * @rmtoll ISR          PECERR        LL_I2C_IsActiveSMBusFlag_PECERR
  1697.   * @param  I2Cx I2C Instance.
  1698.   * @retval State of bit (1 or 0).
  1699.   */
  1700. __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
  1701. {
  1702.   return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL);
  1703. }
  1704.  
  1705. /**
  1706.   * @brief  Indicate the status of SMBus Timeout detection flag.
  1707.   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
  1708.   *         SMBus feature is supported by the I2Cx Instance.
  1709.   * @note   RESET: Clear default value.
  1710.   *         SET: When a timeout or extended clock timeout occurs.
  1711.   * @rmtoll ISR          TIMEOUT       LL_I2C_IsActiveSMBusFlag_TIMEOUT
  1712.   * @param  I2Cx I2C Instance.
  1713.   * @retval State of bit (1 or 0).
  1714.   */
  1715. __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
  1716. {
  1717.   return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL);
  1718. }
  1719.  
  1720. /**
  1721.   * @brief  Indicate the status of SMBus alert flag.
  1722.   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
  1723.   *         SMBus feature is supported by the I2Cx Instance.
  1724.   * @note   RESET: Clear default value.
  1725.   *         SET: When SMBus host configuration, SMBus alert enabled and
  1726.   *              a falling edge event occurs on SMBA pin.
  1727.   * @rmtoll ISR          ALERT         LL_I2C_IsActiveSMBusFlag_ALERT
  1728.   * @param  I2Cx I2C Instance.
  1729.   * @retval State of bit (1 or 0).
  1730.   */
  1731. __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
  1732. {
  1733.   return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL);
  1734. }
  1735.  
  1736. /**
  1737.   * @brief  Indicate the status of Bus Busy flag.
  1738.   * @note   RESET: Clear default value.
  1739.   *         SET: When a Start condition is detected.
  1740.   * @rmtoll ISR          BUSY          LL_I2C_IsActiveFlag_BUSY
  1741.   * @param  I2Cx I2C Instance.
  1742.   * @retval State of bit (1 or 0).
  1743.   */
  1744. __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
  1745. {
  1746.   return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL);
  1747. }
  1748.  
  1749. /**
  1750.   * @brief  Clear Address Matched flag.
  1751.   * @rmtoll ICR          ADDRCF        LL_I2C_ClearFlag_ADDR
  1752.   * @param  I2Cx I2C Instance.
  1753.   * @retval None
  1754.   */
  1755. __STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
  1756. {
  1757.   SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
  1758. }
  1759.  
  1760. /**
  1761.   * @brief  Clear Not Acknowledge flag.
  1762.   * @rmtoll ICR          NACKCF        LL_I2C_ClearFlag_NACK
  1763.   * @param  I2Cx I2C Instance.
  1764.   * @retval None
  1765.   */
  1766. __STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
  1767. {
  1768.   SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
  1769. }
  1770.  
  1771. /**
  1772.   * @brief  Clear Stop detection flag.
  1773.   * @rmtoll ICR          STOPCF        LL_I2C_ClearFlag_STOP
  1774.   * @param  I2Cx I2C Instance.
  1775.   * @retval None
  1776.   */
  1777. __STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
  1778. {
  1779.   SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
  1780. }
  1781.  
  1782. /**
  1783.   * @brief  Clear Transmit data register empty flag (TXE).
  1784.   * @note   This bit can be clear by software in order to flush the transmit data register (TXDR).
  1785.   * @rmtoll ISR          TXE           LL_I2C_ClearFlag_TXE
  1786.   * @param  I2Cx I2C Instance.
  1787.   * @retval None
  1788.   */
  1789. __STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
  1790. {
  1791.   WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
  1792. }
  1793.  
  1794. /**
  1795.   * @brief  Clear Bus error flag.
  1796.   * @rmtoll ICR          BERRCF        LL_I2C_ClearFlag_BERR
  1797.   * @param  I2Cx I2C Instance.
  1798.   * @retval None
  1799.   */
  1800. __STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
  1801. {
  1802.   SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
  1803. }
  1804.  
  1805. /**
  1806.   * @brief  Clear Arbitration lost flag.
  1807.   * @rmtoll ICR          ARLOCF        LL_I2C_ClearFlag_ARLO
  1808.   * @param  I2Cx I2C Instance.
  1809.   * @retval None
  1810.   */
  1811. __STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
  1812. {
  1813.   SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
  1814. }
  1815.  
  1816. /**
  1817.   * @brief  Clear Overrun/Underrun flag.
  1818.   * @rmtoll ICR          OVRCF         LL_I2C_ClearFlag_OVR
  1819.   * @param  I2Cx I2C Instance.
  1820.   * @retval None
  1821.   */
  1822. __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
  1823. {
  1824.   SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
  1825. }
  1826.  
  1827. /**
  1828.   * @brief  Clear SMBus PEC error flag.
  1829.   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
  1830.   *         SMBus feature is supported by the I2Cx Instance.
  1831.   * @rmtoll ICR          PECCF         LL_I2C_ClearSMBusFlag_PECERR
  1832.   * @param  I2Cx I2C Instance.
  1833.   * @retval None
  1834.   */
  1835. __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
  1836. {
  1837.   SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
  1838. }
  1839.  
  1840. /**
  1841.   * @brief  Clear SMBus Timeout detection flag.
  1842.   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
  1843.   *         SMBus feature is supported by the I2Cx Instance.
  1844.   * @rmtoll ICR          TIMOUTCF      LL_I2C_ClearSMBusFlag_TIMEOUT
  1845.   * @param  I2Cx I2C Instance.
  1846.   * @retval None
  1847.   */
  1848. __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
  1849. {
  1850.   SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
  1851. }
  1852.  
  1853. /**
  1854.   * @brief  Clear SMBus Alert flag.
  1855.   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
  1856.   *         SMBus feature is supported by the I2Cx Instance.
  1857.   * @rmtoll ICR          ALERTCF       LL_I2C_ClearSMBusFlag_ALERT
  1858.   * @param  I2Cx I2C Instance.
  1859.   * @retval None
  1860.   */
  1861. __STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
  1862. {
  1863.   SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
  1864. }
  1865.  
  1866. /**
  1867.   * @}
  1868.   */
  1869.  
  1870. /** @defgroup I2C_LL_EF_Data_Management Data_Management
  1871.   * @{
  1872.   */
  1873.  
  1874. /**
  1875.   * @brief  Enable automatic STOP condition generation (master mode).
  1876.   * @note   Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
  1877.   *         This bit has no effect in slave mode or when RELOAD bit is set.
  1878.   * @rmtoll CR2          AUTOEND       LL_I2C_EnableAutoEndMode
  1879.   * @param  I2Cx I2C Instance.
  1880.   * @retval None
  1881.   */
  1882. __STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
  1883. {
  1884.   SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
  1885. }
  1886.  
  1887. /**
  1888.   * @brief  Disable automatic STOP condition generation (master mode).
  1889.   * @note   Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
  1890.   * @rmtoll CR2          AUTOEND       LL_I2C_DisableAutoEndMode
  1891.   * @param  I2Cx I2C Instance.
  1892.   * @retval None
  1893.   */
  1894. __STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
  1895. {
  1896.   CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
  1897. }
  1898.  
  1899. /**
  1900.   * @brief  Check if automatic STOP condition is enabled or disabled.
  1901.   * @rmtoll CR2          AUTOEND       LL_I2C_IsEnabledAutoEndMode
  1902.   * @param  I2Cx I2C Instance.
  1903.   * @retval State of bit (1 or 0).
  1904.   */
  1905. __STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
  1906. {
  1907.   return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL);
  1908. }
  1909.  
  1910. /**
  1911.   * @brief  Enable reload mode (master mode).
  1912.   * @note   The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
  1913.   * @rmtoll CR2          RELOAD       LL_I2C_EnableReloadMode
  1914.   * @param  I2Cx I2C Instance.
  1915.   * @retval None
  1916.   */
  1917. __STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
  1918. {
  1919.   SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
  1920. }
  1921.  
  1922. /**
  1923.   * @brief  Disable reload mode (master mode).
  1924.   * @note   The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
  1925.   * @rmtoll CR2          RELOAD       LL_I2C_DisableReloadMode
  1926.   * @param  I2Cx I2C Instance.
  1927.   * @retval None
  1928.   */
  1929. __STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
  1930. {
  1931.   CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
  1932. }
  1933.  
  1934. /**
  1935.   * @brief  Check if reload mode is enabled or disabled.
  1936.   * @rmtoll CR2          RELOAD       LL_I2C_IsEnabledReloadMode
  1937.   * @param  I2Cx I2C Instance.
  1938.   * @retval State of bit (1 or 0).
  1939.   */
  1940. __STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
  1941. {
  1942.   return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL);
  1943. }
  1944.  
  1945. /**
  1946.   * @brief  Configure the number of bytes for transfer.
  1947.   * @note   Changing these bits when START bit is set is not allowed.
  1948.   * @rmtoll CR2          NBYTES           LL_I2C_SetTransferSize
  1949.   * @param  I2Cx I2C Instance.
  1950.   * @param  TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
  1951.   * @retval None
  1952.   */
  1953. __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
  1954. {
  1955.   MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);
  1956. }
  1957.  
  1958. /**
  1959.   * @brief  Get the number of bytes configured for transfer.
  1960.   * @rmtoll CR2          NBYTES           LL_I2C_GetTransferSize
  1961.   * @param  I2Cx I2C Instance.
  1962.   * @retval Value between Min_Data=0x0 and Max_Data=0xFF
  1963.   */
  1964. __STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
  1965. {
  1966.   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
  1967. }
  1968.  
  1969. /**
  1970.   * @brief  Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code
  1971.             or next received byte.
  1972.   * @note   Usage in Slave mode only.
  1973.   * @rmtoll CR2          NACK          LL_I2C_AcknowledgeNextData
  1974.   * @param  I2Cx I2C Instance.
  1975.   * @param  TypeAcknowledge This parameter can be one of the following values:
  1976.   *         @arg @ref LL_I2C_ACK
  1977.   *         @arg @ref LL_I2C_NACK
  1978.   * @retval None
  1979.   */
  1980. __STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
  1981. {
  1982.   MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
  1983. }
  1984.  
  1985. /**
  1986.   * @brief  Generate a START or RESTART condition
  1987.   * @note   The START bit can be set even if bus is BUSY or I2C is in slave mode.
  1988.   *         This action has no effect when RELOAD is set.
  1989.   * @rmtoll CR2          START           LL_I2C_GenerateStartCondition
  1990.   * @param  I2Cx I2C Instance.
  1991.   * @retval None
  1992.   */
  1993. __STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
  1994. {
  1995.   SET_BIT(I2Cx->CR2, I2C_CR2_START);
  1996. }
  1997.  
  1998. /**
  1999.   * @brief  Generate a STOP condition after the current byte transfer (master mode).
  2000.   * @rmtoll CR2          STOP          LL_I2C_GenerateStopCondition
  2001.   * @param  I2Cx I2C Instance.
  2002.   * @retval None
  2003.   */
  2004. __STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
  2005. {
  2006.   SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
  2007. }
  2008.  
  2009. /**
  2010.   * @brief  Enable automatic RESTART Read request condition for 10bit address header (master mode).
  2011.   * @note   The master sends the complete 10bit slave address read sequence :
  2012.   *         Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address
  2013.             in Read direction.
  2014.   * @rmtoll CR2          HEAD10R       LL_I2C_EnableAuto10BitRead
  2015.   * @param  I2Cx I2C Instance.
  2016.   * @retval None
  2017.   */
  2018. __STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
  2019. {
  2020.   CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
  2021. }
  2022.  
  2023. /**
  2024.   * @brief  Disable automatic RESTART Read request condition for 10bit address header (master mode).
  2025.   * @note   The master only sends the first 7 bits of 10bit address in Read direction.
  2026.   * @rmtoll CR2          HEAD10R       LL_I2C_DisableAuto10BitRead
  2027.   * @param  I2Cx I2C Instance.
  2028.   * @retval None
  2029.   */
  2030. __STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
  2031. {
  2032.   SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
  2033. }
  2034.  
  2035. /**
  2036.   * @brief  Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
  2037.   * @rmtoll CR2          HEAD10R       LL_I2C_IsEnabledAuto10BitRead
  2038.   * @param  I2Cx I2C Instance.
  2039.   * @retval State of bit (1 or 0).
  2040.   */
  2041. __STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
  2042. {
  2043.   return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL);
  2044. }
  2045.  
  2046. /**
  2047.   * @brief  Configure the transfer direction (master mode).
  2048.   * @note   Changing these bits when START bit is set is not allowed.
  2049.   * @rmtoll CR2          RD_WRN           LL_I2C_SetTransferRequest
  2050.   * @param  I2Cx I2C Instance.
  2051.   * @param  TransferRequest This parameter can be one of the following values:
  2052.   *         @arg @ref LL_I2C_REQUEST_WRITE
  2053.   *         @arg @ref LL_I2C_REQUEST_READ
  2054.   * @retval None
  2055.   */
  2056. __STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
  2057. {
  2058.   MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
  2059. }
  2060.  
  2061. /**
  2062.   * @brief  Get the transfer direction requested (master mode).
  2063.   * @rmtoll CR2          RD_WRN           LL_I2C_GetTransferRequest
  2064.   * @param  I2Cx I2C Instance.
  2065.   * @retval Returned value can be one of the following values:
  2066.   *         @arg @ref LL_I2C_REQUEST_WRITE
  2067.   *         @arg @ref LL_I2C_REQUEST_READ
  2068.   */
  2069. __STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
  2070. {
  2071.   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
  2072. }
  2073.  
  2074. /**
  2075.   * @brief  Configure the slave address for transfer (master mode).
  2076.   * @note   Changing these bits when START bit is set is not allowed.
  2077.   * @rmtoll CR2          SADD           LL_I2C_SetSlaveAddr
  2078.   * @param  I2Cx I2C Instance.
  2079.   * @param  SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
  2080.   * @retval None
  2081.   */
  2082. __STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
  2083. {
  2084.   MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
  2085. }
  2086.  
  2087. /**
  2088.   * @brief  Get the slave address programmed for transfer.
  2089.   * @rmtoll CR2          SADD           LL_I2C_GetSlaveAddr
  2090.   * @param  I2Cx I2C Instance.
  2091.   * @retval Value between Min_Data=0x0 and Max_Data=0x3F
  2092.   */
  2093. __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
  2094. {
  2095.   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
  2096. }
  2097.  
  2098. /**
  2099.   * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
  2100.   * @rmtoll CR2          SADD          LL_I2C_HandleTransfer\n
  2101.   *         CR2          ADD10         LL_I2C_HandleTransfer\n
  2102.   *         CR2          RD_WRN        LL_I2C_HandleTransfer\n
  2103.   *         CR2          START         LL_I2C_HandleTransfer\n
  2104.   *         CR2          STOP          LL_I2C_HandleTransfer\n
  2105.   *         CR2          RELOAD        LL_I2C_HandleTransfer\n
  2106.   *         CR2          NBYTES        LL_I2C_HandleTransfer\n
  2107.   *         CR2          AUTOEND       LL_I2C_HandleTransfer\n
  2108.   *         CR2          HEAD10R       LL_I2C_HandleTransfer
  2109.   * @param  I2Cx I2C Instance.
  2110.   * @param  SlaveAddr Specifies the slave address to be programmed.
  2111.   * @param  SlaveAddrSize This parameter can be one of the following values:
  2112.   *         @arg @ref LL_I2C_ADDRSLAVE_7BIT
  2113.   *         @arg @ref LL_I2C_ADDRSLAVE_10BIT
  2114.   * @param  TransferSize Specifies the number of bytes to be programmed.
  2115.   *                       This parameter must be a value between Min_Data=0 and Max_Data=255.
  2116.   * @param  EndMode This parameter can be one of the following values:
  2117.   *         @arg @ref LL_I2C_MODE_RELOAD
  2118.   *         @arg @ref LL_I2C_MODE_AUTOEND
  2119.   *         @arg @ref LL_I2C_MODE_SOFTEND
  2120.   *         @arg @ref LL_I2C_MODE_SMBUS_RELOAD
  2121.   *         @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
  2122.   *         @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
  2123.   *         @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
  2124.   *         @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
  2125.   * @param  Request This parameter can be one of the following values:
  2126.   *         @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
  2127.   *         @arg @ref LL_I2C_GENERATE_STOP
  2128.   *         @arg @ref LL_I2C_GENERATE_START_READ
  2129.   *         @arg @ref LL_I2C_GENERATE_START_WRITE
  2130.   *         @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
  2131.   *         @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
  2132.   *         @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
  2133.   *         @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
  2134.   * @retval None
  2135.   */
  2136. __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
  2137.                                            uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
  2138. {
  2139.   MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 |
  2140.              (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) |
  2141.              I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
  2142.              I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
  2143.              SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request);
  2144. }
  2145.  
  2146. /**
  2147.   * @brief  Indicate the value of transfer direction (slave mode).
  2148.   * @note   RESET: Write transfer, Slave enters in receiver mode.
  2149.   *         SET: Read transfer, Slave enters in transmitter mode.
  2150.   * @rmtoll ISR          DIR           LL_I2C_GetTransferDirection
  2151.   * @param  I2Cx I2C Instance.
  2152.   * @retval Returned value can be one of the following values:
  2153.   *         @arg @ref LL_I2C_DIRECTION_WRITE
  2154.   *         @arg @ref LL_I2C_DIRECTION_READ
  2155.   */
  2156. __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
  2157. {
  2158.   return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
  2159. }
  2160.  
  2161. /**
  2162.   * @brief  Return the slave matched address.
  2163.   * @rmtoll ISR          ADDCODE       LL_I2C_GetAddressMatchCode
  2164.   * @param  I2Cx I2C Instance.
  2165.   * @retval Value between Min_Data=0x00 and Max_Data=0x3F
  2166.   */
  2167. __STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
  2168. {
  2169.   return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
  2170. }
  2171.  
  2172. /**
  2173.   * @brief  Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
  2174.   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
  2175.   *         SMBus feature is supported by the I2Cx Instance.
  2176.   * @note   This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition
  2177.             or an Address Matched is received.
  2178.   *         This bit has no effect when RELOAD bit is set.
  2179.   *         This bit has no effect in device mode when SBC bit is not set.
  2180.   * @rmtoll CR2          PECBYTE       LL_I2C_EnableSMBusPECCompare
  2181.   * @param  I2Cx I2C Instance.
  2182.   * @retval None
  2183.   */
  2184. __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
  2185. {
  2186.   SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
  2187. }
  2188.  
  2189. /**
  2190.   * @brief  Check if the SMBus Packet Error byte internal comparison is requested or not.
  2191.   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
  2192.   *         SMBus feature is supported by the I2Cx Instance.
  2193.   * @rmtoll CR2          PECBYTE       LL_I2C_IsEnabledSMBusPECCompare
  2194.   * @param  I2Cx I2C Instance.
  2195.   * @retval State of bit (1 or 0).
  2196.   */
  2197. __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
  2198. {
  2199.   return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL);
  2200. }
  2201.  
  2202. /**
  2203.   * @brief  Get the SMBus Packet Error byte calculated.
  2204.   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
  2205.   *         SMBus feature is supported by the I2Cx Instance.
  2206.   * @rmtoll PECR         PEC           LL_I2C_GetSMBusPEC
  2207.   * @param  I2Cx I2C Instance.
  2208.   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
  2209.   */
  2210. __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
  2211. {
  2212.   return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
  2213. }
  2214.  
  2215. /**
  2216.   * @brief  Read Receive Data register.
  2217.   * @rmtoll RXDR         RXDATA        LL_I2C_ReceiveData8
  2218.   * @param  I2Cx I2C Instance.
  2219.   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
  2220.   */
  2221. __STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
  2222. {
  2223.   return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
  2224. }
  2225.  
  2226. /**
  2227.   * @brief  Write in Transmit Data Register .
  2228.   * @rmtoll TXDR         TXDATA        LL_I2C_TransmitData8
  2229.   * @param  I2Cx I2C Instance.
  2230.   * @param  Data Value between Min_Data=0x00 and Max_Data=0xFF
  2231.   * @retval None
  2232.   */
  2233. __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
  2234. {
  2235.   WRITE_REG(I2Cx->TXDR, Data);
  2236. }
  2237.  
  2238. /**
  2239.   * @}
  2240.   */
  2241.  
  2242. #if defined(USE_FULL_LL_DRIVER)
  2243. /** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
  2244.   * @{
  2245.   */
  2246.  
  2247. ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
  2248. ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx);
  2249. void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
  2250.  
  2251.  
  2252. /**
  2253.   * @}
  2254.   */
  2255. #endif /* USE_FULL_LL_DRIVER */
  2256.  
  2257. /**
  2258.   * @}
  2259.   */
  2260.  
  2261. /**
  2262.   * @}
  2263.   */
  2264.  
  2265. #endif /* I2C1 || I2C2 */
  2266.  
  2267. /**
  2268.   * @}
  2269.   */
  2270.  
  2271. #ifdef __cplusplus
  2272. }
  2273. #endif
  2274.  
  2275. #endif /* STM32F0xx_LL_I2C_H */
  2276.  
  2277. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  2278.