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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f0xx_ll_crs.h
  4.   * @author  MCD Application Team
  5.   * @brief   Header file of CRS LL module.
  6.   ******************************************************************************
  7.   * @attention
  8.   *
  9.   * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
  10.   * All rights reserved.</center></h2>
  11.   *
  12.   * This software component is licensed by ST under BSD 3-Clause license,
  13.   * the "License"; You may not use this file except in compliance with the
  14.   * License. You may obtain a copy of the License at:
  15.   *                        opensource.org/licenses/BSD-3-Clause
  16.   *
  17.   ******************************************************************************
  18.   */
  19.  
  20. /* Define to prevent recursive inclusion -------------------------------------*/
  21. #ifndef __STM32F0xx_LL_CRS_H
  22. #define __STM32F0xx_LL_CRS_H
  23.  
  24. #ifdef __cplusplus
  25. extern "C" {
  26. #endif
  27.  
  28. /* Includes ------------------------------------------------------------------*/
  29. #include "stm32f0xx.h"
  30.  
  31. /** @addtogroup STM32F0xx_LL_Driver
  32.   * @{
  33.   */
  34.  
  35. #if defined(CRS)
  36.  
  37. /** @defgroup CRS_LL CRS
  38.   * @{
  39.   */
  40.  
  41. /* Private types -------------------------------------------------------------*/
  42. /* Private variables ---------------------------------------------------------*/
  43. /* Private constants ---------------------------------------------------------*/
  44. /* Private macros ------------------------------------------------------------*/
  45.  
  46. /* Exported types ------------------------------------------------------------*/
  47. /* Exported constants --------------------------------------------------------*/
  48. /** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
  49.   * @{
  50.   */
  51.  
  52. /** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
  53.   * @brief    Flags defines which can be used with LL_CRS_ReadReg function
  54.   * @{
  55.   */
  56. #define LL_CRS_ISR_SYNCOKF                 CRS_ISR_SYNCOKF
  57. #define LL_CRS_ISR_SYNCWARNF               CRS_ISR_SYNCWARNF
  58. #define LL_CRS_ISR_ERRF                    CRS_ISR_ERRF
  59. #define LL_CRS_ISR_ESYNCF                  CRS_ISR_ESYNCF
  60. #define LL_CRS_ISR_SYNCERR                 CRS_ISR_SYNCERR
  61. #define LL_CRS_ISR_SYNCMISS                CRS_ISR_SYNCMISS
  62. #define LL_CRS_ISR_TRIMOVF                 CRS_ISR_TRIMOVF
  63. /**
  64.   * @}
  65.   */
  66.  
  67. /** @defgroup CRS_LL_EC_IT IT Defines
  68.   * @brief    IT defines which can be used with LL_CRS_ReadReg and  LL_CRS_WriteReg functions
  69.   * @{
  70.   */
  71. #define LL_CRS_CR_SYNCOKIE                 CRS_CR_SYNCOKIE
  72. #define LL_CRS_CR_SYNCWARNIE               CRS_CR_SYNCWARNIE
  73. #define LL_CRS_CR_ERRIE                    CRS_CR_ERRIE
  74. #define LL_CRS_CR_ESYNCIE                  CRS_CR_ESYNCIE
  75. /**
  76.   * @}
  77.   */
  78.  
  79. /** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
  80.   * @{
  81.   */
  82. #define LL_CRS_SYNC_DIV_1                  ((uint32_t)0x00U)                         /*!< Synchro Signal not divided (default) */
  83. #define LL_CRS_SYNC_DIV_2                  CRS_CFGR_SYNCDIV_0                        /*!< Synchro Signal divided by 2 */
  84. #define LL_CRS_SYNC_DIV_4                  CRS_CFGR_SYNCDIV_1                        /*!< Synchro Signal divided by 4 */
  85. #define LL_CRS_SYNC_DIV_8                  (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
  86. #define LL_CRS_SYNC_DIV_16                 CRS_CFGR_SYNCDIV_2                        /*!< Synchro Signal divided by 16 */
  87. #define LL_CRS_SYNC_DIV_32                 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
  88. #define LL_CRS_SYNC_DIV_64                 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
  89. #define LL_CRS_SYNC_DIV_128                CRS_CFGR_SYNCDIV                          /*!< Synchro Signal divided by 128 */
  90. /**
  91.   * @}
  92.   */
  93.  
  94. /** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
  95.   * @{
  96.   */
  97. #define LL_CRS_SYNC_SOURCE_GPIO            ((uint32_t)0x00U)       /*!< Synchro Signal soucre GPIO */
  98. #define LL_CRS_SYNC_SOURCE_LSE             CRS_CFGR_SYNCSRC_0      /*!< Synchro Signal source LSE */
  99. #define LL_CRS_SYNC_SOURCE_USB             CRS_CFGR_SYNCSRC_1      /*!< Synchro Signal source USB SOF (default)*/
  100. /**
  101.   * @}
  102.   */
  103.  
  104. /** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
  105.   * @{
  106.   */
  107. #define LL_CRS_SYNC_POLARITY_RISING        ((uint32_t)0x00U)     /*!< Synchro Active on rising edge (default) */
  108. #define LL_CRS_SYNC_POLARITY_FALLING       CRS_CFGR_SYNCPOL      /*!< Synchro Active on falling edge */
  109. /**
  110.   * @}
  111.   */
  112.  
  113. /** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
  114.   * @{
  115.   */
  116. #define LL_CRS_FREQ_ERROR_DIR_UP             ((uint32_t)0x00U)         /*!< Upcounting direction, the actual frequency is above the target */
  117. #define LL_CRS_FREQ_ERROR_DIR_DOWN           ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
  118. /**
  119.   * @}
  120.   */
  121.  
  122. /** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
  123.   * @{
  124.   */
  125. /**
  126.   * @brief Reset value of the RELOAD field
  127.   * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
  128.   *       and a synchronization signal frequency of 1 kHz (SOF signal from USB)
  129.   */
  130. #define LL_CRS_RELOADVALUE_DEFAULT         ((uint32_t)0xBB7FU)      
  131.  
  132. /**
  133.   * @brief Reset value of Frequency error limit.
  134.   */
  135. #define LL_CRS_ERRORLIMIT_DEFAULT          ((uint32_t)0x22U)      
  136.  
  137. /**
  138.   * @brief Reset value of the HSI48 Calibration field
  139.   * @note The default value is 32, which corresponds to the middle of the trimming interval.
  140.   *       The trimming step is around 67 kHz between two consecutive TRIM steps.
  141.   *       A higher TRIM value corresponds to a higher output frequency
  142.   */
  143. #define LL_CRS_HSI48CALIBRATION_DEFAULT    ((uint32_t)0x20U)      
  144. /**
  145.   * @}
  146.   */
  147.  
  148. /**
  149.   * @}
  150.   */
  151.  
  152. /* Exported macro ------------------------------------------------------------*/
  153. /** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
  154.   * @{
  155.   */
  156.  
  157. /** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
  158.   * @{
  159.   */
  160.  
  161. /**
  162.   * @brief  Write a value in CRS register
  163.   * @param  __INSTANCE__ CRS Instance
  164.   * @param  __REG__ Register to be written
  165.   * @param  __VALUE__ Value to be written in the register
  166.   * @retval None
  167.   */
  168. #define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
  169.  
  170. /**
  171.   * @brief  Read a value in CRS register
  172.   * @param  __INSTANCE__ CRS Instance
  173.   * @param  __REG__ Register to be read
  174.   * @retval Register value
  175.   */
  176. #define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
  177. /**
  178.   * @}
  179.   */
  180.  
  181. /** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
  182.   * @{
  183.   */
  184.  
  185. /**
  186.   * @brief  Macro to calculate reload value to be set in CRS register according to target and sync frequencies
  187.   * @note   The RELOAD value should be selected according to the ratio between
  188.   *         the target frequency and the frequency of the synchronization source after
  189.   *         prescaling. It is then decreased by one in order to reach the expected
  190.   *         synchronization on the zero value. The formula is the following:
  191.   *              RELOAD = (fTARGET / fSYNC) -1
  192.   * @param  __FTARGET__ Target frequency (value in Hz)
  193.   * @param  __FSYNC__ Synchronization signal frequency (value in Hz)
  194.   * @retval Reload value (in Hz)
  195.   */
  196. #define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
  197.  
  198. /**
  199.   * @}
  200.   */
  201.  
  202. /**
  203.   * @}
  204.   */
  205.  
  206. /* Exported functions --------------------------------------------------------*/
  207. /** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
  208.   * @{
  209.   */
  210.  
  211. /** @defgroup CRS_LL_EF_Configuration Configuration
  212.   * @{
  213.   */
  214.  
  215. /**
  216.   * @brief  Enable Frequency error counter
  217.   * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
  218.   * @rmtoll CR           CEN           LL_CRS_EnableFreqErrorCounter
  219.   * @retval None
  220.   */
  221. __STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
  222. {
  223.   SET_BIT(CRS->CR, CRS_CR_CEN);
  224. }
  225.  
  226. /**
  227.   * @brief  Disable Frequency error counter
  228.   * @rmtoll CR           CEN           LL_CRS_DisableFreqErrorCounter
  229.   * @retval None
  230.   */
  231. __STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
  232. {
  233.   CLEAR_BIT(CRS->CR, CRS_CR_CEN);
  234. }
  235.  
  236. /**
  237.   * @brief  Check if Frequency error counter is enabled or not
  238.   * @rmtoll CR           CEN           LL_CRS_IsEnabledFreqErrorCounter
  239.   * @retval State of bit (1 or 0).
  240.   */
  241. __STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
  242. {
  243.   return (READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN));
  244. }
  245.  
  246. /**
  247.   * @brief  Enable Automatic trimming counter
  248.   * @rmtoll CR           AUTOTRIMEN    LL_CRS_EnableAutoTrimming
  249.   * @retval None
  250.   */
  251. __STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
  252. {
  253.   SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
  254. }
  255.  
  256. /**
  257.   * @brief  Disable Automatic trimming counter
  258.   * @rmtoll CR           AUTOTRIMEN    LL_CRS_DisableAutoTrimming
  259.   * @retval None
  260.   */
  261. __STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
  262. {
  263.   CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
  264. }
  265.  
  266. /**
  267.   * @brief  Check if Automatic trimming is enabled or not
  268.   * @rmtoll CR           AUTOTRIMEN    LL_CRS_IsEnabledAutoTrimming
  269.   * @retval State of bit (1 or 0).
  270.   */
  271. __STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
  272. {
  273.   return (READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN));
  274. }
  275.  
  276. /**
  277.   * @brief  Set HSI48 oscillator smooth trimming
  278.   * @note   When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
  279.   * @rmtoll CR           TRIM          LL_CRS_SetHSI48SmoothTrimming
  280.   * @param  Value a number between Min_Data = 0 and Max_Data = 63
  281.   * @note   Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
  282.   * @retval None
  283.   */
  284. __STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
  285. {
  286.   MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos);
  287. }
  288.  
  289. /**
  290.   * @brief  Get HSI48 oscillator smooth trimming
  291.   * @rmtoll CR           TRIM          LL_CRS_GetHSI48SmoothTrimming
  292.   * @retval a number between Min_Data = 0 and Max_Data = 63
  293.   */
  294. __STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
  295. {
  296.   return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
  297. }
  298.  
  299. /**
  300.   * @brief  Set counter reload value
  301.   * @rmtoll CFGR         RELOAD        LL_CRS_SetReloadCounter
  302.   * @param  Value a number between Min_Data = 0 and Max_Data = 0xFFFF
  303.   * @note   Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
  304.   *         Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
  305.   * @retval None
  306.   */
  307. __STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
  308. {
  309.   MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
  310. }
  311.  
  312. /**
  313.   * @brief  Get counter reload value
  314.   * @rmtoll CFGR         RELOAD        LL_CRS_GetReloadCounter
  315.   * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
  316.   */
  317. __STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
  318. {
  319.   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
  320. }
  321.  
  322. /**
  323.   * @brief  Set frequency error limit
  324.   * @rmtoll CFGR         FELIM         LL_CRS_SetFreqErrorLimit
  325.   * @param  Value a number between Min_Data = 0 and Max_Data = 255
  326.   * @note   Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
  327.   * @retval None
  328.   */
  329. __STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
  330. {
  331.   MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos);
  332. }
  333.  
  334. /**
  335.   * @brief  Get frequency error limit
  336.   * @rmtoll CFGR         FELIM         LL_CRS_GetFreqErrorLimit
  337.   * @retval A number between Min_Data = 0 and Max_Data = 255
  338.   */
  339. __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
  340. {
  341.   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos);
  342. }
  343.  
  344. /**
  345.   * @brief  Set division factor for SYNC signal
  346.   * @rmtoll CFGR         SYNCDIV       LL_CRS_SetSyncDivider
  347.   * @param  Divider This parameter can be one of the following values:
  348.   *         @arg @ref LL_CRS_SYNC_DIV_1
  349.   *         @arg @ref LL_CRS_SYNC_DIV_2
  350.   *         @arg @ref LL_CRS_SYNC_DIV_4
  351.   *         @arg @ref LL_CRS_SYNC_DIV_8
  352.   *         @arg @ref LL_CRS_SYNC_DIV_16
  353.   *         @arg @ref LL_CRS_SYNC_DIV_32
  354.   *         @arg @ref LL_CRS_SYNC_DIV_64
  355.   *         @arg @ref LL_CRS_SYNC_DIV_128
  356.   * @retval None
  357.   */
  358. __STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
  359. {
  360.   MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
  361. }
  362.  
  363. /**
  364.   * @brief  Get division factor for SYNC signal
  365.   * @rmtoll CFGR         SYNCDIV       LL_CRS_GetSyncDivider
  366.   * @retval Returned value can be one of the following values:
  367.   *         @arg @ref LL_CRS_SYNC_DIV_1
  368.   *         @arg @ref LL_CRS_SYNC_DIV_2
  369.   *         @arg @ref LL_CRS_SYNC_DIV_4
  370.   *         @arg @ref LL_CRS_SYNC_DIV_8
  371.   *         @arg @ref LL_CRS_SYNC_DIV_16
  372.   *         @arg @ref LL_CRS_SYNC_DIV_32
  373.   *         @arg @ref LL_CRS_SYNC_DIV_64
  374.   *         @arg @ref LL_CRS_SYNC_DIV_128
  375.   */
  376. __STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
  377. {
  378.   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
  379. }
  380.  
  381. /**
  382.   * @brief  Set SYNC signal source
  383.   * @rmtoll CFGR         SYNCSRC       LL_CRS_SetSyncSignalSource
  384.   * @param  Source This parameter can be one of the following values:
  385.   *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO
  386.   *         @arg @ref LL_CRS_SYNC_SOURCE_LSE
  387.   *         @arg @ref LL_CRS_SYNC_SOURCE_USB
  388.   * @retval None
  389.   */
  390. __STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
  391. {
  392.   MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
  393. }
  394.  
  395. /**
  396.   * @brief  Get SYNC signal source
  397.   * @rmtoll CFGR         SYNCSRC       LL_CRS_GetSyncSignalSource
  398.   * @retval Returned value can be one of the following values:
  399.   *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO
  400.   *         @arg @ref LL_CRS_SYNC_SOURCE_LSE
  401.   *         @arg @ref LL_CRS_SYNC_SOURCE_USB
  402.   */
  403. __STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
  404. {
  405.   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
  406. }
  407.  
  408. /**
  409.   * @brief  Set input polarity for the SYNC signal source
  410.   * @rmtoll CFGR         SYNCPOL       LL_CRS_SetSyncPolarity
  411.   * @param  Polarity This parameter can be one of the following values:
  412.   *         @arg @ref LL_CRS_SYNC_POLARITY_RISING
  413.   *         @arg @ref LL_CRS_SYNC_POLARITY_FALLING
  414.   * @retval None
  415.   */
  416. __STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
  417. {
  418.   MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
  419. }
  420.  
  421. /**
  422.   * @brief  Get input polarity for the SYNC signal source
  423.   * @rmtoll CFGR         SYNCPOL       LL_CRS_GetSyncPolarity
  424.   * @retval Returned value can be one of the following values:
  425.   *         @arg @ref LL_CRS_SYNC_POLARITY_RISING
  426.   *         @arg @ref LL_CRS_SYNC_POLARITY_FALLING
  427.   */
  428. __STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
  429. {
  430.   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
  431. }
  432.  
  433. /**
  434.   * @brief  Configure CRS for the synchronization
  435.   * @rmtoll CR           TRIM          LL_CRS_ConfigSynchronization\n
  436.   *         CFGR         RELOAD        LL_CRS_ConfigSynchronization\n
  437.   *         CFGR         FELIM         LL_CRS_ConfigSynchronization\n
  438.   *         CFGR         SYNCDIV       LL_CRS_ConfigSynchronization\n
  439.   *         CFGR         SYNCSRC       LL_CRS_ConfigSynchronization\n
  440.   *         CFGR         SYNCPOL       LL_CRS_ConfigSynchronization
  441.   * @param  HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
  442.   * @param  ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
  443.   * @param  ReloadValue a number between Min_Data = 0 and Max_Data = 255
  444.   * @param  Settings This parameter can be a combination of the following values:
  445.   *         @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
  446.   *              or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
  447.   *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
  448.   *         @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
  449.   * @retval None
  450.   */
  451. __STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
  452. {
  453.   MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue << CRS_CR_TRIM_Pos);
  454.   MODIFY_REG(CRS->CFGR,
  455.              CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
  456.              ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings);
  457. }
  458.  
  459. /**
  460.   * @}
  461.   */
  462.  
  463. /** @defgroup CRS_LL_EF_CRS_Management CRS_Management
  464.   * @{
  465.   */
  466.  
  467. /**
  468.   * @brief  Generate software SYNC event
  469.   * @rmtoll CR           SWSYNC        LL_CRS_GenerateEvent_SWSYNC
  470.   * @retval None
  471.   */
  472. __STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
  473. {
  474.   SET_BIT(CRS->CR, CRS_CR_SWSYNC);
  475. }
  476.  
  477. /**
  478.   * @brief  Get the frequency error direction latched in the time of the last
  479.   * SYNC event
  480.   * @rmtoll ISR          FEDIR         LL_CRS_GetFreqErrorDirection
  481.   * @retval Returned value can be one of the following values:
  482.   *         @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
  483.   *         @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
  484.   */
  485. __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
  486. {
  487.   return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
  488. }
  489.  
  490. /**
  491.   * @brief  Get the frequency error counter value latched in the time of the last SYNC event
  492.   * @rmtoll ISR          FECAP         LL_CRS_GetFreqErrorCapture
  493.   * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
  494.   */
  495. __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
  496. {
  497.   return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
  498. }
  499.  
  500. /**
  501.   * @}
  502.   */
  503.  
  504. /** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
  505.   * @{
  506.   */
  507.  
  508. /**
  509.   * @brief  Check if SYNC event OK signal occurred or not
  510.   * @rmtoll ISR          SYNCOKF       LL_CRS_IsActiveFlag_SYNCOK
  511.   * @retval State of bit (1 or 0).
  512.   */
  513. __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
  514. {
  515.   return (READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF));
  516. }
  517.  
  518. /**
  519.   * @brief  Check if SYNC warning signal occurred or not
  520.   * @rmtoll ISR          SYNCWARNF     LL_CRS_IsActiveFlag_SYNCWARN
  521.   * @retval State of bit (1 or 0).
  522.   */
  523. __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
  524. {
  525.   return (READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF));
  526. }
  527.  
  528. /**
  529.   * @brief  Check if Synchronization or trimming error signal occurred or not
  530.   * @rmtoll ISR          ERRF          LL_CRS_IsActiveFlag_ERR
  531.   * @retval State of bit (1 or 0).
  532.   */
  533. __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
  534. {
  535.   return (READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF));
  536. }
  537.  
  538. /**
  539.   * @brief  Check if Expected SYNC signal occurred or not
  540.   * @rmtoll ISR          ESYNCF        LL_CRS_IsActiveFlag_ESYNC
  541.   * @retval State of bit (1 or 0).
  542.   */
  543. __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
  544. {
  545.   return (READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF));
  546. }
  547.  
  548. /**
  549.   * @brief  Check if SYNC error signal occurred or not
  550.   * @rmtoll ISR          SYNCERR       LL_CRS_IsActiveFlag_SYNCERR
  551.   * @retval State of bit (1 or 0).
  552.   */
  553. __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
  554. {
  555.   return (READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR));
  556. }
  557.  
  558. /**
  559.   * @brief  Check if SYNC missed error signal occurred or not
  560.   * @rmtoll ISR          SYNCMISS      LL_CRS_IsActiveFlag_SYNCMISS
  561.   * @retval State of bit (1 or 0).
  562.   */
  563. __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
  564. {
  565.   return (READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS));
  566. }
  567.  
  568. /**
  569.   * @brief  Check if Trimming overflow or underflow occurred or not
  570.   * @rmtoll ISR          TRIMOVF       LL_CRS_IsActiveFlag_TRIMOVF
  571.   * @retval State of bit (1 or 0).
  572.   */
  573. __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
  574. {
  575.   return (READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF));
  576. }
  577.  
  578. /**
  579.   * @brief  Clear the SYNC event OK flag
  580.   * @rmtoll ICR          SYNCOKC       LL_CRS_ClearFlag_SYNCOK
  581.   * @retval None
  582.   */
  583. __STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
  584. {
  585.   WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
  586. }
  587.  
  588. /**
  589.   * @brief  Clear the  SYNC warning flag
  590.   * @rmtoll ICR          SYNCWARNC     LL_CRS_ClearFlag_SYNCWARN
  591.   * @retval None
  592.   */
  593. __STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
  594. {
  595.   WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
  596. }
  597.  
  598. /**
  599.   * @brief  Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
  600.   * the ERR flag
  601.   * @rmtoll ICR          ERRC          LL_CRS_ClearFlag_ERR
  602.   * @retval None
  603.   */
  604. __STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
  605. {
  606.   WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
  607. }
  608.  
  609. /**
  610.   * @brief  Clear Expected SYNC flag
  611.   * @rmtoll ICR          ESYNCC        LL_CRS_ClearFlag_ESYNC
  612.   * @retval None
  613.   */
  614. __STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
  615. {
  616.   WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
  617. }
  618.  
  619. /**
  620.   * @}
  621.   */
  622.  
  623. /** @defgroup CRS_LL_EF_IT_Management IT_Management
  624.   * @{
  625.   */
  626.  
  627. /**
  628.   * @brief  Enable SYNC event OK interrupt
  629.   * @rmtoll CR           SYNCOKIE      LL_CRS_EnableIT_SYNCOK
  630.   * @retval None
  631.   */
  632. __STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
  633. {
  634.   SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
  635. }
  636.  
  637. /**
  638.   * @brief  Disable SYNC event OK interrupt
  639.   * @rmtoll CR           SYNCOKIE      LL_CRS_DisableIT_SYNCOK
  640.   * @retval None
  641.   */
  642. __STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
  643. {
  644.   CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
  645. }
  646.  
  647. /**
  648.   * @brief  Check if SYNC event OK interrupt is enabled or not
  649.   * @rmtoll CR           SYNCOKIE      LL_CRS_IsEnabledIT_SYNCOK
  650.   * @retval State of bit (1 or 0).
  651.   */
  652. __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
  653. {
  654.   return (READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE));
  655. }
  656.  
  657. /**
  658.   * @brief  Enable SYNC warning interrupt
  659.   * @rmtoll CR           SYNCWARNIE    LL_CRS_EnableIT_SYNCWARN
  660.   * @retval None
  661.   */
  662. __STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
  663. {
  664.   SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
  665. }
  666.  
  667. /**
  668.   * @brief  Disable SYNC warning interrupt
  669.   * @rmtoll CR           SYNCWARNIE    LL_CRS_DisableIT_SYNCWARN
  670.   * @retval None
  671.   */
  672. __STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
  673. {
  674.   CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
  675. }
  676.  
  677. /**
  678.   * @brief  Check if SYNC warning interrupt is enabled or not
  679.   * @rmtoll CR           SYNCWARNIE    LL_CRS_IsEnabledIT_SYNCWARN
  680.   * @retval State of bit (1 or 0).
  681.   */
  682. __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
  683. {
  684.   return (READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE));
  685. }
  686.  
  687. /**
  688.   * @brief  Enable Synchronization or trimming error interrupt
  689.   * @rmtoll CR           ERRIE         LL_CRS_EnableIT_ERR
  690.   * @retval None
  691.   */
  692. __STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
  693. {
  694.   SET_BIT(CRS->CR, CRS_CR_ERRIE);
  695. }
  696.  
  697. /**
  698.   * @brief  Disable Synchronization or trimming error interrupt
  699.   * @rmtoll CR           ERRIE         LL_CRS_DisableIT_ERR
  700.   * @retval None
  701.   */
  702. __STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
  703. {
  704.   CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
  705. }
  706.  
  707. /**
  708.   * @brief  Check if Synchronization or trimming error interrupt is enabled or not
  709.   * @rmtoll CR           ERRIE         LL_CRS_IsEnabledIT_ERR
  710.   * @retval State of bit (1 or 0).
  711.   */
  712. __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
  713. {
  714.   return (READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE));
  715. }
  716.  
  717. /**
  718.   * @brief  Enable Expected SYNC interrupt
  719.   * @rmtoll CR           ESYNCIE       LL_CRS_EnableIT_ESYNC
  720.   * @retval None
  721.   */
  722. __STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
  723. {
  724.   SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
  725. }
  726.  
  727. /**
  728.   * @brief  Disable Expected SYNC interrupt
  729.   * @rmtoll CR           ESYNCIE       LL_CRS_DisableIT_ESYNC
  730.   * @retval None
  731.   */
  732. __STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
  733. {
  734.   CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
  735. }
  736.  
  737. /**
  738.   * @brief  Check if Expected SYNC interrupt is enabled or not
  739.   * @rmtoll CR           ESYNCIE       LL_CRS_IsEnabledIT_ESYNC
  740.   * @retval State of bit (1 or 0).
  741.   */
  742. __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
  743. {
  744.   return (READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE));
  745. }
  746.  
  747. /**
  748.   * @}
  749.   */
  750.  
  751. #if defined(USE_FULL_LL_DRIVER)
  752. /** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
  753.   * @{
  754.   */
  755.  
  756. ErrorStatus LL_CRS_DeInit(void);
  757.  
  758. /**
  759.   * @}
  760.   */
  761. #endif /* USE_FULL_LL_DRIVER */
  762.  
  763. /**
  764.   * @}
  765.   */
  766.  
  767. /**
  768.   * @}
  769.   */
  770.  
  771. #endif /* defined(CRS) */
  772.  
  773. /**
  774.   * @}
  775.   */
  776.  
  777. #ifdef __cplusplus
  778. }
  779. #endif
  780.  
  781. #endif /* __STM32F0xx_LL_CRS_H */
  782.  
  783. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  784.