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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f0xx_hal_dma_ex.h
  4.   * @author  MCD Application Team
  5.   * @brief   Header file of DMA HAL Extension module.
  6.   ******************************************************************************
  7.   * @attention
  8.   *
  9.   * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
  10.   * All rights reserved.</center></h2>
  11.   *
  12.   * This software component is licensed by ST under BSD 3-Clause license,
  13.   * the "License"; You may not use this file except in compliance with the
  14.   * License. You may obtain a copy of the License at:
  15.   *                        opensource.org/licenses/BSD-3-Clause
  16.   *
  17.   ******************************************************************************
  18.   */
  19.  
  20. /* Define to prevent recursive inclusion -------------------------------------*/
  21. #ifndef __STM32F0xx_HAL_DMA_EX_H
  22. #define __STM32F0xx_HAL_DMA_EX_H
  23.  
  24. #ifdef __cplusplus
  25.  extern "C" {
  26. #endif
  27.  
  28. /* Includes ------------------------------------------------------------------*/
  29. #include "stm32f0xx_hal_def.h"
  30.  
  31. /** @addtogroup STM32F0xx_HAL_Driver
  32.   * @{
  33.   */
  34.  
  35. /** @defgroup DMAEx DMAEx
  36.   * @brief DMA HAL module driver
  37.   * @{
  38.   */
  39.  
  40. /* Exported types ------------------------------------------------------------*/
  41. /* Exported constants --------------------------------------------------------*/
  42. #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
  43. /** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
  44.   * @{
  45.   */
  46. #define DMA1_CHANNEL1_RMP                                     0x00000000 /*!< Internal define for remaping on STM32F09x/30xC */
  47. #define DMA1_CHANNEL2_RMP                                     0x10000000 /*!< Internal define for remaping on STM32F09x/30xC */
  48. #define DMA1_CHANNEL3_RMP                                     0x20000000 /*!< Internal define for remaping on STM32F09x/30xC */
  49. #define DMA1_CHANNEL4_RMP                                     0x30000000 /*!< Internal define for remaping on STM32F09x/30xC */
  50. #define DMA1_CHANNEL5_RMP                                     0x40000000 /*!< Internal define for remaping on STM32F09x/30xC */
  51. #if !defined(STM32F030xC)
  52. #define DMA1_CHANNEL6_RMP                                     0x50000000 /*!< Internal define for remaping on STM32F09x/30xC */
  53. #define DMA1_CHANNEL7_RMP                                     0x60000000 /*!< Internal define for remaping on STM32F09x/30xC */
  54. #define DMA2_CHANNEL1_RMP                                     0x00000000 /*!< Internal define for remaping on STM32F09x/30xC */
  55. #define DMA2_CHANNEL2_RMP                                     0x10000000 /*!< Internal define for remaping on STM32F09x/30xC */
  56. #define DMA2_CHANNEL3_RMP                                     0x20000000 /*!< Internal define for remaping on STM32F09x/30xC */
  57. #define DMA2_CHANNEL4_RMP                                     0x30000000 /*!< Internal define for remaping on STM32F09x/30xC */
  58. #define DMA2_CHANNEL5_RMP                                     0x40000000 /*!< Internal define for remaping on STM32F09x/30xC */
  59. #endif /* !defined(STM32F030xC) */
  60.  
  61. /****************** DMA1 remap bit field definition********************/
  62. /* DMA1 - Channel 1 */
  63. #define HAL_DMA1_CH1_DEFAULT      (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_DEFAULT)       /*!< Default remap position for DMA1 */  
  64. #define HAL_DMA1_CH1_ADC          (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_ADC)       /*!< Remap ADC on DMA1 Channel 1*/  
  65. #define HAL_DMA1_CH1_TIM17_CH1    (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 1 */
  66. #define HAL_DMA1_CH1_TIM17_UP     (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_TIM17_UP)  /*!< Remap TIM17 up on DMA1 channel 1 */
  67. #define HAL_DMA1_CH1_USART1_RX    (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 1 */
  68. #define HAL_DMA1_CH1_USART2_RX    (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 1 */
  69. #define HAL_DMA1_CH1_USART3_RX    (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 1 */
  70. #define HAL_DMA1_CH1_USART4_RX    (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 1 */
  71. #define HAL_DMA1_CH1_USART5_RX    (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 1 */
  72. #define HAL_DMA1_CH1_USART6_RX    (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 1 */
  73. #if !defined(STM32F030xC)
  74. #define HAL_DMA1_CH1_USART7_RX    (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 1 */
  75. #define HAL_DMA1_CH1_USART8_RX    (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 1 */
  76. #endif /* !defined(STM32F030xC) */
  77.  
  78. /* DMA1 - Channel 2 */
  79. #define HAL_DMA1_CH2_DEFAULT      (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_DEFAULT)       /*!< Default remap position for DMA1 */  
  80. #define HAL_DMA1_CH2_ADC          (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_ADC)       /*!< Remap ADC on DMA1 channel 2 */  
  81. #define HAL_DMA1_CH2_I2C1_TX      (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_I2C1_TX)   /*!< Remap I2C1 Tx on DMA1 channel 2 */
  82. #define HAL_DMA1_CH2_SPI1_RX      (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_SPI1_RX)   /*!< Remap SPI1 Rx on DMA1 channel 2 */
  83. #define HAL_DMA1_CH2_TIM1_CH1     (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM1_CH1)  /*!< Remap TIM1 channel 1 on DMA1 channel 2 */
  84. #define HAL_DMA1_CH2_TIM17_CH1    (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 2 */
  85. #define HAL_DMA1_CH2_TIM17_UP     (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM17_UP)  /*!< Remap TIM17 up on DMA1 channel 2 */
  86. #define HAL_DMA1_CH2_USART1_TX    (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 2 */
  87. #define HAL_DMA1_CH2_USART2_TX    (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 2 */
  88. #define HAL_DMA1_CH2_USART3_TX    (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 2 */
  89. #define HAL_DMA1_CH2_USART4_TX    (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 2 */
  90. #define HAL_DMA1_CH2_USART5_TX    (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 2 */
  91. #define HAL_DMA1_CH2_USART6_TX    (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 2 */
  92. #if !defined(STM32F030xC)
  93. #define HAL_DMA1_CH2_USART7_TX    (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 2 */
  94. #define HAL_DMA1_CH2_USART8_TX    (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 2 */
  95. #endif /* !defined(STM32F030xC) */
  96.  
  97. /* DMA1 - Channel 3 */
  98. #define HAL_DMA1_CH3_DEFAULT      (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_DEFAULT)       /*!< Default remap position for DMA1 */  
  99. #define HAL_DMA1_CH3_TIM6_UP      (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM6_UP)   /*!< Remap TIM6 up on DMA1 channel 3 */
  100. #if !defined(STM32F030xC)
  101. #define HAL_DMA1_CH3_DAC_CH1      (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_DAC_CH1)   /*!< Remap DAC Channel 1on DMA1 channel 3 */
  102. #endif /* !defined(STM32F030xC) */
  103. #define HAL_DMA1_CH3_I2C1_RX      (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_I2C1_RX)   /*!< Remap I2C1 Rx on DMA1 channel 3 */
  104. #define HAL_DMA1_CH3_SPI1_TX      (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_SPI1_TX)   /*!< Remap SPI1 Tx on DMA1 channel 3 */
  105. #define HAL_DMA1_CH3_TIM1_CH2     (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM1_CH2)  /*!< Remap TIM1 channel 2 on DMA1 channel 3 */
  106. #if !defined(STM32F030xC)
  107. #define HAL_DMA1_CH3_TIM2_CH2     (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM2_CH2)  /*!< Remap TIM2 channel 2 on DMA1 channel 3 */
  108. #endif /* !defined(STM32F030xC) */
  109. #define HAL_DMA1_CH3_TIM16_CH1    (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 3 */
  110. #define HAL_DMA1_CH3_TIM16_UP     (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM16_UP)  /*!< Remap TIM16 up on DMA1 channel 3 */
  111. #define HAL_DMA1_CH3_USART1_RX    (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 3 */
  112. #define HAL_DMA1_CH3_USART2_RX    (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 3 */
  113. #define HAL_DMA1_CH3_USART3_RX    (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 3 */
  114. #define HAL_DMA1_CH3_USART4_RX    (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 3 */
  115. #define HAL_DMA1_CH3_USART5_RX    (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 3 */
  116. #define HAL_DMA1_CH3_USART6_RX    (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 3 */
  117. #if !defined(STM32F030xC)
  118. #define HAL_DMA1_CH3_USART7_RX    (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 3 */
  119. #define HAL_DMA1_CH3_USART8_RX    (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 3 */
  120. #endif /* !defined(STM32F030xC) */
  121.  
  122. /* DMA1 - Channel 4 */
  123. #define HAL_DMA1_CH4_DEFAULT      (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_DEFAULT)       /*!< Default remap position for DMA1 */  
  124. #define HAL_DMA1_CH4_TIM7_UP      (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM7_UP)   /*!< Remap TIM7 up on DMA1 channel 4 */
  125. #if !defined(STM32F030xC)
  126. #define HAL_DMA1_CH4_DAC_CH2      (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_DAC_CH2)   /*!< Remap DAC Channel 2 on DMA1 channel 4 */
  127. #endif /* !defined(STM32F030xC) */
  128. #define HAL_DMA1_CH4_I2C2_TX      (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_I2C2_TX)   /*!< Remap I2C2 Tx on DMA1 channel 4 */
  129. #define HAL_DMA1_CH4_SPI2_RX      (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_SPI2_RX)   /*!< Remap SPI2 Rx on DMA1 channel 4 */
  130. #if !defined(STM32F030xC)
  131. #define HAL_DMA1_CH4_TIM2_CH4     (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM2_CH4)  /*!< Remap TIM2 channel 4 on DMA1 channel 4 */
  132. #endif /* !defined(STM32F030xC) */
  133. #define HAL_DMA1_CH4_TIM3_CH1     (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM3_CH1)  /*!< Remap TIM3 channel 1 on DMA1 channel 4 */
  134. #define HAL_DMA1_CH4_TIM3_TRIG    (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 4 */
  135. #define HAL_DMA1_CH4_TIM16_CH1    (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 4 */
  136. #define HAL_DMA1_CH4_TIM16_UP     (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM16_UP)  /*!< Remap TIM16 up on DMA1 channel 4 */
  137. #define HAL_DMA1_CH4_USART1_TX    (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 4 */
  138. #define HAL_DMA1_CH4_USART2_TX    (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 4 */
  139. #define HAL_DMA1_CH4_USART3_TX    (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 4 */
  140. #define HAL_DMA1_CH4_USART4_TX    (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 4 */
  141. #define HAL_DMA1_CH4_USART5_TX    (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 4 */
  142. #define HAL_DMA1_CH4_USART6_TX    (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 4 */
  143. #if !defined(STM32F030xC)
  144. #define HAL_DMA1_CH4_USART7_TX    (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 4 */
  145. #define HAL_DMA1_CH4_USART8_TX    (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 4 */
  146. #endif /* !defined(STM32F030xC) */
  147.  
  148. /* DMA1 - Channel 5 */
  149. #define HAL_DMA1_CH5_DEFAULT      (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_DEFAULT)       /*!< Default remap position for DMA1 */  
  150. #define HAL_DMA1_CH5_I2C2_RX      (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_I2C2_RX)   /*!< Remap I2C2 Rx on DMA1 channel 5 */
  151. #define HAL_DMA1_CH5_SPI2_TX      (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_SPI2_TX)   /*!< Remap SPI1 Tx on DMA1 channel 5 */
  152. #define HAL_DMA1_CH5_TIM1_CH3     (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_TIM1_CH3)  /*!< Remap TIM1 channel 3 on DMA1 channel 5 */
  153. #define HAL_DMA1_CH5_USART1_RX    (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 5 */
  154. #define HAL_DMA1_CH5_USART2_RX    (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 5 */
  155. #define HAL_DMA1_CH5_USART3_RX    (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 5 */
  156. #define HAL_DMA1_CH5_USART4_RX    (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 5 */
  157. #define HAL_DMA1_CH5_USART5_RX    (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 5 */
  158. #define HAL_DMA1_CH5_USART6_RX    (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 5 */
  159. #if !defined(STM32F030xC)
  160. #define HAL_DMA1_CH5_USART7_RX    (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 5 */
  161. #define HAL_DMA1_CH5_USART8_RX    (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 5 */
  162. #endif /* !defined(STM32F030xC) */
  163.  
  164. #if !defined(STM32F030xC)
  165. /* DMA1 - Channel 6 */
  166. #define HAL_DMA1_CH6_DEFAULT      (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_DEFAULT)       /*!< Default remap position for DMA1 */  
  167. #define HAL_DMA1_CH6_I2C1_TX      (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_I2C1_TX)   /*!< Remap I2C1 Tx on DMA1 channel 6 */
  168. #define HAL_DMA1_CH6_SPI2_RX      (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_SPI2_RX)   /*!< Remap SPI2 Rx on DMA1 channel 6 */
  169. #define HAL_DMA1_CH6_TIM1_CH1     (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH1)  /*!< Remap TIM1 channel 1 on DMA1 channel 6 */
  170. #define HAL_DMA1_CH6_TIM1_CH2     (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH2)  /*!< Remap TIM1 channel 2 on DMA1 channel 6 */
  171. #define HAL_DMA1_CH6_TIM1_CH3     (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH3)  /*!< Remap TIM1 channel 3 on DMA1 channel 6 */
  172. #define HAL_DMA1_CH6_TIM3_CH1     (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM3_CH1)  /*!< Remap TIM3 channel 1 on DMA1 channel 6 */
  173. #define HAL_DMA1_CH6_TIM3_TRIG    (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 6 */
  174. #define HAL_DMA1_CH6_TIM16_CH1    (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 6 */
  175. #define HAL_DMA1_CH6_TIM16_UP     (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM16_UP)  /*!< Remap TIM16 up on DMA1 channel 6 */
  176. #define HAL_DMA1_CH6_USART1_RX    (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 6 */
  177. #define HAL_DMA1_CH6_USART2_RX    (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 6 */
  178. #define HAL_DMA1_CH6_USART3_RX    (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 6 */
  179. #define HAL_DMA1_CH6_USART4_RX    (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 6 */
  180. #define HAL_DMA1_CH6_USART5_RX    (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 6 */
  181. #define HAL_DMA1_CH6_USART6_RX    (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 6 */
  182. #define HAL_DMA1_CH6_USART7_RX    (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 6 */
  183. #define HAL_DMA1_CH6_USART8_RX    (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 6 */
  184. /* DMA1 - Channel 7 */
  185. #define HAL_DMA1_CH7_DEFAULT      (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_DEFAULT)       /*!< Default remap position for DMA1 */  
  186. #define HAL_DMA1_CH7_I2C1_RX      (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_I2C1_RX)   /*!< Remap I2C1 Rx on DMA1 channel 7 */
  187. #define HAL_DMA1_CH7_SPI2_TX      (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_SPI2_TX)   /*!< Remap SPI2 Tx on DMA1 channel 7 */
  188. #define HAL_DMA1_CH7_TIM2_CH2     (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM2_CH2)  /*!< Remap TIM2 channel 2 on DMA1 channel 7 */
  189. #define HAL_DMA1_CH7_TIM2_CH4     (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM2_CH4)  /*!< Remap TIM2 channel 4 on DMA1 channel 7 */
  190. #define HAL_DMA1_CH7_TIM17_CH1    (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 7 */
  191. #define HAL_DMA1_CH7_TIM17_UP     (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM17_UP)  /*!< Remap TIM17 up on DMA1 channel 7 */
  192. #define HAL_DMA1_CH7_USART1_TX    (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 7 */
  193. #define HAL_DMA1_CH7_USART2_TX    (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 7 */
  194. #define HAL_DMA1_CH7_USART3_TX    (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 7 */
  195. #define HAL_DMA1_CH7_USART4_TX    (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 7 */
  196. #define HAL_DMA1_CH7_USART5_TX    (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 7 */
  197. #define HAL_DMA1_CH7_USART6_TX    (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 7 */
  198. #define HAL_DMA1_CH7_USART7_TX    (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 7 */
  199. #define HAL_DMA1_CH7_USART8_TX    (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 7 */
  200.  
  201. /****************** DMA2 remap bit field definition********************/
  202. /* DMA2 - Channel 1 */
  203. #define HAL_DMA2_CH1_DEFAULT      (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_DEFAULT)       /*!< Default remap position for DMA2 */  
  204. #define HAL_DMA2_CH1_I2C2_TX      (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_I2C2_TX)   /*!< Remap I2C2 TX on DMA2 channel 1 */
  205. #define HAL_DMA2_CH1_USART1_TX    (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 1 */
  206. #define HAL_DMA2_CH1_USART2_TX    (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 1 */
  207. #define HAL_DMA2_CH1_USART3_TX    (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 1 */
  208. #define HAL_DMA2_CH1_USART4_TX    (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 1 */
  209. #define HAL_DMA2_CH1_USART5_TX    (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 1 */
  210. #define HAL_DMA2_CH1_USART6_TX    (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 1 */
  211. #define HAL_DMA2_CH1_USART7_TX    (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 1 */
  212. #define HAL_DMA2_CH1_USART8_TX    (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 1 */
  213. /* DMA2 - Channel 2 */
  214. #define HAL_DMA2_CH2_DEFAULT      (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_DEFAULT)       /*!< Default remap position for DMA2 */  
  215. #define HAL_DMA2_CH2_I2C2_RX      (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_I2C2_RX)   /*!< Remap I2C2 Rx on DMA2 channel 2 */
  216. #define HAL_DMA2_CH2_USART1_RX    (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 2 */
  217. #define HAL_DMA2_CH2_USART2_RX    (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 2 */
  218. #define HAL_DMA2_CH2_USART3_RX    (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 2 */
  219. #define HAL_DMA2_CH2_USART4_RX    (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 2 */
  220. #define HAL_DMA2_CH2_USART5_RX    (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 2 */
  221. #define HAL_DMA2_CH2_USART6_RX    (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 2 */
  222. #define HAL_DMA2_CH2_USART7_RX    (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 2 */
  223. #define HAL_DMA2_CH2_USART8_RX    (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 2 */
  224. /* DMA2 - Channel 3 */
  225. #define HAL_DMA2_CH3_DEFAULT      (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_DEFAULT)       /*!< Default remap position for DMA2 */  
  226. #define HAL_DMA2_CH3_TIM6_UP      (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_TIM6_UP)   /*!< Remap TIM6 up on DMA2 channel 3 */
  227. #define HAL_DMA2_CH3_DAC_CH1      (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_DAC_CH1)   /*!< Remap DAC channel 1 on DMA2 channel 3 */
  228. #define HAL_DMA2_CH3_SPI1_RX      (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_SPI1_RX)   /*!< Remap SPI1 Rx on DMA2 channel 3 */
  229. #define HAL_DMA2_CH3_USART1_RX    (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 3 */
  230. #define HAL_DMA2_CH3_USART2_RX    (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 3 */
  231. #define HAL_DMA2_CH3_USART3_RX    (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 3 */
  232. #define HAL_DMA2_CH3_USART4_RX    (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 3 */
  233. #define HAL_DMA2_CH3_USART5_RX    (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 3 */
  234. #define HAL_DMA2_CH3_USART6_RX    (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 3 */
  235. #define HAL_DMA2_CH3_USART7_RX    (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 3 */
  236. #define HAL_DMA2_CH3_USART8_RX    (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 3 */
  237. /* DMA2 - Channel 4 */
  238. #define HAL_DMA2_CH4_DEFAULT      (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_DEFAULT)       /*!< Default remap position for DMA2 */  
  239. #define HAL_DMA2_CH4_TIM7_UP      (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_TIM7_UP)   /*!< Remap TIM7 up on DMA2 channel 4 */
  240. #define HAL_DMA2_CH4_DAC_CH2      (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_DAC_CH2)   /*!< Remap DAC channel 2 on DMA2 channel 4 */
  241. #define HAL_DMA2_CH4_SPI1_TX      (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_SPI1_TX)   /*!< Remap SPI1 Tx on DMA2 channel 4 */
  242. #define HAL_DMA2_CH4_USART1_TX    (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 4 */
  243. #define HAL_DMA2_CH4_USART2_TX    (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 4 */
  244. #define HAL_DMA2_CH4_USART3_TX    (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 4 */
  245. #define HAL_DMA2_CH4_USART4_TX    (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 4 */
  246. #define HAL_DMA2_CH4_USART5_TX    (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 4 */
  247. #define HAL_DMA2_CH4_USART6_TX    (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 4 */
  248. #define HAL_DMA2_CH4_USART7_TX    (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 4 */
  249. #define HAL_DMA2_CH4_USART8_TX    (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 4 */
  250. /* DMA2 - Channel 5 */
  251. #define HAL_DMA2_CH5_DEFAULT      (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_DEFAULT)       /*!< Default remap position for DMA2 */  
  252. #define HAL_DMA2_CH5_ADC          (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_ADC)       /*!< Remap ADC on DMA2 channel 5 */  
  253. #define HAL_DMA2_CH5_USART1_TX    (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 5 */
  254. #define HAL_DMA2_CH5_USART2_TX    (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 5 */
  255. #define HAL_DMA2_CH5_USART3_TX    (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 5 */
  256. #define HAL_DMA2_CH5_USART4_TX    (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 5 */
  257. #define HAL_DMA2_CH5_USART5_TX    (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 5 */
  258. #define HAL_DMA2_CH5_USART6_TX    (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 5 */
  259. #define HAL_DMA2_CH5_USART7_TX    (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 5 */
  260. #define HAL_DMA2_CH5_USART8_TX    (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 5 */
  261. #endif /* !defined(STM32F030xC) */
  262.  
  263. #if defined(STM32F091xC) || defined(STM32F098xx)
  264. #define IS_HAL_DMA1_REMAP(REQUEST)  (((REQUEST) == HAL_DMA1_CH1_DEFAULT)  ||\
  265.                                     ((REQUEST) == HAL_DMA1_CH1_ADC)       ||\
  266.                                     ((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\
  267.                                     ((REQUEST) == HAL_DMA1_CH1_TIM17_UP)  ||\
  268.                                     ((REQUEST) == HAL_DMA1_CH1_USART1_RX) ||\
  269.                                     ((REQUEST) == HAL_DMA1_CH1_USART2_RX) ||\
  270.                                     ((REQUEST) == HAL_DMA1_CH1_USART3_RX) ||\
  271.                                     ((REQUEST) == HAL_DMA1_CH1_USART4_RX) ||\
  272.                                     ((REQUEST) == HAL_DMA1_CH1_USART5_RX) ||\
  273.                                     ((REQUEST) == HAL_DMA1_CH1_USART6_RX) ||\
  274.                                     ((REQUEST) == HAL_DMA1_CH1_USART7_RX) ||\
  275.                                     ((REQUEST) == HAL_DMA1_CH1_USART8_RX) ||\
  276.                                     ((REQUEST) == HAL_DMA1_CH2_DEFAULT)   ||\
  277.                                     ((REQUEST) == HAL_DMA1_CH2_ADC)       ||\
  278.                                     ((REQUEST) == HAL_DMA1_CH2_I2C1_TX)   ||\
  279.                                     ((REQUEST) == HAL_DMA1_CH2_SPI1_RX)   ||\
  280.                                     ((REQUEST) == HAL_DMA1_CH2_TIM1_CH1)  ||\
  281.                                     ((REQUEST) == HAL_DMA1_CH2_I2C1_TX)   ||\
  282.                                     ((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) ||\
  283.                                     ((REQUEST) == HAL_DMA1_CH2_TIM17_UP)  ||\
  284.                                     ((REQUEST) == HAL_DMA1_CH2_USART1_TX) ||\
  285.                                     ((REQUEST) == HAL_DMA1_CH2_USART2_TX) ||\
  286.                                     ((REQUEST) == HAL_DMA1_CH2_USART3_TX) ||\
  287.                                     ((REQUEST) == HAL_DMA1_CH2_USART4_TX) ||\
  288.                                     ((REQUEST) == HAL_DMA1_CH2_USART5_TX) ||\
  289.                                     ((REQUEST) == HAL_DMA1_CH2_USART6_TX) ||\
  290.                                     ((REQUEST) == HAL_DMA1_CH2_USART7_TX) ||\
  291.                                     ((REQUEST) == HAL_DMA1_CH2_USART8_TX) ||\
  292.                                     ((REQUEST) == HAL_DMA1_CH3_DEFAULT)   ||\
  293.                                     ((REQUEST) == HAL_DMA1_CH3_TIM6_UP)   ||\
  294.                                     ((REQUEST) == HAL_DMA1_CH3_DAC_CH1)   ||\
  295.                                     ((REQUEST) == HAL_DMA1_CH3_I2C1_RX)   ||\
  296.                                     ((REQUEST) == HAL_DMA1_CH3_SPI1_TX)   ||\
  297.                                     ((REQUEST) == HAL_DMA1_CH3_TIM1_CH2)  ||\
  298.                                     ((REQUEST) == HAL_DMA1_CH3_TIM2_CH2)  ||\
  299.                                     ((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) ||\
  300.                                     ((REQUEST) == HAL_DMA1_CH3_TIM16_UP)  ||\
  301.                                     ((REQUEST) == HAL_DMA1_CH3_USART1_RX) ||\
  302.                                     ((REQUEST) == HAL_DMA1_CH3_USART2_RX) ||\
  303.                                     ((REQUEST) == HAL_DMA1_CH3_USART3_RX) ||\
  304.                                     ((REQUEST) == HAL_DMA1_CH3_USART4_RX) ||\
  305.                                     ((REQUEST) == HAL_DMA1_CH3_USART5_RX) ||\
  306.                                     ((REQUEST) == HAL_DMA1_CH3_USART6_RX) ||\
  307.                                     ((REQUEST) == HAL_DMA1_CH3_USART7_RX) ||\
  308.                                     ((REQUEST) == HAL_DMA1_CH3_USART8_RX) ||\
  309.                                     ((REQUEST) == HAL_DMA1_CH4_DEFAULT)   ||\
  310.                                     ((REQUEST) == HAL_DMA1_CH4_TIM7_UP)   ||\
  311.                                     ((REQUEST) == HAL_DMA1_CH4_DAC_CH2)   ||\
  312.                                     ((REQUEST) == HAL_DMA1_CH4_I2C2_TX)   ||\
  313.                                     ((REQUEST) == HAL_DMA1_CH4_SPI2_RX)   ||\
  314.                                     ((REQUEST) == HAL_DMA1_CH4_TIM2_CH4)  ||\
  315.                                     ((REQUEST) == HAL_DMA1_CH4_TIM3_CH1)  ||\
  316.                                     ((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) ||\
  317.                                     ((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) ||\
  318.                                     ((REQUEST) == HAL_DMA1_CH4_TIM16_UP)  ||\
  319.                                     ((REQUEST) == HAL_DMA1_CH4_USART1_TX) ||\
  320.                                     ((REQUEST) == HAL_DMA1_CH4_USART2_TX) ||\
  321.                                     ((REQUEST) == HAL_DMA1_CH4_USART3_TX) ||\
  322.                                     ((REQUEST) == HAL_DMA1_CH4_USART4_TX) ||\
  323.                                     ((REQUEST) == HAL_DMA1_CH4_USART5_TX) ||\
  324.                                     ((REQUEST) == HAL_DMA1_CH4_USART6_TX) ||\
  325.                                     ((REQUEST) == HAL_DMA1_CH4_USART7_TX) ||\
  326.                                     ((REQUEST) == HAL_DMA1_CH4_USART8_TX) ||\
  327.                                     ((REQUEST) == HAL_DMA1_CH5_DEFAULT)   ||\
  328.                                     ((REQUEST) == HAL_DMA1_CH5_I2C2_RX)   ||\
  329.                                     ((REQUEST) == HAL_DMA1_CH5_SPI2_TX)   ||\
  330.                                     ((REQUEST) == HAL_DMA1_CH5_TIM1_CH3)  ||\
  331.                                     ((REQUEST) == HAL_DMA1_CH5_USART1_RX) ||\
  332.                                     ((REQUEST) == HAL_DMA1_CH5_USART2_RX) ||\
  333.                                     ((REQUEST) == HAL_DMA1_CH5_USART3_RX) ||\
  334.                                     ((REQUEST) == HAL_DMA1_CH5_USART4_RX) ||\
  335.                                     ((REQUEST) == HAL_DMA1_CH5_USART5_RX) ||\
  336.                                     ((REQUEST) == HAL_DMA1_CH5_USART6_RX) ||\
  337.                                     ((REQUEST) == HAL_DMA1_CH5_USART7_RX) ||\
  338.                                     ((REQUEST) == HAL_DMA1_CH5_USART8_RX) ||\
  339.                                     ((REQUEST) == HAL_DMA1_CH6_DEFAULT)   ||\
  340.                                     ((REQUEST) == HAL_DMA1_CH6_I2C1_TX)   ||\
  341.                                     ((REQUEST) == HAL_DMA1_CH6_SPI2_RX)   ||\
  342.                                     ((REQUEST) == HAL_DMA1_CH6_TIM1_CH1)  ||\
  343.                                     ((REQUEST) == HAL_DMA1_CH6_TIM1_CH2)  ||\
  344.                                     ((REQUEST) == HAL_DMA1_CH6_TIM1_CH3)  ||\
  345.                                     ((REQUEST) == HAL_DMA1_CH6_TIM3_CH1)  ||\
  346.                                     ((REQUEST) == HAL_DMA1_CH6_TIM3_TRIG) ||\
  347.                                     ((REQUEST) == HAL_DMA1_CH6_TIM16_CH1) ||\
  348.                                     ((REQUEST) == HAL_DMA1_CH6_TIM16_UP)  ||\
  349.                                     ((REQUEST) == HAL_DMA1_CH6_USART1_RX) ||\
  350.                                     ((REQUEST) == HAL_DMA1_CH6_USART2_RX) ||\
  351.                                     ((REQUEST) == HAL_DMA1_CH6_USART3_RX) ||\
  352.                                     ((REQUEST) == HAL_DMA1_CH6_USART4_RX) ||\
  353.                                     ((REQUEST) == HAL_DMA1_CH6_USART5_RX) ||\
  354.                                     ((REQUEST) == HAL_DMA1_CH6_USART6_RX) ||\
  355.                                     ((REQUEST) == HAL_DMA1_CH6_USART7_RX) ||\
  356.                                     ((REQUEST) == HAL_DMA1_CH6_USART8_RX) ||\
  357.                                     ((REQUEST) == HAL_DMA1_CH7_DEFAULT)   ||\
  358.                                     ((REQUEST) == HAL_DMA1_CH7_I2C1_RX)   ||\
  359.                                     ((REQUEST) == HAL_DMA1_CH7_SPI2_TX)   ||\
  360.                                     ((REQUEST) == HAL_DMA1_CH7_TIM2_CH2)  ||\
  361.                                     ((REQUEST) == HAL_DMA1_CH7_TIM2_CH4)  ||\
  362.                                     ((REQUEST) == HAL_DMA1_CH7_TIM17_CH1) ||\
  363.                                     ((REQUEST) == HAL_DMA1_CH7_TIM17_UP)  ||\
  364.                                     ((REQUEST) == HAL_DMA1_CH7_USART1_TX) ||\
  365.                                     ((REQUEST) == HAL_DMA1_CH7_USART2_TX) ||\
  366.                                     ((REQUEST) == HAL_DMA1_CH7_USART3_TX) ||\
  367.                                     ((REQUEST) == HAL_DMA1_CH7_USART4_TX) ||\
  368.                                     ((REQUEST) == HAL_DMA1_CH7_USART5_TX) ||\
  369.                                     ((REQUEST) == HAL_DMA1_CH7_USART6_TX) ||\
  370.                                     ((REQUEST) == HAL_DMA1_CH7_USART7_TX) ||\
  371.                                     ((REQUEST) == HAL_DMA1_CH7_USART8_TX))
  372.  
  373. #define IS_HAL_DMA2_REMAP(REQUEST)  (((REQUEST) == HAL_DMA2_CH1_DEFAULT)   ||\
  374.                                     ((REQUEST) == HAL_DMA2_CH1_I2C2_TX)   ||\
  375.                                     ((REQUEST) == HAL_DMA2_CH1_USART1_TX) ||\
  376.                                     ((REQUEST) == HAL_DMA2_CH1_USART2_TX) ||\
  377.                                     ((REQUEST) == HAL_DMA2_CH1_USART3_TX) ||\
  378.                                     ((REQUEST) == HAL_DMA2_CH1_USART4_TX) ||\
  379.                                     ((REQUEST) == HAL_DMA2_CH1_USART5_TX) ||\
  380.                                     ((REQUEST) == HAL_DMA2_CH1_USART6_TX) ||\
  381.                                     ((REQUEST) == HAL_DMA2_CH1_USART7_TX) ||\
  382.                                     ((REQUEST) == HAL_DMA2_CH1_USART8_TX) ||\
  383.                                     ((REQUEST) == HAL_DMA2_CH2_DEFAULT)   ||\
  384.                                     ((REQUEST) == HAL_DMA2_CH2_I2C2_RX)   ||\
  385.                                     ((REQUEST) == HAL_DMA2_CH2_USART1_RX) ||\
  386.                                     ((REQUEST) == HAL_DMA2_CH2_USART2_RX) ||\
  387.                                     ((REQUEST) == HAL_DMA2_CH2_USART3_RX) ||\
  388.                                     ((REQUEST) == HAL_DMA2_CH2_USART4_RX) ||\
  389.                                     ((REQUEST) == HAL_DMA2_CH2_USART5_RX) ||\
  390.                                     ((REQUEST) == HAL_DMA2_CH2_USART6_RX) ||\
  391.                                     ((REQUEST) == HAL_DMA2_CH2_USART7_RX) ||\
  392.                                     ((REQUEST) == HAL_DMA2_CH2_USART8_RX) ||\
  393.                                     ((REQUEST) == HAL_DMA2_CH3_DEFAULT)   ||\
  394.                                     ((REQUEST) == HAL_DMA2_CH3_TIM6_UP)   ||\
  395.                                     ((REQUEST) == HAL_DMA2_CH3_DAC_CH1)   ||\
  396.                                     ((REQUEST) == HAL_DMA2_CH3_SPI1_RX)   ||\
  397.                                     ((REQUEST) == HAL_DMA2_CH3_USART1_RX) ||\
  398.                                     ((REQUEST) == HAL_DMA2_CH3_USART2_RX) ||\
  399.                                     ((REQUEST) == HAL_DMA2_CH3_USART3_RX) ||\
  400.                                     ((REQUEST) == HAL_DMA2_CH3_USART4_RX) ||\
  401.                                     ((REQUEST) == HAL_DMA2_CH3_USART5_RX) ||\
  402.                                     ((REQUEST) == HAL_DMA2_CH3_USART6_RX) ||\
  403.                                     ((REQUEST) == HAL_DMA2_CH3_USART7_RX) ||\
  404.                                     ((REQUEST) == HAL_DMA2_CH3_USART8_RX) ||\
  405.                                     ((REQUEST) == HAL_DMA2_CH4_DEFAULT)   ||\
  406.                                     ((REQUEST) == HAL_DMA2_CH4_TIM7_UP)   ||\
  407.                                     ((REQUEST) == HAL_DMA2_CH4_DAC_CH2)   ||\
  408.                                     ((REQUEST) == HAL_DMA2_CH4_SPI1_TX)   ||\
  409.                                     ((REQUEST) == HAL_DMA2_CH4_USART1_TX) ||\
  410.                                     ((REQUEST) == HAL_DMA2_CH4_USART2_TX) ||\
  411.                                     ((REQUEST) == HAL_DMA2_CH4_USART3_TX) ||\
  412.                                     ((REQUEST) == HAL_DMA2_CH4_USART4_TX) ||\
  413.                                     ((REQUEST) == HAL_DMA2_CH4_USART5_TX) ||\
  414.                                     ((REQUEST) == HAL_DMA2_CH4_USART6_TX) ||\
  415.                                     ((REQUEST) == HAL_DMA2_CH4_USART7_TX) ||\
  416.                                     ((REQUEST) == HAL_DMA2_CH4_USART8_TX) ||\
  417.                                     ((REQUEST) == HAL_DMA2_CH5_DEFAULT)   ||\
  418.                                     ((REQUEST) == HAL_DMA2_CH5_ADC)       ||\
  419.                                     ((REQUEST) == HAL_DMA2_CH5_USART1_TX) ||\
  420.                                     ((REQUEST) == HAL_DMA2_CH5_USART2_TX) ||\
  421.                                     ((REQUEST) == HAL_DMA2_CH5_USART3_TX) ||\
  422.                                     ((REQUEST) == HAL_DMA2_CH5_USART4_TX) ||\
  423.                                     ((REQUEST) == HAL_DMA2_CH5_USART5_TX) ||\
  424.                                     ((REQUEST) == HAL_DMA2_CH5_USART6_TX) ||\
  425.                                     ((REQUEST) == HAL_DMA2_CH5_USART7_TX) ||\
  426.                                     ((REQUEST) == HAL_DMA2_CH5_USART8_TX ))
  427. #endif /* STM32F091xC || STM32F098xx */
  428.  
  429. #if defined(STM32F030xC)
  430. #define IS_HAL_DMA1_REMAP(REQUEST)  (((REQUEST) == HAL_DMA1_CH1_DEFAULT)  ||\
  431.                                     ((REQUEST) == HAL_DMA1_CH1_ADC)       ||\
  432.                                     ((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\
  433.                                     ((REQUEST) == HAL_DMA1_CH1_TIM17_UP)  ||\
  434.                                     ((REQUEST) == HAL_DMA1_CH1_USART1_RX) ||\
  435.                                     ((REQUEST) == HAL_DMA1_CH1_USART2_RX) ||\
  436.                                     ((REQUEST) == HAL_DMA1_CH1_USART3_RX) ||\
  437.                                     ((REQUEST) == HAL_DMA1_CH1_USART4_RX) ||\
  438.                                     ((REQUEST) == HAL_DMA1_CH1_USART5_RX) ||\
  439.                                     ((REQUEST) == HAL_DMA1_CH1_USART6_RX) ||\
  440.                                     ((REQUEST) == HAL_DMA1_CH2_DEFAULT)   ||\
  441.                                     ((REQUEST) == HAL_DMA1_CH2_ADC)       ||\
  442.                                     ((REQUEST) == HAL_DMA1_CH2_I2C1_TX)   ||\
  443.                                     ((REQUEST) == HAL_DMA1_CH2_SPI1_RX)   ||\
  444.                                     ((REQUEST) == HAL_DMA1_CH2_TIM1_CH1)  ||\
  445.                                     ((REQUEST) == HAL_DMA1_CH2_I2C1_TX)   ||\
  446.                                     ((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) ||\
  447.                                     ((REQUEST) == HAL_DMA1_CH2_TIM17_UP)  ||\
  448.                                     ((REQUEST) == HAL_DMA1_CH2_USART1_TX) ||\
  449.                                     ((REQUEST) == HAL_DMA1_CH2_USART2_TX) ||\
  450.                                     ((REQUEST) == HAL_DMA1_CH2_USART3_TX) ||\
  451.                                     ((REQUEST) == HAL_DMA1_CH2_USART4_TX) ||\
  452.                                     ((REQUEST) == HAL_DMA1_CH2_USART5_TX) ||\
  453.                                     ((REQUEST) == HAL_DMA1_CH2_USART6_TX) ||\
  454.                                     ((REQUEST) == HAL_DMA1_CH3_DEFAULT)   ||\
  455.                                     ((REQUEST) == HAL_DMA1_CH3_TIM6_UP)   ||\
  456.                                     ((REQUEST) == HAL_DMA1_CH3_I2C1_RX)   ||\
  457.                                     ((REQUEST) == HAL_DMA1_CH3_SPI1_TX)   ||\
  458.                                     ((REQUEST) == HAL_DMA1_CH3_TIM1_CH2)  ||\
  459.                                     ((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) ||\
  460.                                     ((REQUEST) == HAL_DMA1_CH3_TIM16_UP)  ||\
  461.                                     ((REQUEST) == HAL_DMA1_CH3_USART1_RX) ||\
  462.                                     ((REQUEST) == HAL_DMA1_CH3_USART2_RX) ||\
  463.                                     ((REQUEST) == HAL_DMA1_CH3_USART3_RX) ||\
  464.                                     ((REQUEST) == HAL_DMA1_CH3_USART4_RX) ||\
  465.                                     ((REQUEST) == HAL_DMA1_CH3_USART5_RX) ||\
  466.                                     ((REQUEST) == HAL_DMA1_CH3_USART6_RX) ||\
  467.                                     ((REQUEST) == HAL_DMA1_CH4_DEFAULT)   ||\
  468.                                     ((REQUEST) == HAL_DMA1_CH4_TIM7_UP)   ||\
  469.                                     ((REQUEST) == HAL_DMA1_CH4_I2C2_TX)   ||\
  470.                                     ((REQUEST) == HAL_DMA1_CH4_SPI2_RX)   ||\
  471.                                     ((REQUEST) == HAL_DMA1_CH4_TIM3_CH1)  ||\
  472.                                     ((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) ||\
  473.                                     ((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) ||\
  474.                                     ((REQUEST) == HAL_DMA1_CH4_TIM16_UP)  ||\
  475.                                     ((REQUEST) == HAL_DMA1_CH4_USART1_TX) ||\
  476.                                     ((REQUEST) == HAL_DMA1_CH4_USART2_TX) ||\
  477.                                     ((REQUEST) == HAL_DMA1_CH4_USART3_TX) ||\
  478.                                     ((REQUEST) == HAL_DMA1_CH4_USART4_TX) ||\
  479.                                     ((REQUEST) == HAL_DMA1_CH4_USART5_TX) ||\
  480.                                     ((REQUEST) == HAL_DMA1_CH4_USART6_TX) ||\
  481.                                     ((REQUEST) == HAL_DMA1_CH5_DEFAULT)   ||\
  482.                                     ((REQUEST) == HAL_DMA1_CH5_I2C2_RX)   ||\
  483.                                     ((REQUEST) == HAL_DMA1_CH5_SPI2_TX)   ||\
  484.                                     ((REQUEST) == HAL_DMA1_CH5_TIM1_CH3)  ||\
  485.                                     ((REQUEST) == HAL_DMA1_CH5_USART1_RX) ||\
  486.                                     ((REQUEST) == HAL_DMA1_CH5_USART2_RX) ||\
  487.                                     ((REQUEST) == HAL_DMA1_CH5_USART3_RX) ||\
  488.                                     ((REQUEST) == HAL_DMA1_CH5_USART4_RX) ||\
  489.                                     ((REQUEST) == HAL_DMA1_CH5_USART5_RX) ||\
  490.                                     ((REQUEST) == HAL_DMA1_CH5_USART6_RX))
  491. #endif /* STM32F030xC */
  492.  
  493. /**
  494.   * @}
  495.   */
  496. #endif /* STM32F091xC  || STM32F098xx || STM32F030xC */
  497.  
  498. /* Exported macros -----------------------------------------------------------*/
  499.  
  500. /** @defgroup DMAEx_Exported_Macros DMAEx Exported Macros
  501.   * @{
  502.   */
  503. /* Interrupt & Flag management */
  504.  
  505. #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
  506. /**
  507.   * @brief  Returns the current DMA Channel transfer complete flag.
  508.   * @param  __HANDLE__ DMA handle
  509.   * @retval The specified transfer complete flag index.
  510.   */      
  511. #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
  512. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
  513.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
  514.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
  515.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
  516.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
  517.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
  518.    DMA_FLAG_TC7)
  519.  
  520. /**
  521.   * @brief  Returns the current DMA Channel half transfer complete flag.
  522.   * @param  __HANDLE__ DMA handle
  523.   * @retval The specified half transfer complete flag index.
  524.   */      
  525. #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
  526. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
  527.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
  528.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
  529.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
  530.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
  531.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
  532.    DMA_FLAG_HT7)
  533.  
  534. /**
  535.   * @brief  Returns the current DMA Channel transfer error flag.
  536.   * @param  __HANDLE__ DMA handle
  537.   * @retval The specified transfer error flag index.
  538.   */
  539. #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
  540. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
  541.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
  542.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
  543.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
  544.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
  545.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
  546.    DMA_FLAG_TE7)
  547.  
  548. /**
  549.   * @brief  Return the current DMA Channel Global interrupt flag.
  550.   * @param  __HANDLE__ DMA handle
  551.   * @retval The specified transfer error flag index.
  552.   */
  553. #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
  554. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
  555.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
  556.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
  557.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
  558.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
  559.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
  560.    DMA_FLAG_GL7)
  561.  
  562. /**
  563.   * @brief  Get the DMA Channel pending flags.
  564.   * @param  __HANDLE__ DMA handle
  565.   * @param  __FLAG__ Get the specified flag.
  566.   *          This parameter can be any combination of the following values:
  567.   *            @arg DMA_FLAG_TCx:  Transfer complete flag
  568.   *            @arg DMA_FLAG_HTx:  Half transfer complete flag
  569.   *            @arg DMA_FLAG_TEx:  Transfer error flag
  570.   *         Where x can be 1_7 to select the DMA Channel flag.  
  571.   * @retval The state of FLAG (SET or RESET).
  572.   */
  573.  
  574. #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)   (DMA1->ISR & (__FLAG__))
  575.  
  576. /**
  577.   * @brief  Clears the DMA Channel pending flags.
  578.   * @param  __HANDLE__ DMA handle
  579.   * @param  __FLAG__ specifies the flag to clear.
  580.   *          This parameter can be any combination of the following values:
  581.   *            @arg DMA_FLAG_TCx:  Transfer complete flag
  582.   *            @arg DMA_FLAG_HTx:  Half transfer complete flag
  583.   *            @arg DMA_FLAG_TEx:  Transfer error flag
  584.   *         Where x can be 1_7 to select the DMA Channel flag.  
  585.   * @retval None
  586.   */
  587. #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
  588.  
  589. #elif defined(STM32F091xC) || defined(STM32F098xx)
  590. /**
  591.   * @brief  Returns the current DMA Channel transfer complete flag.
  592.   * @param  __HANDLE__ DMA handle
  593.   * @retval The specified transfer complete flag index.
  594.   */      
  595. #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
  596. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
  597.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
  598.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
  599.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
  600.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
  601.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
  602.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
  603.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
  604.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
  605.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
  606.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
  607.    DMA_FLAG_TC5)
  608.  
  609. /**
  610.   * @brief  Returns the current DMA Channel half transfer complete flag.
  611.   * @param  __HANDLE__ DMA handle
  612.   * @retval The specified half transfer complete flag index.
  613.   */      
  614. #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
  615. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
  616.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
  617.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
  618.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
  619.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
  620.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
  621.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
  622.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
  623.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
  624.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
  625.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
  626.    DMA_FLAG_HT5)
  627.  
  628. /**
  629.   * @brief  Returns the current DMA Channel transfer error flag.
  630.   * @param  __HANDLE__ DMA handle
  631.   * @retval The specified transfer error flag index.
  632.   */
  633. #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
  634. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
  635.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
  636.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
  637.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
  638.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
  639.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
  640.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
  641.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
  642.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
  643.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
  644.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
  645.    DMA_FLAG_TE5)
  646.  
  647. /**
  648.   * @brief  Return the current DMA Channel Global interrupt flag.
  649.   * @param  __HANDLE__ DMA handle
  650.   * @retval The specified transfer error flag index.
  651.   */
  652. #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
  653. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
  654.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
  655.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
  656.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
  657.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
  658.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
  659.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\
  660.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\
  661.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\
  662.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\
  663.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\
  664.    DMA_FLAG_GL5)
  665.  
  666. /**
  667.   * @brief  Get the DMA Channel pending flags.
  668.   * @param  __HANDLE__ DMA handle
  669.   * @param  __FLAG__ Get the specified flag.
  670.   *          This parameter can be any combination of the following values:
  671.   *            @arg DMA_FLAG_TCx:  Transfer complete flag
  672.   *            @arg DMA_FLAG_HTx:  Half transfer complete flag
  673.   *            @arg DMA_FLAG_TEx:  Transfer error flag
  674.   *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.  
  675.   * @retval The state of FLAG (SET or RESET).
  676.   */
  677.  
  678. #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
  679. (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
  680.   (DMA1->ISR & (__FLAG__)))
  681.  
  682. /**
  683.   * @brief  Clears the DMA Channel pending flags.
  684.   * @param  __HANDLE__ DMA handle
  685.   * @param  __FLAG__ specifies the flag to clear.
  686.   *          This parameter can be any combination of the following values:
  687.   *            @arg DMA_FLAG_TCx:  Transfer complete flag
  688.   *            @arg DMA_FLAG_HTx:  Half transfer complete flag
  689.   *            @arg DMA_FLAG_TEx:  Transfer error flag
  690.   *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.  
  691.   * @retval None
  692.   */
  693. #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
  694. (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
  695.   (DMA1->IFCR = (__FLAG__)))
  696.  
  697. #else /* STM32F030x8_STM32F030xC_STM32F031x6_STM32F038xx_STM32F051x8_STM32F058xx_STM32F070x6_STM32F070xB Product devices */
  698. /**
  699.   * @brief  Returns the current DMA Channel transfer complete flag.
  700.   * @param  __HANDLE__ DMA handle
  701.   * @retval The specified transfer complete flag index.
  702.   */      
  703. #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
  704. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
  705.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
  706.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
  707.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
  708.    DMA_FLAG_TC5)
  709.  
  710. /**
  711.   * @brief  Returns the current DMA Channel half transfer complete flag.
  712.   * @param  __HANDLE__ DMA handle
  713.   * @retval The specified half transfer complete flag index.
  714.   */      
  715. #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
  716. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
  717.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
  718.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
  719.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
  720.    DMA_FLAG_HT5)
  721.  
  722. /**
  723.   * @brief  Returns the current DMA Channel transfer error flag.
  724.   * @param  __HANDLE__ DMA handle
  725.   * @retval The specified transfer error flag index.
  726.   */
  727. #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
  728. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
  729.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
  730.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
  731.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
  732.    DMA_FLAG_TE5)
  733.  
  734. /**
  735.   * @brief  Return the current DMA Channel Global interrupt flag.
  736.   * @param  __HANDLE__ DMA handle
  737.   * @retval The specified transfer error flag index.
  738.   */
  739. #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
  740. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
  741.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
  742.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
  743.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
  744.    DMA_FLAG_GL5)
  745.  
  746. /**
  747.   * @brief  Get the DMA Channel pending flags.
  748.   * @param  __HANDLE__ DMA handle
  749.   * @param  __FLAG__ Get the specified flag.
  750.   *          This parameter can be any combination of the following values:
  751.   *            @arg DMA_FLAG_TCx:  Transfer complete flag
  752.   *            @arg DMA_FLAG_HTx:  Half transfer complete flag
  753.   *            @arg DMA_FLAG_TEx:  Transfer error flag
  754.   *         Where x can be 1_5 to select the DMA Channel flag.  
  755.   * @retval The state of FLAG (SET or RESET).
  756.   */
  757.  
  758. #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)   (DMA1->ISR & (__FLAG__))
  759.  
  760. /**
  761.   * @brief  Clears the DMA Channel pending flags.
  762.   * @param  __HANDLE__ DMA handle
  763.   * @param  __FLAG__ specifies the flag to clear.
  764.   *          This parameter can be any combination of the following values:
  765.   *            @arg DMA_FLAG_TCx:  Transfer complete flag
  766.   *            @arg DMA_FLAG_HTx:  Half transfer complete flag
  767.   *            @arg DMA_FLAG_TEx:  Transfer error flag
  768.   *         Where x can be 1_5 to select the DMA Channel flag.  
  769.   * @retval None
  770.   */
  771. #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
  772.  
  773. #endif
  774.  
  775.  
  776. #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
  777. #define __HAL_DMA1_REMAP(__REQUEST__)                                                              \
  778.          do { assert_param(IS_HAL_DMA1_REMAP(__REQUEST__));                                             \
  779.               DMA1->CSELR &= ~(0x0FU << (uint32_t)(((__REQUEST__) >> 28U) * 4U)); \
  780.               DMA1->CSELR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFFU);                                     \
  781.   }while(0)
  782.  
  783. #if defined(STM32F091xC) || defined(STM32F098xx)
  784. #define __HAL_DMA2_REMAP(__REQUEST__)                                                              \
  785.          do { assert_param(IS_HAL_DMA2_REMAP(__REQUEST__));                                             \
  786.               DMA2->CSELR &= ~(0x0FU << (uint32_t)(((__REQUEST__) >> 28U) * 4U)); \
  787.               DMA2->CSELR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFFU);                                     \
  788.          }while(0)
  789. #endif /* STM32F091xC || STM32F098xx */
  790.  
  791. #endif /* STM32F091xC || STM32F098xx || STM32F030xC */
  792.  
  793. /**
  794.   * @}
  795.   */
  796.  
  797. /**
  798.   * @}
  799.   */
  800.  
  801. /**
  802.   * @}
  803.   */
  804.  
  805. #ifdef __cplusplus
  806. }
  807. #endif
  808.  
  809. #endif /* __STM32F0xx_HAL_DMA_EX_H */
  810.  
  811. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  812.