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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f0xx_hal.h
  4.   * @author  MCD Application Team
  5.   * @brief   This file contains all the functions prototypes for the HAL
  6.   *          module driver.
  7.   ******************************************************************************
  8.   * @attention
  9.   *
  10.   * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
  11.   * All rights reserved.</center></h2>
  12.   *
  13.   * This software component is licensed by ST under BSD 3-Clause license,
  14.   * the "License"; You may not use this file except in compliance with the
  15.   * License. You may obtain a copy of the License at:
  16.   *                        opensource.org/licenses/BSD-3-Clause
  17.   *
  18.   ******************************************************************************
  19.   */
  20.  
  21. /* Define to prevent recursive inclusion -------------------------------------*/
  22. #ifndef __STM32F0xx_HAL_H
  23. #define __STM32F0xx_HAL_H
  24.  
  25. #ifdef __cplusplus
  26.  extern "C" {
  27. #endif
  28.  
  29. /* Includes ------------------------------------------------------------------*/
  30. #include "stm32f0xx_hal_conf.h"
  31.  
  32. /** @addtogroup STM32F0xx_HAL_Driver
  33.   * @{
  34.   */
  35.  
  36. /** @addtogroup HAL
  37.   * @{
  38.   */
  39.  
  40. /* Private macros ------------------------------------------------------------*/
  41. /** @addtogroup HAL_Private_Macros
  42.   * @{
  43.   */
  44. #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) || \
  45.     defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \
  46.     defined(STM32F070xB) || defined(STM32F030x6)
  47. #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PA9)  == SYSCFG_FASTMODEPLUS_PA9)  || \
  48.                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PA10) == SYSCFG_FASTMODEPLUS_PA10) || \
  49.                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB6)  == SYSCFG_FASTMODEPLUS_PB6)  || \
  50.                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7)  == SYSCFG_FASTMODEPLUS_PB7)  || \
  51.                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8)  == SYSCFG_FASTMODEPLUS_PB8)  || \
  52.                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9)  == SYSCFG_FASTMODEPLUS_PB9))
  53. #else
  54. #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6)  == SYSCFG_FASTMODEPLUS_PB6)  || \
  55.                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7)  == SYSCFG_FASTMODEPLUS_PB7)  || \
  56.                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8)  == SYSCFG_FASTMODEPLUS_PB8)  || \
  57.                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9)  == SYSCFG_FASTMODEPLUS_PB9))
  58. #endif
  59. #if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
  60. #define IS_HAL_REMAP_PIN(RMP) ((RMP) == HAL_REMAP_PA11_PA12)
  61. #endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
  62. #if defined(STM32F091xC) || defined(STM32F098xx)
  63. #define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL)   (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16)   || \
  64.                                            ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1)   || \
  65.                                            ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART4))
  66. #endif /* STM32F091xC || STM32F098xx */
  67. /**
  68.   * @}
  69.   */
  70.  
  71. /* Exported types ------------------------------------------------------------*/
  72. /* Exported constants --------------------------------------------------------*/
  73. /** @defgroup HAL_Exported_Constants HAL Exported Constants
  74.   * @{
  75.   */
  76.  
  77. /** @defgroup HAL_TICK_FREQ Tick Frequency
  78.   * @{
  79.   */
  80. typedef enum
  81. {
  82.   HAL_TICK_FREQ_10HZ         = 100U,
  83.   HAL_TICK_FREQ_100HZ        = 10U,
  84.   HAL_TICK_FREQ_1KHZ         = 1U,
  85.   HAL_TICK_FREQ_DEFAULT      = HAL_TICK_FREQ_1KHZ
  86. } HAL_TickFreqTypeDef;
  87.  
  88. /**
  89.   * @}
  90.   */
  91.  
  92. #if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
  93. /** @defgroup HAL_Pin_remapping HAL Pin remapping
  94.   * @{
  95.   */
  96. #define HAL_REMAP_PA11_PA12                 (SYSCFG_CFGR1_PA11_PA12_RMP)  /*!< PA11 and PA12 remapping bit for small packages (28 and 20 pins).
  97.                                                                            0: No remap (pin pair PA9/10 mapped on the pins)
  98.                                                                            1: Remap (pin pair PA11/12 mapped instead of PA9/10) */
  99.  
  100. /**
  101.   * @}
  102.   */
  103. #endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
  104.  
  105. #if defined(STM32F091xC) || defined(STM32F098xx)
  106. /** @defgroup HAL_IRDA_ENV_SEL HAL IRDA Enveloppe Selection
  107.   * @note Applicable on STM32F09x
  108.   * @{
  109.   */
  110. #define HAL_SYSCFG_IRDA_ENV_SEL_TIM16     (SYSCFG_CFGR1_IRDA_ENV_SEL_0 & SYSCFG_CFGR1_IRDA_ENV_SEL_1)    /* 00: Timer16 is selected as IRDA Modulation enveloppe source */
  111. #define HAL_SYSCFG_IRDA_ENV_SEL_USART1    (SYSCFG_CFGR1_IRDA_ENV_SEL_0)  /* 01: USART1 is selected as IRDA Modulation enveloppe source */
  112. #define HAL_SYSCFG_IRDA_ENV_SEL_USART4    (SYSCFG_CFGR1_IRDA_ENV_SEL_1)  /* 10: USART4 is selected as IRDA Modulation enveloppe source */
  113.  
  114. /**
  115.   * @}
  116.   */
  117. #endif /* STM32F091xC || STM32F098xx */
  118.  
  119.  
  120. /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
  121.   * @{
  122.   */
  123.  
  124. /** @brief  Fast-mode Plus driving capability on a specific GPIO
  125.   */  
  126. #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) || \
  127.     defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \
  128.     defined(STM32F070xB) || defined(STM32F030x6)
  129. #define SYSCFG_FASTMODEPLUS_PA9        SYSCFG_CFGR1_I2C_FMP_PA9  /*!< Enable Fast-mode Plus on PA9  */
  130. #define SYSCFG_FASTMODEPLUS_PA10       SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast-mode Plus on PA10 */
  131. #endif
  132. #define SYSCFG_FASTMODEPLUS_PB6        SYSCFG_CFGR1_I2C_FMP_PB6  /*!< Enable Fast-mode Plus on PB6  */
  133. #define SYSCFG_FASTMODEPLUS_PB7        SYSCFG_CFGR1_I2C_FMP_PB7  /*!< Enable Fast-mode Plus on PB7  */
  134. #define SYSCFG_FASTMODEPLUS_PB8        SYSCFG_CFGR1_I2C_FMP_PB8  /*!< Enable Fast-mode Plus on PB8  */
  135. #define SYSCFG_FASTMODEPLUS_PB9        SYSCFG_CFGR1_I2C_FMP_PB9  /*!< Enable Fast-mode Plus on PB9  */
  136.  
  137. /**
  138.  * @}
  139.  */
  140.  
  141.  
  142. #if defined(STM32F091xC) || defined (STM32F098xx)
  143. /** @defgroup HAL_ISR_Wrapper HAL ISR Wrapper
  144.   * @brief ISR Wrapper
  145.   * @note applicable on STM32F09x
  146.   * @{
  147.   */
  148. #define HAL_SYSCFG_ITLINE0                           ( 0x00000000U) /*!< Internal define for macro handling */
  149. #define HAL_SYSCFG_ITLINE1                           ( 0x00000001U) /*!< Internal define for macro handling */
  150. #define HAL_SYSCFG_ITLINE2                           ( 0x00000002U) /*!< Internal define for macro handling */
  151. #define HAL_SYSCFG_ITLINE3                           ( 0x00000003U) /*!< Internal define for macro handling */
  152. #define HAL_SYSCFG_ITLINE4                           ( 0x00000004U) /*!< Internal define for macro handling */
  153. #define HAL_SYSCFG_ITLINE5                           ( 0x00000005U) /*!< Internal define for macro handling */
  154. #define HAL_SYSCFG_ITLINE6                           ( 0x00000006U) /*!< Internal define for macro handling */
  155. #define HAL_SYSCFG_ITLINE7                           ( 0x00000007U) /*!< Internal define for macro handling */
  156. #define HAL_SYSCFG_ITLINE8                           ( 0x00000008U) /*!< Internal define for macro handling */
  157. #define HAL_SYSCFG_ITLINE9                           ( 0x00000009U) /*!< Internal define for macro handling */
  158. #define HAL_SYSCFG_ITLINE10                          ( 0x0000000AU) /*!< Internal define for macro handling */
  159. #define HAL_SYSCFG_ITLINE11                          ( 0x0000000BU) /*!< Internal define for macro handling */
  160. #define HAL_SYSCFG_ITLINE12                          ( 0x0000000CU) /*!< Internal define for macro handling */
  161. #define HAL_SYSCFG_ITLINE13                          ( 0x0000000DU) /*!< Internal define for macro handling */
  162. #define HAL_SYSCFG_ITLINE14                          ( 0x0000000EU) /*!< Internal define for macro handling */
  163. #define HAL_SYSCFG_ITLINE15                          ( 0x0000000FU) /*!< Internal define for macro handling */
  164. #define HAL_SYSCFG_ITLINE16                          ( 0x00000010U) /*!< Internal define for macro handling */
  165. #define HAL_SYSCFG_ITLINE17                          ( 0x00000011U) /*!< Internal define for macro handling */
  166. #define HAL_SYSCFG_ITLINE18                          ( 0x00000012U) /*!< Internal define for macro handling */
  167. #define HAL_SYSCFG_ITLINE19                          ( 0x00000013U) /*!< Internal define for macro handling */
  168. #define HAL_SYSCFG_ITLINE20                          ( 0x00000014U) /*!< Internal define for macro handling */
  169. #define HAL_SYSCFG_ITLINE21                          ( 0x00000015U) /*!< Internal define for macro handling */
  170. #define HAL_SYSCFG_ITLINE22                          ( 0x00000016U) /*!< Internal define for macro handling */
  171. #define HAL_SYSCFG_ITLINE23                          ( 0x00000017U) /*!< Internal define for macro handling */
  172. #define HAL_SYSCFG_ITLINE24                          ( 0x00000018U) /*!< Internal define for macro handling */
  173. #define HAL_SYSCFG_ITLINE25                          ( 0x00000019U) /*!< Internal define for macro handling */
  174. #define HAL_SYSCFG_ITLINE26                          ( 0x0000001AU) /*!< Internal define for macro handling */
  175. #define HAL_SYSCFG_ITLINE27                          ( 0x0000001BU) /*!< Internal define for macro handling */
  176. #define HAL_SYSCFG_ITLINE28                          ( 0x0000001CU) /*!< Internal define for macro handling */
  177. #define HAL_SYSCFG_ITLINE29                          ( 0x0000001DU) /*!< Internal define for macro handling */
  178. #define HAL_SYSCFG_ITLINE30                          ( 0x0000001EU) /*!< Internal define for macro handling */
  179. #define HAL_SYSCFG_ITLINE31                          ( 0x0000001FU) /*!< Internal define for macro handling */
  180.  
  181. #define HAL_ITLINE_EWDG           ((uint32_t) ((HAL_SYSCFG_ITLINE0 << 0x18U) | SYSCFG_ITLINE0_SR_EWDG)) /*!< EWDG has expired .... */
  182. #if defined(STM32F091xC)
  183. #define HAL_ITLINE_PVDOUT         ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_PVDOUT)) /*!< Power voltage detection Interrupt .... */
  184. #endif
  185. #define HAL_ITLINE_VDDIO2         ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_VDDIO2)) /*!< VDDIO2 Interrupt .... */
  186. #define HAL_ITLINE_RTC_WAKEUP     ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC_WAKEUP)) /*!< RTC WAKEUP -> exti[20] Interrupt */
  187. #define HAL_ITLINE_RTC_TSTAMP     ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC_TSTAMP)) /*!< RTC Time Stamp -> exti[19] interrupt */
  188. #define HAL_ITLINE_RTC_ALRA       ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC_ALRA)) /*!< RTC Alarm -> exti[17] interrupt .... */
  189. #define HAL_ITLINE_FLASH_ITF      ((uint32_t) ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ITF)) /*!< Flash ITF Interrupt */
  190. #define HAL_ITLINE_CRS            ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CRS)) /*!< CRS Interrupt */
  191. #define HAL_ITLINE_CLK_CTRL       ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CLK_CTRL)) /*!< CLK Control Interrupt */
  192. #define HAL_ITLINE_EXTI0          ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI0)) /*!< External Interrupt 0 */
  193. #define HAL_ITLINE_EXTI1          ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI1)) /*!< External Interrupt 1 */
  194. #define HAL_ITLINE_EXTI2          ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI2)) /*!< External Interrupt 2 */
  195. #define HAL_ITLINE_EXTI3          ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI3)) /*!< External Interrupt 3 */
  196. #define HAL_ITLINE_EXTI4          ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI4)) /*!< EXTI4 Interrupt */
  197. #define HAL_ITLINE_EXTI5          ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI5)) /*!< EXTI5 Interrupt */
  198. #define HAL_ITLINE_EXTI6          ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI6)) /*!< EXTI6 Interrupt */
  199. #define HAL_ITLINE_EXTI7          ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI7)) /*!< EXTI7 Interrupt */
  200. #define HAL_ITLINE_EXTI8          ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI8)) /*!< EXTI8 Interrupt */
  201. #define HAL_ITLINE_EXTI9          ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI9)) /*!< EXTI9 Interrupt */
  202. #define HAL_ITLINE_EXTI10         ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI10)) /*!< EXTI10 Interrupt */
  203. #define HAL_ITLINE_EXTI11         ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI11)) /*!< EXTI11 Interrupt */
  204. #define HAL_ITLINE_EXTI12         ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI12)) /*!< EXTI12 Interrupt */
  205. #define HAL_ITLINE_EXTI13         ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI13)) /*!< EXTI13 Interrupt */
  206. #define HAL_ITLINE_EXTI14         ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI14)) /*!< EXTI14 Interrupt */
  207. #define HAL_ITLINE_EXTI15         ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI15)) /*!< EXTI15 Interrupt */
  208. #define HAL_ITLINE_TSC_EOA        ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_TSC_EOA)) /*!< Touch control EOA Interrupt */
  209. #define HAL_ITLINE_TSC_MCE        ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_TSC_MCE)) /*!< Touch control MCE Interrupt */
  210. #define HAL_ITLINE_DMA1_CH1       ((uint32_t) ((HAL_SYSCFG_ITLINE9 << 0x18U) | SYSCFG_ITLINE9_SR_DMA1_CH1)) /*!< DMA1 Channel 1 Interrupt */
  211. #define HAL_ITLINE_DMA1_CH2       ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH2)) /*!< DMA1 Channel 2 Interrupt */
  212. #define HAL_ITLINE_DMA1_CH3       ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH3)) /*!< DMA1 Channel 3 Interrupt */
  213. #define HAL_ITLINE_DMA2_CH1       ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA2_CH1)) /*!< DMA2 Channel 1 Interrupt */
  214. #define HAL_ITLINE_DMA2_CH2       ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA2_CH2)) /*!< DMA2 Channel 2 Interrupt */
  215. #define HAL_ITLINE_DMA1_CH4       ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH4)) /*!< DMA1 Channel 4 Interrupt */
  216. #define HAL_ITLINE_DMA1_CH5       ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH5)) /*!< DMA1 Channel 5 Interrupt */
  217. #define HAL_ITLINE_DMA1_CH6       ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH6)) /*!< DMA1 Channel 6 Interrupt */
  218. #define HAL_ITLINE_DMA1_CH7       ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH7)) /*!< DMA1 Channel 7 Interrupt */
  219. #define HAL_ITLINE_DMA2_CH3       ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH3)) /*!< DMA2 Channel 3 Interrupt */
  220. #define HAL_ITLINE_DMA2_CH4       ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH4)) /*!< DMA2 Channel 4 Interrupt */
  221. #define HAL_ITLINE_DMA2_CH5       ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH5)) /*!< DMA2 Channel 5 Interrupt */
  222. #define HAL_ITLINE_ADC            ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_ADC)) /*!< ADC Interrupt */
  223. #define HAL_ITLINE_COMP1          ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP1)) /*!< COMP1 Interrupt -> exti[21] */
  224. #define HAL_ITLINE_COMP2          ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP2)) /*!< COMP2 Interrupt -> exti[21] */
  225. #define HAL_ITLINE_TIM1_BRK       ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_BRK)) /*!< TIM1 BRK Interrupt */
  226. #define HAL_ITLINE_TIM1_UPD       ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_UPD)) /*!< TIM1 UPD Interrupt */
  227. #define HAL_ITLINE_TIM1_TRG       ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_TRG)) /*!< TIM1 TRG Interrupt */
  228. #define HAL_ITLINE_TIM1_CCU       ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_CCU)) /*!< TIM1 CCU Interrupt */
  229. #define HAL_ITLINE_TIM1_CC        ((uint32_t) ((HAL_SYSCFG_ITLINE14 << 0x18U) | SYSCFG_ITLINE14_SR_TIM1_CC)) /*!< TIM1 CC Interrupt */
  230. #define HAL_ITLINE_TIM2           ((uint32_t) ((HAL_SYSCFG_ITLINE15 << 0x18U) | SYSCFG_ITLINE15_SR_TIM2_GLB)) /*!< TIM2 Interrupt */
  231. #define HAL_ITLINE_TIM3           ((uint32_t) ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM3_GLB)) /*!< TIM3 Interrupt */
  232. #define HAL_ITLINE_DAC            ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_DAC)) /*!< DAC Interrupt */
  233. #define HAL_ITLINE_TIM6           ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_TIM6_GLB)) /*!< TIM6 Interrupt */
  234. #define HAL_ITLINE_TIM7           ((uint32_t) ((HAL_SYSCFG_ITLINE18 << 0x18U) | SYSCFG_ITLINE18_SR_TIM7_GLB)) /*!< TIM7 Interrupt */
  235. #define HAL_ITLINE_TIM14          ((uint32_t) ((HAL_SYSCFG_ITLINE19 << 0x18U) | SYSCFG_ITLINE19_SR_TIM14_GLB)) /*!< TIM14 Interrupt */
  236. #define HAL_ITLINE_TIM15          ((uint32_t) ((HAL_SYSCFG_ITLINE20 << 0x18U) | SYSCFG_ITLINE20_SR_TIM15_GLB)) /*!< TIM15 Interrupt */
  237. #define HAL_ITLINE_TIM16          ((uint32_t) ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_TIM16_GLB)) /*!< TIM16 Interrupt */
  238. #define HAL_ITLINE_TIM17          ((uint32_t) ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_TIM17_GLB)) /*!< TIM17 Interrupt */
  239. #define HAL_ITLINE_I2C1           ((uint32_t) ((HAL_SYSCFG_ITLINE23 << 0x18U) | SYSCFG_ITLINE23_SR_I2C1_GLB)) /*!< I2C1 Interrupt -> exti[23] */
  240. #define HAL_ITLINE_I2C2           ((uint32_t) ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C2_GLB)) /*!< I2C2 Interrupt */
  241. #define HAL_ITLINE_SPI1           ((uint32_t) ((HAL_SYSCFG_ITLINE25 << 0x18U) | SYSCFG_ITLINE25_SR_SPI1)) /*!< I2C1 Interrupt -> exti[23] */
  242. #define HAL_ITLINE_SPI2           ((uint32_t) ((HAL_SYSCFG_ITLINE26 << 0x18U) | SYSCFG_ITLINE26_SR_SPI2)) /*!< SPI1 Interrupt */
  243. #define HAL_ITLINE_USART1         ((uint32_t) ((HAL_SYSCFG_ITLINE27 << 0x18U) | SYSCFG_ITLINE27_SR_USART1_GLB)) /*!< USART1 GLB Interrupt -> exti[25] */
  244. #define HAL_ITLINE_USART2         ((uint32_t) ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_USART2_GLB)) /*!< USART2 GLB Interrupt -> exti[26] */
  245. #define HAL_ITLINE_USART3         ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART3_GLB)) /*!< USART3 Interrupt .... */
  246. #define HAL_ITLINE_USART4         ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART4_GLB)) /*!< USART4 Interrupt .... */
  247. #define HAL_ITLINE_USART5         ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART5_GLB)) /*!< USART5 Interrupt .... */
  248. #define HAL_ITLINE_USART6         ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART6_GLB)) /*!< USART6 Interrupt .... */
  249. #define HAL_ITLINE_USART7         ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART7_GLB)) /*!< USART7 Interrupt .... */
  250. #define HAL_ITLINE_USART8         ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART8_GLB)) /*!< USART8 Interrupt .... */
  251. #define HAL_ITLINE_CAN            ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_CAN)) /*!< CAN Interrupt */
  252. #define HAL_ITLINE_CEC            ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_CEC)) /*!< CEC Interrupt -> exti[27] */
  253. /**
  254.   * @}
  255.   */
  256. #endif /* STM32F091xC || STM32F098xx */
  257.  
  258. /**
  259.   * @}
  260.   */  
  261.  
  262. /* Exported macros -----------------------------------------------------------*/
  263. /** @defgroup HAL_Exported_Macros HAL Exported Macros
  264.   * @{  
  265.   */
  266.  
  267. /** @defgroup HAL_Freeze_Unfreeze_Peripherals HAL Freeze Unfreeze Peripherals
  268.   * @brief  Freeze/Unfreeze Peripherals in Debug mode
  269.   * @{  
  270.   */
  271.  
  272. #if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
  273. #define __HAL_FREEZE_CAN_DBGMCU()            (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP))
  274. #define __HAL_UNFREEZE_CAN_DBGMCU()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP))
  275. #endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */
  276.  
  277. #if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP)
  278. #define __HAL_DBGMCU_FREEZE_RTC()            (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
  279. #define __HAL_DBGMCU_UNFREEZE_RTC()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
  280. #endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */
  281.  
  282. #if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
  283. #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
  284. #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
  285. #endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */
  286.  
  287. #if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP)
  288. #define __HAL_DBGMCU_FREEZE_IWDG()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
  289. #define __HAL_DBGMCU_UNFREEZE_IWDG()         (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
  290. #endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */
  291.  
  292. #if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP)
  293. #define __HAL_DBGMCU_FREEZE_WWDG()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
  294. #define __HAL_DBGMCU_UNFREEZE_WWDG()         (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
  295. #endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */
  296.  
  297. #if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
  298. #define __HAL_DBGMCU_FREEZE_TIM2()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
  299. #define __HAL_DBGMCU_UNFREEZE_TIM2()         (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
  300. #endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */
  301.  
  302. #if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
  303. #define __HAL_DBGMCU_FREEZE_TIM3()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
  304. #define __HAL_DBGMCU_UNFREEZE_TIM3()         (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
  305. #endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */
  306.  
  307. #if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
  308. #define __HAL_DBGMCU_FREEZE_TIM6()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
  309. #define __HAL_DBGMCU_UNFREEZE_TIM6()         (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
  310. #endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */
  311.  
  312. #if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
  313. #define __HAL_DBGMCU_FREEZE_TIM7()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
  314. #define __HAL_DBGMCU_UNFREEZE_TIM7()         (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
  315. #endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */
  316.  
  317. #if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
  318. #define __HAL_DBGMCU_FREEZE_TIM14()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
  319. #define __HAL_DBGMCU_UNFREEZE_TIM14()        (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
  320. #endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
  321.  
  322. #if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
  323. #define __HAL_DBGMCU_FREEZE_TIM1()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
  324. #define __HAL_DBGMCU_UNFREEZE_TIM1()         (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
  325. #endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */
  326.  
  327. #if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP)
  328. #define __HAL_DBGMCU_FREEZE_TIM15()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP))
  329. #define __HAL_DBGMCU_UNFREEZE_TIM15()        (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP))
  330. #endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */
  331.  
  332. #if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP)
  333. #define __HAL_DBGMCU_FREEZE_TIM16()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP))
  334. #define __HAL_DBGMCU_UNFREEZE_TIM16()        (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP))
  335. #endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */
  336.  
  337. #if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP)
  338. #define __HAL_DBGMCU_FREEZE_TIM17()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP))
  339. #define __HAL_DBGMCU_UNFREEZE_TIM17()        (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP))
  340. #endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */
  341.  
  342. /**
  343.   * @}
  344.   */  
  345.  
  346. /** @defgroup Memory_Mapping_Selection Memory Mapping Selection
  347.   * @{  
  348.   */
  349. #if defined(SYSCFG_CFGR1_MEM_MODE)
  350. /** @brief  Main Flash memory mapped at 0x00000000
  351.   */
  352. #define __HAL_SYSCFG_REMAPMEMORY_FLASH()        (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE))
  353. #endif /* SYSCFG_CFGR1_MEM_MODE */
  354.  
  355. #if defined(SYSCFG_CFGR1_MEM_MODE_0)
  356. /** @brief  System Flash memory mapped at 0x00000000
  357.   */
  358. #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH()  do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
  359.                                              SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0;  \
  360.                                             }while(0)
  361. #endif /* SYSCFG_CFGR1_MEM_MODE_0 */
  362.  
  363. #if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1)
  364. /** @brief  Embedded SRAM mapped at 0x00000000
  365.   */
  366. #define __HAL_SYSCFG_REMAPMEMORY_SRAM()         do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
  367.                                              SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \
  368.                                             }while(0)
  369. #endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */
  370. /**
  371.   * @}
  372.   */
  373.  
  374.  
  375. #if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
  376. /** @defgroup HAL_Pin_remap HAL Pin remap
  377.   * @brief  Pin remapping enable/disable macros
  378.   * @param __PIN_REMAP__ This parameter can be a value of @ref HAL_Pin_remapping
  379.   * @{  
  380.   */
  381. #define __HAL_REMAP_PIN_ENABLE(__PIN_REMAP__)          do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__)));                 \
  382.                                                            SYSCFG->CFGR1 |= (__PIN_REMAP__);                                \
  383.                                                          }while(0)
  384. #define __HAL_REMAP_PIN_DISABLE(__PIN_REMAP__)         do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__)));                 \
  385.                                                            SYSCFG->CFGR1 &= ~(__PIN_REMAP__);                               \
  386.                                                          }while(0)
  387. /**
  388.   * @}
  389.   */  
  390. #endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
  391.  
  392. /** @brief  Fast-mode Plus driving capability enable/disable macros
  393.   * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO values.
  394.   *                          That you can find above these macros.
  395.   */
  396. #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)  do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
  397.                                                                 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
  398.                                                                }while(0)
  399.  
  400. #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
  401.                                                                 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
  402.                                                                }while(0)
  403. #if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
  404. /** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable
  405.   * @{  
  406.   */
  407. /** @brief  SYSCFG Break Lockup lock
  408.   *         Enables and locks the connection of Cortex-M0 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input
  409.   * @note   The selected configuration is locked and can be unlocked by system reset
  410.   */
  411. #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK()   do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
  412.                                                SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK;    \
  413.                                               }while(0)
  414. /**
  415.   * @}
  416.   */  
  417. #endif /* SYSCFG_CFGR2_LOCKUP_LOCK */
  418.  
  419. #if defined(SYSCFG_CFGR2_PVD_LOCK)
  420. /** @defgroup PVD_Lock_Enable PVD Lock
  421.   * @{  
  422.   */
  423. /** @brief  SYSCFG Break PVD lock
  424.   *         Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register
  425.   * @note   The selected configuration is locked and can be unlocked by system reset
  426.   */
  427. #define __HAL_SYSCFG_BREAK_PVD_LOCK()      do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
  428.                                                SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK;    \
  429.                                               }while(0)
  430. /**
  431.   * @}
  432.   */
  433. #endif /* SYSCFG_CFGR2_PVD_LOCK */
  434.  
  435. #if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
  436. /** @defgroup SRAM_Parity_Lock SRAM Parity Lock
  437.   * @{
  438.   */
  439. /** @brief  SYSCFG Break SRAM PARITY lock
  440.   *         Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17
  441.   * @note   The selected configuration is locked and can be unlocked by system reset
  442.   */
  443. #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \
  444.                                                  SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK;    \
  445.                                                 }while(0)
  446. /**
  447.   * @}
  448.   */
  449. #endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */
  450.  
  451. #if defined(SYSCFG_CFGR2_SRAM_PEF)
  452. /** @defgroup HAL_SYSCFG_Parity_check_on_RAM HAL SYSCFG Parity check on RAM
  453.   * @brief  Parity check on RAM disable macro
  454.   * @note   Disabling the parity check on RAM locks the configuration bit.
  455.   *         To re-enable the parity check on RAM perform a system reset.
  456.   * @{  
  457.   */
  458. #define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE()   (SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PEF)
  459. /**
  460.   * @}
  461.   */
  462. #endif /* SYSCFG_CFGR2_SRAM_PEF */
  463.  
  464.  
  465. #if defined(STM32F091xC) || defined (STM32F098xx)
  466. /** @defgroup HAL_ISR_wrapper_check HAL ISR wrapper check
  467.   * @brief  ISR wrapper check
  468.   * @note This feature is applicable on STM32F09x  
  469.   * @note Allow to determine interrupt source per line.
  470.   * @{  
  471.   */
  472. #define __HAL_GET_PENDING_IT(__SOURCE__)       (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFF))
  473. /**
  474.   * @}
  475.   */
  476. #endif /* (STM32F091xC) || defined (STM32F098xx)*/
  477.  
  478. #if defined(STM32F091xC) || defined (STM32F098xx)
  479. /** @defgroup HAL_SYSCFG_IRDA_modulation_envelope_selection HAL SYSCFG IRDA modulation envelope selection
  480.   * @brief  selection of the modulation envelope signal macro, using bits [7:6] of SYS_CTRL(CFGR1) register
  481.   * @note This feature is applicable on STM32F09x
  482.   * @param __SOURCE__ This parameter can be a value of @ref HAL_IRDA_ENV_SEL
  483.   * @{  
  484.   */
  485. #define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__)  do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__))); \
  486.                                                          SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_IRDA_ENV_SEL); \
  487.                                                          SYSCFG->CFGR1 |= (__SOURCE__);    \
  488.                                                         }while(0)
  489.  
  490. #define __HAL_SYSCFG_GET_IRDA_ENV_SELECTION()  ((SYSCFG->CFGR1) & 0x000000C0)
  491. /**
  492.   * @}
  493.   */
  494. #endif /* (STM32F091xC) || defined (STM32F098xx)*/
  495.  
  496. /**
  497.   * @}
  498.   */
  499.  
  500. /** @defgroup HAL_Private_Macros HAL Private Macros
  501.   * @{
  502.   */
  503. #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ)  || \
  504.                            ((FREQ) == HAL_TICK_FREQ_100HZ) || \
  505.                            ((FREQ) == HAL_TICK_FREQ_1KHZ))
  506. /**
  507.   * @}
  508.   */
  509.  
  510. /* Exported functions --------------------------------------------------------*/
  511.  
  512. /** @addtogroup HAL_Exported_Functions
  513.   * @{
  514.   */
  515.  
  516. /** @addtogroup HAL_Exported_Functions_Group1
  517.   * @{
  518.   */    
  519. /* Initialization and de-initialization functions  ******************************/
  520. HAL_StatusTypeDef HAL_Init(void);
  521. HAL_StatusTypeDef HAL_DeInit(void);
  522. void              HAL_MspInit(void);
  523. void              HAL_MspDeInit(void);
  524. HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
  525. /**
  526.   * @}
  527.   */
  528.  
  529. /* Exported variables ---------------------------------------------------------*/
  530. /** @addtogroup HAL_Exported_Variables
  531.   * @{
  532.   */
  533. extern __IO uint32_t uwTick;
  534. extern uint32_t uwTickPrio;
  535. extern HAL_TickFreqTypeDef uwTickFreq;
  536. /**
  537.   * @}
  538.   */
  539.  
  540. /** @addtogroup HAL_Exported_Functions_Group2
  541.   * @{
  542.   */    
  543.  
  544. /* Peripheral Control functions  ************************************************/
  545. void                HAL_IncTick(void);
  546. void                HAL_Delay(uint32_t Delay);
  547. uint32_t            HAL_GetTick(void);
  548. uint32_t            HAL_GetTickPrio(void);
  549. HAL_StatusTypeDef   HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
  550. HAL_TickFreqTypeDef HAL_GetTickFreq(void);
  551. void                HAL_SuspendTick(void);
  552. void                HAL_ResumeTick(void);
  553. uint32_t            HAL_GetHalVersion(void);
  554. uint32_t            HAL_GetREVID(void);
  555. uint32_t            HAL_GetDEVID(void);
  556. uint32_t            HAL_GetUIDw0(void);
  557. uint32_t            HAL_GetUIDw1(void);
  558. uint32_t            HAL_GetUIDw2(void);
  559. void                HAL_DBGMCU_EnableDBGStopMode(void);
  560. void                HAL_DBGMCU_DisableDBGStopMode(void);
  561. void                HAL_DBGMCU_EnableDBGStandbyMode(void);
  562. void                HAL_DBGMCU_DisableDBGStandbyMode(void);
  563. /**
  564.   * @}
  565.   */
  566.  
  567. /**
  568.   * @}
  569.   */
  570.  
  571. /**
  572.   * @}
  573.   */
  574.  
  575. /**
  576.   * @}
  577.   */
  578.  
  579. #ifdef __cplusplus
  580. }
  581. #endif
  582.  
  583. #endif /* __STM32F0xx_HAL_H */
  584.  
  585. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  586.