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  1. /**************************************************************************//**
  2.  * @file     irq_ctrl.h
  3.  * @brief    Interrupt Controller API header file
  4.  * @version  V1.0.0
  5.  * @date     23. June 2017
  6.  ******************************************************************************/
  7. /*
  8.  * Copyright (c) 2017 ARM Limited. All rights reserved.
  9.  *
  10.  * SPDX-License-Identifier: Apache-2.0
  11.  *
  12.  * Licensed under the Apache License, Version 2.0 (the License); you may
  13.  * not use this file except in compliance with the License.
  14.  * You may obtain a copy of the License at
  15.  *
  16.  * www.apache.org/licenses/LICENSE-2.0
  17.  *
  18.  * Unless required by applicable law or agreed to in writing, software
  19.  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  20.  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  21.  * See the License for the specific language governing permissions and
  22.  * limitations under the License.
  23.  */
  24.  
  25. #if   defined ( __ICCARM__ )
  26.   #pragma system_include         /* treat file as system include file for MISRA check */
  27. #elif defined (__clang__)
  28.   #pragma clang system_header   /* treat file as system include file */
  29. #endif
  30.  
  31. #ifndef IRQ_CTRL_H_
  32. #define IRQ_CTRL_H_
  33.  
  34. #include <stdint.h>
  35.  
  36. #ifndef IRQHANDLER_T
  37. #define IRQHANDLER_T
  38. /// Interrupt handler data type
  39. typedef void (*IRQHandler_t) (void);
  40. #endif
  41.  
  42. #ifndef IRQN_ID_T
  43. #define IRQN_ID_T
  44. /// Interrupt ID number data type
  45. typedef int32_t IRQn_ID_t;
  46. #endif
  47.  
  48. /* Interrupt mode bit-masks */
  49. #define IRQ_MODE_TRIG_Pos           (0U)
  50. #define IRQ_MODE_TRIG_Msk           (0x07UL /*<< IRQ_MODE_TRIG_Pos*/)
  51. #define IRQ_MODE_TRIG_LEVEL         (0x00UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: level triggered interrupt
  52. #define IRQ_MODE_TRIG_LEVEL_LOW     (0x01UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: low level triggered interrupt
  53. #define IRQ_MODE_TRIG_LEVEL_HIGH    (0x02UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: high level triggered interrupt
  54. #define IRQ_MODE_TRIG_EDGE          (0x04UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: edge triggered interrupt
  55. #define IRQ_MODE_TRIG_EDGE_RISING   (0x05UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising edge triggered interrupt
  56. #define IRQ_MODE_TRIG_EDGE_FALLING  (0x06UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: falling edge triggered interrupt
  57. #define IRQ_MODE_TRIG_EDGE_BOTH     (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising and falling edge triggered interrupt
  58.  
  59. #define IRQ_MODE_TYPE_Pos           (3U)
  60. #define IRQ_MODE_TYPE_Msk           (0x01UL << IRQ_MODE_TYPE_Pos)
  61. #define IRQ_MODE_TYPE_IRQ           (0x00UL << IRQ_MODE_TYPE_Pos)     ///< Type: interrupt source triggers CPU IRQ line
  62. #define IRQ_MODE_TYPE_FIQ           (0x01UL << IRQ_MODE_TYPE_Pos)     ///< Type: interrupt source triggers CPU FIQ line
  63.  
  64. #define IRQ_MODE_DOMAIN_Pos         (4U)
  65. #define IRQ_MODE_DOMAIN_Msk         (0x01UL << IRQ_MODE_DOMAIN_Pos)
  66. #define IRQ_MODE_DOMAIN_NONSECURE   (0x00UL << IRQ_MODE_DOMAIN_Pos)   ///< Domain: interrupt is targeting non-secure domain
  67. #define IRQ_MODE_DOMAIN_SECURE      (0x01UL << IRQ_MODE_DOMAIN_Pos)   ///< Domain: interrupt is targeting secure domain
  68.  
  69. #define IRQ_MODE_CPU_Pos            (5U)
  70. #define IRQ_MODE_CPU_Msk            (0xFFUL << IRQ_MODE_CPU_Pos)
  71. #define IRQ_MODE_CPU_ALL            (0x00UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets all CPUs
  72. #define IRQ_MODE_CPU_0              (0x01UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 0
  73. #define IRQ_MODE_CPU_1              (0x02UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 1
  74. #define IRQ_MODE_CPU_2              (0x04UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 2
  75. #define IRQ_MODE_CPU_3              (0x08UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 3
  76. #define IRQ_MODE_CPU_4              (0x10UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 4
  77. #define IRQ_MODE_CPU_5              (0x20UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 5
  78. #define IRQ_MODE_CPU_6              (0x40UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 6
  79. #define IRQ_MODE_CPU_7              (0x80UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 7
  80.  
  81. #define IRQ_MODE_ERROR              (0x80000000UL)                    ///< Bit indicating mode value error
  82.  
  83. /* Interrupt priority bit-masks */
  84. #define IRQ_PRIORITY_Msk            (0x0000FFFFUL)                    ///< Interrupt priority value bit-mask
  85. #define IRQ_PRIORITY_ERROR          (0x80000000UL)                    ///< Bit indicating priority value error
  86.  
  87. /// Initialize interrupt controller.
  88. /// \return 0 on success, -1 on error.
  89. int32_t IRQ_Initialize (void);
  90.  
  91. /// Register interrupt handler.
  92. /// \param[in]     irqn          interrupt ID number
  93. /// \param[in]     handler       interrupt handler function address
  94. /// \return 0 on success, -1 on error.
  95. int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler);
  96.  
  97. /// Get the registered interrupt handler.
  98. /// \param[in]     irqn          interrupt ID number
  99. /// \return registered interrupt handler function address.
  100. IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn);
  101.  
  102. /// Enable interrupt.
  103. /// \param[in]     irqn          interrupt ID number
  104. /// \return 0 on success, -1 on error.
  105. int32_t IRQ_Enable (IRQn_ID_t irqn);
  106.  
  107. /// Disable interrupt.
  108. /// \param[in]     irqn          interrupt ID number
  109. /// \return 0 on success, -1 on error.
  110. int32_t IRQ_Disable (IRQn_ID_t irqn);
  111.  
  112. /// Get interrupt enable state.
  113. /// \param[in]     irqn          interrupt ID number
  114. /// \return 0 - interrupt is disabled, 1 - interrupt is enabled.
  115. uint32_t IRQ_GetEnableState (IRQn_ID_t irqn);
  116.  
  117. /// Configure interrupt request mode.
  118. /// \param[in]     irqn          interrupt ID number
  119. /// \param[in]     mode          mode configuration
  120. /// \return 0 on success, -1 on error.
  121. int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode);
  122.  
  123. /// Get interrupt mode configuration.
  124. /// \param[in]     irqn          interrupt ID number
  125. /// \return current interrupt mode configuration with optional IRQ_MODE_ERROR bit set.
  126. uint32_t IRQ_GetMode (IRQn_ID_t irqn);
  127.  
  128. /// Get ID number of current interrupt request (IRQ).
  129. /// \return interrupt ID number.
  130. IRQn_ID_t IRQ_GetActiveIRQ (void);
  131.  
  132. /// Get ID number of current fast interrupt request (FIQ).
  133. /// \return interrupt ID number.
  134. IRQn_ID_t IRQ_GetActiveFIQ (void);
  135.  
  136. /// Signal end of interrupt processing.
  137. /// \param[in]     irqn          interrupt ID number
  138. /// \return 0 on success, -1 on error.
  139. int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn);
  140.  
  141. /// Set interrupt pending flag.
  142. /// \param[in]     irqn          interrupt ID number
  143. /// \return 0 on success, -1 on error.
  144. int32_t IRQ_SetPending (IRQn_ID_t irqn);
  145.  
  146. /// Get interrupt pending flag.
  147. /// \param[in]     irqn          interrupt ID number
  148. /// \return 0 - interrupt is not pending, 1 - interrupt is pending.
  149. uint32_t IRQ_GetPending (IRQn_ID_t irqn);
  150.  
  151. /// Clear interrupt pending flag.
  152. /// \param[in]     irqn          interrupt ID number
  153. /// \return 0 on success, -1 on error.
  154. int32_t IRQ_ClearPending (IRQn_ID_t irqn);
  155.  
  156. /// Set interrupt priority value.
  157. /// \param[in]     irqn          interrupt ID number
  158. /// \param[in]     priority      interrupt priority value
  159. /// \return 0 on success, -1 on error.
  160. int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority);
  161.  
  162. /// Get interrupt priority.
  163. /// \param[in]     irqn          interrupt ID number
  164. /// \return current interrupt priority value with optional IRQ_PRIORITY_ERROR bit set.
  165. uint32_t IRQ_GetPriority (IRQn_ID_t irqn);
  166.  
  167. /// Set priority masking threshold.
  168. /// \param[in]     priority      priority masking threshold value
  169. /// \return 0 on success, -1 on error.
  170. int32_t IRQ_SetPriorityMask (uint32_t priority);
  171.  
  172. /// Get priority masking threshold
  173. /// \return current priority masking threshold value with optional IRQ_PRIORITY_ERROR bit set.
  174. uint32_t IRQ_GetPriorityMask (void);
  175.  
  176. /// Set priority grouping field split point
  177. /// \param[in]     bits          number of MSB bits included in the group priority field comparison
  178. /// \return 0 on success, -1 on error.
  179. int32_t IRQ_SetPriorityGroupBits (uint32_t bits);
  180.  
  181. /// Get priority grouping field split point
  182. /// \return current number of MSB bits included in the group priority field comparison with
  183. ///         optional IRQ_PRIORITY_ERROR bit set.
  184. uint32_t IRQ_GetPriorityGroupBits (void);
  185.  
  186. #endif  // IRQ_CTRL_H_
  187.