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  1. /**
  2.   ******************************************************************************
  3.   * @file    system_stm32f1xx.c
  4.   * @author  MCD Application Team
  5.   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
  6.   *
  7.   * 1.  This file provides two functions and one global variable to be called from
  8.   *     user application:
  9.   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
  10.   *                      factors, AHB/APBx prescalers and Flash settings).
  11.   *                      This function is called at startup just after reset and
  12.   *                      before branch to main program. This call is made inside
  13.   *                      the "startup_stm32f1xx_xx.s" file.
  14.   *
  15.   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
  16.   *                                  by the user application to setup the SysTick
  17.   *                                  timer or configure other parameters.
  18.   *                                    
  19.   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
  20.   *                                 be called whenever the core clock is changed
  21.   *                                 during program execution.
  22.   *
  23.   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
  24.   *    Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to
  25.   *    configure the system clock before to branch to main program.
  26.   *
  27.   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on
  28.   *    the product used), refer to "HSE_VALUE".
  29.   *    When HSE is used as system clock source, directly or through PLL, and you
  30.   *    are using different crystal you have to adapt the HSE value to your own
  31.   *    configuration.
  32.   *        
  33.   ******************************************************************************
  34.   * @attention
  35.   *
  36.   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  37.   * All rights reserved.</center></h2>
  38.   *
  39.   * This software component is licensed by ST under BSD 3-Clause license,
  40.   * the "License"; You may not use this file except in compliance with the
  41.   * License. You may obtain a copy of the License at:
  42.   *                        opensource.org/licenses/BSD-3-Clause
  43.   *
  44.   ******************************************************************************
  45.   */
  46.  
  47. /** @addtogroup CMSIS
  48.   * @{
  49.   */
  50.  
  51. /** @addtogroup stm32f1xx_system
  52.   * @{
  53.   */  
  54.  
  55. /** @addtogroup STM32F1xx_System_Private_Includes
  56.   * @{
  57.   */
  58.  
  59. #include "stm32f1xx.h"
  60.  
  61. /**
  62.   * @}
  63.   */
  64.  
  65. /** @addtogroup STM32F1xx_System_Private_TypesDefinitions
  66.   * @{
  67.   */
  68.  
  69. /**
  70.   * @}
  71.   */
  72.  
  73. /** @addtogroup STM32F1xx_System_Private_Defines
  74.   * @{
  75.   */
  76.  
  77. #if !defined  (HSE_VALUE)
  78.   #define HSE_VALUE               8000000U /*!< Default value of the External oscillator in Hz.
  79.                                                 This value can be provided and adapted by the user application. */
  80. #endif /* HSE_VALUE */
  81.  
  82. #if !defined  (HSI_VALUE)
  83.   #define HSI_VALUE               8000000U /*!< Default value of the Internal oscillator in Hz.
  84.                                                 This value can be provided and adapted by the user application. */
  85. #endif /* HSI_VALUE */
  86.  
  87. /*!< Uncomment the following line if you need to use external SRAM  */
  88. #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
  89. /* #define DATA_IN_ExtSRAM */
  90. #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
  91.  
  92. /* Note: Following vector table addresses must be defined in line with linker
  93.          configuration. */
  94. /*!< Uncomment the following line if you need to relocate the vector table
  95.      anywhere in Flash or Sram, else the vector table is kept at the automatic
  96.      remap of boot address selected */
  97. /* #define USER_VECT_TAB_ADDRESS */
  98.  
  99. #if defined(USER_VECT_TAB_ADDRESS)
  100. /*!< Uncomment the following line if you need to relocate your vector Table
  101.      in Sram else user remap will be done in Flash. */
  102. /* #define VECT_TAB_SRAM */
  103. #if defined(VECT_TAB_SRAM)
  104. #define VECT_TAB_BASE_ADDRESS   SRAM_BASE       /*!< Vector Table base address field.
  105.                                                      This value must be a multiple of 0x200. */
  106. #define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
  107.                                                      This value must be a multiple of 0x200. */
  108. #else
  109. #define VECT_TAB_BASE_ADDRESS   FLASH_BASE      /*!< Vector Table base address field.
  110.                                                      This value must be a multiple of 0x200. */
  111. #define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
  112.                                                      This value must be a multiple of 0x200. */
  113. #endif /* VECT_TAB_SRAM */
  114. #endif /* USER_VECT_TAB_ADDRESS */
  115.  
  116. /******************************************************************************/
  117.  
  118. /**
  119.   * @}
  120.   */
  121.  
  122. /** @addtogroup STM32F1xx_System_Private_Macros
  123.   * @{
  124.   */
  125.  
  126. /**
  127.   * @}
  128.   */
  129.  
  130. /** @addtogroup STM32F1xx_System_Private_Variables
  131.   * @{
  132.   */
  133.  
  134.   /* This variable is updated in three ways:
  135.       1) by calling CMSIS function SystemCoreClockUpdate()
  136.       2) by calling HAL API function HAL_RCC_GetHCLKFreq()
  137.       3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
  138.          Note: If you use this function to configure the system clock; then there
  139.                is no need to call the 2 first functions listed above, since SystemCoreClock
  140.                variable is updated automatically.
  141.   */
  142. uint32_t SystemCoreClock = 16000000;
  143. const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
  144. const uint8_t APBPrescTable[8U] =  {0, 0, 0, 0, 1, 2, 3, 4};
  145.  
  146. /**
  147.   * @}
  148.   */
  149.  
  150. /** @addtogroup STM32F1xx_System_Private_FunctionPrototypes
  151.   * @{
  152.   */
  153.  
  154. #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
  155. #ifdef DATA_IN_ExtSRAM
  156.   static void SystemInit_ExtMemCtl(void);
  157. #endif /* DATA_IN_ExtSRAM */
  158. #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
  159.  
  160. /**
  161.   * @}
  162.   */
  163.  
  164. /** @addtogroup STM32F1xx_System_Private_Functions
  165.   * @{
  166.   */
  167.  
  168. /**
  169.   * @brief  Setup the microcontroller system
  170.   *         Initialize the Embedded Flash Interface, the PLL and update the
  171.   *         SystemCoreClock variable.
  172.   * @note   This function should be used only after reset.
  173.   * @param  None
  174.   * @retval None
  175.   */
  176. void SystemInit (void)
  177. {
  178. #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
  179.   #ifdef DATA_IN_ExtSRAM
  180.     SystemInit_ExtMemCtl();
  181.   #endif /* DATA_IN_ExtSRAM */
  182. #endif
  183.  
  184.   /* Configure the Vector Table location -------------------------------------*/
  185. #if defined(USER_VECT_TAB_ADDRESS)
  186.   SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
  187. #endif /* USER_VECT_TAB_ADDRESS */
  188. }
  189.  
  190. /**
  191.   * @brief  Update SystemCoreClock variable according to Clock Register Values.
  192.   *         The SystemCoreClock variable contains the core clock (HCLK), it can
  193.   *         be used by the user application to setup the SysTick timer or configure
  194.   *         other parameters.
  195.   *          
  196.   * @note   Each time the core clock (HCLK) changes, this function must be called
  197.   *         to update SystemCoreClock variable value. Otherwise, any configuration
  198.   *         based on this variable will be incorrect.        
  199.   *    
  200.   * @note   - The system frequency computed by this function is not the real
  201.   *           frequency in the chip. It is calculated based on the predefined
  202.   *           constant and the selected clock source:
  203.   *            
  204.   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
  205.   *                                              
  206.   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
  207.   *                          
  208.   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
  209.   *             or HSI_VALUE(*) multiplied by the PLL factors.
  210.   *        
  211.   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
  212.   *             8 MHz) but the real value may vary depending on the variations
  213.   *             in voltage and temperature.  
  214.   *    
  215.   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
  216.   *              8 MHz or 25 MHz, depending on the product used), user has to ensure
  217.   *              that HSE_VALUE is same as the real frequency of the crystal used.
  218.   *              Otherwise, this function may have wrong result.
  219.   *                
  220.   *         - The result of this function could be not correct when using fractional
  221.   *           value for HSE crystal.
  222.   * @param  None
  223.   * @retval None
  224.   */
  225. void SystemCoreClockUpdate (void)
  226. {
  227.   uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U;
  228.  
  229. #if defined(STM32F105xC) || defined(STM32F107xC)
  230.   uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U;
  231. #endif /* STM32F105xC */
  232.  
  233. #if defined(STM32F100xB) || defined(STM32F100xE)
  234.   uint32_t prediv1factor = 0U;
  235. #endif /* STM32F100xB or STM32F100xE */
  236.    
  237.   /* Get SYSCLK source -------------------------------------------------------*/
  238.   tmp = RCC->CFGR & RCC_CFGR_SWS;
  239.  
  240.   switch (tmp)
  241.   {
  242.     case 0x00U:  /* HSI used as system clock */
  243.       SystemCoreClock = HSI_VALUE;
  244.       break;
  245.     case 0x04U:  /* HSE used as system clock */
  246.       SystemCoreClock = HSE_VALUE;
  247.       break;
  248.     case 0x08U:  /* PLL used as system clock */
  249.  
  250.       /* Get PLL clock source and multiplication factor ----------------------*/
  251.       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
  252.       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
  253.      
  254. #if !defined(STM32F105xC) && !defined(STM32F107xC)      
  255.       pllmull = ( pllmull >> 18U) + 2U;
  256.      
  257.       if (pllsource == 0x00U)
  258.       {
  259.         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
  260.         SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
  261.       }
  262.       else
  263.       {
  264.  #if defined(STM32F100xB) || defined(STM32F100xE)
  265.        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
  266.        /* HSE oscillator clock selected as PREDIV1 clock entry */
  267.        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
  268.  #else
  269.         /* HSE selected as PLL clock entry */
  270.         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
  271.         {/* HSE oscillator clock divided by 2 */
  272.           SystemCoreClock = (HSE_VALUE >> 1U) * pllmull;
  273.         }
  274.         else
  275.         {
  276.           SystemCoreClock = HSE_VALUE * pllmull;
  277.         }
  278.  #endif
  279.       }
  280. #else
  281.       pllmull = pllmull >> 18U;
  282.      
  283.       if (pllmull != 0x0DU)
  284.       {
  285.          pllmull += 2U;
  286.       }
  287.       else
  288.       { /* PLL multiplication factor = PLL input clock * 6.5 */
  289.         pllmull = 13U / 2U;
  290.       }
  291.            
  292.       if (pllsource == 0x00U)
  293.       {
  294.         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
  295.         SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
  296.       }
  297.       else
  298.       {/* PREDIV1 selected as PLL clock entry */
  299.        
  300.         /* Get PREDIV1 clock source and division factor */
  301.         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
  302.         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
  303.        
  304.         if (prediv1source == 0U)
  305.         {
  306.           /* HSE oscillator clock selected as PREDIV1 clock entry */
  307.           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
  308.         }
  309.         else
  310.         {/* PLL2 clock selected as PREDIV1 clock entry */
  311.          
  312.           /* Get PREDIV2 division factor and PLL2 multiplication factor */
  313.           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U;
  314.           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U;
  315.           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                        
  316.         }
  317.       }
  318. #endif /* STM32F105xC */
  319.       break;
  320.  
  321.     default:
  322.       SystemCoreClock = HSI_VALUE;
  323.       break;
  324.   }
  325.  
  326.   /* Compute HCLK clock frequency ----------------*/
  327.   /* Get HCLK prescaler */
  328.   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
  329.   /* HCLK clock frequency */
  330.   SystemCoreClock >>= tmp;  
  331. }
  332.  
  333. #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
  334. /**
  335.   * @brief  Setup the external memory controller. Called in startup_stm32f1xx.s
  336.   *          before jump to __main
  337.   * @param  None
  338.   * @retval None
  339.   */
  340. #ifdef DATA_IN_ExtSRAM
  341. /**
  342.   * @brief  Setup the external memory controller.
  343.   *         Called in startup_stm32f1xx_xx.s/.c before jump to main.
  344.   *         This function configures the external SRAM mounted on STM3210E-EVAL
  345.   *         board (STM32 High density devices). This SRAM will be used as program
  346.   *         data memory (including heap and stack).
  347.   * @param  None
  348.   * @retval None
  349.   */
  350. void SystemInit_ExtMemCtl(void)
  351. {
  352.   __IO uint32_t tmpreg;
  353.   /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
  354.     required, then adjust the Register Addresses */
  355.  
  356.   /* Enable FSMC clock */
  357.   RCC->AHBENR = 0x00000114U;
  358.  
  359.   /* Delay after an RCC peripheral clock enabling */
  360.   tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
  361.  
  362.   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
  363.   RCC->APB2ENR = 0x000001E0U;
  364.  
  365.   /* Delay after an RCC peripheral clock enabling */
  366.   tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);
  367.  
  368.   (void)(tmpreg);
  369.  
  370. /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
  371. /*----------------  SRAM Address lines configuration -------------------------*/
  372. /*----------------  NOE and NWE configuration --------------------------------*/  
  373. /*----------------  NE3 configuration ----------------------------------------*/
  374. /*----------------  NBL0, NBL1 configuration ---------------------------------*/
  375.  
  376.   GPIOD->CRL = 0x44BB44BBU;  
  377.   GPIOD->CRH = 0xBBBBBBBBU;
  378.  
  379.   GPIOE->CRL = 0xB44444BBU;  
  380.   GPIOE->CRH = 0xBBBBBBBBU;
  381.  
  382.   GPIOF->CRL = 0x44BBBBBBU;  
  383.   GPIOF->CRH = 0xBBBB4444U;
  384.  
  385.   GPIOG->CRL = 0x44BBBBBBU;  
  386.   GPIOG->CRH = 0x444B4B44U;
  387.    
  388. /*----------------  FSMC Configuration ---------------------------------------*/  
  389. /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
  390.  
  391.   FSMC_Bank1->BTCR[4U] = 0x00001091U;
  392.   FSMC_Bank1->BTCR[5U] = 0x00110212U;
  393. }
  394. #endif /* DATA_IN_ExtSRAM */
  395. #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
  396.  
  397. /**
  398.   * @}
  399.   */
  400.  
  401. /**
  402.   * @}
  403.   */
  404.  
  405. /**
  406.   * @}
  407.   */    
  408. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  409.