/* $Header: c:/cvsroot/bart/rt_int.h,v 1.4 2004/03/10 20:13:45 mjames Exp $ */
/*
* $Log: rt_int.h,v $
* Revision 1.4 2004/03/10 20:13:45 mjames
* Correcting hard flow
*
* Revision 1.3 2004/03/09 22:09:10 mjames
* Hardware flow control implemented
*
* Revision 1.2 2004/03/06 12:17:48 mjames
* Moved headers around, made it clearer that there are no configurable
* parts to the OS unless it is rebuilt
*
*/
/************************************************************************/
/** CPU clock */
#define SYSCLK 11052000
/** Option for X2 mode */
#define CPU_IS_X2
/** Option for serial */
#define SERIAL_IS_X2
/******************************************************************************/
/* the serial rates */
/** The full duplex interface can do */
#define SIO1_BAUD 19200
/** The half duplex interface */
#define SIO2_BAUD 4800
#undef SIO2_TX_EN /**< If turned on then the SIO2 will be a half duplex port */
/******************************************************************************/
/* Pin assignments on processor */
#undef SOFT_FLOW /**< If fdefined use XON/XOFF */
#define HARD_FLOW /**< If defined then use RTS/CTS */
#define SIO1_TXD TXD /**< This pin MUST remain fixed here */
#define SIO1_RXD RXD /**< This pin MUST remain fixed here */
/* flow control pin functions to do with serial */
#if defined HARD_FLOW
#define SIO1_CTS P1_5 /**< flow out: This pin can be redefined */
#define SIO1_RTS P1_4 /**< flow in : This pin can be redefined */
#endif
#define SIO2_RXD P1_1 /**< This pin MUST remain fixed here */
#define SIO2_TXD P1_6 /**< This pin can be redefined */
#define PRESCALE (SYSCLK/(32*6))
#define PRESCALE2 (SYSCLK/(12))