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  1. /* $Header: c:/cvsroot/bart/rt_int.h,v 1.4 2004/03/10 20:13:45 mjames Exp $ */
  2. /*
  3.  * $Log: rt_int.h,v $
  4.  * Revision 1.4  2004/03/10 20:13:45  mjames
  5.  * Correcting hard flow
  6.  *
  7.  * Revision 1.3  2004/03/09 22:09:10  mjames
  8.  * Hardware flow control implemented
  9.  *
  10.  * Revision 1.2  2004/03/06 12:17:48  mjames
  11.  * Moved headers around, made it clearer that there are no configurable
  12.  * parts to the OS unless it is rebuilt
  13.  *
  14.  */
  15.  
  16. /************************************************************************/
  17.  
  18. /** CPU clock */
  19. #define SYSCLK 11052000
  20. /** Option for X2 mode */
  21. #define CPU_IS_X2
  22. /** Option for serial */
  23. #define SERIAL_IS_X2
  24.  
  25. /******************************************************************************/
  26.  
  27. /* the serial rates */
  28. /** The full duplex interface can do  */
  29. #define SIO1_BAUD 19200
  30.  
  31. /** The half duplex interface */
  32. #define SIO2_BAUD 4800
  33. #undef  SIO2_TX_EN /**< If turned on then the SIO2 will be a half duplex port */
  34.  
  35. /******************************************************************************/
  36. /* Pin assignments on processor */
  37.  
  38. #undef   SOFT_FLOW   /**< If fdefined use XON/XOFF */
  39. #define  HARD_FLOW   /**< If defined then use RTS/CTS */
  40.  
  41. #define SIO1_TXD       TXD /**< This pin MUST remain fixed here */
  42. #define SIO1_RXD       RXD /**< This pin MUST remain fixed here */
  43.  
  44. /* flow control pin functions to do with serial */
  45. #if defined HARD_FLOW
  46. #define SIO1_CTS       P1_5 /**< flow out: This pin can be redefined */
  47. #define SIO1_RTS       P1_4 /**< flow in : This pin can be redefined */
  48. #endif
  49.  
  50. #define SIO2_RXD     P1_1 /**< This pin MUST remain fixed here */
  51. #define SIO2_TXD     P1_6 /**< This pin can be redefined */
  52.  
  53.  
  54. #define PRESCALE  (SYSCLK/(32*6))
  55.  
  56. #define PRESCALE2 (SYSCLK/(12))
  57.  
  58.