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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32l1xx_hal.h
  4.   * @author  MCD Application Team
  5.   * @version V1.2.0
  6.   * @date    01-July-2016
  7.   * @brief   This file contains all the functions prototypes for the HAL
  8.   *          module driver.
  9.   ******************************************************************************
  10.   * @attention
  11.   *
  12.   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  13.   *
  14.   * Redistribution and use in source and binary forms, with or without modification,
  15.   * are permitted provided that the following conditions are met:
  16.   *   1. Redistributions of source code must retain the above copyright notice,
  17.   *      this list of conditions and the following disclaimer.
  18.   *   2. Redistributions in binary form must reproduce the above copyright notice,
  19.   *      this list of conditions and the following disclaimer in the documentation
  20.   *      and/or other materials provided with the distribution.
  21.   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  22.   *      may be used to endorse or promote products derived from this software
  23.   *      without specific prior written permission.
  24.   *
  25.   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  26.   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  27.   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  28.   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  29.   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  30.   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  31.   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  32.   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  33.   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  34.   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35.   *
  36.   ******************************************************************************
  37.   */
  38.  
  39. /* Define to prevent recursive inclusion -------------------------------------*/
  40. #ifndef __STM32L1xx_HAL_H
  41. #define __STM32L1xx_HAL_H
  42.  
  43. #ifdef __cplusplus
  44.  extern "C" {
  45. #endif
  46.  
  47. /* Includes ------------------------------------------------------------------*/
  48. #include "stm32l1xx_hal_conf.h"
  49.  
  50. /** @addtogroup STM32L1xx_HAL_Driver
  51.   * @{
  52.   */
  53.  
  54. /** @addtogroup HAL
  55.   * @{
  56.   */
  57.  
  58. /* Exported types ------------------------------------------------------------*/
  59. /* Exported constants --------------------------------------------------------*/
  60. /** @defgroup HAL_Exported_Constants HAL Exported Constants
  61.   * @{
  62.   */
  63.  
  64. /** @defgroup SYSCFG_Constants SYSCFG: SYStem ConFiG
  65.   * @{
  66.   */
  67.  
  68. /** @defgroup SYSCFG_BootMode Boot Mode
  69.   * @{
  70.   */
  71.  
  72. #define SYSCFG_BOOT_MAINFLASH          (0x00000000U)
  73. #define SYSCFG_BOOT_SYSTEMFLASH        ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_0)
  74. #if defined(FSMC_R_BASE)
  75. #define SYSCFG_BOOT_FSMC               ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_1)
  76. #endif /* FSMC_R_BASE  */
  77. #define SYSCFG_BOOT_SRAM               ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE)
  78.  
  79. /**
  80.   * @}
  81.   */
  82.  
  83. /**
  84.   * @}
  85.   */
  86.  
  87. /** @defgroup RI_Constants RI: Routing Interface
  88.   * @{
  89.   */
  90.  
  91. /** @defgroup RI_InputCapture Input Capture
  92.   * @{
  93.   */
  94.  
  95. #define RI_INPUTCAPTURE_IC1  RI_ICR_IC1    /*!< Input Capture 1 */
  96. #define RI_INPUTCAPTURE_IC2  RI_ICR_IC2    /*!< Input Capture 2 */
  97. #define RI_INPUTCAPTURE_IC3  RI_ICR_IC3    /*!< Input Capture 3 */
  98. #define RI_INPUTCAPTURE_IC4  RI_ICR_IC4    /*!< Input Capture 4 */
  99.  
  100. /**
  101.   * @}
  102.   */
  103.  
  104. /** @defgroup TIM_Select TIM Select
  105.   * @{
  106.   */
  107.  
  108. #define TIM_SELECT_NONE  (0x00000000U)    /*!< None selected */
  109. #define TIM_SELECT_TIM2  ((uint32_t)RI_ICR_TIM_0)  /*!< Timer 2 selected */
  110. #define TIM_SELECT_TIM3  ((uint32_t)RI_ICR_TIM_1)  /*!< Timer 3 selected */
  111. #define TIM_SELECT_TIM4  ((uint32_t)RI_ICR_TIM)    /*!< Timer 4 selected */
  112.  
  113. #define IS_RI_TIM(__TIM__) (((__TIM__) == TIM_SELECT_NONE) || \
  114.                         ((__TIM__) == TIM_SELECT_TIM2) || \
  115.                         ((__TIM__) == TIM_SELECT_TIM3) || \
  116.                         ((__TIM__) == TIM_SELECT_TIM4))
  117.  
  118. /**
  119.   * @}
  120.   */
  121.  
  122. /** @defgroup RI_InputCaptureRouting Input Capture Routing
  123.   * @{
  124.   */
  125.                                                           /* TIMx_IC1 TIMx_IC2  TIMx_IC3  TIMx_IC4 */  
  126. #define RI_INPUTCAPTUREROUTING_0   (0x00000000U) /* PA0       PA1      PA2       PA3      */
  127. #define RI_INPUTCAPTUREROUTING_1   (0x00000001U) /* PA4       PA5      PA6       PA7      */
  128. #define RI_INPUTCAPTUREROUTING_2   (0x00000002U) /* PA8       PA9      PA10      PA11     */
  129. #define RI_INPUTCAPTUREROUTING_3   (0x00000003U) /* PA12      PA13     PA14      PA15     */
  130. #define RI_INPUTCAPTUREROUTING_4   (0x00000004U) /* PC0       PC1      PC2       PC3      */
  131. #define RI_INPUTCAPTUREROUTING_5   (0x00000005U) /* PC4       PC5      PC6       PC7      */
  132. #define RI_INPUTCAPTUREROUTING_6   (0x00000006U) /* PC8       PC9      PC10      PC11     */
  133. #define RI_INPUTCAPTUREROUTING_7   (0x00000007U) /* PC12      PC13     PC14      PC15     */
  134. #define RI_INPUTCAPTUREROUTING_8   (0x00000008U) /* PD0       PD1      PD2       PD3      */
  135. #define RI_INPUTCAPTUREROUTING_9   (0x00000009U) /* PD4       PD5      PD6       PD7      */
  136. #define RI_INPUTCAPTUREROUTING_10  (0x0000000AU) /* PD8       PD9      PD10      PD11     */
  137. #define RI_INPUTCAPTUREROUTING_11  (0x0000000BU) /* PD12      PD13     PD14      PD15     */
  138. #define RI_INPUTCAPTUREROUTING_12  (0x0000000CU) /* PE0       PE1      PE2       PE3      */
  139. #define RI_INPUTCAPTUREROUTING_13  (0x0000000DU) /* PE4       PE5      PE6       PE7      */
  140. #define RI_INPUTCAPTUREROUTING_14  (0x0000000EU) /* PE8       PE9      PE10      PE11     */
  141. #define RI_INPUTCAPTUREROUTING_15  (0x0000000FU) /* PE12      PE13     PE14      PE15     */
  142.  
  143. #define IS_RI_INPUTCAPTURE_ROUTING(__ROUTING__) (((__ROUTING__) == RI_INPUTCAPTUREROUTING_0) || \
  144.                                              ((__ROUTING__) == RI_INPUTCAPTUREROUTING_1) || \
  145.                                              ((__ROUTING__) == RI_INPUTCAPTUREROUTING_2) || \
  146.                                              ((__ROUTING__) == RI_INPUTCAPTUREROUTING_3) || \
  147.                                              ((__ROUTING__) == RI_INPUTCAPTUREROUTING_4) || \
  148.                                              ((__ROUTING__) == RI_INPUTCAPTUREROUTING_5) || \
  149.                                              ((__ROUTING__) == RI_INPUTCAPTUREROUTING_6) || \
  150.                                              ((__ROUTING__) == RI_INPUTCAPTUREROUTING_7) || \
  151.                                              ((__ROUTING__) == RI_INPUTCAPTUREROUTING_8) || \
  152.                                              ((__ROUTING__) == RI_INPUTCAPTUREROUTING_9) || \
  153.                                              ((__ROUTING__) == RI_INPUTCAPTUREROUTING_10) || \
  154.                                              ((__ROUTING__) == RI_INPUTCAPTUREROUTING_11) || \
  155.                                              ((__ROUTING__) == RI_INPUTCAPTUREROUTING_12) || \
  156.                                              ((__ROUTING__) == RI_INPUTCAPTUREROUTING_13) || \
  157.                                              ((__ROUTING__) == RI_INPUTCAPTUREROUTING_14) || \
  158.                                              ((__ROUTING__) == RI_INPUTCAPTUREROUTING_15))
  159.  
  160. /**
  161.   * @}
  162.   */
  163.  
  164. /** @defgroup RI_IOSwitch IO Switch
  165.   * @{
  166.   */
  167. #define RI_ASCR1_REGISTER       (0x80000000U)
  168. /* ASCR1 I/O switch: bit 31 is set to '1' to indicate that the mask is in ASCR1 register */
  169. #define RI_IOSWITCH_CH0         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_0)
  170. #define RI_IOSWITCH_CH1         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_1)
  171. #define RI_IOSWITCH_CH2         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_2)
  172. #define RI_IOSWITCH_CH3         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_3)
  173. #define RI_IOSWITCH_CH4         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_4)
  174. #define RI_IOSWITCH_CH5         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_5)
  175. #define RI_IOSWITCH_CH6         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_6)
  176. #define RI_IOSWITCH_CH7         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_7)
  177. #define RI_IOSWITCH_CH8         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_8)
  178. #define RI_IOSWITCH_CH9         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_9)
  179. #define RI_IOSWITCH_CH10        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_10)
  180. #define RI_IOSWITCH_CH11        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_11)
  181. #define RI_IOSWITCH_CH12        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_12)
  182. #define RI_IOSWITCH_CH13        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_13)
  183. #define RI_IOSWITCH_CH14        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_14)
  184. #define RI_IOSWITCH_CH15        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_15)
  185. #define RI_IOSWITCH_CH18        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_18)
  186. #define RI_IOSWITCH_CH19        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_19)
  187. #define RI_IOSWITCH_CH20        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_20)
  188. #define RI_IOSWITCH_CH21        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_21)
  189. #define RI_IOSWITCH_CH22        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_22)
  190. #define RI_IOSWITCH_CH23        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_23)
  191. #define RI_IOSWITCH_CH24        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_24)
  192. #define RI_IOSWITCH_CH25        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_25)
  193. #define RI_IOSWITCH_VCOMP       ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_VCOMP) /* VCOMP (ADC channel 26) is an internal switch used to connect selected channel to COMP1 non inverting input */
  194. #if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */
  195. #define RI_IOSWITCH_CH27        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_27)
  196. #define RI_IOSWITCH_CH28        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_28)
  197. #define RI_IOSWITCH_CH29        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_29)
  198. #define RI_IOSWITCH_CH30        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_30)
  199. #define RI_IOSWITCH_CH31        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_31)
  200. #endif /* RI_ASCR2_CH1b */
  201.  
  202. /* ASCR2 IO switch: bit 31 is set to '0' to indicate that the mask is in ASCR2 register */  
  203. #define RI_IOSWITCH_GR10_1      ((uint32_t)RI_ASCR2_GR10_1)
  204. #define RI_IOSWITCH_GR10_2      ((uint32_t)RI_ASCR2_GR10_2)
  205. #define RI_IOSWITCH_GR10_3      ((uint32_t)RI_ASCR2_GR10_3)
  206. #define RI_IOSWITCH_GR10_4      ((uint32_t)RI_ASCR2_GR10_4)
  207. #define RI_IOSWITCH_GR6_1       ((uint32_t)RI_ASCR2_GR6_1)
  208. #define RI_IOSWITCH_GR6_2       ((uint32_t)RI_ASCR2_GR6_2)
  209. #define RI_IOSWITCH_GR5_1       ((uint32_t)RI_ASCR2_GR5_1)
  210. #define RI_IOSWITCH_GR5_2       ((uint32_t)RI_ASCR2_GR5_2)
  211. #define RI_IOSWITCH_GR5_3       ((uint32_t)RI_ASCR2_GR5_3)
  212. #define RI_IOSWITCH_GR4_1       ((uint32_t)RI_ASCR2_GR4_1)
  213. #define RI_IOSWITCH_GR4_2       ((uint32_t)RI_ASCR2_GR4_2)
  214. #define RI_IOSWITCH_GR4_3       ((uint32_t)RI_ASCR2_GR4_3)
  215. #if defined (RI_ASCR2_CH0b) /* STM32L1 devices category Cat.3, Cat.4 and Cat.5 */
  216. #define RI_IOSWITCH_CH0b        ((uint32_t)RI_ASCR2_CH0b)
  217. #if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */
  218. #define RI_IOSWITCH_CH1b        ((uint32_t)RI_ASCR2_CH1b)
  219. #define RI_IOSWITCH_CH2b        ((uint32_t)RI_ASCR2_CH2b)
  220. #define RI_IOSWITCH_CH3b        ((uint32_t)RI_ASCR2_CH3b)
  221. #define RI_IOSWITCH_CH6b        ((uint32_t)RI_ASCR2_CH6b)
  222. #define RI_IOSWITCH_CH7b        ((uint32_t)RI_ASCR2_CH7b)
  223. #define RI_IOSWITCH_CH8b        ((uint32_t)RI_ASCR2_CH8b)
  224. #define RI_IOSWITCH_CH9b        ((uint32_t)RI_ASCR2_CH9b)
  225. #define RI_IOSWITCH_CH10b       ((uint32_t)RI_ASCR2_CH10b)
  226. #define RI_IOSWITCH_CH11b       ((uint32_t)RI_ASCR2_CH11b)
  227. #define RI_IOSWITCH_CH12b       ((uint32_t)RI_ASCR2_CH12b)
  228. #endif /* RI_ASCR2_CH1b */
  229. #define RI_IOSWITCH_GR6_3       ((uint32_t)RI_ASCR2_GR6_3)
  230. #define RI_IOSWITCH_GR6_4       ((uint32_t)RI_ASCR2_GR6_4)
  231. #endif /* RI_ASCR2_CH0b */
  232.  
  233.  
  234. #if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */
  235.  
  236. #define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1)    || \
  237.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH2)     || ((__IOSWITCH__) == RI_IOSWITCH_CH3)    || \
  238.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH4)     || ((__IOSWITCH__) == RI_IOSWITCH_CH5)    || \
  239.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH6)     || ((__IOSWITCH__) == RI_IOSWITCH_CH7)    || \
  240.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH8)     || ((__IOSWITCH__) == RI_IOSWITCH_CH9)    || \
  241.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH10)    || ((__IOSWITCH__) == RI_IOSWITCH_CH11)   || \
  242.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH12)    || ((__IOSWITCH__) == RI_IOSWITCH_CH13)   || \
  243.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH14)    || ((__IOSWITCH__) == RI_IOSWITCH_CH15)   || \
  244.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH18)    || ((__IOSWITCH__) == RI_IOSWITCH_CH19)   || \
  245.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH20)    || ((__IOSWITCH__) == RI_IOSWITCH_CH21)   || \
  246.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH22)    || ((__IOSWITCH__) == RI_IOSWITCH_CH23)   || \
  247.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH24)    || ((__IOSWITCH__) == RI_IOSWITCH_CH25)   || \
  248.                                   ((__IOSWITCH__) == RI_IOSWITCH_VCOMP)   || ((__IOSWITCH__) == RI_IOSWITCH_CH27)   || \
  249.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH28)    || ((__IOSWITCH__) == RI_IOSWITCH_CH29)   || \
  250.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH30)    || ((__IOSWITCH__) == RI_IOSWITCH_CH31)   || \
  251.                                   ((__IOSWITCH__) == RI_IOSWITCH_GR10_1)  || ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || \
  252.                                   ((__IOSWITCH__) == RI_IOSWITCH_GR10_3)  || ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || \
  253.                                   ((__IOSWITCH__) == RI_IOSWITCH_GR6_1)   || ((__IOSWITCH__) == RI_IOSWITCH_GR6_2)  || \
  254.                                   ((__IOSWITCH__) == RI_IOSWITCH_GR6_3)   || ((__IOSWITCH__) == RI_IOSWITCH_GR6_4)  || \
  255.                                   ((__IOSWITCH__) == RI_IOSWITCH_GR5_1)   || ((__IOSWITCH__) == RI_IOSWITCH_GR5_2)  || \
  256.                                   ((__IOSWITCH__) == RI_IOSWITCH_GR5_3)   || ((__IOSWITCH__) == RI_IOSWITCH_GR4_1)  || \
  257.                                   ((__IOSWITCH__) == RI_IOSWITCH_GR4_2)   || ((__IOSWITCH__) == RI_IOSWITCH_GR4_3)  || \
  258.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH0b)    || ((__IOSWITCH__) == RI_IOSWITCH_CH1b)   || \
  259.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH2b)    || ((__IOSWITCH__) == RI_IOSWITCH_CH3b)   || \
  260.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH6b)    || ((__IOSWITCH__) == RI_IOSWITCH_CH7b)   || \
  261.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH8b)    || ((__IOSWITCH__) == RI_IOSWITCH_CH9b)   || \
  262.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH10b)   || ((__IOSWITCH__) == RI_IOSWITCH_CH11b)  || \
  263.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH12b))
  264.  
  265. #else /* !RI_ASCR2_CH1b */
  266.  
  267. #if defined (RI_ASCR2_CH0b) /* STM32L1 devices category Cat.3 */
  268.  
  269. #define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1)    || \
  270.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH2)     || ((__IOSWITCH__) == RI_IOSWITCH_CH3)    || \
  271.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH4)     || ((__IOSWITCH__) == RI_IOSWITCH_CH5)    || \
  272.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH6)     || ((__IOSWITCH__) == RI_IOSWITCH_CH7)    || \
  273.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH8)     || ((__IOSWITCH__) == RI_IOSWITCH_CH9)    || \
  274.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH10)    || ((__IOSWITCH__) == RI_IOSWITCH_CH11)   || \
  275.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH12)    || ((__IOSWITCH__) == RI_IOSWITCH_CH13)   || \
  276.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH14)    || ((__IOSWITCH__) == RI_IOSWITCH_CH15)   || \
  277.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH18)    || ((__IOSWITCH__) == RI_IOSWITCH_CH19)   || \
  278.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH20)    || ((__IOSWITCH__) == RI_IOSWITCH_CH21)   || \
  279.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH22)    || ((__IOSWITCH__) == RI_IOSWITCH_CH23)   || \
  280.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH24)    || ((__IOSWITCH__) == RI_IOSWITCH_CH25)   || \
  281.                                   ((__IOSWITCH__) == RI_IOSWITCH_VCOMP)   || ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || \
  282.                                   ((__IOSWITCH__) == RI_IOSWITCH_GR10_2)  || ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || \
  283.                                   ((__IOSWITCH__) == RI_IOSWITCH_GR10_4)  || ((__IOSWITCH__) == RI_IOSWITCH_GR6_1)  || \
  284.                                   ((__IOSWITCH__) == RI_IOSWITCH_GR6_2)   || ((__IOSWITCH__) == RI_IOSWITCH_GR5_1)  || \
  285.                                   ((__IOSWITCH__) == RI_IOSWITCH_GR5_2)   || ((__IOSWITCH__) == RI_IOSWITCH_GR5_3)  || \
  286.                                   ((__IOSWITCH__) == RI_IOSWITCH_GR4_1)   || ((__IOSWITCH__) == RI_IOSWITCH_GR4_2)  || \
  287.                                   ((__IOSWITCH__) == RI_IOSWITCH_GR4_3)   || ((__IOSWITCH__) == RI_IOSWITCH_CH0b))
  288.  
  289. #else /* !RI_ASCR2_CH0b */  /* STM32L1 devices category Cat.1 and Cat.2 */
  290.  
  291. #define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1)    || \
  292.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH2)     || ((__IOSWITCH__) == RI_IOSWITCH_CH3)    || \
  293.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH4)     || ((__IOSWITCH__) == RI_IOSWITCH_CH5)    || \
  294.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH6)     || ((__IOSWITCH__) == RI_IOSWITCH_CH7)    || \
  295.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH8)     || ((__IOSWITCH__) == RI_IOSWITCH_CH9)    || \
  296.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH10)    || ((__IOSWITCH__) == RI_IOSWITCH_CH11)   || \
  297.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH12)    || ((__IOSWITCH__) == RI_IOSWITCH_CH13)   || \
  298.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH14)    || ((__IOSWITCH__) == RI_IOSWITCH_CH15)   || \
  299.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH18)    || ((__IOSWITCH__) == RI_IOSWITCH_CH19)   || \
  300.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH20)    || ((__IOSWITCH__) == RI_IOSWITCH_CH21)   || \
  301.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH22)    || ((__IOSWITCH__) == RI_IOSWITCH_CH23)   || \
  302.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH24)    || ((__IOSWITCH__) == RI_IOSWITCH_CH25)   || \
  303.                                   ((__IOSWITCH__) == RI_IOSWITCH_VCOMP)   || ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || \
  304.                                   ((__IOSWITCH__) == RI_IOSWITCH_GR10_2)  || ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || \
  305.                                   ((__IOSWITCH__) == RI_IOSWITCH_GR10_4)  || ((__IOSWITCH__) == RI_IOSWITCH_GR6_1)  || \
  306.                                   ((__IOSWITCH__) == RI_IOSWITCH_GR6_2)   || ((__IOSWITCH__) == RI_IOSWITCH_GR5_1)  || \
  307.                                   ((__IOSWITCH__) == RI_IOSWITCH_GR5_2)   || ((__IOSWITCH__) == RI_IOSWITCH_GR5_3)  || \
  308.                                   ((__IOSWITCH__) == RI_IOSWITCH_GR4_1)   || ((__IOSWITCH__) == RI_IOSWITCH_GR4_2)  || \
  309.                                   ((__IOSWITCH__) == RI_IOSWITCH_GR4_3))
  310.  
  311. #endif /* RI_ASCR2_CH0b */
  312. #endif /* RI_ASCR2_CH1b */
  313.  
  314. /**
  315.   * @}
  316.   */
  317.  
  318. /** @defgroup RI_Pin PIN define
  319.   * @{
  320.   */
  321. #define RI_PIN_0                 ((uint16_t)0x0001)  /*!< Pin 0 selected */
  322. #define RI_PIN_1                 ((uint16_t)0x0002)  /*!< Pin 1 selected */
  323. #define RI_PIN_2                 ((uint16_t)0x0004)  /*!< Pin 2 selected */
  324. #define RI_PIN_3                 ((uint16_t)0x0008)  /*!< Pin 3 selected */
  325. #define RI_PIN_4                 ((uint16_t)0x0010)  /*!< Pin 4 selected */
  326. #define RI_PIN_5                 ((uint16_t)0x0020)  /*!< Pin 5 selected */
  327. #define RI_PIN_6                 ((uint16_t)0x0040)  /*!< Pin 6 selected */
  328. #define RI_PIN_7                 ((uint16_t)0x0080)  /*!< Pin 7 selected */
  329. #define RI_PIN_8                 ((uint16_t)0x0100)  /*!< Pin 8 selected */
  330. #define RI_PIN_9                 ((uint16_t)0x0200)  /*!< Pin 9 selected */
  331. #define RI_PIN_10                ((uint16_t)0x0400)  /*!< Pin 10 selected */
  332. #define RI_PIN_11                ((uint16_t)0x0800)  /*!< Pin 11 selected */
  333. #define RI_PIN_12                ((uint16_t)0x1000)  /*!< Pin 12 selected */
  334. #define RI_PIN_13                ((uint16_t)0x2000)  /*!< Pin 13 selected */
  335. #define RI_PIN_14                ((uint16_t)0x4000)  /*!< Pin 14 selected */
  336. #define RI_PIN_15                ((uint16_t)0x8000)  /*!< Pin 15 selected */
  337. #define RI_PIN_ALL               ((uint16_t)0xFFFF)  /*!< All pins selected */
  338.  
  339. #define IS_RI_PIN(__PIN__) ((__PIN__) != (uint16_t)0x00)
  340.  
  341. /**
  342.   * @}
  343.   */
  344.  
  345. /**
  346.   * @}
  347.   */
  348.  
  349. /**
  350.   * @}
  351.   */
  352.  
  353. /* Exported macro ------------------------------------------------------------*/
  354.  
  355. /** @defgroup HAL_Exported_Macros HAL Exported Macros
  356.   * @{
  357.   */
  358.  
  359. /** @defgroup DBGMCU_Macros DBGMCU: Debug MCU
  360.   * @{
  361.   */
  362.  
  363. /** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode
  364.   * @brief   Freeze/Unfreeze Peripherals in Debug mode
  365.   * @{
  366.   */
  367.  
  368. /**
  369.   * @brief  TIM2 Peripherals Debug mode
  370.   */  
  371. #if defined (DBGMCU_APB1_FZ_DBG_TIM2_STOP)
  372. #define __HAL_DBGMCU_FREEZE_TIM2()            SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP)
  373. #define __HAL_DBGMCU_UNFREEZE_TIM2()          CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP)
  374. #endif
  375.  
  376. /**
  377.   * @brief  TIM3 Peripherals Debug mode
  378.   */
  379. #if defined (DBGMCU_APB1_FZ_DBG_TIM3_STOP)
  380. #define __HAL_DBGMCU_FREEZE_TIM3()            SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP)
  381. #define __HAL_DBGMCU_UNFREEZE_TIM3()          CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP)
  382. #endif
  383.  
  384. /**
  385.   * @brief  TIM4 Peripherals Debug mode
  386.   */
  387. #if defined (DBGMCU_APB1_FZ_DBG_TIM4_STOP)
  388. #define __HAL_DBGMCU_FREEZE_TIM4()            SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP)
  389. #define __HAL_DBGMCU_UNFREEZE_TIM4()          CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP)
  390. #endif
  391.  
  392. /**
  393.   * @brief  TIM5 Peripherals Debug mode
  394.   */
  395. #if defined (DBGMCU_APB1_FZ_DBG_TIM5_STOP)
  396. #define __HAL_DBGMCU_FREEZE_TIM5()            SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP)
  397. #define __HAL_DBGMCU_UNFREEZE_TIM5()          CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP)
  398. #endif
  399.  
  400. /**
  401.   * @brief  TIM6 Peripherals Debug mode
  402.   */
  403. #if defined (DBGMCU_APB1_FZ_DBG_TIM6_STOP)
  404. #define __HAL_DBGMCU_FREEZE_TIM6()            SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP)
  405. #define __HAL_DBGMCU_UNFREEZE_TIM6()          CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP)
  406. #endif
  407.  
  408. /**
  409.   * @brief  TIM7 Peripherals Debug mode
  410.   */
  411. #if defined (DBGMCU_APB1_FZ_DBG_TIM7_STOP)
  412. #define __HAL_DBGMCU_FREEZE_TIM7()            SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP)
  413. #define __HAL_DBGMCU_UNFREEZE_TIM7()          CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP)
  414. #endif
  415.  
  416. /**
  417.   * @brief  RTC Peripherals Debug mode
  418.   */
  419. #if defined (DBGMCU_APB1_FZ_DBG_RTC_STOP)
  420. #define __HAL_DBGMCU_FREEZE_RTC()             SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP)
  421. #define __HAL_DBGMCU_UNFREEZE_RTC()           CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP)
  422. #endif
  423.  
  424. /**
  425.   * @brief  WWDG Peripherals Debug mode
  426.   */
  427. #if defined (DBGMCU_APB1_FZ_DBG_WWDG_STOP)
  428. #define __HAL_DBGMCU_FREEZE_WWDG()            SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP)
  429. #define __HAL_DBGMCU_UNFREEZE_WWDG()          CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP)
  430. #endif
  431.  
  432. /**
  433.   * @brief  IWDG Peripherals Debug mode
  434.   */
  435. #if defined (DBGMCU_APB1_FZ_DBG_IWDG_STOP)
  436. #define __HAL_DBGMCU_FREEZE_IWDG()            SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP)
  437. #define __HAL_DBGMCU_UNFREEZE_IWDG()          CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP)
  438. #endif
  439.  
  440. /**
  441.   * @brief  I2C1 Peripherals Debug mode
  442.   */
  443. #if defined (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
  444. #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()    SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
  445. #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT()  CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
  446. #endif
  447.  
  448. /**
  449.   * @brief  I2C2 Peripherals Debug mode
  450.   */
  451. #if defined (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
  452. #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT()    SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
  453. #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT()  CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
  454. #endif
  455.  
  456. /**
  457.   * @brief  TIM9 Peripherals Debug mode
  458.   */
  459. #if defined (DBGMCU_APB2_FZ_DBG_TIM9_STOP)
  460. #define __HAL_DBGMCU_FREEZE_TIM9()            SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP)
  461. #define __HAL_DBGMCU_UNFREEZE_TIM9()          CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP)
  462. #endif
  463.  
  464. /**
  465.   * @brief  TIM10 Peripherals Debug mode
  466.   */
  467. #if defined (DBGMCU_APB2_FZ_DBG_TIM10_STOP)
  468. #define __HAL_DBGMCU_FREEZE_TIM10()           SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP)
  469. #define __HAL_DBGMCU_UNFREEZE_TIM10()         CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP)
  470. #endif
  471.  
  472. /**
  473.   * @brief  TIM11 Peripherals Debug mode
  474.   */
  475. #if defined (DBGMCU_APB2_FZ_DBG_TIM11_STOP)
  476. #define __HAL_DBGMCU_FREEZE_TIM11()           SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP)
  477. #define __HAL_DBGMCU_UNFREEZE_TIM11()         CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP)
  478. #endif
  479.  
  480.  
  481. /**
  482.   * @}
  483.   */
  484.  
  485. /**
  486.   * @}
  487.   */
  488.  
  489. /** @defgroup SYSCFG_Macros SYSCFG: SYStem ConFiG
  490.   * @{
  491.   */
  492.  
  493. /** @defgroup SYSCFG_VrefInt VREFINT configuration
  494.   * @{
  495.   */
  496.  
  497. /**
  498.   * @brief  Enables or disables the output of internal reference voltage
  499.   *         (VREFINT) on I/O pin.
  500.   *         The VREFINT output can be routed to any I/O in group 3:
  501.   *          - For Cat.1 and Cat.2 devices: CH8 (PB0) or CH9 (PB1).
  502.   *          - For Cat.3 devices: CH8 (PB0), CH9 (PB1) or CH0b (PB2).
  503.   *          - For Cat.4 and Cat.5 devices: CH8 (PB0), CH9 (PB1), CH0b (PB2),
  504.   *            CH1b (PF11) or CH2b (PF12).
  505.   *         Note: Comparator peripheral clock must be preliminarility enabled,
  506.   *               either in COMP user function "HAL_COMP_MspInit()" (should be
  507.   *               done if comparators are used) or by direct clock enable:
  508.   *               Refer to macro "__HAL_RCC_COMP_CLK_ENABLE()".
  509.   *         Note: In addition with this macro, Vrefint output buffer must be
  510.   *               connected to the selected I/O pin. Refer to macro
  511.   *               "__HAL_RI_IOSWITCH_CLOSE()".
  512.   * @note  ENABLE: Internal reference voltage connected to I/O group 3
  513.   * @note  DISABLE: Internal reference voltage disconnected from I/O group 3
  514.   * @retval None
  515.   */
  516. #define __HAL_SYSCFG_VREFINT_OUT_ENABLE()       SET_BIT(COMP->CSR, COMP_CSR_VREFOUTEN)
  517. #define __HAL_SYSCFG_VREFINT_OUT_DISABLE()      CLEAR_BIT(COMP->CSR, COMP_CSR_VREFOUTEN)
  518.  
  519. /**
  520.   * @}
  521.   */
  522.  
  523. /** @defgroup SYSCFG_BootModeConfig Boot Mode Configuration
  524.   * @{
  525.   */
  526.  
  527. /**
  528.   * @brief  Main Flash memory mapped at 0x00000000
  529.   */
  530. #define __HAL_SYSCFG_REMAPMEMORY_FLASH()             CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
  531.  
  532. /** @brief  System Flash memory mapped at 0x00000000
  533.   */
  534. #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH()       MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)
  535.  
  536. /** @brief  Embedded SRAM mapped at 0x00000000
  537.   */
  538. #define __HAL_SYSCFG_REMAPMEMORY_SRAM()              MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1)
  539.  
  540. #if defined(FSMC_R_BASE)
  541. /** @brief  FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
  542.   */
  543. #define __HAL_SYSCFG_REMAPMEMORY_FSMC()              MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)
  544.  
  545. #endif /* FSMC_R_BASE */
  546.  
  547. /**
  548.   * @brief  Returns the boot mode as configured by user.
  549.   * @retval The boot mode as configured by user. The returned value can be one
  550.   *         of the following values:
  551.   *           @arg SYSCFG_BOOT_MAINFLASH
  552.   *           @arg SYSCFG_BOOT_SYSTEMFLASH
  553.   *           @arg SYSCFG_BOOT_FSMC (available only for STM32L151xD, STM32L152xD & STM32L162xD)
  554.   *           @arg SYSCFG_BOOT_SRAM
  555.   */
  556. #define __HAL_SYSCFG_GET_BOOT_MODE()          READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BOOT_MODE)
  557.  
  558. /**
  559.   * @}
  560.   */
  561.  
  562. /** @defgroup SYSCFG_USBConfig USB DP line Configuration
  563.   * @{
  564.   */
  565.  
  566. /**
  567.   * @brief  Control the internal pull-up on USB DP line.
  568.   */
  569. #define __HAL_SYSCFG_USBPULLUP_ENABLE()       SET_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU)
  570.  
  571. #define __HAL_SYSCFG_USBPULLUP_DISABLE()      CLEAR_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU)
  572.  
  573. /**
  574.   * @}
  575.   */
  576.  
  577. /**
  578.   * @}
  579.   */
  580.  
  581. /** @defgroup RI_Macris RI: Routing Interface
  582.   * @{
  583.   */
  584.  
  585. /** @defgroup RI_InputCaputureConfig Input Capture configuration
  586.   * @{
  587.   */
  588.  
  589. /**
  590.   * @brief  Configures the routing interface to map Input Capture 1 of TIMx to a selected I/O pin.
  591.   * @param  __TIMSELECT__: Timer select.
  592.   *   This parameter can be one of the following values:
  593.   *     @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.
  594.   *     @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.
  595.   *     @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.
  596.   *     @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.
  597.   * @param  __INPUT__: selects which pin to be routed to Input Capture.
  598.   *   This parameter must be a value of @ref RI_InputCaptureRouting
  599.   *     e.g.
  600.   *       __HAL_RI_REMAP_INPUTCAPTURE1(TIM_SELECT_TIM2, RI_INPUTCAPTUREROUTING_1)
  601.   *       allows routing of Input capture IC1 of TIM2 to PA4.
  602.   *       For details about correspondence between RI_INPUTCAPTUREROUTING_x
  603.   *       and I/O pins refer to the parameters' description in the header file
  604.   *       or refer to the product reference manual.
  605.   * @note Input capture selection bits are not reset by this function.
  606.   *       To reset input capture selection bits, use SYSCFG_RIDeInit() function.
  607.   * @note The I/O should be configured in alternate function mode (AF14) using
  608.   *       GPIO_PinAFConfig() function.
  609.   * @retval None.
  610.   */
  611. #define __HAL_RI_REMAP_INPUTCAPTURE1(__TIMSELECT__, __INPUT__)  \
  612.           do {assert_param(IS_RI_TIM(__TIMSELECT__)); \
  613.               assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \
  614.               MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
  615.               SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC1); \
  616.               MODIFY_REG(RI->ICR, RI_ICR_IC1OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC1OS)); \
  617.           }while(0)
  618.  
  619. /**
  620.   * @brief  Configures the routing interface to map Input Capture 2 of TIMx to a selected I/O pin.
  621.   * @param  __TIMSELECT__: Timer select.
  622.   *   This parameter can be one of the following values:
  623.   *     @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.
  624.   *     @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.
  625.   *     @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.
  626.   *     @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.
  627.   * @param  __INPUT__: selects which pin to be routed to Input Capture.
  628.   *   This parameter must be a value of @ref RI_InputCaptureRouting
  629.   * @retval None.
  630.   */
  631. #define __HAL_RI_REMAP_INPUTCAPTURE2(__TIMSELECT__, __INPUT__)  \
  632.           do {assert_param(IS_RI_TIM(__TIMSELECT__)); \
  633.               assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \
  634.               MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
  635.               SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC2); \
  636.               MODIFY_REG(RI->ICR, RI_ICR_IC2OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC2OS)); \
  637.           }while(0)
  638.  
  639. /**
  640.   * @brief  Configures the routing interface to map Input Capture 3 of TIMx to a selected I/O pin.
  641.   * @param  __TIMSELECT__: Timer select.
  642.   *   This parameter can be one of the following values:
  643.   *     @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.
  644.   *     @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.
  645.   *     @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.
  646.   *     @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.
  647.   * @param  __INPUT__: selects which pin to be routed to Input Capture.
  648.   *   This parameter must be a value of @ref RI_InputCaptureRouting
  649.   * @retval None.
  650.   */
  651. #define __HAL_RI_REMAP_INPUTCAPTURE3(__TIMSELECT__, __INPUT__)  \
  652.           do {assert_param(IS_RI_TIM(__TIMSELECT__)); \
  653.               assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \
  654.               MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
  655.               SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC3); \
  656.               MODIFY_REG(RI->ICR, RI_ICR_IC3OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC3OS)); \
  657.           }while(0)
  658.  
  659. /**
  660.   * @brief  Configures the routing interface to map Input Capture 4 of TIMx to a selected I/O pin.
  661.   * @param  __TIMSELECT__: Timer select.
  662.   *   This parameter can be one of the following values:
  663.   *     @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.
  664.   *     @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.
  665.   *     @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.
  666.   *     @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.
  667.   * @param  __INPUT__: selects which pin to be routed to Input Capture.
  668.   *   This parameter must be a value of @ref RI_InputCaptureRouting
  669.   * @retval None.
  670.   */
  671. #define __HAL_RI_REMAP_INPUTCAPTURE4(__TIMSELECT__, __INPUT__)  \
  672.           do {assert_param(IS_RI_TIM(__TIMSELECT__)); \
  673.               assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \
  674.               MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
  675.               SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC4); \
  676.               MODIFY_REG(RI->ICR, RI_ICR_IC4OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC4OS)); \
  677.           }while(0)
  678.  
  679. /**
  680.   * @}
  681.   */
  682.  
  683. /** @defgroup RI_SwitchControlConfig Switch Control configuration
  684.   * @{
  685.   */
  686.  
  687. /**
  688.   * @brief  Enable or disable the switch control mode.
  689.   * @note  ENABLE: ADC analog switches closed if the corresponding
  690.   *                    I/O switch is also closed.
  691.   *                    When using COMP1, switch control mode must be enabled.
  692.   * @note  DISABLE: ADC analog switches open or controlled by the ADC interface.
  693.   *                    When using the ADC for acquisition, switch control mode
  694.   *                    must be disabled.
  695.   * @note COMP1 comparator and ADC cannot be used at the same time since
  696.   *       they share the ADC switch matrix.
  697.   * @retval None
  698.   */
  699. #define __HAL_RI_SWITCHCONTROLMODE_ENABLE()       SET_BIT(RI->ASCR1, RI_ASCR1_SCM)
  700.  
  701. #define __HAL_RI_SWITCHCONTROLMODE_DISABLE()      CLEAR_BIT(RI->ASCR1, RI_ASCR1_SCM)
  702.  
  703. /*
  704.   * @brief  Close or Open the routing interface Input Output switches.
  705.   * @param  __IOSWITCH__: selects the I/O analog switch number.
  706.   *   This parameter must be a value of @ref RI_IOSwitch
  707.   * @retval None
  708.   */
  709. #define __HAL_RI_IOSWITCH_CLOSE(__IOSWITCH__) do { assert_param(IS_RI_IOSWITCH(__IOSWITCH__)); \
  710.             if ((__IOSWITCH__) >> 31 != 0 ) \
  711.             { \
  712.               SET_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \
  713.             } \
  714.             else \
  715.             { \
  716.               SET_BIT(RI->ASCR2, (__IOSWITCH__)); \
  717.             } \
  718.           }while(0)
  719.  
  720. #define __HAL_RI_IOSWITCH_OPEN(__IOSWITCH__) do { assert_param(IS_RI_IOSWITCH(__IOSWITCH__)); \
  721.             if ((__IOSWITCH__) >> 31 != 0 ) \
  722.             { \
  723.               CLEAR_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \
  724.             } \
  725.             else \
  726.             { \
  727.               CLEAR_BIT(RI->ASCR2, (__IOSWITCH__)); \
  728.             } \
  729.           }while(0)
  730.  
  731. #if defined (COMP_CSR_SW1)
  732. /**
  733.   * @brief  Close or open the internal switch COMP1_SW1.
  734.   *         This switch connects I/O pin PC3 (can be used as ADC channel 13)
  735.   *         and OPAMP3 ouput to ADC switch matrix (ADC channel VCOMP, channel
  736.   *         26) and COMP1 non-inverting input.
  737.   *         Pin PC3 connection depends on another switch setting, refer to
  738.   *         macro "__HAL_ADC_CHANNEL_SPEED_FAST()".
  739.   * @retval None.
  740.   */
  741. #define __HAL_RI_SWITCH_COMP1_SW1_CLOSE()  SET_BIT(COMP->CSR, COMP_CSR_SW1)
  742.  
  743. #define __HAL_RI_SWITCH_COMP1_SW1_OPEN()   CLEAR_BIT(COMP->CSR, COMP_CSR_SW1)
  744. #endif /* COMP_CSR_SW1 */
  745.  
  746. /**
  747.   * @}
  748.   */
  749.  
  750. /** @defgroup RI_HystConfig Hysteresis Activation and Deactivation
  751.   * @{
  752.   */
  753.  
  754. /**
  755.   * @brief  Enable or disable Hysteresis of the input schmitt triger of Ports A
  756.   *         When the I/Os are programmed in input mode by standard I/O port
  757.   *         registers, the Schmitt trigger and the hysteresis are enabled by default.
  758.   *         When hysteresis is disabled, it is possible to read the
  759.   *         corresponding port with a trigger level of VDDIO/2.
  760.   *  @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
  761.   *   This parameter must be a value of @ref RI_Pin
  762.   * @retval None
  763.   */
  764. #define __HAL_RI_HYSTERIS_PORTA_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
  765.             CLEAR_BIT(RI->HYSCR1, (__IOPIN__)); \
  766.           } while(0)
  767.  
  768. #define __HAL_RI_HYSTERIS_PORTA_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
  769.             SET_BIT(RI->HYSCR1, (__IOPIN__)); \
  770.           } while(0)
  771.  
  772. /**
  773.   * @brief  Enable or disable Hysteresis of the input schmitt triger of Ports B
  774.   *         When the I/Os are programmed in input mode by standard I/O port
  775.   *         registers, the Schmitt trigger and the hysteresis are enabled by default.
  776.   *         When hysteresis is disabled, it is possible to read the
  777.   *         corresponding port with a trigger level of VDDIO/2.
  778.   *  @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
  779.   *   This parameter must be a value of @ref RI_Pin
  780.   * @retval None
  781.   */
  782. #define __HAL_RI_HYSTERIS_PORTB_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
  783.             CLEAR_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \
  784.           } while(0)
  785.  
  786. #define __HAL_RI_HYSTERIS_PORTB_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
  787.             SET_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \
  788.           } while(0)
  789.  
  790. /**
  791.   * @brief  Enable or disable Hysteresis of the input schmitt triger of Ports C
  792.   *         When the I/Os are programmed in input mode by standard I/O port
  793.   *         registers, the Schmitt trigger and the hysteresis are enabled by default.
  794.   *         When hysteresis is disabled, it is possible to read the
  795.   *         corresponding port with a trigger level of VDDIO/2.
  796.   *  @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
  797.   *   This parameter must be a value of @ref RI_Pin
  798.   * @retval None
  799.   */
  800. #define __HAL_RI_HYSTERIS_PORTC_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
  801.             CLEAR_BIT(RI->HYSCR2, (__IOPIN__)); \
  802.           } while(0)
  803.  
  804. #define __HAL_RI_HYSTERIS_PORTC_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
  805.             SET_BIT(RI->HYSCR2, (__IOPIN__)); \
  806.           } while(0)
  807.  
  808. /**
  809.   * @brief  Enable or disable Hysteresis of the input schmitt triger of Ports D
  810.   *         When the I/Os are programmed in input mode by standard I/O port
  811.   *         registers, the Schmitt trigger and the hysteresis are enabled by default.
  812.   *         When hysteresis is disabled, it is possible to read the
  813.   *         corresponding port with a trigger level of VDDIO/2.
  814.   *  @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
  815.   *   This parameter must be a value of @ref RI_Pin
  816.   * @retval None
  817.   */
  818. #define __HAL_RI_HYSTERIS_PORTD_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
  819.             CLEAR_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \
  820.           } while(0)
  821.  
  822. #define __HAL_RI_HYSTERIS_PORTD_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
  823.             SET_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \
  824.           } while(0)
  825.  
  826. #if defined (GPIOE_BASE)
  827.    
  828. /**
  829.   * @brief  Enable or disable Hysteresis of the input schmitt triger of Ports E
  830.   *         When the I/Os are programmed in input mode by standard I/O port
  831.   *         registers, the Schmitt trigger and the hysteresis are enabled by default.
  832.   *         When hysteresis is disabled, it is possible to read the
  833.   *         corresponding port with a trigger level of VDDIO/2.
  834.   *  @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
  835.   *   This parameter must be a value of @ref RI_Pin
  836.   * @retval None
  837.   */
  838. #define __HAL_RI_HYSTERIS_PORTE_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
  839.             CLEAR_BIT(RI->HYSCR3, (__IOPIN__)); \
  840.           } while(0)
  841.  
  842. #define __HAL_RI_HYSTERIS_PORTE_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
  843.             SET_BIT(RI->HYSCR3, (__IOPIN__)); \
  844.           } while(0)
  845.  
  846. #endif /* GPIOE_BASE */
  847.  
  848. #if defined(GPIOF_BASE) || defined(GPIOG_BASE)
  849.  
  850. /**
  851.   * @brief  Enable or disable Hysteresis of the input schmitt triger of Ports F
  852.   *         When the I/Os are programmed in input mode by standard I/O port
  853.   *         registers, the Schmitt trigger and the hysteresis are enabled by default.
  854.   *         When hysteresis is disabled, it is possible to read the
  855.   *         corresponding port with a trigger level of VDDIO/2.
  856.   *  @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
  857.   *   This parameter must be a value of @ref RI_Pin
  858.   * @retval None
  859.   */
  860. #define __HAL_RI_HYSTERIS_PORTF_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
  861.             CLEAR_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \
  862.           } while(0)
  863.  
  864. #define __HAL_RI_HYSTERIS_PORTF_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
  865.             SET_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \
  866.           } while(0)
  867.  
  868. /**
  869.   * @brief  Enable or disable Hysteresis of the input schmitt triger of Ports G
  870.   *         When the I/Os are programmed in input mode by standard I/O port
  871.   *         registers, the Schmitt trigger and the hysteresis are enabled by default.
  872.   *         When hysteresis is disabled, it is possible to read the
  873.   *         corresponding port with a trigger level of VDDIO/2.
  874.   *  @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
  875.   *   This parameter must be a value of @ref RI_Pin
  876.   * @retval None
  877.   */
  878. #define __HAL_RI_HYSTERIS_PORTG_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
  879.             CLEAR_BIT(RI->HYSCR4, (__IOPIN__)); \
  880.           } while(0)
  881.  
  882. #define __HAL_RI_HYSTERIS_PORTG_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
  883.             SET_BIT(RI->HYSCR4, (__IOPIN__)); \
  884.           } while(0)
  885.  
  886. #endif /* GPIOF_BASE || GPIOG_BASE */
  887.  
  888. /**
  889.   * @}
  890.   */
  891.  
  892. /**
  893.   * @}
  894.   */
  895.  
  896. /**
  897.   * @}
  898.   */
  899.  
  900. /* Exported functions --------------------------------------------------------*/
  901.  
  902. /** @addtogroup HAL_Exported_Functions
  903.   * @{
  904.   */
  905.  
  906. /** @addtogroup HAL_Exported_Functions_Group1
  907.   * @{
  908.   */
  909.  
  910. /* Initialization and de-initialization functions  ******************************/
  911. HAL_StatusTypeDef HAL_Init(void);
  912. HAL_StatusTypeDef HAL_DeInit(void);
  913. void              HAL_MspInit(void);
  914. void              HAL_MspDeInit(void);
  915. HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
  916.  
  917. /**
  918.   * @}
  919.   */
  920.  
  921. /** @addtogroup HAL_Exported_Functions_Group2
  922.   * @{
  923.   */
  924.  
  925. /* Peripheral Control functions  ************************************************/
  926. void              HAL_IncTick(void);
  927. void              HAL_Delay(__IO uint32_t Delay);
  928. uint32_t          HAL_GetTick(void);
  929. void              HAL_SuspendTick(void);
  930. void              HAL_ResumeTick(void);
  931. uint32_t          HAL_GetHalVersion(void);
  932. uint32_t          HAL_GetREVID(void);
  933. uint32_t          HAL_GetDEVID(void);
  934. void              HAL_DBGMCU_EnableDBGSleepMode(void);
  935. void              HAL_DBGMCU_DisableDBGSleepMode(void);
  936. void              HAL_DBGMCU_EnableDBGStopMode(void);
  937. void              HAL_DBGMCU_DisableDBGStopMode(void);
  938. void              HAL_DBGMCU_EnableDBGStandbyMode(void);
  939. void              HAL_DBGMCU_DisableDBGStandbyMode(void);
  940.  
  941. /**
  942.   * @}
  943.   */
  944.  
  945. /**
  946.   * @}
  947.   */
  948.  
  949.  
  950. /**
  951.   * @}
  952.   */
  953.  
  954. /**
  955.   * @}
  956.   */
  957.  
  958. #ifdef __cplusplus
  959. }
  960. #endif
  961.  
  962. #endif /* __STM32L1xx_HAL_H */
  963.  
  964. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  965.