/*
* $Id: print_vlog.c,v 1.2 2004/06/22 21:44:14 mjames Exp $
*
* $Log: print_vlog.c,v $
* Revision 1.2 2004/06/22 21:44:14 mjames
* Firrst build most files
*
* Revision 1.28 2002/09/09 10:11:27 mjames
* Moved pin remapping function to pin ident editing function from
* sorting pin name routine.
*
* Revision 1.27 2002/08/23 14:18:02 mjames
* Removed some constants to the header file
*
* Revision 1.26 2002/01/21 09:27:49 mjames
* Filtering of not routable nets was not 100% complete. Added
* code for this. Also a comma was suppressed on the first port listed on
* a top level component declaration, if this was a member of a bundle with less
* than (currently) 4 pins.
*
* Revision 1.25 2001/12/24 20:05:18 mjames
* Prevented wires being listed if not routable.
* Printing net names rather than identifiers.
*
* Revision 1.24 2001/12/20 13:37:34 mjames
* Small bundles printed as induvidual signals
*
* Revision 1.23 2001/12/11 20:32:23 mjames
* Implemented regular expression pin name editing
* Allows for elimination of pin_xx prefixing (as this is wrong for
* many verilog netlist)
*
* Revision 1.22 2001/11/19 10:41:35 mjames
* Merged back DTC release
*
* Revision 1.21.2.1 2001/11/15 22:04:43 mjames
* Removed unused variables
*
* Revision 1.21 2001/10/31 22:20:13 mjames
* Tidying up problematical comments caused by CVS
* 'intelligent' comment guessing
*
* Revision 1.20 2001/10/31 16:20:06 mjames
* fixed fpga alternate file printing to work in all cases.
*
* Revision 1.19 2001/10/22 10:57:52 mjames
* Identify bundle attributes with its declaration
* Allow the user to define a replacement string for the
* set fpga <socket_id> "string"
* which is printed out instead of the component declaration
*
* Revision 1.18 2001/10/11 11:52:32 mjames
* Syntax is now checked as compatible with Certify
*
* Revision 1.17 2001/10/10 20:18:22 mjames
* Added a vert_regcomp function to compile regular expressions
* with '^' (match start string) and '$' (match end string) bracketing
* this => wildcard must match entire string not just a part of it.
*
* Revision 1.16 2001/09/16 20:36:03 mjames
* Second attempt to modify wire bundles to be connector rather than net
* centric. Allows more than one connector to carry the same net,
*
* Revision 1.15 2001/09/16 19:49:34 mjames
* Second attempt at bundling the pins on sockets
*
* Revision 1.14 2001/09/13 21:07:18 mjames
* Printing of wire bundles in place of induvidual pins for Ceritfy support.
*
* Revision 1.13 2001/08/09 20:30:37 mjames
* Needed to write net name not identifier carried on net when listing device pins
*
* Revision 1.12 2001/07/16 15:55:14 MJAMES
* Conversion to correctly print port list of extracted components.
*
* Revision 1.11 2001/07/12 09:12:10 mjames
* Commented out dead function to do with printing signal types:
* This was a hangover from VHDL printing.
*
* Revision 1.10 2001/06/22 11:06:49 mjames
* Modified to tag Verilog code generated so that
* Vertical can recognise it.
*
* Revision 1.9 2001/06/19 05:21:26 mjames
* Fine tuning to try and reproduce files that are compatible with
* Certify
*
* Revision 1.8 2001/06/07 13:34:22 MJAMES
* Correctly removing unused nets from printouts
*
* Revision 1.7 2001/06/06 12:10:19 mjames
* Move from HPUX
*
* Revision 1.6 2001/04/06 22:47:02 mjames
* Added doc2, the creator of documentation to Vertical scripts uses PERL
*
*
* Also correcting generic behaviour and the printing of Verilog.
*
* Revision 1.5 2001/04/04 22:12:31 mjames
* Added some online documentation to the C program command handler
* THis is scanned by a utility called 'doc' that currently creates
* simple HTML from part formatted C comments
*
* Also working well on printing VERILOG
*
* still have problems with C comments and VERTICAL pragmas.
*
* Revision 1.4 2001/03/29 22:08:56 mjames
* Modified to define the scope of set generic commands : now can be global
* or defined for a socket or a simple wildcarded list of sockets.
*
* In addition the is_FPGA property has been activated so that FPGA components
* are not listed out when used in a Verilog (.vb) file.
*
* Version raised to 11.02
*
* Revision 1.3 2001/03/29 08:27:07 mjames
* Converted frbread for use with the newer files from the drawing office
*
* Revision 1.2 2001/01/02 07:53:53 mjames
* Made changes to allow for interface with TCL/Tk
*
* Revision 1.1.1.1 2000/10/19 21:58:39 mjames
* Mike put it here
*
*
* Revision 1.21 2000/10/04 10:37:08 10:37:08 mjames (Mike James)
* Modified for Vertical2 : support COMPONENTS and SIGNALS
*
* Revision 1.21 2000/10/04 10:37:08 10:37:08 mjames (Mike James)
* Part of Release PSAVAT01
*
* Revision 1.20 2000/10/02 11:04:18 11:04:18 mjames (Mike James)
* new_vhdl
*
* Revision 1.19 2000/09/27 14:42:18 14:42:18 mjames (Mike James)
* Part of Release Sep_27_ST_2000
*
* Revision 1.18 2000/09/21 10:15:48 10:15:48 mjames (Mike James)
* Part of Release Sep21Alpha
*
* Revision 1.17 2000/08/25 09:57:14 09:57:14 mjames (Mike James)
* Part of Release Aug25_alpha
*
* Revision 1.16 2000/08/16 08:57:30 08:57:30 mjames (Mike James)
* Part of Release CD01_Aug2000
*
* Revision 1.15 2000/08/14 14:45:12 14:45:12 mjames (Mike James)
* Part of Release Aug_14_2000
*
* Revision 1.14 2000/08/14 14:43:27 14:43:27 mjames (Mike James)
* Added power pins
*
* Revision 1.13 2000/08/11 14:17:18 14:17:18 mjames (Mike James)
* Failed to suppress declaring internal components
* when printing verilog.
*
* Revision 1.12 2000/08/11 08:30:32 08:30:32 mjames (Mike James)
* Part of Release Aug_11_2000
*
* Revision 1.11 2000/08/09 10:31:47 10:31:47 mjames (Mike James)
* Part of Release Aug__9_2000
*
* Revision 1.10 2000/05/31 11:42:57 11:42:57 mjames (Mike James)
* Part of Release May_31_2000
*
* Revision 1.9 2000/05/08 17:01:38 17:01:38 mjames (Mike James)
* Part of Release May__8_2000
*
* Revision 1.8 2000/05/08 16:59:31 16:59:31 mjames (Mike James)
* Part of Release May__8_2000
*
* Revision 1.7 2000/05/08 16:57:07 16:57:07 mjames (Mike James)
* Part of Release May__8_2000
*
* Revision 1.6 2000/03/08 16:19:23 16:19:23 mjames (Mike James)
* New version including PC
*
* Revision 1.3 2000/01/20 15:58:47 15:58:47 mjames (Mike James)
* Part of Release R22
*
* Revision 1.2 99/12/22 11:15:28 11:15:28 mjames (Mike James)
* Part of Release Dec_22_1999
*
* Revision 1.1 99/11/23 13:52:43 13:52:43 mjames (Mike James)
* Initial revision
*
*/
#include "cmdlog.h"
#include "cmdparse.h"
#include "database.h"
#include "expression.h"
#include "generic.h"
#include "print_vhdl.h"
#include "printout.h"
#include "sorting.h"
#include "vertcl_main.h"
#include <ctype.h>
#include <regex.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
/* ********************************************************************** */
/* Decoding pin direction in VLOG */
static char *decode_pin_VLOG[] = {"inout", /* was -NONE- */
"inout", /* was in */
"out",
"out", /* buffer is a sort of Output pin */
"inout",
"inout", /* config is a sort of input pin */
"inout"}; /* power is a sort of input pin */
/* ********************************************************************** */
/* VHDL output of the entities */
/* ********************************************************************** */
static char illegal[] = "-+:|/.\\$ ";
static char replace[] = "NPCxxxxS_";
char *make_VLOG_name (char *buffer, char *str)
{
int i, l, j;
{
l += 1;
sprintf (buffer
, "\%s", str
); /* might as well use the verilog quotation method
in this case */
}
else
/* spot illegal strings in the net name */
for (i = 0; i < l; i++)
{
for (j = 0; j < sizeof (illegal); j++)
if (buffer[i] == illegal[j])
buffer[i] = replace[j];
}
i = l - 1;
/* convert pin indices back from Altera form if we are looking at FIT files */
if (l)
{
/* name ends in underscore, this forces mapping name_nn_ --> name(nn) */
if (buffer[i] == '_')
{
buffer[i--] = ']';
while (i >= 0 && buffer[i] != '_')
i--;
if (i >= 0)
buffer[i] = '[';
}
}
return buffer;
}
/* ********************************************************************** */
/* decodes the 'vector' part of a bus , if known */
int decode_VLOG_bus (FILE *f, vhdl_t *vhdl)
{
if (!vhdl)
vhdl = default_vhdl_datatype;
if (vhdl->is_vector)
{
int bus_high, bus_low;
bus_high = 0;
bus_low = 0;
eval_vhdl_expression (vhdl->expr, &bus_high, &bus_low);
if (bus_high == bus_low)
return fprintf (f
, "[%d]", bus_high
);
else
return fprintf (f
, "[%d:%d]", bus_high
, bus_low
);
}
return 0;
}
/* ********************************************************************** */
/* ?? looks like hangover from VHDL */
#if defined NEED_VLOG_TYPE
void decode_VLOG_type (FILE *f, vhdl_t *vhdl)
{
/* avoid crashing on a null pointer */
if (!vhdl)
vhdl = default_vhdl_datatype;
fprintf (f
, "%s ", vhdl
->basetype
);
decode_VLOG_bus (f, vhdl);
}
#endif
/* ********************************************************************** */
/* Certify specific stuff */
/* this copies declaration directives over */
void assign_declaration_directives (socket_t *skt, generic_info_t *list)
{
while (list)
{
if (list->g_type == IS_DECLARATION_DIRECTIVE)
set_generic_value (&(skt->generics), list);
if (list->g_type == IS_INSTANCE_DIRECTIVE)
set_generic_value (&(skt->generics), list);
list = list->next;
}
}
/* ********************************************************************** */
/* print out a VLOG component declaration */
void print_VLOG_component (FILE *f, socket_t *dev, int All)
{
node_t *n;
char printed = 0;
char nam[MAXIDLEN], typ[MAXIDLEN];
generic_info_t *g_list = dev->generics;
make_VLOG_name (typ, check_null_str (dev->type));
fprintf (f
, "\nmodule %s (\n", typ
);
/* sort the identifiers of the nodes */
sort_nodes (dev, NO_EXTRACT_XY);
n = dev->nodes;
while (n)
{
/* print the pin ID if it is connected to a net and the net is routable */
if (All || (n->net && n->net->how_routed != Not_Routable))
{
char nam1[MAXIDLEN];
if (printed)
printed = 1;
sprintf (nam1
, "%s", check_null_str
(n
->identifier
));
fprintf (f
, " %s", make_VLOG_name
(nam
, nam1
));
}
n = n->sktnext; /* traverse to next pin on socket */
};
/* list any declaration directives */
while (g_list)
{
if (g_list->g_type == IS_DECLARATION_DIRECTIVE)
{
if (!g_list->expr || ISNULLSTR (g_list->expr->left.s))
fprintf (f
, "/* synthesis %s */\n", g_list
->name
);
else
f,
"/* synthesis %s = %s*/\n",
g_list->name,
check_null_str (g_list->expr->left.s));
}
g_list = g_list->next;
}
n = dev->nodes;
while (n)
{
if (dev->is_template || (n->net && n->net->how_routed != Not_Routable))
{
f,
" %8s %s ",
decode_pin_VLOG[(int) n->pindir],
make_VLOG_name (nam, check_null_str (n->identifier)));
decode_VLOG_bus (f, n->vhdltype);
}
n = n->sktnext; /* traverse to next pin on socket */
};
}
/* ********************************************************************** */
/* Printout an instance of a component */
/* ********************************************************************** */
void print_VLOG_instance (FILE *f, socket_t *dev, int All)
{
node_t *n;
int need_term = 0;
char nam[MAXIDLEN], id[MAXIDLEN];
generic_info_t *g_list = dev->generics;
make_VLOG_name (nam, check_null_str (dev->type));
make_VLOG_name (id, check_null_str (dev->identifier));
fprintf (f
, "\n\n/* Component instance */\n");
while (g_list)
{
if (g_list->g_type == IS_INSTANCE_DIRECTIVE)
{
if (!g_list->expr || ISNULLSTR (g_list->expr->left.s))
fprintf (f
, "/* synthesis %s */\n", g_list
->name
);
else
f,
"/* synthesis %s = %s*/\n",
g_list->name,
check_null_str (g_list->expr->left.s));
}
g_list = g_list->next;
}
sort_nodes (dev, NO_EXTRACT_XY);
n = dev->nodes;
while (n)
{
char nam1[MAXIDLEN], nam2[MAXIDLEN];
/* is there need to add a buffer signal prefix */
if (n->net && n->net->how_routed != Not_Routable)
{
if (need_term)
else
need_term = 1;
if (n->net_assigned && n->in_use && !ISNULLSTR (n->identifier))
{
f,
" .%s(%s",
make_VLOG_name (nam1, check_null_str (n->identifier)),
make_VLOG_name (
nam2, check_null_str (n->net->name))); /* was
identifier */
decode_VLOG_bus (f, n->vhdltype);
}
else
{
/* No assigned net : pin exists */
f,
" .%s()",
make_VLOG_name (nam1, check_null_str (n->identifier)));
}
}
else
{
if (n->net && n->net->how_routed != Not_Routable)
{
/* If we are printing comments then dont need a comma next time
*/
if (need_term)
else
need_term = 1;
f,
" .pin_%s()",
make_VLOG_name (nam1, check_null_str (n->identifier)));
}
}
n = n->sktnext; /* traverse to next pin on socket */
};
}
/* ********************************************************************** */
void print_VLOG_sigs (FILE *f)
{
net_t *net = named_list;
int width = 0;
char nam[MAXIDLEN], *sig_prefix;
while (net)
{
if (net->needs_buff_sig)
sig_prefix = BUFPREFIX;
else
sig_prefix = "";
if ((net->how_routed != Not_Routable) &&
((net->bundle_member) || ((net->inside_partition) && net->has_external)))
{ /* May 21 2001 only print nets that connect to 'external' tagged modules */
/* add to this those in a bundled connection */
f, " wire %s%s;", sig_prefix, make_VLOG_name (nam, net->name));
if (strcmp (nam
, net
->name
) != 0) /* names changed by printout */
width
+= fprintf (f
, "/* \"%s\" */", net
->name
);
}
else
{
if (level & 1)
{
f,
" /* wire %s%s; ",
sig_prefix,
make_VLOG_name (nam, net->name));
}
}
if (level & 1)
{
f,
" /* partition : %s %s %s %s %s*/\n",
net->inside_partition ? "used in," : "unused in,",
net->leaves_partition ? "leaves," : "buried,",
net->needs_buff_sig ? ", buffered," : "",
net->has_external ? "external skt" : "internal skt",
net->bundle_member ? "bundle member" : " not bundled");
}
if ((level & 1) || (width > MAXWIDTH))
{
width = 0;
}
net = net->next;
}
}
/* ********************************************************************** */
void print_VLOG_assignments (FILE *f)
{
net_t *net = named_list;
socket_t *socket = socket_head;
fprintf (f
, "/* Bundle signals */\n\n");
while (socket)
{
node_t *nodes = socket->nodes;
if (socket->highest_bundle &&
(socket->bundle_width > MINBUNDLE)) /* will not do assigns on small bundles
*/
while (nodes)
{
/* if (strcmp("X6",socket->identifier)==0) */
/* { */
/* printf("-- X6 index = %d\n",nodes->bundle_index); */
/* } */
if (nodes->bundle_index >= 0)
{
char nam[MAXIDLEN];
net_t *net = nodes->net;
make_VLOG_name (nam, net->name);
f,
" assign %s[%d] = %s;\n",
socket->identifier,
nodes->bundle_index,
nam);
}
nodes = nodes->sktnext;
}
/* else
fprintf(f,"-- %s;\n",
net->name);
*/
socket = socket->next;
}
fprintf (f
, "/* end bundle signals */ \n\n");
#if defined USE_PREV
fprintf (f
, "/* Bundle signals */\n\n");
while (net)
{
if (net->bundle_parent)
{
char nam[MAXIDLEN];
make_VLOG_name (nam, net->name);
f,
" assign %s[%d] = %s;\n",
net->bundle_parent->identifier,
net->bundle_index,
nam);
}
/* else
fprintf(f,"-- %s;\n",
net->name);
*/
net = net->next;
}
fprintf (f
, "/* end bundle signals */ \n\n");
#endif
net = named_list;
fprintf (f
, "/* Buffered signals */\n\n");
while (net)
{
if (net->inside_partition && net->needs_buff_sig)
{
char nam[MAXIDLEN];
make_VLOG_name (nam, net->name);
fprintf (f
, " assign " BUFPREFIX
"%s = %s;\n", nam
, nam
);
}
net = net->next;
}
fprintf (f
, "/* end Buffered signals */ \n\n");
}
/* ********************************************************************** */
void print_VLOG_entity (FILE *f, char *entityname)
{
net_t *net;
int need_term = 0;
int width = 0;
socket_t *skt;
char nam[MAXIDLEN];
fprintf (f
, "\nmodule %s ", entityname
);
skt = socket_head;
/* bundles of pins are replaced by signals named the same as a socket which
they are bundled through , unless the bundles are too small in which case they
are replaced by separate wires */
while (skt)
{
if (skt->highest_bundle)
{
if (skt->bundle_width > MINBUNDLE)
{
if (need_term)
{
need_term = 0;
}
if (width > MAXWIDTH)
{
width = 0;
}
width
+= fprintf (f
, "%s", skt
->identifier
);
need_term = 1;
}
else
/* if the 'bundle' has less than MINBUNDLE pins, */
/* list out all of the nets in turn as pins */
{
node_t *node;
node = skt->nodes;
while (node)
{
net = node->net;
/*
printf("node %s\n",node->identifier);
*/
if (net && (net->how_routed != Not_Routable) &&
net->bundle_member)
{
if (need_term)
{
need_term = 0;
}
if (width > 60)
{
width = 0;
}
width
+= fprintf (f
, "%s", net
->identifier
);
need_term = 1;
}
node = node->sktnext;
}
}
}
skt = skt->next;
}
net = named_list;
while (net)
{
/* print out only unbundled nets as ports of the pcb */
if (net->leaves_partition && !net->bundle_member)
{
if (need_term)
{
}
if (width > MAXWIDTH)
{
width = 0;
}
width
+= fprintf (f
, " %s", make_VLOG_name
(nam
, net
->name
));
/* width+= decode_VLOG_bus(f,net->vhdltype); Not used in verilog
*/
if (strcmp (nam
, net
->name
) != 0) /* names changed by printout */
width
+= fprintf (f
, " /* \"%s\" */", net
->name
);
need_term = 1;
}
net = net->next;
}
/* terminate port list */
fprintf (f
, "/* synthesis syn_partition = \"board\" */ \n\n");
need_term = 0;
skt = socket_head;
/* now write out the verilog types of ll of the ports*/
while (skt)
{
if (skt->highest_bundle)
{
/* big bundles are listed as a single item */
if (skt->bundle_width > MINBUNDLE)
{
f,
" inout [%d:%d] %s; // row(%d:%d) col(%d:%d) \n",
skt->highest_bundle,
skt->lowest_bundle,
skt->identifier,
skt->min_pin_row,
skt->max_pin_row,
skt->min_pin_col,
skt->max_pin_col);
}
else
/* small bundles are enumerated as induvidual wires */
{
node_t *node;
node = skt->nodes;
while (node)
{
net = node->net;
/*
printf("node %s\n",node->identifier);
*/
if (net && net->bundle_member)
{
f, " %s ", decode_pin_VLOG[net->ext_dir]);
decode_VLOG_bus (f, net->vhdltype);
f,
" %s;\n",
make_VLOG_name (nam, net->name));
}
node = node->sktnext;
}
}
}
skt = skt->next;
}
net = named_list;
while (net)
{
char nam[MAXIDLEN];
if (net->leaves_partition && !net->bundle_member)
{
fprintf (f
, " %s ", decode_pin_VLOG
[net
->ext_dir
]);
decode_VLOG_bus (f, net->vhdltype);
fprintf (f
, " %s;\n", make_VLOG_name
(nam
, net
->identifier
));
}
net = net->next;
}
}
/* ********************************************************************** */
/* generate default VLOG Libraries */
/* ********************************************************************** */
void print_VLOG_libs (FILE *f)
{
fprintf (f
, "/* Default text */\n\n");
}
/* **********************************************************************
* clear verilog 'type seen' flags (providing a single declaration for all
* instances of a given type
* **********************************************************************
* Using this as a means to avoid duplicate components: only print those
* not seen before */
void clr_type_seen (void)
{
socket_t *skt;
skt = template_head;
while (skt)
{
skt->socket_type_seen = 0;
skt = skt->next;
}
}
/* **********************************************************************
* set verilog 'type seen' flags for all instances of a given type
* ********************************************************************** */
void set_type_seen (char *type)
{
socket_t *skt;
skt = socket_head;
while (skt)
{
if (strcmp (type
, skt
->type
) == 0)
skt->socket_type_seen = 1;
skt = skt->next;
}
}
/* ********************************************************************** */
/* declare all used modules (once !!) */
/* ********************************************************************** */
/* to do: fix up a generic giving an alternative verilog line for the
FPGA declaration case eg 'include something.v
Need to
bundle a socket then del external it for port bundling
*/
void print_VLOG_declarations (FILE *f, char *entityname)
{
socket_t *skt;
skt = socket_head;
clr_type_seen ();
skt = socket_head;
/* list out templates for those sockets selected, and which have not been
converted into a bundle */
while (skt)
{
if (skt->is_external && skt->highest_bundle == 0)
{
/* suppress printout of duplicate components .... */
if (skt->template_socket)
{
if (skt->template_socket->socket_type_seen == 0)
{
if (!skt->is_FPGA)
{ /* only printout component decls for non-FPGA:
Certify has its own private store of these
declarations
and it is fiddly to match these exactly. */
f, "\n// defined by component template\n");
print_VLOG_component (
f, skt->template_socket, 1);
}
else
{
generic_info_t *info = get_generic_ref (
&skt->generics, "fpga_file");
f,
"\n/* socket '%s' is an FPGA: component "
"declaration skipped */\n",
skt->identifier);
if (info && info->g_type == IS_ATTRIBUTE)
{
f,
"/* replacement for declaration "
"*/\n%s\n",
info->expr->left.s
? info->expr->left.s
: "");
}
}
skt->template_socket->socket_type_seen = 1;
}
}
else
{
/* no components, use socket/entity as its own component */
if (!skt->is_FPGA)
{
print_VLOG_component (f, skt, 1);
}
else
{
generic_info_t *info =
get_generic_ref (&skt->generics, "fpga_file");
f,
"\n/* socket '%s' is an FPGA: socket declaration "
"skipped */\n",
skt->identifier);
if (info && info->g_type == IS_ATTRIBUTE)
{
f,
"/* replacement for declaration */\n%s\n",
info->expr->left.s ? info->expr->left.s
: "");
}
}
}
}
skt = skt->next;
}
}
/* ********************************************************************** */
/* generate a VLOG architecture */
/* ********************************************************************** */
void print_VLOG_architecture (FILE *f, char *entityname)
{
socket_t *skt;
print_VLOG_entity (f, entityname);
print_VLOG_sigs (f);
skt = socket_head;
while (skt)
{
if (skt->is_external && skt->highest_bundle == 0)
print_VLOG_instance (f, skt, 0);
skt = skt->next;
}
print_VLOG_assignments (f);
}
/* ********************************************************************** */
/* generate a VLOG file */
/* ********************************************************************** */
void produce_VLOG (FILE *f, char *entityname, char *template)
{
char linebuff[256];
int done_architecture = 0, done_declarations = 0;
if (!template || !template[0])
{ /* check null pointer or empty string */
fprintf (f
, "// vertical verilog\n");
print_VLOG_header (f, "WRITE VLOG");
print_VLOG_declarations (f, entityname);
print_VLOG_architecture (f, entityname);
fprintf (f
, "\n// vertical end;\n");
}
else
{ /* there is a template file */
FILE *tp;
tp
= fopen (template
, "r");
if (tp)
{
fprintf (f
, "// vertical verilog\n");
print_VLOG_header (f, "WRITE VLOG");
fprintf (f
, "/* Using template '%s' */\n", template
);
{
if (fgets (linebuff
, 256, tp
))
{
if (strstr (linebuff
, "$DECL$"))
{
print_VLOG_declarations (f, entityname);
done_declarations++;
}
else if (strstr (linebuff
, "$ARCH$"))
{
print_VLOG_architecture (f, entityname);
done_architecture++;
}
else
fprintf (f
, "%s", linebuff
); /* it already has
a '\n' on the
end */
}
}
fprintf (f
, "\n// vertical end;\n");
if (done_declarations != 1)
Log (
LOG_ERROR,
"-- Error: %d $DECL$ tags counted (need 1) in "
"template '%s'\n",
template);
if (done_architecture != 1)
Log (
LOG_ERROR,
"-- Error: %d $ARCH$ tags counted (need 1) in "
"template '%s'\n",
template);
}
else
Log (
LOG_ERROR,
"-- Error: Cannot open VLOG template '%s'\n",
template);
}
}