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  1. /*
  2.  * $Header: c:\\cygwin\\cvsroot/Vert03/vertlib/print_vhdl.h,v 1.1.1.1 2003/11/04 23:34:57 mjames Exp $
  3.  *
  4.  * $Log: print_vhdl.h,v $
  5.  * Revision 1.1.1.1  2003/11/04 23:34:57  mjames
  6.  * Imported into local repositrory
  7.  *
  8.  * Revision 1.5  2002/08/23 14:18:24  mjames
  9.  * Removed some constants to the header file
  10.  *
  11.  * Revision 1.4  2001/10/31 22:20:13  mjames
  12.  * Tidying up problematical comments caused by CVS
  13.  * 'intelligent' comment guessing
  14.  *
  15.  * Revision 1.3  2001/06/06 12:10:19  mjames
  16.  * Move from HPUX
  17.  *
  18.  * Revision 1.2  2000/11/29 23:25:39  mjames
  19.  * Corrected a failure to cope with integer type ports on entities
  20.  * in acf_yacc.y
  21.  *
  22.  * Altered the elaborate command to call up the template command aw well
  23.  *
  24.  * Altered equivalent pins handler to cope with the absence of any templates
  25.  *
  26.  * Altered printout routines to use correct datatype for expansion of
  27.  * VHDL constants
  28.  *
  29.  * Revision 1.1.1.1  2000/10/19 21:58:39  mjames
  30.  * Mike put it here
  31.  *
  32.  *
  33.  * Revision 1.13  2000/10/04  10:37:15  10:37:15  mjames (Mike James)
  34.  * Modified for Vertical2 : support COMPONENTS and SIGNALS
  35.  *
  36.  * Revision 1.13  2000/10/04  10:37:15  10:37:15  mjames (Mike James)
  37.  * Part of Release PSAVAT01
  38.  *
  39.  * Revision 1.12  2000/10/02  11:04:18  11:04:18  mjames (Mike James)
  40.  * new_vhdl
  41.  *
  42.  * Revision 1.11  2000/09/27  14:42:31  14:42:31  mjames (Mike James)
  43.  * Part of Release Sep_27_ST_2000
  44.  *
  45.  * Revision 1.10  2000/09/21  10:16:00  10:16:00  mjames (Mike James)
  46.  * Part of Release Sep21Alpha
  47.  *
  48.  * Revision 1.9  2000/08/25  09:57:24  09:57:24  mjames (Mike James)
  49.  * Part of Release Aug25_alpha
  50.  *
  51.  * Revision 1.8  2000/08/16  08:57:40  08:57:40  mjames (Mike James)
  52.  * Part of Release CD01_Aug2000
  53.  *
  54.  * Revision 1.7  2000/08/14  14:45:19  14:45:19  mjames (Mike James)
  55.  * Part of Release Aug_14_2000
  56.  *
  57.  * Revision 1.6  2000/08/11  08:30:40  08:30:40  mjames (Mike James)
  58.  * Part of Release Aug_11_2000
  59.  *
  60.  * Revision 1.5  2000/08/09  10:31:57  10:31:57  mjames (Mike James)
  61.  * Part of Release Aug__9_2000
  62.  *
  63.  * Revision 1.4  2000/05/31  11:43:11  11:43:11  mjames (Mike James)
  64.  * Part of Release May_31_2000
  65.  *
  66.  * Revision 1.3  2000/05/08  17:01:47  17:01:47  mjames (Mike James)
  67.  * Part of Release May__8_2000
  68.  *
  69.  * Revision 1.2  2000/05/08  16:59:40  16:59:40  mjames (Mike James)
  70.  * Part of Release May__8_2000
  71.  *
  72.  * Revision 1.1  99/11/23  13:52:31  13:52:31  mjames (Mike James)
  73.  * Initial revision
  74.  *
  75.  * Revision 1.1  1999/11/02 10:04:23  Mike_on_acorn
  76.  * Initial revision
  77.  */
  78.  
  79. /* listing width */
  80. #define MAXWIDTH 60
  81.  
  82. /* lessthan this pin count, connector pins are seen as wires not busses
  83.  in both VHDL and verilog bundles */
  84.  
  85. #define MINBUNDLE 5
  86.  
  87.  
  88.  
  89. extern char * make_vhdl_name(char * buffer,char * str);
  90.  
  91.  
  92. /* prints out the used subrange */
  93. extern void decode_vhdl_bus(FILE * f,vhdl_t * vhdl,generic_print_style recurse_generics);
  94.  
  95. /* prints out the bus type and range if needed */
  96. extern void decode_vhdl_type(FILE * f,vhdl_t * vhdl,generic_print_style recurse_generics);
  97.  
  98.  
  99. extern void print_VHDL_component(FILE * f,socket_t * dev, int All);
  100.  
  101. extern void print_VHDL_instance(FILE * f,socket_t * dev, int All);
  102.  
  103. extern void produce_VHDL(FILE * f,char * entityname,char * template);
  104.