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  1. /* $Id: print_vhdl.c,v 1.1.1.1 2003/11/04 23:34:57 mjames Exp $ */
  2. /*
  3.  * $Log: print_vhdl.c,v $
  4.  * Revision 1.1.1.1  2003/11/04 23:34:57  mjames
  5.  * Imported into local repositrory
  6.  *
  7.  * Revision 1.17  2003/01/02 21:37:16  mjames
  8.  * Experiment on creating NOT_ROUTABLE_H and NOT_ROUTABLE_L
  9.  * properties on the nets so that pin jumpers can be made without a problem.
  10.  *
  11.  * Still need to sort out pin assignments made to these not_routable nets
  12.  * which will become legal in some cases so that pullups and pulldown
  13.  * pins can be used on the FPGA.
  14.  *
  15.  * Revision 1.16  2002/09/30 13:23:05  MJAMES
  16.  * Modified partition rules to include 'default assignment on declaration'
  17.  * which maps to inputs being driven with default values on
  18.  * productuion of a partition.
  19.  *
  20.  * signal c : std_logic := '0';
  21.  *
  22.  * becomes
  23.  *
  24.  * signal c: std_logic;
  25.  *
  26.  * begin
  27.  *   c<= '0';
  28.  *
  29.  * Revision 1.15  2002/09/27 22:35:33  MJAMES
  30.  * Added lhs_expr for cases like
  31.  *
  32.  * x(0) <= y
  33.  *
  34.  * where x is std_logic_vector(0 downto 0) and y is std_logic.
  35.  *
  36.  * Also added printing for default values on signals : this to be extended
  37.  *
  38.  * Revision 1.14  2002/09/09 10:12:02  mjames
  39.  * Moved pin remapping function to pin ident editing function from
  40.  * sorting pin name routine.
  41.  *
  42.  * Revision 1.13  2002/08/23 14:19:19  mjames
  43.  * Introduced bundles and external sockets to VHDL from the Verilog printer.
  44.  *
  45.  * Revision 1.12  2001/12/13 22:18:52  mjames
  46.  * Using #ident with header to identify file
  47.  *
  48.  * Corrected an attempt to reference a null net
  49.  *
  50.  * Revision 1.11  2001/11/19 10:41:35  mjames
  51.  * Merged back DTC release
  52.  *
  53.  * Revision 1.10.2.1  2001/11/15 22:25:39  mjames
  54.  * Removed unused variables, added brackets
  55.  *
  56.  * Revision 1.10  2001/11/01 11:04:36  mjames
  57.  * Pin node identifier is printed out in a component declaration rather than
  58.  * node name which is more a property of the attached net.
  59.  *
  60.  * Revision 1.9  2001/10/31 22:20:12  mjames
  61.  * Tidying up problematical comments caused by CVS
  62.  * 'intelligent' comment guessing
  63.  *
  64.  * Revision 1.8  2001/10/10 20:18:22  mjames
  65.  * Added a vert_regcomp function to compile regular expressions
  66.  * with '^' (match start string) and  '$' (match end string) bracketing
  67.  * this => wildcard must match entire string not just a part of it.
  68.  *
  69.  * Revision 1.7  2001/09/21 14:22:27  mjames
  70.  * Added prefix to instance name in order to avoid a Model Technology name
  71.  * space collision  e.g.
  72.  *
  73.  * U1 : U1 port map () ...
  74.  *
  75.  * Now prints
  76.  *
  77.  * I_U1 : U1 port map which is safer.
  78.  *
  79.  * Revision 1.6  2001/06/22 11:06:19  mjames
  80.  * Modified to tag VHDL code generated so that
  81.  * Vertical can recognise it.
  82.  *
  83.  * Revision 1.5  2001/06/20 13:45:40  mjames
  84.  * For all components defined by 'Component' declarations, forced the
  85.  * printout of only one component for several instances sharing the same component declaration.
  86.  *
  87.  * Revision 1.4  2001/06/06 12:10:19  mjames
  88.  * Move from HPUX
  89.  *
  90.  * Revision 1.3  2001/04/27 08:08:44  mjames
  91.  * Extra tidying of the print_vhdl code
  92.  *
  93.  * Revision 1.2  2000/11/29 21:51:18  mjames
  94.  * Fine tuning of software
  95.  *
  96.  * Revision 1.1.1.1  2000/10/19 21:58:39  mjames
  97.  * Mike put it here
  98.  *
  99.  *
  100.  * Revision 1.23  2000/10/12  15:32:32  15:32:32  mjames (Mike James)
  101.  * Removed <cr>
  102.  *
  103.  * Revision 1.22  2000/10/12  14:25:55  14:25:55  mjames (Mike James)
  104.  * changed listing vhdl signals to expand expressions
  105.  * until a constant is located
  106.  *
  107.  * Revision 1.21  2000/10/04  10:37:08  10:37:08  mjames (Mike James)
  108.  * Modified for Vertical2 : support COMPONENTS and SIGNALS
  109.  *
  110.  * Revision 1.21  2000/10/04  10:37:08  10:37:08  mjames (Mike James)
  111.  * Part of Release PSAVAT01
  112.  *
  113.  * Revision 1.20  2000/10/02  11:04:17  11:04:17  mjames (Mike James)
  114.  * new_vhdl
  115.  *
  116.  * Revision 1.18  2000/09/21  10:15:48  10:15:48  mjames (Mike James)
  117.  * Part of Release Sep21Alpha
  118.  *
  119.  * Revision 1.17  2000/08/25  09:57:14  09:57:14  mjames (Mike James)
  120.  * Part of Release Aug25_alpha
  121.  *
  122.  * Revision 1.16  2000/08/25  09:55:33  09:55:33  mjames (Mike James)
  123.  * Corrected for the disappearance of generic information
  124.  *
  125.  * Revision 1.15  2000/08/16  08:57:30  08:57:30  mjames (Mike James)
  126.  * Part of Release CD01_Aug2000
  127.  *
  128.  * Revision 1.14  2000/08/14  14:45:11  14:45:11  mjames (Mike James)
  129.  * Part of Release Aug_14_2000
  130.  *
  131.  * Revision 1.13  2000/08/14  14:43:15  14:43:15  mjames (Mike James)
  132.  * Added power pins
  133.  *
  134.  * Revision 1.12  2000/08/11  08:30:32  08:30:32  mjames (Mike James)
  135.  * Part of Release Aug_11_2000
  136.  *
  137.  * Revision 1.11  2000/08/09  10:31:47  10:31:47  mjames (Mike James)
  138.  * Part of Release Aug__9_2000
  139.  *
  140.  * Revision 1.10  2000/05/31  11:42:56  11:42:56  mjames (Mike James)
  141.  * Part of Release May_31_2000
  142.  *
  143.  * Revision 1.9  2000/05/08  17:01:37  17:01:37  mjames (Mike James)
  144.  * Part of Release May__8_2000
  145.  *
  146.  * Revision 1.8  2000/05/08  16:59:30  16:59:30  mjames (Mike James)
  147.  * Part of Release May__8_2000
  148.  *
  149.  * Revision 1.7  2000/05/08  16:57:07  16:57:07  mjames (Mike James)
  150.  * Part of Release May__8_2000
  151.  *
  152.  * Revision 1.6  2000/03/08  16:19:22  16:19:22  mjames (Mike James)
  153.  * New version including PC
  154.  *
  155.  * Revision 1.3  2000/01/20  15:58:47  15:58:47  mjames (Mike James)
  156.  * Part of Release R22
  157.  *
  158.  * Revision 1.2  99/12/22  11:15:28  11:15:28  mjames (Mike James)
  159.  * Part of Release Dec_22_1999
  160.  *
  161.  * Revision 1.1  99/11/23  13:52:14  13:52:14  mjames (Mike James)
  162.  * Initial revision
  163.  *
  164.  */
  165.  
  166.  
  167. #include <stdio.h>
  168. #include <string.h>
  169. #include <stdlib.h>
  170. #include <ctype.h>
  171. #include <time.h>
  172. #include <regex.h>
  173.  
  174. #include "vertcl_main.h"
  175. #include "expression.h"
  176. #include "generic.h"
  177. #include "database.h"
  178. #include "printout.h"
  179. #include "print_vhdl.h"
  180. #include "print_vlog.h"
  181. #include "sorting.h"
  182. #include "cmdparse.h"
  183. #include "cmdlog.h"
  184. /* for streq */
  185. #include "lx_support.h"
  186. /* ********************************************************************** */
  187.  
  188. /* Decoding pin direction in VHDL */
  189. static char * decode_pin_VHDL[]=
  190. {
  191.   "-NONE-",
  192.   "IN",
  193.   "OUT",
  194.   "BUFFER", /* buffer is a sort of Output pin */
  195.   "INOUT",
  196.   "CONFIG_PIN",
  197.   "POWER_PIN"};
  198. /* ********************************************************************** */
  199. /* VHDL output of the entities                                            */
  200. /* ********************************************************************** */
  201. static char illegal[]="$:|/.\\ ";
  202. static char replace[]="Sxxxxx_";
  203.  
  204. char * make_vhdl_name(char * buffer,char * str)
  205. {
  206.   int i,j,l;
  207.   buffer[0]=0;
  208.   if(str)
  209.     {
  210.     strcpy(buffer,str); /* should be a call to strncpy !! */
  211.     }
  212.   l=strlen(buffer);
  213.   /* edit out illegal strings from the net name */
  214.   for(i=0;i<l;i++){
  215.     for(j=0;j<sizeof(illegal);j++)
  216.       if (buffer[i]==illegal[j])
  217.         buffer[i] = replace[j];
  218.     }
  219.   i=l-1;
  220.   /* convert pin indices back from Altera form if we are looking at FIT files */
  221.   if(l){
  222.     /* name ends in underscore, this forces mapping name_nn_ --> name(nn) */
  223.     if(buffer[i] =='_'){
  224.       buffer[i--]=')';
  225.       while(i>=0 && buffer[i] != '_')
  226.         i--;
  227.       if(i>=0)
  228.         buffer[i] = '(';
  229.       }
  230.   }
  231.   return buffer;
  232. }
  233.  
  234. /* ********************************************************************** */
  235. /* decodes the 'vector' part of a bus , if known                           */
  236. void decode_vhdl_bus(FILE * f,vhdl_t * vhdl,generic_print_style recurse_generics) {
  237.   if(!vhdl)
  238.      vhdl=default_vhdl_datatype;
  239.   if(vhdl->is_vector)
  240.     print_range_expression(f,vhdl->expr,recurse_generics);
  241.   }
  242.  
  243. /* ********************************************************************** */
  244.  
  245. void decode_vhdl_type(FILE * f,vhdl_t * vhdl,generic_print_style recurse_generics)
  246. {
  247.  
  248. /* avoid crashing on a null pointer */
  249.    if(!vhdl)
  250.      vhdl=default_vhdl_datatype;
  251.   fprintf (f,"%s ",vhdl->basetype);
  252.   if(vhdl->is_vector)
  253.     decode_vhdl_bus(f,vhdl,recurse_generics);
  254.  
  255. }
  256.  
  257.  
  258.  
  259. /* ********************************************************************** */
  260.  
  261. /* print out a VHDL component declaration */
  262. void print_VHDL_component(FILE * f,socket_t * dev, int All)
  263. {
  264.   node_t * n;
  265.   /* sort the identifiers of the nodes */
  266.   sort_nodes(dev,NO_EXTRACT_XY);
  267.  
  268.   fprintf(f,"COMPONENT  %s\n",check_null_str(dev->type));
  269.   fprintf(f,"--  DEV_IDENT \"%s\"\n\n",check_null_str(dev->identifier));
  270.   if(dev->is_template)
  271.     fprintf(f,"--  Defined by COMPONENT definition\n");
  272.    
  273.   if(dev->generics)
  274.     list_VHDL_generic_values(f,&dev->generics);
  275.  
  276.  
  277.  
  278.   fprintf(f,"  PORT ( \n");
  279.   /* sort the identifiers of the nodes */
  280.   sort_nodes(dev,NO_EXTRACT_XY);
  281.   n=dev->nodes;
  282.   while(n)
  283.   {
  284.     vhdl_t * pin_datatype = default_vhdl_datatype;
  285.     expression_t * default_expr = NULL;
  286.     char nam[MAXIDLEN];
  287.     if (n->orig_vhdltype)
  288.       {
  289.       pin_datatype = n->orig_vhdltype;
  290.       default_expr = n->orig_vhdltype->default_expr;
  291.       }
  292.     else if (n->vhdltype)
  293.       {
  294.       pin_datatype = n->vhdltype;
  295.       default_expr = n->vhdltype->default_expr;
  296.       }
  297.     if((n->net_assigned && n->in_use) || (All || dev->is_template)){
  298.       fprintf(f,"  %-16s : %6s  ",
  299.                 make_vhdl_name(nam,check_null_str(n->identifier)), /* was n->name */
  300.                 decode_pin_VHDL[(int)n->pindir]);
  301.       decode_vhdl_type(f,pin_datatype,NO_RECURSE); /* until a generic found */
  302. /* ought to be optional dependent on synthesis style */
  303.       if(default_expr)
  304.         {
  305.         fprintf(f,":= ");
  306.         print_expression(f,default_expr,NO_RECURSE);
  307.         }
  308.        
  309.  
  310.       if (n->sktnext)
  311.         fprintf(f,";");
  312.       fprintf(f," -- i=%s r=%d --\n",
  313.               n->identifier,
  314.               n->refcount);
  315.       }
  316.     n=n->sktnext; /* traverse to next pin on socket */
  317.   };
  318.   fprintf(f,");\nEND COMPONENT;\n\n");
  319.  
  320. }
  321.  
  322. /* ********************************************************************** */
  323. /* Printout an instance of a component */
  324. /* ********************************************************************** */
  325. void print_VHDL_instance(FILE * f,socket_t * dev, int All)
  326. {
  327.   node_t * n;
  328.   int need_term = 0;
  329.   char * prefix;
  330.   /* only prefix devices with similar idents and types */
  331.   if(!ISNULLSTR(dev->identifier) &&
  332.      !ISNULLSTR(dev->type) &&
  333.      streq(dev->identifier,dev->type))
  334.     {
  335.     prefix = "I_";
  336.     }
  337.   else
  338.     {
  339.     prefix = "";
  340.     }
  341.    
  342.   fprintf(f,"%s%s : %s \n",
  343.             prefix,
  344.             check_null_str(dev->identifier),
  345.             check_null_str(dev->type));
  346.  
  347.   if(dev->generics)
  348.     list_VHDL_generic_map_values(f,&dev->generics);
  349.  
  350.   fprintf(f,"  PORT MAP ( \n");
  351.   /* sort the identifiers of the nodes */
  352.   sort_nodes(dev,NO_EXTRACT_XY);
  353.   n=dev->nodes;
  354.   while(n)
  355.   {
  356.     vhdl_t * pin_datatype = default_vhdl_datatype;
  357.     char nam1[MAXIDLEN] , nam2[MAXIDLEN];
  358.     if (n->vhdltype)
  359.       pin_datatype = n->vhdltype;
  360.     if((n->net_assigned && n->in_use) || All ){
  361.       char * sig_prefix;
  362.       if(need_term)
  363.         fprintf(f,",\n");
  364.       else
  365.         fprintf(f,"\n");
  366.       need_term = 1;
  367.       /* is there a slice in the output */
  368.       if(n->net && n->net->needs_buff_sig)
  369.         sig_prefix = BUFPREFIX;
  370.       else
  371.         sig_prefix = "";        
  372.        
  373.       if(n->net)
  374.         {      
  375.         fprintf(f,"  %s",
  376.               make_vhdl_name(nam1,check_null_str(n->identifier))); /* was n->name */
  377.         if(n->lhs_expr)
  378.           {
  379.           print_range_expression(f,n->lhs_expr,RECURSE_CONST);
  380.           }
  381.         fprintf(f,"=> %s%s ",
  382.                sig_prefix,
  383.                make_vhdl_name(nam2,check_null_str(n->net->name)));
  384.         }
  385.       else
  386.         {      
  387.         fprintf(f,"  %-20s => OPEN ",
  388.                make_vhdl_name(nam1,check_null_str(n->identifier))); /* was n->name */
  389.         }
  390.       /* do bus slicing only if the connected net is a bus */
  391.       if(n->net && n->net->vhdltype )
  392.         {
  393.         decode_vhdl_bus(f,n->net->vhdltype,RECURSE_CONST);
  394.         }
  395.       else
  396.         {
  397.         /*  fprintf(f,"\n"); */
  398.         }
  399.      
  400.     }
  401.     n=n->sktnext; /* traverse to next pin on socket */
  402.   };
  403.   fprintf(f,"\n   );\n\n");
  404. }
  405.  
  406. /* ********************************************************************** */
  407.  
  408. void print_VHDL_sigs(FILE * f)
  409. {
  410.   net_t * net = named_list;
  411.   char  nam[MAXIDLEN], * sig_prefix;
  412.   while(net){
  413.    if(net->needs_buff_sig)
  414.      sig_prefix = BUFPREFIX;
  415.    else
  416.      sig_prefix = "";
  417.     /* May 21 2001 only print nets that connect to 'external' tagged modules */
  418.    if((IS_ROUTABLE(net->how_routed)) &&
  419.      ((net->bundle_member) || ((net->inside_partition) && net->has_external)) )
  420.       {                                                                                
  421.       fprintf(f,"    ");
  422.       }
  423.     else
  424.       {
  425.       fprintf(f,"  --");
  426.       }
  427.  
  428.  
  429.     fprintf(f," signal %s%s : ",
  430.                  sig_prefix,
  431.                  make_vhdl_name(nam,net->name));
  432.     decode_vhdl_type(f,net->vhdltype,RECURSE_CONST);
  433.     if(net->vhdltype ) {
  434.       if (net->vhdltype->decl_expr)
  435.         {
  436.         print_expression(f,net->vhdltype->decl_expr,NO_RECURSE);
  437.         }
  438.      if( net->vhdltype->default_expr)
  439.         {
  440.         fprintf(f,":= ");
  441.         print_expression(f,net->vhdltype->default_expr,NO_RECURSE);
  442.         }
  443.       }    
  444.     fprintf(f,"; -- partition : %s %s %s %s %s\n",
  445.             net->inside_partition?"used in,":"unused in,",
  446.             net->leaves_partition?"leaves,":"buried,",
  447.             net->needs_buff_sig?", buffered,":"",
  448.             net->has_external?"external skt":"internal skt",
  449.             net->bundle_member?"bundle member":" not bundled");
  450.     net=net->next;
  451.   }
  452. }
  453. /* ********************************************************************** */
  454.  
  455. void print_VHDL_assignments(FILE * f)
  456. {
  457.   net_t * net = named_list;
  458.   socket_t * socket = socket_head;
  459.  
  460. /* code borrowed from Verilog */
  461.   fprintf(f,"-- Bundled signals\n\n");
  462.  
  463.     while(socket)
  464.     {
  465.     node_t * nodes = socket->nodes;
  466.     if (socket->highest_bundle  && (socket->bundle_width > MINBUNDLE)) /* will not do assigns on small bundles */
  467.     while(nodes)
  468.       {
  469.       if (nodes->bundle_index >= 0)
  470.         {
  471.         char  nam[MAXIDLEN];
  472.         net_t * net = nodes->net;
  473.         make_vhdl_name(nam,net->name);
  474.         fprintf(f," %s <= %s(%d);\n",
  475.                nam,socket->identifier,nodes->bundle_index);
  476.         }
  477.       nodes = nodes->sktnext;
  478.       }
  479. /*    else
  480.       fprintf(f,"-- %s;\n",
  481.                net->name);
  482. */
  483.  
  484.     socket = socket->next;
  485.     }
  486.  
  487.  
  488.   fprintf(f,"-- Buffered signals\n\n");
  489.   while(net){
  490.       if(net->inside_partition && net->needs_buff_sig)
  491.         {
  492.         char  nam[MAXIDLEN];
  493.         make_vhdl_name(nam,net->name),
  494.  
  495.         fprintf(f," %-20s <= "BUFPREFIX"%s; -- buffer\n",
  496.                   nam,nam);
  497.         }
  498.       if(net->vhdl_connect_net && net->subnets)
  499.         {
  500.        
  501.         char nam[MAXIDLEN],nam1[MAXIDLEN];
  502.         make_vhdl_name(nam,net->identifier);
  503.         make_vhdl_name(nam1,net->subnets->identifier);
  504.         fprintf(f," %-20s <= %s; -- connector\n",
  505.                   nam,nam1);
  506.         }
  507.       else if (net->inside_partition && net->vhdltype && net->vhdltype->default_expr)
  508.         {
  509.         char nam[MAXIDLEN];
  510.         make_vhdl_name(nam,net->identifier);
  511.         fprintf(f," %-20s <= ",nam);
  512.         print_range_expression(f, net->vhdltype->default_expr,NO_RECURSE);
  513.         fprintf(f,"; -- Defined default drive value\n");
  514.  
  515.         }
  516.  
  517.     net=net->next;
  518.   }
  519.   fprintf(f,"-- \n\n");
  520.  
  521.  
  522.  
  523.  
  524. }
  525.  
  526. /* ********************************************************************** */
  527. /* code lists bundles although they are probably broken */
  528. void print_VHDL_entity(FILE * f,char * entityname)
  529. {
  530.   net_t * net;
  531.   int need_term = 0;
  532.   socket_t * skt;
  533.   char nam[MAXIDLEN];
  534.  
  535.   fprintf(f,"ENTITY %s IS\n",entityname);
  536.   /* print out global generic settings */
  537. /*
  538.   list_VHDL_generic_values (f,&partition_generics);  
  539. */
  540.   fprintf(f,"  PORT (\n");
  541.  
  542.   skt = socket_head;
  543. /* bundles of pins are replaced by signals named the same as a socket which
  544.    they are bundled through , unless the bundles are too small in which case they
  545.    are replaced by separate wires */
  546.   while(skt)
  547.     {
  548.     if(skt->highest_bundle)
  549.       {
  550.       if (skt->bundle_width > MINBUNDLE)
  551.         {
  552.         if(need_term)
  553.           {
  554.           fprintf(f,";\n");
  555.           need_term = 0;
  556.           }
  557.         else
  558.           {
  559.           fprintf(f,"\n");
  560.           }
  561.         fprintf(f,"  %-15s : %6s %s (%d downto 0) ",
  562.                make_vhdl_name(nam,skt->identifier),
  563.                decode_pin_VHDL[BIDIR],
  564.                default_vhdl_bustype->basetype,
  565.                skt->bundle_width-1);
  566.            
  567.          
  568.         need_term = 1;
  569.        }
  570.       else
  571. /* if the 'bundle' has less than MINBUNDLE pins, */
  572. /* list out all of the nets in turn as pins      */
  573.         {
  574.         node_t * node;
  575.         node = skt-> nodes;
  576.         while (node)
  577.          {
  578.          net = node->net;
  579. /*
  580.     printf("node %s\n",node->identifier);
  581. */
  582.          if(net && IS_ROUTABLE(net->how_routed) && net->bundle_member)
  583.            {
  584.           if(need_term)
  585.             {
  586.             fprintf(f,";\n");
  587.             need_term = 0;
  588.             }
  589.           else
  590.             {
  591.             fprintf(f,"\n");
  592.             }
  593.            fprintf(f,"  %-15s : %6s ",
  594.                make_vhdl_name(nam,net->name),
  595.                decode_pin_VHDL[net->ext_dir]);
  596.            decode_vhdl_type(f,net->vhdltype,RECURSE_NUMBER);
  597.            need_term = 1;
  598.            }
  599.          node = node->sktnext;
  600.          }
  601.  
  602.         }
  603.       }
  604.    
  605.     skt = skt->next;
  606.     }
  607.  
  608.  
  609.  
  610.  
  611.   /* go back and list all of the non-bundle pins */
  612.  
  613.  
  614.  
  615.  
  616.   net = named_list;
  617.  
  618.   while(net){
  619.     /* print out only unbundled nets as ports of the pcb */
  620.     if(net->leaves_partition && !net->bundle_member)
  621.       {
  622.       if(need_term)
  623.         {
  624.         fprintf(f,";\n");
  625.         }
  626.       else
  627.         {
  628.         fprintf(f,"\n");
  629.         }
  630.       fprintf(f,"  %-15s : %6s ",
  631.                make_vhdl_name(nam,net->name),
  632.                decode_pin_VHDL[net->ext_dir]);
  633.         decode_vhdl_type(f,net->vhdltype,RECURSE_NUMBER);
  634.          
  635.       need_term = 1;
  636.       }
  637.     net=net->next;
  638.  
  639.   }
  640.   fprintf(f,"\n     );\n");
  641.   fprintf(f,"END %s;\n\n",entityname);
  642.  
  643. }
  644.  
  645.  
  646. /* ********************************************************************** */
  647. /* generate default VHDL Libraries */
  648. /* ********************************************************************** */
  649. void print_VHDL_libs(FILE * f)
  650. {
  651.   fprintf(f,"LIBRARY IEEE,WORK;\nUSE IEEE.std_logic_1164.ALL;\n\n");
  652. }
  653.  
  654. /* ********************************************************************** */
  655. /* generate a VHDL architecture forselected sockets */
  656. /* ********************************************************************** */
  657. void print_VHDL_architecture(FILE * f,char * entityname) {
  658.   socket_t * skt;
  659.   char * arch_name;
  660.   generic_info_t gen[1];
  661.   /* if we are using VHDL then look at the VHDL architecture name if  defined*/
  662.  
  663.   arch_name = (get_generic_value(&global_generics, "vhdl_arch_name",gen) == IS_ENV_VAL && gen->expr) ?
  664.                gen->expr->left.s : "top_arch" ;
  665.   fprintf(f,"\n\nARCHITECTURE %s OF  %s IS\n\n",arch_name,entityname);
  666. /* not allowed to have generics at the top level so put them here */
  667.   list_VHDL_constants(f,&partition_generics);
  668.  
  669.   list_VHDL_constants(f,&global_generics);
  670.    /* clear type seen flags on all socket templates = components */
  671.   clr_type_seen();
  672.  
  673.   skt = socket_head;
  674.   /* list out templates for those sockets selected */
  675.     while(skt){
  676.     if(skt->is_external && skt->highest_bundle==0 ) {
  677.   /* suppress printout of duplicate components .... */
  678.       if(skt->template_socket)
  679.         {
  680.         if( skt->template_socket->socket_type_seen == 0)
  681.           {
  682.           print_VHDL_component(f,skt->template_socket,0);
  683.           skt->template_socket->socket_type_seen = 1;
  684.           }
  685.         }
  686.       else
  687.         /* no components, use socket/entity as its own component */
  688.         print_VHDL_component(f,skt,0);
  689.       }
  690.     skt = skt->next;
  691.     }
  692.  
  693.  
  694.  
  695.  
  696.   print_VHDL_sigs(f);
  697.   fprintf(f,"\n\nBEGIN\n\n");
  698.   skt = socket_head;
  699.   while(skt){
  700.     if(skt->is_external && skt->highest_bundle == 0)
  701.        print_VHDL_instance(f,skt,0);
  702.     skt = skt->next;
  703.   }
  704.   print_VHDL_assignments(f);
  705.   fprintf(f,"END %s;\n\n",arch_name);
  706.   }
  707.  
  708. /* ********************************************************************** */
  709. /* generate a VHDL file */
  710. /* ********************************************************************** */
  711.  
  712. void produce_VHDL(FILE * f,char * entityname,char *template) {
  713.   char linebuff[256];
  714.   int done_entity =0,done_architecture=0;
  715.   if(!template || !template[0]) { /* check null pointer or empty string */
  716.     fprintf(f,"-- vertical vhdl\n");
  717.     print_header(f,"WRITE VHDL");
  718.     print_VHDL_libs(f);
  719.     fprintf(f,"\n-- vertical read_off\n");
  720.     print_VHDL_entity(f,entityname);
  721.     fprintf(f,"\n-- vertical read_on\n");
  722.     print_VHDL_libs(f);
  723.     print_VHDL_architecture(f,entityname);
  724.     fprintf(f,"\n-- vertical end;\n");
  725.     }
  726.   else { /* there is a template file */
  727.     FILE * tp;
  728.     tp=fopen(template,"r");
  729.     if(tp) {
  730.    
  731.       fprintf(f,"-- vertical vhdl\n");
  732.       print_header(f,"WRITE VHDL");
  733.       fprintf(f,"-- Using template '%s'\n",template);
  734.       while(!feof(tp)){
  735.         if(fgets(linebuff,256,tp)) {
  736.           if(strstr(linebuff,"$ENT")) {
  737.             fprintf(f,"\n-- vertical read_off\n");
  738.             print_VHDL_entity(f,entityname);
  739.             fprintf(f,"\n-- vertical read_on\n");
  740.             done_entity++;
  741.             }
  742.           else if (strstr(linebuff,"$ARCH")){
  743.             print_VHDL_architecture(f,entityname);
  744.             done_architecture++;
  745.             }
  746.           else
  747.             fprintf(f,"%s",linebuff); /* it already has a '\n' on the end */
  748.           }
  749.         }
  750.       fprintf(f,"\n-- vertical end;\n");
  751.       fclose(tp);
  752.       if(done_entity!=1)
  753.         Log(LOG_ERROR,"-- Error: %d  $ENT$ tags counted in template '%s'\n",template);
  754.       if(done_architecture!=1)
  755.         Log(LOG_ERROR,"-- Error: %d  $ARCH$ tags counted in template '%s'\n",template);
  756.        
  757.       }
  758.     else
  759.       Log(LOG_ERROR,"-- Error: Cannot open VHDL  template '%s'\n",template);
  760.      
  761.     }
  762.   }
  763.        
  764.  
  765.  
  766.  
  767.