/*
* $Id: print_ports.c,v 1.1.1.1 2003/11/04 23:34:57 mjames Exp $
*
* $Log: print_ports.c,v $
* Revision 1.1.1.1 2003/11/04 23:34:57 mjames
* Imported into local repositrory
*
* Revision 1.11 2002/09/09 10:12:13 mjames
* Moved pin remapping function to pin ident editing function from
* sorting pin name routine.
*
* Revision 1.10 2002/01/03 16:36:10 mjames
* Method of accessing Vertical version changed to avoid
* global variable
*
* Revision 1.9 2001/12/13 22:16:51 mjames
* Using #ident with header to identify file
*
* fixed missing return code on function
*
* Revision 1.8 2001/10/31 22:20:11 mjames
* Tidying up problematical comments caused by CVS
* 'intelligent' comment guessing
*
* Revision 1.7 2001/10/31 16:20:39 mjames
* Added a datastructure to hide regular expression information from programs.
* Changed call to regexec to indicate 0 subexpressions to be matched
* rather than a number dependent on strlen(string) which was wrong.
*
* Revision 1.6 2001/10/23 21:11:08 mjames
* Refined the printout to make the generated HTML indicate
* bundle information in the cross reference list.
*
* Revision 1.5 2001/10/10 20:18:23 mjames
* Added a vert_regcomp function to compile regular expressions
* with '^' (match start string) and '$' (match end string) bracketing
* this => wildcard must match entire string not just a part of it.
*
* Revision 1.4 2001/10/07 20:50:52 mjames
* Added wildcard checking (warn user about
* using wildcard '*' on the end of a string in stead of wildcard '.*')
*
* Revision 1.3 2001/09/28 10:17:14 mjames
* Removed coredump caused by trying to free() an auto variable in the
* regular expression handler
*
* Revision 1.2 2001/09/25 23:15:23 mjames
* Converted wildcards to use proper regexp pattern match library
*
* Revision 1.1 2001/09/21 14:19:52 mjames
* Implemented Write Pin command : fixed up HTML output
*
*/
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <ctype.h>
#include <time.h>
#include <sys/types.h>
#include <regex.h>
#include "vertcl_main.h"
#include "expression.h"
#include "generic.h"
#include "database.h"
#include "printout.h"
#include "print_vhdl.h"
#include "print_vlog.h"
#include "print_ports.h"
#include "sorting.h"
#include "cmdparse.h"
#include "cmdlog.h"
#include "equivalent.h"
#include "version.h"
#include "chck_names.h"
#ident "@(#)$Header: c:\\cygwin\\cvsroot/Vert03/vertlib/print_ports.c,v 1.1.1.1 2003/11/04 23:34:57 mjames Exp $"
/* for each pin on the connector, list out all of the information */
int list_intersection(FILE * f,char * con_id, char * fpga_id)
{
socket_t * connector = socket_head;
int found = 0;
int rc;
socket_t * fpga;
noderef_t * bnode;
node_t * node;
unsigned int sockets = 0;
unsigned int printed = 0;
/* compile regular expression */
vert_regex_t * preg;
fpga = find_socket(Ident,fpga_id, Search,&socket_head);
if(!fpga)
{
Log(LOG_ERROR,"-- write pin cannot find fpga '%s'\n",
fpga_id);
return TCL_ERROR;
}
rc = vert_regcomp(&preg,con_id);
if (rc != 0 )
{
char errbuff[100];
regerror(rc,preg->preg,errbuff,100);
Log(LOG_ERROR,"-- Problem (rc=%d) %s with '%s' as regular expression\n",rc,errbuff,con_id);
return TCL_ERROR;
}
else
{
Log(LOG_GENERAL,"-- Using '%s' as match pattern\n",con_id);
}
fprintf(f
,"<title>Cross ref for socket(s) '%s' and (FPGA) socket '%s'</title>\n", con_id,fpga_id);
fprintf(f
,"<h2>Column names:</h2>\n" "<dl>\n"
"<dt><b>socket pin</b><dd>The pin of the relevant socket.\n"
"<dt><b>index</b><dd>The Certify pin bundle index(if assigned)\n"
"<dt><b>net ident.</b><dd>The PCB netlist name (or jumper name)\n"
"<dt><b>sig. name</b><dd>The name of any signal routed through this net\n"
"</dl>\n"
"Please note only one fpga pin is given out of many if a multiple connection exists\n");
while(connector)
{
found = regexec(preg->preg,connector->identifier,0,preg->regpatt,0);
if(!found)
{
int first_print = 1; /* suppress tables until needed */
sockets ++;
sort_nodes(connector,NO_EXTRACT_XY); /* sort the pins on the connector */
node = connector->nodes;
/*
printf("completed sort\n");
*/
while(node)
{
if (node->net)
{
int found_node = 0;
bnode = node->net->nodes;
while(bnode && !found_node)
{
char * msg;
char bundle_msg[20];
if (bnode->node && bnode->node->socket==fpga)
{
if(first_print)
{
"<h3>connector id=%s name=%s and fpga id=%s name=%s</h3>\n",
connector->identifier,
connector->name?connector->name:"",
fpga->identifier,
fpga->name?fpga->name:"");
fprintf(f
,"<tr><td> socket pin</td> <td>index</td> <td>fpga pin</td> <td>net ident.</td><td>sig. name</td></tr>\n"); first_print = 0;
}
if (node->bundle_index==0)
{
msg = "-";
}
else if (node->bundle_index < 0)
{
msg = "NC";
}
else
{
sprintf(bundle_msg
,"%d",node
->bundle_index
); msg = bundle_msg;
}
fprintf(f
,"<tr><td>%s(%s)</td><td>%s</td> <td>%s(%s)</td> <td>%s</td><td>%s</td></tr>\n", connector->identifier,node->identifier,
msg,
fpga->identifier,bnode->node->identifier,
bnode->net->name?bnode->net->identifier:"",
bnode->net->name?bnode->net->name:"" );
found_node = 1 ; /* force loop termination */
}
bnode = bnode->next;
}
}
node = node->sktnext;
}
if(!first_print)
{
printed++;
}
}
connector= connector->next;
}
fprintf(f
,"Tables generated by Vertical %s\n" "<br>© Philips Semiconductors SLS. "__DATE__
"<a href=mailto:Mike.D.James@philips.com><address>mailto:Mike.D.James@philips.com</address></a>\n"
"</html>\n",Vertical_Version);
vert_regfree(&preg);
Log(LOG_GENERAL,"-- located %d sockets matching pattern\n",sockets);
Log(LOG_GENERAL,"-- of which %d actually connect to '%s'\n",printed,fpga_id);
return TCL_OK;
}