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  1. --       Altera EPLD / PCB / VHDL tools        --
  2. -- (c) Philips Semiconductors Southampton 1996-2001 --
  3.  
  4. -- by: Mike James (Mike.D.James@philips.com)
  5.  
  6. -- package version:12.02 Verilog  compiled: May 21 2001--
  7.  
  8. -- Produced by WRITE VHDL (PC-CygWin)
  9. -- at 16:10:14  on 21/05/2001
  10.  
  11. LIBRARY IEEE,WORK;
  12. USE IEEE.std_logic_1164.ALL;
  13.  
  14. ENTITY top IS
  15.   PORT (
  16.  
  17.      );
  18. END top;
  19.  
  20. LIBRARY IEEE,WORK;
  21. USE IEEE.std_logic_1164.ALL;
  22.  
  23.  
  24.  
  25. ARCHITECTURE top_arch OF  top IS
  26.  
  27.  
  28.  
  29. COMPONENT  rpl_sub_n5_3
  30. --  DEV_IDENT "rpl_sub_n5_3"
  31.  
  32.   PORT (
  33. );
  34. END COMPONENT;
  35.  
  36.  
  37.  
  38. BEGIN
  39.  
  40. rpl_sub_n5_3 : rpl_sub_n5_3
  41.   PORT MAP (
  42.  
  43.    );
  44.  
  45. -- Buffered signals
  46.  
  47. --
  48.  
  49. END top_arch;
  50.  
  51.