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// vertical verilog
/*       Altera EPLD / PCB / VHDL tools        */
/* (c) Philips Semiconductors Southampton 1996-2001 */

/* by: Mike James (Mike.D.James@philips.com) */
/* package version: 15.2a Package  compiled: Jan 16 2002 at 22:03:40*/

/* Produced by WRITE VLOG (PC-CygWin)
 * at 22:06:54  on 16/01/2002 

*/
module top (
  );
/* synthesis syn_partition = "board" */ 


/* Bundle signals */

/* end bundle signals */ 

/* Buffered signals */

/* end Buffered signals */ 

endmodule


// vertical end;