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// vertical verilog
/* Altera EPLD / PCB / VHDL tools */
/* (c) Philips Semiconductors Southampton 1996-2001 */
/* by: Mike James (Mike.D.James@philips.com) */
/* package version: 14.6a Regexp compiled: Nov 28 2001 at 10:13:27*/
/* Produced by WRITE VLOG (PC-CygWin)
* at 10:59:37 on 28/11/2001
*/
module top (
);
/* synthesis syn_partition = "board" */
/* Bundle signals */
/* end bundle signals */
/* Buffered signals */
/* end Buffered signals */
endmodule
// vertical end;