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ARM GAS C:\Users\mike\AppData\Local\Temp\cc5OGnig.s page 1
1 .cpu cortex-m3
2 .eabi_attribute 20, 1
3 .eabi_attribute 21, 1
4 .eabi_attribute 23, 3
5 .eabi_attribute 24, 1
6 .eabi_attribute 25, 1
7 .eabi_attribute 26, 1
8 .eabi_attribute 30, 1
9 .eabi_attribute 34, 1
10 .eabi_attribute 18, 4
11 .file "system_stm32f1xx.c"
12 .text
13 .Ltext0:
14 .cfi_sections .debug_frame
15 .section .text.SystemInit,"ax",%progbits
16 .align 1
17 .global SystemInit
18 .arch armv7-m
19 .syntax unified
20 .thumb
21 .thumb_func
22 .fpu softvfp
24 SystemInit:
25 .LFB65:
26 .file 1 "Core/Src/system_stm32f1xx.c"
1:Core/Src/system_stm32f1xx.c **** /**
2:Core/Src/system_stm32f1xx.c **** ******************************************************************************
3:Core/Src/system_stm32f1xx.c **** * @file system_stm32f1xx.c
4:Core/Src/system_stm32f1xx.c **** * @author MCD Application Team
5:Core/Src/system_stm32f1xx.c **** * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
6:Core/Src/system_stm32f1xx.c **** *
7:Core/Src/system_stm32f1xx.c **** * 1. This file provides two functions and one global variable to be called from
8:Core/Src/system_stm32f1xx.c **** * user application:
9:Core/Src/system_stm32f1xx.c **** * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
10:Core/Src/system_stm32f1xx.c **** * factors, AHB/APBx prescalers and Flash settings).
11:Core/Src/system_stm32f1xx.c **** * This function is called at startup just after reset and
12:Core/Src/system_stm32f1xx.c **** * before branch to main program. This call is made inside
13:Core/Src/system_stm32f1xx.c **** * the "startup_stm32f1xx_xx.s" file.
14:Core/Src/system_stm32f1xx.c **** *
15:Core/Src/system_stm32f1xx.c **** * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
16:Core/Src/system_stm32f1xx.c **** * by the user application to setup the SysTick
17:Core/Src/system_stm32f1xx.c **** * timer or configure other parameters.
18:Core/Src/system_stm32f1xx.c **** *
19:Core/Src/system_stm32f1xx.c **** * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
20:Core/Src/system_stm32f1xx.c **** * be called whenever the core clock is changed
21:Core/Src/system_stm32f1xx.c **** * during program execution.
22:Core/Src/system_stm32f1xx.c **** *
23:Core/Src/system_stm32f1xx.c **** * 2. After each device reset the HSI (8 MHz) is used as system clock source.
24:Core/Src/system_stm32f1xx.c **** * Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to
25:Core/Src/system_stm32f1xx.c **** * configure the system clock before to branch to main program.
26:Core/Src/system_stm32f1xx.c **** *
27:Core/Src/system_stm32f1xx.c **** * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on
28:Core/Src/system_stm32f1xx.c **** * the product used), refer to "HSE_VALUE".
29:Core/Src/system_stm32f1xx.c **** * When HSE is used as system clock source, directly or through PLL, and you
30:Core/Src/system_stm32f1xx.c **** * are using different crystal you have to adapt the HSE value to your own
31:Core/Src/system_stm32f1xx.c **** * configuration.
32:Core/Src/system_stm32f1xx.c **** *
ARM GAS C:\Users\mike\AppData\Local\Temp\cc5OGnig.s page 2
33:Core/Src/system_stm32f1xx.c **** ******************************************************************************
34:Core/Src/system_stm32f1xx.c **** * @attention
35:Core/Src/system_stm32f1xx.c **** *
36:Core/Src/system_stm32f1xx.c **** * <h2><center>© Copyright (c) 2017 STMicroelectronics.
37:Core/Src/system_stm32f1xx.c **** * All rights reserved.</center></h2>
38:Core/Src/system_stm32f1xx.c **** *
39:Core/Src/system_stm32f1xx.c **** * This software component is licensed by ST under BSD 3-Clause license,
40:Core/Src/system_stm32f1xx.c **** * the "License"; You may not use this file except in compliance with the
41:Core/Src/system_stm32f1xx.c **** * License. You may obtain a copy of the License at:
42:Core/Src/system_stm32f1xx.c **** * opensource.org/licenses/BSD-3-Clause
43:Core/Src/system_stm32f1xx.c **** *
44:Core/Src/system_stm32f1xx.c **** ******************************************************************************
45:Core/Src/system_stm32f1xx.c **** */
46:Core/Src/system_stm32f1xx.c ****
47:Core/Src/system_stm32f1xx.c **** /** @addtogroup CMSIS
48:Core/Src/system_stm32f1xx.c **** * @{
49:Core/Src/system_stm32f1xx.c **** */
50:Core/Src/system_stm32f1xx.c ****
51:Core/Src/system_stm32f1xx.c **** /** @addtogroup stm32f1xx_system
52:Core/Src/system_stm32f1xx.c **** * @{
53:Core/Src/system_stm32f1xx.c **** */
54:Core/Src/system_stm32f1xx.c ****
55:Core/Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_Includes
56:Core/Src/system_stm32f1xx.c **** * @{
57:Core/Src/system_stm32f1xx.c **** */
58:Core/Src/system_stm32f1xx.c ****
59:Core/Src/system_stm32f1xx.c **** #include "stm32f1xx.h"
60:Core/Src/system_stm32f1xx.c ****
61:Core/Src/system_stm32f1xx.c **** /**
62:Core/Src/system_stm32f1xx.c **** * @}
63:Core/Src/system_stm32f1xx.c **** */
64:Core/Src/system_stm32f1xx.c ****
65:Core/Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_TypesDefinitions
66:Core/Src/system_stm32f1xx.c **** * @{
67:Core/Src/system_stm32f1xx.c **** */
68:Core/Src/system_stm32f1xx.c ****
69:Core/Src/system_stm32f1xx.c **** /**
70:Core/Src/system_stm32f1xx.c **** * @}
71:Core/Src/system_stm32f1xx.c **** */
72:Core/Src/system_stm32f1xx.c ****
73:Core/Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_Defines
74:Core/Src/system_stm32f1xx.c **** * @{
75:Core/Src/system_stm32f1xx.c **** */
76:Core/Src/system_stm32f1xx.c ****
77:Core/Src/system_stm32f1xx.c **** #if !defined (HSE_VALUE)
78:Core/Src/system_stm32f1xx.c **** #define HSE_VALUE 8000000U /*!< Default value of the External oscillator in Hz.
79:Core/Src/system_stm32f1xx.c **** This value can be provided and adapted by the user
80:Core/Src/system_stm32f1xx.c **** #endif /* HSE_VALUE */
81:Core/Src/system_stm32f1xx.c ****
82:Core/Src/system_stm32f1xx.c **** #if !defined (HSI_VALUE)
83:Core/Src/system_stm32f1xx.c **** #define HSI_VALUE 8000000U /*!< Default value of the Internal oscillator in Hz.
84:Core/Src/system_stm32f1xx.c **** This value can be provided and adapted by the user
85:Core/Src/system_stm32f1xx.c **** #endif /* HSI_VALUE */
86:Core/Src/system_stm32f1xx.c ****
87:Core/Src/system_stm32f1xx.c **** /*!< Uncomment the following line if you need to use external SRAM */
88:Core/Src/system_stm32f1xx.c **** #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) ||
89:Core/Src/system_stm32f1xx.c **** /* #define DATA_IN_ExtSRAM */
ARM GAS C:\Users\mike\AppData\Local\Temp\cc5OGnig.s page 3
90:Core/Src/system_stm32f1xx.c **** #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
91:Core/Src/system_stm32f1xx.c ****
92:Core/Src/system_stm32f1xx.c **** /*!< Uncomment the following line if you need to relocate your vector Table in
93:Core/Src/system_stm32f1xx.c **** Internal SRAM. */
94:Core/Src/system_stm32f1xx.c **** /* #define VECT_TAB_SRAM */
95:Core/Src/system_stm32f1xx.c **** #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
96:Core/Src/system_stm32f1xx.c **** This value must be a multiple of 0x200. */
97:Core/Src/system_stm32f1xx.c ****
98:Core/Src/system_stm32f1xx.c ****
99:Core/Src/system_stm32f1xx.c **** /**
100:Core/Src/system_stm32f1xx.c **** * @}
101:Core/Src/system_stm32f1xx.c **** */
102:Core/Src/system_stm32f1xx.c ****
103:Core/Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_Macros
104:Core/Src/system_stm32f1xx.c **** * @{
105:Core/Src/system_stm32f1xx.c **** */
106:Core/Src/system_stm32f1xx.c ****
107:Core/Src/system_stm32f1xx.c **** /**
108:Core/Src/system_stm32f1xx.c **** * @}
109:Core/Src/system_stm32f1xx.c **** */
110:Core/Src/system_stm32f1xx.c ****
111:Core/Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_Variables
112:Core/Src/system_stm32f1xx.c **** * @{
113:Core/Src/system_stm32f1xx.c **** */
114:Core/Src/system_stm32f1xx.c ****
115:Core/Src/system_stm32f1xx.c **** /* This variable is updated in three ways:
116:Core/Src/system_stm32f1xx.c **** 1) by calling CMSIS function SystemCoreClockUpdate()
117:Core/Src/system_stm32f1xx.c **** 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
118:Core/Src/system_stm32f1xx.c **** 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
119:Core/Src/system_stm32f1xx.c **** Note: If you use this function to configure the system clock; then there
120:Core/Src/system_stm32f1xx.c **** is no need to call the 2 first functions listed above, since SystemCoreClock
121:Core/Src/system_stm32f1xx.c **** variable is updated automatically.
122:Core/Src/system_stm32f1xx.c **** */
123:Core/Src/system_stm32f1xx.c **** uint32_t SystemCoreClock = 16000000;
124:Core/Src/system_stm32f1xx.c **** const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
125:Core/Src/system_stm32f1xx.c **** const uint8_t APBPrescTable[8U] = {0, 0, 0, 0, 1, 2, 3, 4};
126:Core/Src/system_stm32f1xx.c ****
127:Core/Src/system_stm32f1xx.c **** /**
128:Core/Src/system_stm32f1xx.c **** * @}
129:Core/Src/system_stm32f1xx.c **** */
130:Core/Src/system_stm32f1xx.c ****
131:Core/Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_FunctionPrototypes
132:Core/Src/system_stm32f1xx.c **** * @{
133:Core/Src/system_stm32f1xx.c **** */
134:Core/Src/system_stm32f1xx.c ****
135:Core/Src/system_stm32f1xx.c **** #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) ||
136:Core/Src/system_stm32f1xx.c **** #ifdef DATA_IN_ExtSRAM
137:Core/Src/system_stm32f1xx.c **** static void SystemInit_ExtMemCtl(void);
138:Core/Src/system_stm32f1xx.c **** #endif /* DATA_IN_ExtSRAM */
139:Core/Src/system_stm32f1xx.c **** #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
140:Core/Src/system_stm32f1xx.c ****
141:Core/Src/system_stm32f1xx.c **** /**
142:Core/Src/system_stm32f1xx.c **** * @}
143:Core/Src/system_stm32f1xx.c **** */
144:Core/Src/system_stm32f1xx.c ****
145:Core/Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_Functions
146:Core/Src/system_stm32f1xx.c **** * @{
ARM GAS C:\Users\mike\AppData\Local\Temp\cc5OGnig.s page 4
147:Core/Src/system_stm32f1xx.c **** */
148:Core/Src/system_stm32f1xx.c ****
149:Core/Src/system_stm32f1xx.c **** /**
150:Core/Src/system_stm32f1xx.c **** * @brief Setup the microcontroller system
151:Core/Src/system_stm32f1xx.c **** * Initialize the Embedded Flash Interface, the PLL and update the
152:Core/Src/system_stm32f1xx.c **** * SystemCoreClock variable.
153:Core/Src/system_stm32f1xx.c **** * @note This function should be used only after reset.
154:Core/Src/system_stm32f1xx.c **** * @param None
155:Core/Src/system_stm32f1xx.c **** * @retval None
156:Core/Src/system_stm32f1xx.c **** */
157:Core/Src/system_stm32f1xx.c **** void SystemInit (void)
158:Core/Src/system_stm32f1xx.c **** {
27 .loc 1 158 1 view -0
28 .cfi_startproc
29 @ args = 0, pretend = 0, frame = 0
30 @ frame_needed = 0, uses_anonymous_args = 0
31 @ link register save eliminated.
159:Core/Src/system_stm32f1xx.c **** /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
160:Core/Src/system_stm32f1xx.c **** /* Set HSION bit */
161:Core/Src/system_stm32f1xx.c **** RCC->CR |= 0x00000001U;
32 .loc 1 161 3 view .LVU1
33 .loc 1 161 11 is_stmt 0 view .LVU2
34 0000 0F4B ldr r3, .L2
35 0002 1A68 ldr r2, [r3]
36 0004 42F00102 orr r2, r2, #1
37 0008 1A60 str r2, [r3]
162:Core/Src/system_stm32f1xx.c ****
163:Core/Src/system_stm32f1xx.c **** /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
164:Core/Src/system_stm32f1xx.c **** #if !defined(STM32F105xC) && !defined(STM32F107xC)
165:Core/Src/system_stm32f1xx.c **** RCC->CFGR &= 0xF8FF0000U;
38 .loc 1 165 3 is_stmt 1 view .LVU3
39 .loc 1 165 13 is_stmt 0 view .LVU4
40 000a 5968 ldr r1, [r3, #4]
41 000c 0D4A ldr r2, .L2+4
42 000e 0A40 ands r2, r2, r1
43 0010 5A60 str r2, [r3, #4]
166:Core/Src/system_stm32f1xx.c **** #else
167:Core/Src/system_stm32f1xx.c **** RCC->CFGR &= 0xF0FF0000U;
168:Core/Src/system_stm32f1xx.c **** #endif /* STM32F105xC */
169:Core/Src/system_stm32f1xx.c ****
170:Core/Src/system_stm32f1xx.c **** /* Reset HSEON, CSSON and PLLON bits */
171:Core/Src/system_stm32f1xx.c **** RCC->CR &= 0xFEF6FFFFU;
44 .loc 1 171 3 is_stmt 1 view .LVU5
45 .loc 1 171 11 is_stmt 0 view .LVU6
46 0012 1A68 ldr r2, [r3]
47 0014 22F08472 bic r2, r2, #17301504
48 0018 22F48032 bic r2, r2, #65536
49 001c 1A60 str r2, [r3]
172:Core/Src/system_stm32f1xx.c ****
173:Core/Src/system_stm32f1xx.c **** /* Reset HSEBYP bit */
174:Core/Src/system_stm32f1xx.c **** RCC->CR &= 0xFFFBFFFFU;
50 .loc 1 174 3 is_stmt 1 view .LVU7
51 .loc 1 174 11 is_stmt 0 view .LVU8
52 001e 1A68 ldr r2, [r3]
53 0020 22F48022 bic r2, r2, #262144
54 0024 1A60 str r2, [r3]
175:Core/Src/system_stm32f1xx.c ****
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176:Core/Src/system_stm32f1xx.c **** /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
177:Core/Src/system_stm32f1xx.c **** RCC->CFGR &= 0xFF80FFFFU;
55 .loc 1 177 3 is_stmt 1 view .LVU9
56 .loc 1 177 13 is_stmt 0 view .LVU10
57 0026 5A68 ldr r2, [r3, #4]
58 0028 22F4FE02 bic r2, r2, #8323072
59 002c 5A60 str r2, [r3, #4]
178:Core/Src/system_stm32f1xx.c ****
179:Core/Src/system_stm32f1xx.c **** #if defined(STM32F105xC) || defined(STM32F107xC)
180:Core/Src/system_stm32f1xx.c **** /* Reset PLL2ON and PLL3ON bits */
181:Core/Src/system_stm32f1xx.c **** RCC->CR &= 0xEBFFFFFFU;
182:Core/Src/system_stm32f1xx.c ****
183:Core/Src/system_stm32f1xx.c **** /* Disable all interrupts and clear pending bits */
184:Core/Src/system_stm32f1xx.c **** RCC->CIR = 0x00FF0000U;
185:Core/Src/system_stm32f1xx.c ****
186:Core/Src/system_stm32f1xx.c **** /* Reset CFGR2 register */
187:Core/Src/system_stm32f1xx.c **** RCC->CFGR2 = 0x00000000U;
188:Core/Src/system_stm32f1xx.c **** #elif defined(STM32F100xB) || defined(STM32F100xE)
189:Core/Src/system_stm32f1xx.c **** /* Disable all interrupts and clear pending bits */
190:Core/Src/system_stm32f1xx.c **** RCC->CIR = 0x009F0000U;
191:Core/Src/system_stm32f1xx.c ****
192:Core/Src/system_stm32f1xx.c **** /* Reset CFGR2 register */
193:Core/Src/system_stm32f1xx.c **** RCC->CFGR2 = 0x00000000U;
194:Core/Src/system_stm32f1xx.c **** #else
195:Core/Src/system_stm32f1xx.c **** /* Disable all interrupts and clear pending bits */
196:Core/Src/system_stm32f1xx.c **** RCC->CIR = 0x009F0000U;
60 .loc 1 196 3 is_stmt 1 view .LVU11
61 .loc 1 196 12 is_stmt 0 view .LVU12
62 002e 4FF41F02 mov r2, #10420224
63 0032 9A60 str r2, [r3, #8]
197:Core/Src/system_stm32f1xx.c **** #endif /* STM32F105xC */
198:Core/Src/system_stm32f1xx.c ****
199:Core/Src/system_stm32f1xx.c **** #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) ||
200:Core/Src/system_stm32f1xx.c **** #ifdef DATA_IN_ExtSRAM
201:Core/Src/system_stm32f1xx.c **** SystemInit_ExtMemCtl();
202:Core/Src/system_stm32f1xx.c **** #endif /* DATA_IN_ExtSRAM */
203:Core/Src/system_stm32f1xx.c **** #endif
204:Core/Src/system_stm32f1xx.c ****
205:Core/Src/system_stm32f1xx.c **** #ifdef VECT_TAB_SRAM
206:Core/Src/system_stm32f1xx.c **** SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
207:Core/Src/system_stm32f1xx.c **** #else
208:Core/Src/system_stm32f1xx.c **** SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
64 .loc 1 208 3 is_stmt 1 view .LVU13
65 .loc 1 208 13 is_stmt 0 view .LVU14
66 0034 044B ldr r3, .L2+8
67 0036 4FF00062 mov r2, #134217728
68 003a 9A60 str r2, [r3, #8]
209:Core/Src/system_stm32f1xx.c **** #endif
210:Core/Src/system_stm32f1xx.c **** }
69 .loc 1 210 1 view .LVU15
70 003c 7047 bx lr
71 .L3:
72 003e 00BF .align 2
73 .L2:
74 0040 00100240 .word 1073876992
75 0044 0000FFF8 .word -117506048
76 0048 00ED00E0 .word -536810240
ARM GAS C:\Users\mike\AppData\Local\Temp\cc5OGnig.s page 6
77 .cfi_endproc
78 .LFE65:
80 .section .text.SystemCoreClockUpdate,"ax",%progbits
81 .align 1
82 .global SystemCoreClockUpdate
83 .syntax unified
84 .thumb
85 .thumb_func
86 .fpu softvfp
88 SystemCoreClockUpdate:
89 .LFB66:
211:Core/Src/system_stm32f1xx.c ****
212:Core/Src/system_stm32f1xx.c **** /**
213:Core/Src/system_stm32f1xx.c **** * @brief Update SystemCoreClock variable according to Clock Register Values.
214:Core/Src/system_stm32f1xx.c **** * The SystemCoreClock variable contains the core clock (HCLK), it can
215:Core/Src/system_stm32f1xx.c **** * be used by the user application to setup the SysTick timer or configure
216:Core/Src/system_stm32f1xx.c **** * other parameters.
217:Core/Src/system_stm32f1xx.c **** *
218:Core/Src/system_stm32f1xx.c **** * @note Each time the core clock (HCLK) changes, this function must be called
219:Core/Src/system_stm32f1xx.c **** * to update SystemCoreClock variable value. Otherwise, any configuration
220:Core/Src/system_stm32f1xx.c **** * based on this variable will be incorrect.
221:Core/Src/system_stm32f1xx.c **** *
222:Core/Src/system_stm32f1xx.c **** * @note - The system frequency computed by this function is not the real
223:Core/Src/system_stm32f1xx.c **** * frequency in the chip. It is calculated based on the predefined
224:Core/Src/system_stm32f1xx.c **** * constant and the selected clock source:
225:Core/Src/system_stm32f1xx.c **** *
226:Core/Src/system_stm32f1xx.c **** * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
227:Core/Src/system_stm32f1xx.c **** *
228:Core/Src/system_stm32f1xx.c **** * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
229:Core/Src/system_stm32f1xx.c **** *
230:Core/Src/system_stm32f1xx.c **** * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
231:Core/Src/system_stm32f1xx.c **** * or HSI_VALUE(*) multiplied by the PLL factors.
232:Core/Src/system_stm32f1xx.c **** *
233:Core/Src/system_stm32f1xx.c **** * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
234:Core/Src/system_stm32f1xx.c **** * 8 MHz) but the real value may vary depending on the variations
235:Core/Src/system_stm32f1xx.c **** * in voltage and temperature.
236:Core/Src/system_stm32f1xx.c **** *
237:Core/Src/system_stm32f1xx.c **** * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
238:Core/Src/system_stm32f1xx.c **** * 8 MHz or 25 MHz, depending on the product used), user has to ensure
239:Core/Src/system_stm32f1xx.c **** * that HSE_VALUE is same as the real frequency of the crystal used.
240:Core/Src/system_stm32f1xx.c **** * Otherwise, this function may have wrong result.
241:Core/Src/system_stm32f1xx.c **** *
242:Core/Src/system_stm32f1xx.c **** * - The result of this function could be not correct when using fractional
243:Core/Src/system_stm32f1xx.c **** * value for HSE crystal.
244:Core/Src/system_stm32f1xx.c **** * @param None
245:Core/Src/system_stm32f1xx.c **** * @retval None
246:Core/Src/system_stm32f1xx.c **** */
247:Core/Src/system_stm32f1xx.c **** void SystemCoreClockUpdate (void)
248:Core/Src/system_stm32f1xx.c **** {
90 .loc 1 248 1 is_stmt 1 view -0
91 .cfi_startproc
92 @ args = 0, pretend = 0, frame = 0
93 @ frame_needed = 0, uses_anonymous_args = 0
94 @ link register save eliminated.
249:Core/Src/system_stm32f1xx.c **** uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U;
95 .loc 1 249 3 view .LVU17
96 .LVL0:
ARM GAS C:\Users\mike\AppData\Local\Temp\cc5OGnig.s page 7
250:Core/Src/system_stm32f1xx.c ****
251:Core/Src/system_stm32f1xx.c **** #if defined(STM32F105xC) || defined(STM32F107xC)
252:Core/Src/system_stm32f1xx.c **** uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U;
253:Core/Src/system_stm32f1xx.c **** #endif /* STM32F105xC */
254:Core/Src/system_stm32f1xx.c ****
255:Core/Src/system_stm32f1xx.c **** #if defined(STM32F100xB) || defined(STM32F100xE)
256:Core/Src/system_stm32f1xx.c **** uint32_t prediv1factor = 0U;
257:Core/Src/system_stm32f1xx.c **** #endif /* STM32F100xB or STM32F100xE */
258:Core/Src/system_stm32f1xx.c ****
259:Core/Src/system_stm32f1xx.c **** /* Get SYSCLK source -------------------------------------------------------*/
260:Core/Src/system_stm32f1xx.c **** tmp = RCC->CFGR & RCC_CFGR_SWS;
97 .loc 1 260 3 view .LVU18
98 .loc 1 260 12 is_stmt 0 view .LVU19
99 0000 1F4B ldr r3, .L12
100 0002 5B68 ldr r3, [r3, #4]
101 .loc 1 260 7 view .LVU20
102 0004 03F00C03 and r3, r3, #12
103 .LVL1:
261:Core/Src/system_stm32f1xx.c ****
262:Core/Src/system_stm32f1xx.c **** switch (tmp)
104 .loc 1 262 3 is_stmt 1 view .LVU21
105 0008 042B cmp r3, #4
106 000a 14D0 beq .L5
107 000c 082B cmp r3, #8
108 000e 16D0 beq .L6
109 0010 1BB1 cbz r3, .L11
263:Core/Src/system_stm32f1xx.c **** {
264:Core/Src/system_stm32f1xx.c **** case 0x00U: /* HSI used as system clock */
265:Core/Src/system_stm32f1xx.c **** SystemCoreClock = HSI_VALUE;
266:Core/Src/system_stm32f1xx.c **** break;
267:Core/Src/system_stm32f1xx.c **** case 0x04U: /* HSE used as system clock */
268:Core/Src/system_stm32f1xx.c **** SystemCoreClock = HSE_VALUE;
269:Core/Src/system_stm32f1xx.c **** break;
270:Core/Src/system_stm32f1xx.c **** case 0x08U: /* PLL used as system clock */
271:Core/Src/system_stm32f1xx.c ****
272:Core/Src/system_stm32f1xx.c **** /* Get PLL clock source and multiplication factor ----------------------*/
273:Core/Src/system_stm32f1xx.c **** pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
274:Core/Src/system_stm32f1xx.c **** pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
275:Core/Src/system_stm32f1xx.c ****
276:Core/Src/system_stm32f1xx.c **** #if !defined(STM32F105xC) && !defined(STM32F107xC)
277:Core/Src/system_stm32f1xx.c **** pllmull = ( pllmull >> 18U) + 2U;
278:Core/Src/system_stm32f1xx.c ****
279:Core/Src/system_stm32f1xx.c **** if (pllsource == 0x00U)
280:Core/Src/system_stm32f1xx.c **** {
281:Core/Src/system_stm32f1xx.c **** /* HSI oscillator clock divided by 2 selected as PLL clock entry */
282:Core/Src/system_stm32f1xx.c **** SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
283:Core/Src/system_stm32f1xx.c **** }
284:Core/Src/system_stm32f1xx.c **** else
285:Core/Src/system_stm32f1xx.c **** {
286:Core/Src/system_stm32f1xx.c **** #if defined(STM32F100xB) || defined(STM32F100xE)
287:Core/Src/system_stm32f1xx.c **** prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
288:Core/Src/system_stm32f1xx.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */
289:Core/Src/system_stm32f1xx.c **** SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
290:Core/Src/system_stm32f1xx.c **** #else
291:Core/Src/system_stm32f1xx.c **** /* HSE selected as PLL clock entry */
292:Core/Src/system_stm32f1xx.c **** if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
293:Core/Src/system_stm32f1xx.c **** {/* HSE oscillator clock divided by 2 */
ARM GAS C:\Users\mike\AppData\Local\Temp\cc5OGnig.s page 8
294:Core/Src/system_stm32f1xx.c **** SystemCoreClock = (HSE_VALUE >> 1U) * pllmull;
295:Core/Src/system_stm32f1xx.c **** }
296:Core/Src/system_stm32f1xx.c **** else
297:Core/Src/system_stm32f1xx.c **** {
298:Core/Src/system_stm32f1xx.c **** SystemCoreClock = HSE_VALUE * pllmull;
299:Core/Src/system_stm32f1xx.c **** }
300:Core/Src/system_stm32f1xx.c **** #endif
301:Core/Src/system_stm32f1xx.c **** }
302:Core/Src/system_stm32f1xx.c **** #else
303:Core/Src/system_stm32f1xx.c **** pllmull = pllmull >> 18U;
304:Core/Src/system_stm32f1xx.c ****
305:Core/Src/system_stm32f1xx.c **** if (pllmull != 0x0DU)
306:Core/Src/system_stm32f1xx.c **** {
307:Core/Src/system_stm32f1xx.c **** pllmull += 2U;
308:Core/Src/system_stm32f1xx.c **** }
309:Core/Src/system_stm32f1xx.c **** else
310:Core/Src/system_stm32f1xx.c **** { /* PLL multiplication factor = PLL input clock * 6.5 */
311:Core/Src/system_stm32f1xx.c **** pllmull = 13U / 2U;
312:Core/Src/system_stm32f1xx.c **** }
313:Core/Src/system_stm32f1xx.c ****
314:Core/Src/system_stm32f1xx.c **** if (pllsource == 0x00U)
315:Core/Src/system_stm32f1xx.c **** {
316:Core/Src/system_stm32f1xx.c **** /* HSI oscillator clock divided by 2 selected as PLL clock entry */
317:Core/Src/system_stm32f1xx.c **** SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
318:Core/Src/system_stm32f1xx.c **** }
319:Core/Src/system_stm32f1xx.c **** else
320:Core/Src/system_stm32f1xx.c **** {/* PREDIV1 selected as PLL clock entry */
321:Core/Src/system_stm32f1xx.c ****
322:Core/Src/system_stm32f1xx.c **** /* Get PREDIV1 clock source and division factor */
323:Core/Src/system_stm32f1xx.c **** prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
324:Core/Src/system_stm32f1xx.c **** prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
325:Core/Src/system_stm32f1xx.c ****
326:Core/Src/system_stm32f1xx.c **** if (prediv1source == 0U)
327:Core/Src/system_stm32f1xx.c **** {
328:Core/Src/system_stm32f1xx.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */
329:Core/Src/system_stm32f1xx.c **** SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
330:Core/Src/system_stm32f1xx.c **** }
331:Core/Src/system_stm32f1xx.c **** else
332:Core/Src/system_stm32f1xx.c **** {/* PLL2 clock selected as PREDIV1 clock entry */
333:Core/Src/system_stm32f1xx.c ****
334:Core/Src/system_stm32f1xx.c **** /* Get PREDIV2 division factor and PLL2 multiplication factor */
335:Core/Src/system_stm32f1xx.c **** prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U;
336:Core/Src/system_stm32f1xx.c **** pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U;
337:Core/Src/system_stm32f1xx.c **** SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
338:Core/Src/system_stm32f1xx.c **** }
339:Core/Src/system_stm32f1xx.c **** }
340:Core/Src/system_stm32f1xx.c **** #endif /* STM32F105xC */
341:Core/Src/system_stm32f1xx.c **** break;
342:Core/Src/system_stm32f1xx.c ****
343:Core/Src/system_stm32f1xx.c **** default:
344:Core/Src/system_stm32f1xx.c **** SystemCoreClock = HSI_VALUE;
110 .loc 1 344 7 view .LVU22
111 .loc 1 344 23 is_stmt 0 view .LVU23
112 0012 1C4B ldr r3, .L12+4
113 .LVL2:
114 .loc 1 344 23 view .LVU24
115 0014 1C4A ldr r2, .L12+8
ARM GAS C:\Users\mike\AppData\Local\Temp\cc5OGnig.s page 9
116 0016 1A60 str r2, [r3]
345:Core/Src/system_stm32f1xx.c **** break;
117 .loc 1 345 7 is_stmt 1 view .LVU25
118 0018 02E0 b .L8
119 .LVL3:
120 .L11:
265:Core/Src/system_stm32f1xx.c **** break;
121 .loc 1 265 7 view .LVU26
265:Core/Src/system_stm32f1xx.c **** break;
122 .loc 1 265 23 is_stmt 0 view .LVU27
123 001a 1A4B ldr r3, .L12+4
124 .LVL4:
265:Core/Src/system_stm32f1xx.c **** break;
125 .loc 1 265 23 view .LVU28
126 001c 1A4A ldr r2, .L12+8
127 001e 1A60 str r2, [r3]
266:Core/Src/system_stm32f1xx.c **** case 0x04U: /* HSE used as system clock */
128 .loc 1 266 7 is_stmt 1 view .LVU29
129 .LVL5:
130 .L8:
346:Core/Src/system_stm32f1xx.c **** }
347:Core/Src/system_stm32f1xx.c ****
348:Core/Src/system_stm32f1xx.c **** /* Compute HCLK clock frequency ----------------*/
349:Core/Src/system_stm32f1xx.c **** /* Get HCLK prescaler */
350:Core/Src/system_stm32f1xx.c **** tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
131 .loc 1 350 3 view .LVU30
132 .loc 1 350 28 is_stmt 0 view .LVU31
133 0020 174B ldr r3, .L12
134 0022 5B68 ldr r3, [r3, #4]
135 .loc 1 350 52 view .LVU32
136 0024 C3F30313 ubfx r3, r3, #4, #4
137 .loc 1 350 22 view .LVU33
138 0028 184A ldr r2, .L12+12
139 002a D15C ldrb r1, [r2, r3] @ zero_extendqisi2
140 .LVL6:
351:Core/Src/system_stm32f1xx.c **** /* HCLK clock frequency */
352:Core/Src/system_stm32f1xx.c **** SystemCoreClock >>= tmp;
141 .loc 1 352 3 is_stmt 1 view .LVU34
142 .loc 1 352 19 is_stmt 0 view .LVU35
143 002c 154A ldr r2, .L12+4
144 002e 1368 ldr r3, [r2]
145 0030 CB40 lsrs r3, r3, r1
146 0032 1360 str r3, [r2]
353:Core/Src/system_stm32f1xx.c **** }
147 .loc 1 353 1 view .LVU36
148 0034 7047 bx lr
149 .LVL7:
150 .L5:
268:Core/Src/system_stm32f1xx.c **** break;
151 .loc 1 268 7 is_stmt 1 view .LVU37
268:Core/Src/system_stm32f1xx.c **** break;
152 .loc 1 268 23 is_stmt 0 view .LVU38
153 0036 134B ldr r3, .L12+4
154 .LVL8:
268:Core/Src/system_stm32f1xx.c **** break;
155 .loc 1 268 23 view .LVU39
156 0038 134A ldr r2, .L12+8
ARM GAS C:\Users\mike\AppData\Local\Temp\cc5OGnig.s page 10
157 003a 1A60 str r2, [r3]
269:Core/Src/system_stm32f1xx.c **** case 0x08U: /* PLL used as system clock */
158 .loc 1 269 7 is_stmt 1 view .LVU40
159 003c F0E7 b .L8
160 .LVL9:
161 .L6:
273:Core/Src/system_stm32f1xx.c **** pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
162 .loc 1 273 7 view .LVU41
273:Core/Src/system_stm32f1xx.c **** pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
163 .loc 1 273 20 is_stmt 0 view .LVU42
164 003e 104A ldr r2, .L12
165 0040 5368 ldr r3, [r2, #4]
166 .LVL10:
274:Core/Src/system_stm32f1xx.c ****
167 .loc 1 274 7 is_stmt 1 view .LVU43
274:Core/Src/system_stm32f1xx.c ****
168 .loc 1 274 22 is_stmt 0 view .LVU44
169 0042 5268 ldr r2, [r2, #4]
170 .LVL11:
277:Core/Src/system_stm32f1xx.c ****
171 .loc 1 277 7 is_stmt 1 view .LVU45
277:Core/Src/system_stm32f1xx.c ****
172 .loc 1 277 27 is_stmt 0 view .LVU46
173 0044 C3F38343 ubfx r3, r3, #18, #4
174 .LVL12:
277:Core/Src/system_stm32f1xx.c ****
175 .loc 1 277 15 view .LVU47
176 0048 0233 adds r3, r3, #2
177 .LVL13:
279:Core/Src/system_stm32f1xx.c **** {
178 .loc 1 279 7 is_stmt 1 view .LVU48
279:Core/Src/system_stm32f1xx.c **** {
179 .loc 1 279 10 is_stmt 0 view .LVU49
180 004a 12F4803F tst r2, #65536
181 004e 05D1 bne .L9
282:Core/Src/system_stm32f1xx.c **** }
182 .loc 1 282 9 is_stmt 1 view .LVU50
282:Core/Src/system_stm32f1xx.c **** }
183 .loc 1 282 45 is_stmt 0 view .LVU51
184 0050 0F4A ldr r2, .L12+16
185 .LVL14:
282:Core/Src/system_stm32f1xx.c **** }
186 .loc 1 282 45 view .LVU52
187 0052 02FB03F3 mul r3, r2, r3
188 .LVL15:
282:Core/Src/system_stm32f1xx.c **** }
189 .loc 1 282 25 view .LVU53
190 0056 0B4A ldr r2, .L12+4
191 0058 1360 str r3, [r2]
192 005a E1E7 b .L8
193 .LVL16:
194 .L9:
292:Core/Src/system_stm32f1xx.c **** {/* HSE oscillator clock divided by 2 */
195 .loc 1 292 9 is_stmt 1 view .LVU54
292:Core/Src/system_stm32f1xx.c **** {/* HSE oscillator clock divided by 2 */
196 .loc 1 292 17 is_stmt 0 view .LVU55
197 005c 084A ldr r2, .L12
ARM GAS C:\Users\mike\AppData\Local\Temp\cc5OGnig.s page 11
198 .LVL17:
292:Core/Src/system_stm32f1xx.c **** {/* HSE oscillator clock divided by 2 */
199 .loc 1 292 17 view .LVU56
200 005e 5268 ldr r2, [r2, #4]
292:Core/Src/system_stm32f1xx.c **** {/* HSE oscillator clock divided by 2 */
201 .loc 1 292 12 view .LVU57
202 0060 12F4003F tst r2, #131072
203 0064 05D0 beq .L10
294:Core/Src/system_stm32f1xx.c **** }
204 .loc 1 294 11 is_stmt 1 view .LVU58
294:Core/Src/system_stm32f1xx.c **** }
205 .loc 1 294 47 is_stmt 0 view .LVU59
206 0066 0A4A ldr r2, .L12+16
207 0068 02FB03F3 mul r3, r2, r3
208 .LVL18:
294:Core/Src/system_stm32f1xx.c **** }
209 .loc 1 294 27 view .LVU60
210 006c 054A ldr r2, .L12+4
211 006e 1360 str r3, [r2]
212 0070 D6E7 b .L8
213 .LVL19:
214 .L10:
298:Core/Src/system_stm32f1xx.c **** }
215 .loc 1 298 11 is_stmt 1 view .LVU61
298:Core/Src/system_stm32f1xx.c **** }
216 .loc 1 298 39 is_stmt 0 view .LVU62
217 0072 054A ldr r2, .L12+8
218 0074 02FB03F3 mul r3, r2, r3
219 .LVL20:
298:Core/Src/system_stm32f1xx.c **** }
220 .loc 1 298 27 view .LVU63
221 0078 024A ldr r2, .L12+4
222 007a 1360 str r3, [r2]
223 007c D0E7 b .L8
224 .L13:
225 007e 00BF .align 2
226 .L12:
227 0080 00100240 .word 1073876992
228 0084 00000000 .word .LANCHOR0
229 0088 00127A00 .word 8000000
230 008c 00000000 .word .LANCHOR1
231 0090 00093D00 .word 4000000
232 .cfi_endproc
233 .LFE66:
235 .global APBPrescTable
236 .global AHBPrescTable
237 .global SystemCoreClock
238 .section .data.SystemCoreClock,"aw"
239 .align 2
240 .set .LANCHOR0,. + 0
243 SystemCoreClock:
244 0000 0024F400 .word 16000000
245 .section .rodata.AHBPrescTable,"a"
246 .align 2
247 .set .LANCHOR1,. + 0
250 AHBPrescTable:
251 0000 00 .byte 0
ARM GAS C:\Users\mike\AppData\Local\Temp\cc5OGnig.s page 12
252 0001 00 .byte 0
253 0002 00 .byte 0
254 0003 00 .byte 0
255 0004 00 .byte 0
256 0005 00 .byte 0
257 0006 00 .byte 0
258 0007 00 .byte 0
259 0008 01 .byte 1
260 0009 02 .byte 2
261 000a 03 .byte 3
262 000b 04 .byte 4
263 000c 06 .byte 6
264 000d 07 .byte 7
265 000e 08 .byte 8
266 000f 09 .byte 9
267 .section .rodata.APBPrescTable,"a"
268 .align 2
271 APBPrescTable:
272 0000 00 .byte 0
273 0001 00 .byte 0
274 0002 00 .byte 0
275 0003 00 .byte 0
276 0004 01 .byte 1
277 0005 02 .byte 2
278 0006 03 .byte 3
279 0007 04 .byte 4
280 .text
281 .Letext0:
282 .file 2 "c:\\users\\mike\\appdata\\roaming\\xpacks\\@gnu-mcu-eclipse\\arm-none-eabi-gcc\\8.2.1-1.7
283 .file 3 "c:\\users\\mike\\appdata\\roaming\\xpacks\\@gnu-mcu-eclipse\\arm-none-eabi-gcc\\8.2.1-1.7
284 .file 4 "Drivers/CMSIS/Include/core_cm3.h"
285 .file 5 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h"
286 .file 6 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h"
287 .file 7 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h"
288 .file 8 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h"
ARM GAS C:\Users\mike\AppData\Local\Temp\cc5OGnig.s page 13
DEFINED SYMBOLS
*ABS*:0000000000000000 system_stm32f1xx.c
C:\Users\mike\AppData\Local\Temp\cc5OGnig.s:16 .text.SystemInit:0000000000000000 $t
C:\Users\mike\AppData\Local\Temp\cc5OGnig.s:24 .text.SystemInit:0000000000000000 SystemInit
C:\Users\mike\AppData\Local\Temp\cc5OGnig.s:74 .text.SystemInit:0000000000000040 $d
C:\Users\mike\AppData\Local\Temp\cc5OGnig.s:81 .text.SystemCoreClockUpdate:0000000000000000 $t
C:\Users\mike\AppData\Local\Temp\cc5OGnig.s:88 .text.SystemCoreClockUpdate:0000000000000000 SystemCoreClockUpdate
C:\Users\mike\AppData\Local\Temp\cc5OGnig.s:227 .text.SystemCoreClockUpdate:0000000000000080 $d
C:\Users\mike\AppData\Local\Temp\cc5OGnig.s:271 .rodata.APBPrescTable:0000000000000000 APBPrescTable
C:\Users\mike\AppData\Local\Temp\cc5OGnig.s:250 .rodata.AHBPrescTable:0000000000000000 AHBPrescTable
C:\Users\mike\AppData\Local\Temp\cc5OGnig.s:243 .data.SystemCoreClock:0000000000000000 SystemCoreClock
C:\Users\mike\AppData\Local\Temp\cc5OGnig.s:239 .data.SystemCoreClock:0000000000000000 $d
C:\Users\mike\AppData\Local\Temp\cc5OGnig.s:246 .rodata.AHBPrescTable:0000000000000000 $d
C:\Users\mike\AppData\Local\Temp\cc5OGnig.s:268 .rodata.APBPrescTable:0000000000000000 $d
NO UNDEFINED SYMBOLS