Rev 16 | Rev 19 | Go to most recent revision | Blame | Compare with Previous | Last modification | View Log | Download | RSS feed
ARM GAS C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s page 1
1 .cpu cortex-m3
2 .eabi_attribute 20, 1
3 .eabi_attribute 21, 1
4 .eabi_attribute 23, 3
5 .eabi_attribute 24, 1
6 .eabi_attribute 25, 1
7 .eabi_attribute 26, 1
8 .eabi_attribute 30, 1
9 .eabi_attribute 34, 1
10 .eabi_attribute 18, 4
11 .file "stm32f1xx_hal_msp.c"
12 .text
13 .Ltext0:
14 .cfi_sections .debug_frame
15 .section .text.HAL_MspInit,"ax",%progbits
16 .align 1
17 .global HAL_MspInit
18 .arch armv7-m
19 .syntax unified
20 .thumb
21 .thumb_func
22 .fpu softvfp
24 HAL_MspInit:
25 .LFB65:
26 .file 1 "Core/Src/stm32f1xx_hal_msp.c"
1:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN Header */
2:Core/Src/stm32f1xx_hal_msp.c **** /**
3:Core/Src/stm32f1xx_hal_msp.c **** ******************************************************************************
4:Core/Src/stm32f1xx_hal_msp.c **** * File Name : stm32f1xx_hal_msp.c
5:Core/Src/stm32f1xx_hal_msp.c **** * Description : This file provides code for the MSP Initialization
6:Core/Src/stm32f1xx_hal_msp.c **** * and de-Initialization codes.
7:Core/Src/stm32f1xx_hal_msp.c **** ******************************************************************************
8:Core/Src/stm32f1xx_hal_msp.c **** * @attention
9:Core/Src/stm32f1xx_hal_msp.c **** *
10:Core/Src/stm32f1xx_hal_msp.c **** * <h2><center>© Copyright (c) 2020 STMicroelectronics.
11:Core/Src/stm32f1xx_hal_msp.c **** * All rights reserved.</center></h2>
12:Core/Src/stm32f1xx_hal_msp.c **** *
13:Core/Src/stm32f1xx_hal_msp.c **** * This software component is licensed by ST under BSD 3-Clause license,
14:Core/Src/stm32f1xx_hal_msp.c **** * the "License"; You may not use this file except in compliance with the
15:Core/Src/stm32f1xx_hal_msp.c **** * License. You may obtain a copy of the License at:
16:Core/Src/stm32f1xx_hal_msp.c **** * opensource.org/licenses/BSD-3-Clause
17:Core/Src/stm32f1xx_hal_msp.c **** *
18:Core/Src/stm32f1xx_hal_msp.c **** ******************************************************************************
19:Core/Src/stm32f1xx_hal_msp.c **** */
20:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END Header */
21:Core/Src/stm32f1xx_hal_msp.c ****
22:Core/Src/stm32f1xx_hal_msp.c **** /* Includes ------------------------------------------------------------------*/
23:Core/Src/stm32f1xx_hal_msp.c **** #include "main.h"
24:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN Includes */
25:Core/Src/stm32f1xx_hal_msp.c ****
26:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END Includes */
27:Core/Src/stm32f1xx_hal_msp.c ****
28:Core/Src/stm32f1xx_hal_msp.c **** /* Private typedef -----------------------------------------------------------*/
29:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN TD */
30:Core/Src/stm32f1xx_hal_msp.c ****
31:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END TD */
32:Core/Src/stm32f1xx_hal_msp.c ****
ARM GAS C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s page 2
33:Core/Src/stm32f1xx_hal_msp.c **** /* Private define ------------------------------------------------------------*/
34:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN Define */
35:Core/Src/stm32f1xx_hal_msp.c ****
36:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END Define */
37:Core/Src/stm32f1xx_hal_msp.c ****
38:Core/Src/stm32f1xx_hal_msp.c **** /* Private macro -------------------------------------------------------------*/
39:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN Macro */
40:Core/Src/stm32f1xx_hal_msp.c ****
41:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END Macro */
42:Core/Src/stm32f1xx_hal_msp.c ****
43:Core/Src/stm32f1xx_hal_msp.c **** /* Private variables ---------------------------------------------------------*/
44:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN PV */
45:Core/Src/stm32f1xx_hal_msp.c ****
46:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END PV */
47:Core/Src/stm32f1xx_hal_msp.c ****
48:Core/Src/stm32f1xx_hal_msp.c **** /* Private function prototypes -----------------------------------------------*/
49:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN PFP */
50:Core/Src/stm32f1xx_hal_msp.c ****
51:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END PFP */
52:Core/Src/stm32f1xx_hal_msp.c ****
53:Core/Src/stm32f1xx_hal_msp.c **** /* External functions --------------------------------------------------------*/
54:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN ExternalFunctions */
55:Core/Src/stm32f1xx_hal_msp.c ****
56:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END ExternalFunctions */
57:Core/Src/stm32f1xx_hal_msp.c ****
58:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN 0 */
59:Core/Src/stm32f1xx_hal_msp.c ****
60:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END 0 */
61:Core/Src/stm32f1xx_hal_msp.c **** /**
62:Core/Src/stm32f1xx_hal_msp.c **** * Initializes the Global MSP.
63:Core/Src/stm32f1xx_hal_msp.c **** */
64:Core/Src/stm32f1xx_hal_msp.c **** void HAL_MspInit(void)
65:Core/Src/stm32f1xx_hal_msp.c **** {
27 .loc 1 65 1 view -0
28 .cfi_startproc
29 @ args = 0, pretend = 0, frame = 8
30 @ frame_needed = 0, uses_anonymous_args = 0
31 @ link register save eliminated.
32 0000 82B0 sub sp, sp, #8
33 .LCFI0:
34 .cfi_def_cfa_offset 8
66:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN MspInit 0 */
67:Core/Src/stm32f1xx_hal_msp.c ****
68:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END MspInit 0 */
69:Core/Src/stm32f1xx_hal_msp.c ****
70:Core/Src/stm32f1xx_hal_msp.c **** __HAL_RCC_AFIO_CLK_ENABLE();
35 .loc 1 70 3 view .LVU1
36 .LBB2:
37 .loc 1 70 3 view .LVU2
38 .loc 1 70 3 view .LVU3
39 0002 0E4B ldr r3, .L3
40 0004 9A69 ldr r2, [r3, #24]
41 0006 42F00102 orr r2, r2, #1
42 000a 9A61 str r2, [r3, #24]
43 .loc 1 70 3 view .LVU4
44 000c 9A69 ldr r2, [r3, #24]
45 000e 02F00102 and r2, r2, #1
ARM GAS C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s page 3
46 0012 0092 str r2, [sp]
47 .loc 1 70 3 view .LVU5
48 0014 009A ldr r2, [sp]
49 .LBE2:
71:Core/Src/stm32f1xx_hal_msp.c **** __HAL_RCC_PWR_CLK_ENABLE();
50 .loc 1 71 3 view .LVU6
51 .LBB3:
52 .loc 1 71 3 view .LVU7
53 .loc 1 71 3 view .LVU8
54 0016 DA69 ldr r2, [r3, #28]
55 0018 42F08052 orr r2, r2, #268435456
56 001c DA61 str r2, [r3, #28]
57 .loc 1 71 3 view .LVU9
58 001e DB69 ldr r3, [r3, #28]
59 0020 03F08053 and r3, r3, #268435456
60 0024 0193 str r3, [sp, #4]
61 .loc 1 71 3 view .LVU10
62 0026 019B ldr r3, [sp, #4]
63 .LBE3:
72:Core/Src/stm32f1xx_hal_msp.c ****
73:Core/Src/stm32f1xx_hal_msp.c **** /* System interrupt init*/
74:Core/Src/stm32f1xx_hal_msp.c ****
75:Core/Src/stm32f1xx_hal_msp.c **** /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled
76:Core/Src/stm32f1xx_hal_msp.c **** */
77:Core/Src/stm32f1xx_hal_msp.c **** __HAL_AFIO_REMAP_SWJ_NOJTAG();
64 .loc 1 77 3 view .LVU11
65 .LBB4:
66 .loc 1 77 3 view .LVU12
67 0028 054A ldr r2, .L3+4
68 002a 5368 ldr r3, [r2, #4]
69 .LVL0:
70 .loc 1 77 3 view .LVU13
71 002c 23F0E063 bic r3, r3, #117440512
72 .LVL1:
73 .loc 1 77 3 view .LVU14
74 0030 43F00073 orr r3, r3, #33554432
75 .LVL2:
76 .loc 1 77 3 view .LVU15
77 0034 5360 str r3, [r2, #4]
78 .LBE4:
78:Core/Src/stm32f1xx_hal_msp.c ****
79:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN MspInit 1 */
80:Core/Src/stm32f1xx_hal_msp.c ****
81:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END MspInit 1 */
82:Core/Src/stm32f1xx_hal_msp.c **** }
79 .loc 1 82 1 is_stmt 0 view .LVU16
80 0036 02B0 add sp, sp, #8
81 .LCFI1:
82 .cfi_def_cfa_offset 0
83 @ sp needed
84 0038 7047 bx lr
85 .L4:
86 003a 00BF .align 2
87 .L3:
88 003c 00100240 .word 1073876992
89 0040 00000140 .word 1073807360
90 .cfi_endproc
ARM GAS C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s page 4
91 .LFE65:
93 .section .text.HAL_I2C_MspInit,"ax",%progbits
94 .align 1
95 .global HAL_I2C_MspInit
96 .syntax unified
97 .thumb
98 .thumb_func
99 .fpu softvfp
101 HAL_I2C_MspInit:
102 .LVL3:
103 .LFB66:
83:Core/Src/stm32f1xx_hal_msp.c ****
84:Core/Src/stm32f1xx_hal_msp.c **** /**
85:Core/Src/stm32f1xx_hal_msp.c **** * @brief I2C MSP Initialization
86:Core/Src/stm32f1xx_hal_msp.c **** * This function configures the hardware resources used in this example
87:Core/Src/stm32f1xx_hal_msp.c **** * @param hi2c: I2C handle pointer
88:Core/Src/stm32f1xx_hal_msp.c **** * @retval None
89:Core/Src/stm32f1xx_hal_msp.c **** */
90:Core/Src/stm32f1xx_hal_msp.c **** void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
91:Core/Src/stm32f1xx_hal_msp.c **** {
104 .loc 1 91 1 is_stmt 1 view -0
105 .cfi_startproc
106 @ args = 0, pretend = 0, frame = 32
107 @ frame_needed = 0, uses_anonymous_args = 0
108 .loc 1 91 1 is_stmt 0 view .LVU18
109 0000 10B5 push {r4, lr}
110 .LCFI2:
111 .cfi_def_cfa_offset 8
112 .cfi_offset 4, -8
113 .cfi_offset 14, -4
114 0002 88B0 sub sp, sp, #32
115 .LCFI3:
116 .cfi_def_cfa_offset 40
92:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitTypeDef GPIO_InitStruct = {0};
117 .loc 1 92 3 is_stmt 1 view .LVU19
118 .loc 1 92 20 is_stmt 0 view .LVU20
119 0004 0023 movs r3, #0
120 0006 0493 str r3, [sp, #16]
121 0008 0593 str r3, [sp, #20]
122 000a 0693 str r3, [sp, #24]
123 000c 0793 str r3, [sp, #28]
93:Core/Src/stm32f1xx_hal_msp.c **** if(hi2c->Instance==I2C2)
124 .loc 1 93 3 is_stmt 1 view .LVU21
125 .loc 1 93 10 is_stmt 0 view .LVU22
126 000e 0268 ldr r2, [r0]
127 .loc 1 93 5 view .LVU23
128 0010 164B ldr r3, .L9
129 0012 9A42 cmp r2, r3
130 0014 01D0 beq .L8
131 .LVL4:
132 .L5:
94:Core/Src/stm32f1xx_hal_msp.c **** {
95:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN I2C2_MspInit 0 */
96:Core/Src/stm32f1xx_hal_msp.c **** __HAL_RCC_I2C2_CLK_ENABLE();
97:Core/Src/stm32f1xx_hal_msp.c ****
98:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END I2C2_MspInit 0 */
99:Core/Src/stm32f1xx_hal_msp.c ****
ARM GAS C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s page 5
100:Core/Src/stm32f1xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
101:Core/Src/stm32f1xx_hal_msp.c **** /**I2C2 GPIO Configuration
102:Core/Src/stm32f1xx_hal_msp.c **** PB10 ------> I2C2_SCL
103:Core/Src/stm32f1xx_hal_msp.c **** PB11 ------> I2C2_SDA
104:Core/Src/stm32f1xx_hal_msp.c **** */
105:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11;
106:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
107:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
108:Core/Src/stm32f1xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
109:Core/Src/stm32f1xx_hal_msp.c ****
110:Core/Src/stm32f1xx_hal_msp.c **** /* Peripheral clock enable */
111:Core/Src/stm32f1xx_hal_msp.c **** __HAL_RCC_I2C2_CLK_ENABLE();
112:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN I2C2_MspInit 1 */
113:Core/Src/stm32f1xx_hal_msp.c ****
114:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END I2C2_MspInit 1 */
115:Core/Src/stm32f1xx_hal_msp.c **** }
116:Core/Src/stm32f1xx_hal_msp.c ****
117:Core/Src/stm32f1xx_hal_msp.c **** }
133 .loc 1 117 1 view .LVU24
134 0016 08B0 add sp, sp, #32
135 .LCFI4:
136 .cfi_remember_state
137 .cfi_def_cfa_offset 8
138 @ sp needed
139 0018 10BD pop {r4, pc}
140 .LVL5:
141 .L8:
142 .LCFI5:
143 .cfi_restore_state
96:Core/Src/stm32f1xx_hal_msp.c ****
144 .loc 1 96 7 is_stmt 1 view .LVU25
145 .LBB5:
96:Core/Src/stm32f1xx_hal_msp.c ****
146 .loc 1 96 7 view .LVU26
96:Core/Src/stm32f1xx_hal_msp.c ****
147 .loc 1 96 7 view .LVU27
148 001a 154C ldr r4, .L9+4
149 001c E369 ldr r3, [r4, #28]
150 001e 43F48003 orr r3, r3, #4194304
151 0022 E361 str r3, [r4, #28]
96:Core/Src/stm32f1xx_hal_msp.c ****
152 .loc 1 96 7 view .LVU28
153 0024 E369 ldr r3, [r4, #28]
154 0026 03F48003 and r3, r3, #4194304
155 002a 0193 str r3, [sp, #4]
96:Core/Src/stm32f1xx_hal_msp.c ****
156 .loc 1 96 7 view .LVU29
157 002c 019B ldr r3, [sp, #4]
158 .LBE5:
100:Core/Src/stm32f1xx_hal_msp.c **** /**I2C2 GPIO Configuration
159 .loc 1 100 5 view .LVU30
160 .LBB6:
100:Core/Src/stm32f1xx_hal_msp.c **** /**I2C2 GPIO Configuration
161 .loc 1 100 5 view .LVU31
100:Core/Src/stm32f1xx_hal_msp.c **** /**I2C2 GPIO Configuration
162 .loc 1 100 5 view .LVU32
163 002e A369 ldr r3, [r4, #24]
ARM GAS C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s page 6
164 0030 43F00803 orr r3, r3, #8
165 0034 A361 str r3, [r4, #24]
100:Core/Src/stm32f1xx_hal_msp.c **** /**I2C2 GPIO Configuration
166 .loc 1 100 5 view .LVU33
167 0036 A369 ldr r3, [r4, #24]
168 0038 03F00803 and r3, r3, #8
169 003c 0293 str r3, [sp, #8]
100:Core/Src/stm32f1xx_hal_msp.c **** /**I2C2 GPIO Configuration
170 .loc 1 100 5 view .LVU34
171 003e 029B ldr r3, [sp, #8]
172 .LBE6:
105:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
173 .loc 1 105 5 view .LVU35
105:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
174 .loc 1 105 25 is_stmt 0 view .LVU36
175 0040 4FF44063 mov r3, #3072
176 0044 0493 str r3, [sp, #16]
106:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
177 .loc 1 106 5 is_stmt 1 view .LVU37
106:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
178 .loc 1 106 26 is_stmt 0 view .LVU38
179 0046 1223 movs r3, #18
180 0048 0593 str r3, [sp, #20]
107:Core/Src/stm32f1xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
181 .loc 1 107 5 is_stmt 1 view .LVU39
107:Core/Src/stm32f1xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
182 .loc 1 107 27 is_stmt 0 view .LVU40
183 004a 0323 movs r3, #3
184 004c 0793 str r3, [sp, #28]
108:Core/Src/stm32f1xx_hal_msp.c ****
185 .loc 1 108 5 is_stmt 1 view .LVU41
186 004e 04A9 add r1, sp, #16
187 0050 0848 ldr r0, .L9+8
188 .LVL6:
108:Core/Src/stm32f1xx_hal_msp.c ****
189 .loc 1 108 5 is_stmt 0 view .LVU42
190 0052 FFF7FEFF bl HAL_GPIO_Init
191 .LVL7:
111:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN I2C2_MspInit 1 */
192 .loc 1 111 5 is_stmt 1 view .LVU43
193 .LBB7:
111:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN I2C2_MspInit 1 */
194 .loc 1 111 5 view .LVU44
111:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN I2C2_MspInit 1 */
195 .loc 1 111 5 view .LVU45
196 0056 E369 ldr r3, [r4, #28]
197 0058 43F48003 orr r3, r3, #4194304
198 005c E361 str r3, [r4, #28]
111:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN I2C2_MspInit 1 */
199 .loc 1 111 5 view .LVU46
200 005e E369 ldr r3, [r4, #28]
201 0060 03F48003 and r3, r3, #4194304
202 0064 0393 str r3, [sp, #12]
111:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN I2C2_MspInit 1 */
203 .loc 1 111 5 view .LVU47
204 0066 039B ldr r3, [sp, #12]
205 .LBE7:
ARM GAS C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s page 7
206 .loc 1 117 1 is_stmt 0 view .LVU48
207 0068 D5E7 b .L5
208 .L10:
209 006a 00BF .align 2
210 .L9:
211 006c 00580040 .word 1073764352
212 0070 00100240 .word 1073876992
213 0074 000C0140 .word 1073810432
214 .cfi_endproc
215 .LFE66:
217 .section .text.HAL_I2C_MspDeInit,"ax",%progbits
218 .align 1
219 .global HAL_I2C_MspDeInit
220 .syntax unified
221 .thumb
222 .thumb_func
223 .fpu softvfp
225 HAL_I2C_MspDeInit:
226 .LVL8:
227 .LFB67:
118:Core/Src/stm32f1xx_hal_msp.c ****
119:Core/Src/stm32f1xx_hal_msp.c **** /**
120:Core/Src/stm32f1xx_hal_msp.c **** * @brief I2C MSP De-Initialization
121:Core/Src/stm32f1xx_hal_msp.c **** * This function freeze the hardware resources used in this example
122:Core/Src/stm32f1xx_hal_msp.c **** * @param hi2c: I2C handle pointer
123:Core/Src/stm32f1xx_hal_msp.c **** * @retval None
124:Core/Src/stm32f1xx_hal_msp.c **** */
125:Core/Src/stm32f1xx_hal_msp.c **** void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c)
126:Core/Src/stm32f1xx_hal_msp.c **** {
228 .loc 1 126 1 is_stmt 1 view -0
229 .cfi_startproc
230 @ args = 0, pretend = 0, frame = 0
231 @ frame_needed = 0, uses_anonymous_args = 0
127:Core/Src/stm32f1xx_hal_msp.c **** if(hi2c->Instance==I2C2)
232 .loc 1 127 3 view .LVU50
233 .loc 1 127 10 is_stmt 0 view .LVU51
234 0000 0268 ldr r2, [r0]
235 .loc 1 127 5 view .LVU52
236 0002 0B4B ldr r3, .L18
237 0004 9A42 cmp r2, r3
238 0006 00D0 beq .L17
239 0008 7047 bx lr
240 .L17:
126:Core/Src/stm32f1xx_hal_msp.c **** if(hi2c->Instance==I2C2)
241 .loc 1 126 1 view .LVU53
242 000a 10B5 push {r4, lr}
243 .LCFI6:
244 .cfi_def_cfa_offset 8
245 .cfi_offset 4, -8
246 .cfi_offset 14, -4
128:Core/Src/stm32f1xx_hal_msp.c **** {
129:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN I2C2_MspDeInit 0 */
130:Core/Src/stm32f1xx_hal_msp.c ****
131:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END I2C2_MspDeInit 0 */
132:Core/Src/stm32f1xx_hal_msp.c **** /* Peripheral clock disable */
133:Core/Src/stm32f1xx_hal_msp.c **** __HAL_RCC_I2C2_CLK_DISABLE();
247 .loc 1 133 5 is_stmt 1 view .LVU54
ARM GAS C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s page 8
248 000c 094A ldr r2, .L18+4
249 000e D369 ldr r3, [r2, #28]
250 0010 23F48003 bic r3, r3, #4194304
251 0014 D361 str r3, [r2, #28]
134:Core/Src/stm32f1xx_hal_msp.c ****
135:Core/Src/stm32f1xx_hal_msp.c **** /**I2C2 GPIO Configuration
136:Core/Src/stm32f1xx_hal_msp.c **** PB10 ------> I2C2_SCL
137:Core/Src/stm32f1xx_hal_msp.c **** PB11 ------> I2C2_SDA
138:Core/Src/stm32f1xx_hal_msp.c **** */
139:Core/Src/stm32f1xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10);
252 .loc 1 139 5 view .LVU55
253 0016 084C ldr r4, .L18+8
254 0018 4FF48061 mov r1, #1024
255 001c 2046 mov r0, r4
256 .LVL9:
257 .loc 1 139 5 is_stmt 0 view .LVU56
258 001e FFF7FEFF bl HAL_GPIO_DeInit
259 .LVL10:
140:Core/Src/stm32f1xx_hal_msp.c ****
141:Core/Src/stm32f1xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOB, GPIO_PIN_11);
260 .loc 1 141 5 is_stmt 1 view .LVU57
261 0022 4FF40061 mov r1, #2048
262 0026 2046 mov r0, r4
263 0028 FFF7FEFF bl HAL_GPIO_DeInit
264 .LVL11:
142:Core/Src/stm32f1xx_hal_msp.c ****
143:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN I2C2_MspDeInit 1 */
144:Core/Src/stm32f1xx_hal_msp.c ****
145:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END I2C2_MspDeInit 1 */
146:Core/Src/stm32f1xx_hal_msp.c **** }
147:Core/Src/stm32f1xx_hal_msp.c ****
148:Core/Src/stm32f1xx_hal_msp.c **** }
265 .loc 1 148 1 is_stmt 0 view .LVU58
266 002c 10BD pop {r4, pc}
267 .L19:
268 002e 00BF .align 2
269 .L18:
270 0030 00580040 .word 1073764352
271 0034 00100240 .word 1073876992
272 0038 000C0140 .word 1073810432
273 .cfi_endproc
274 .LFE67:
276 .section .text.HAL_RTC_MspInit,"ax",%progbits
277 .align 1
278 .global HAL_RTC_MspInit
279 .syntax unified
280 .thumb
281 .thumb_func
282 .fpu softvfp
284 HAL_RTC_MspInit:
285 .LVL12:
286 .LFB68:
149:Core/Src/stm32f1xx_hal_msp.c ****
150:Core/Src/stm32f1xx_hal_msp.c **** /**
151:Core/Src/stm32f1xx_hal_msp.c **** * @brief RTC MSP Initialization
152:Core/Src/stm32f1xx_hal_msp.c **** * This function configures the hardware resources used in this example
153:Core/Src/stm32f1xx_hal_msp.c **** * @param hrtc: RTC handle pointer
ARM GAS C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s page 9
154:Core/Src/stm32f1xx_hal_msp.c **** * @retval None
155:Core/Src/stm32f1xx_hal_msp.c **** */
156:Core/Src/stm32f1xx_hal_msp.c **** void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
157:Core/Src/stm32f1xx_hal_msp.c **** {
287 .loc 1 157 1 is_stmt 1 view -0
288 .cfi_startproc
289 @ args = 0, pretend = 0, frame = 8
290 @ frame_needed = 0, uses_anonymous_args = 0
158:Core/Src/stm32f1xx_hal_msp.c **** if(hrtc->Instance==RTC)
291 .loc 1 158 3 view .LVU60
292 .loc 1 158 10 is_stmt 0 view .LVU61
293 0000 0268 ldr r2, [r0]
294 .loc 1 158 5 view .LVU62
295 0002 0C4B ldr r3, .L27
296 0004 9A42 cmp r2, r3
297 0006 00D0 beq .L26
298 0008 7047 bx lr
299 .L26:
157:Core/Src/stm32f1xx_hal_msp.c **** if(hrtc->Instance==RTC)
300 .loc 1 157 1 view .LVU63
301 000a 00B5 push {lr}
302 .LCFI7:
303 .cfi_def_cfa_offset 4
304 .cfi_offset 14, -4
305 000c 83B0 sub sp, sp, #12
306 .LCFI8:
307 .cfi_def_cfa_offset 16
159:Core/Src/stm32f1xx_hal_msp.c **** {
160:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN RTC_MspInit 0 */
161:Core/Src/stm32f1xx_hal_msp.c ****
162:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END RTC_MspInit 0 */
163:Core/Src/stm32f1xx_hal_msp.c **** HAL_PWR_EnableBkUpAccess();
308 .loc 1 163 5 is_stmt 1 view .LVU64
309 000e FFF7FEFF bl HAL_PWR_EnableBkUpAccess
310 .LVL13:
164:Core/Src/stm32f1xx_hal_msp.c **** /* Enable BKP CLK enable for backup registers */
165:Core/Src/stm32f1xx_hal_msp.c **** __HAL_RCC_BKP_CLK_ENABLE();
311 .loc 1 165 5 view .LVU65
312 .LBB8:
313 .loc 1 165 5 view .LVU66
314 .loc 1 165 5 view .LVU67
315 0012 094B ldr r3, .L27+4
316 0014 DA69 ldr r2, [r3, #28]
317 0016 42F00062 orr r2, r2, #134217728
318 001a DA61 str r2, [r3, #28]
319 .loc 1 165 5 view .LVU68
320 001c DB69 ldr r3, [r3, #28]
321 001e 03F00063 and r3, r3, #134217728
322 0022 0193 str r3, [sp, #4]
323 .loc 1 165 5 view .LVU69
324 0024 019B ldr r3, [sp, #4]
325 .LBE8:
166:Core/Src/stm32f1xx_hal_msp.c **** /* Peripheral clock enable */
167:Core/Src/stm32f1xx_hal_msp.c **** __HAL_RCC_RTC_ENABLE();
326 .loc 1 167 5 view .LVU70
327 0026 054B ldr r3, .L27+8
328 0028 0122 movs r2, #1
ARM GAS C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s page 10
329 002a 1A60 str r2, [r3]
168:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN RTC_MspInit 1 */
169:Core/Src/stm32f1xx_hal_msp.c ****
170:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END RTC_MspInit 1 */
171:Core/Src/stm32f1xx_hal_msp.c **** }
172:Core/Src/stm32f1xx_hal_msp.c ****
173:Core/Src/stm32f1xx_hal_msp.c **** }
330 .loc 1 173 1 is_stmt 0 view .LVU71
331 002c 03B0 add sp, sp, #12
332 .LCFI9:
333 .cfi_def_cfa_offset 4
334 @ sp needed
335 002e 5DF804FB ldr pc, [sp], #4
336 .L28:
337 0032 00BF .align 2
338 .L27:
339 0034 00280040 .word 1073752064
340 0038 00100240 .word 1073876992
341 003c 3C044242 .word 1111622716
342 .cfi_endproc
343 .LFE68:
345 .section .text.HAL_RTC_MspDeInit,"ax",%progbits
346 .align 1
347 .global HAL_RTC_MspDeInit
348 .syntax unified
349 .thumb
350 .thumb_func
351 .fpu softvfp
353 HAL_RTC_MspDeInit:
354 .LVL14:
355 .LFB69:
174:Core/Src/stm32f1xx_hal_msp.c ****
175:Core/Src/stm32f1xx_hal_msp.c **** /**
176:Core/Src/stm32f1xx_hal_msp.c **** * @brief RTC MSP De-Initialization
177:Core/Src/stm32f1xx_hal_msp.c **** * This function freeze the hardware resources used in this example
178:Core/Src/stm32f1xx_hal_msp.c **** * @param hrtc: RTC handle pointer
179:Core/Src/stm32f1xx_hal_msp.c **** * @retval None
180:Core/Src/stm32f1xx_hal_msp.c **** */
181:Core/Src/stm32f1xx_hal_msp.c **** void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
182:Core/Src/stm32f1xx_hal_msp.c **** {
356 .loc 1 182 1 is_stmt 1 view -0
357 .cfi_startproc
358 @ args = 0, pretend = 0, frame = 0
359 @ frame_needed = 0, uses_anonymous_args = 0
360 @ link register save eliminated.
183:Core/Src/stm32f1xx_hal_msp.c **** if(hrtc->Instance==RTC)
361 .loc 1 183 3 view .LVU73
362 .loc 1 183 10 is_stmt 0 view .LVU74
363 0000 0268 ldr r2, [r0]
364 .loc 1 183 5 view .LVU75
365 0002 044B ldr r3, .L32
366 0004 9A42 cmp r2, r3
367 0006 00D0 beq .L31
368 .L29:
184:Core/Src/stm32f1xx_hal_msp.c **** {
185:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN RTC_MspDeInit 0 */
186:Core/Src/stm32f1xx_hal_msp.c ****
ARM GAS C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s page 11
187:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END RTC_MspDeInit 0 */
188:Core/Src/stm32f1xx_hal_msp.c **** /* Peripheral clock disable */
189:Core/Src/stm32f1xx_hal_msp.c **** __HAL_RCC_RTC_DISABLE();
190:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN RTC_MspDeInit 1 */
191:Core/Src/stm32f1xx_hal_msp.c ****
192:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END RTC_MspDeInit 1 */
193:Core/Src/stm32f1xx_hal_msp.c **** }
194:Core/Src/stm32f1xx_hal_msp.c ****
195:Core/Src/stm32f1xx_hal_msp.c **** }
369 .loc 1 195 1 view .LVU76
370 0008 7047 bx lr
371 .L31:
189:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN RTC_MspDeInit 1 */
372 .loc 1 189 5 is_stmt 1 view .LVU77
373 000a 034B ldr r3, .L32+4
374 000c 0022 movs r2, #0
375 000e 1A60 str r2, [r3]
376 .loc 1 195 1 is_stmt 0 view .LVU78
377 0010 FAE7 b .L29
378 .L33:
379 0012 00BF .align 2
380 .L32:
381 0014 00280040 .word 1073752064
382 0018 3C044242 .word 1111622716
383 .cfi_endproc
384 .LFE69:
386 .section .text.HAL_SPI_MspInit,"ax",%progbits
387 .align 1
388 .global HAL_SPI_MspInit
389 .syntax unified
390 .thumb
391 .thumb_func
392 .fpu softvfp
394 HAL_SPI_MspInit:
395 .LVL15:
396 .LFB70:
196:Core/Src/stm32f1xx_hal_msp.c ****
197:Core/Src/stm32f1xx_hal_msp.c **** /**
198:Core/Src/stm32f1xx_hal_msp.c **** * @brief SPI MSP Initialization
199:Core/Src/stm32f1xx_hal_msp.c **** * This function configures the hardware resources used in this example
200:Core/Src/stm32f1xx_hal_msp.c **** * @param hspi: SPI handle pointer
201:Core/Src/stm32f1xx_hal_msp.c **** * @retval None
202:Core/Src/stm32f1xx_hal_msp.c **** */
203:Core/Src/stm32f1xx_hal_msp.c **** void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
204:Core/Src/stm32f1xx_hal_msp.c **** {
397 .loc 1 204 1 is_stmt 1 view -0
398 .cfi_startproc
399 @ args = 0, pretend = 0, frame = 24
400 @ frame_needed = 0, uses_anonymous_args = 0
401 .loc 1 204 1 is_stmt 0 view .LVU80
402 0000 00B5 push {lr}
403 .LCFI10:
404 .cfi_def_cfa_offset 4
405 .cfi_offset 14, -4
406 0002 87B0 sub sp, sp, #28
407 .LCFI11:
408 .cfi_def_cfa_offset 32
ARM GAS C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s page 12
205:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitTypeDef GPIO_InitStruct = {0};
409 .loc 1 205 3 is_stmt 1 view .LVU81
410 .loc 1 205 20 is_stmt 0 view .LVU82
411 0004 0023 movs r3, #0
412 0006 0293 str r3, [sp, #8]
413 0008 0393 str r3, [sp, #12]
414 000a 0493 str r3, [sp, #16]
415 000c 0593 str r3, [sp, #20]
206:Core/Src/stm32f1xx_hal_msp.c **** if(hspi->Instance==SPI1)
416 .loc 1 206 3 is_stmt 1 view .LVU83
417 .loc 1 206 10 is_stmt 0 view .LVU84
418 000e 0268 ldr r2, [r0]
419 .loc 1 206 5 view .LVU85
420 0010 124B ldr r3, .L38
421 0012 9A42 cmp r2, r3
422 0014 02D0 beq .L37
423 .LVL16:
424 .L34:
207:Core/Src/stm32f1xx_hal_msp.c **** {
208:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN SPI1_MspInit 0 */
209:Core/Src/stm32f1xx_hal_msp.c ****
210:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END SPI1_MspInit 0 */
211:Core/Src/stm32f1xx_hal_msp.c **** /* Peripheral clock enable */
212:Core/Src/stm32f1xx_hal_msp.c **** __HAL_RCC_SPI1_CLK_ENABLE();
213:Core/Src/stm32f1xx_hal_msp.c ****
214:Core/Src/stm32f1xx_hal_msp.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
215:Core/Src/stm32f1xx_hal_msp.c **** /**SPI1 GPIO Configuration
216:Core/Src/stm32f1xx_hal_msp.c **** PA5 ------> SPI1_SCK
217:Core/Src/stm32f1xx_hal_msp.c **** PA7 ------> SPI1_MOSI
218:Core/Src/stm32f1xx_hal_msp.c **** */
219:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Pin = SPI_SCK_Pin|SPI_MOSI_Pin;
220:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
221:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
222:Core/Src/stm32f1xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
223:Core/Src/stm32f1xx_hal_msp.c ****
224:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN SPI1_MspInit 1 */
225:Core/Src/stm32f1xx_hal_msp.c ****
226:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END SPI1_MspInit 1 */
227:Core/Src/stm32f1xx_hal_msp.c **** }
228:Core/Src/stm32f1xx_hal_msp.c ****
229:Core/Src/stm32f1xx_hal_msp.c **** }
425 .loc 1 229 1 view .LVU86
426 0016 07B0 add sp, sp, #28
427 .LCFI12:
428 .cfi_remember_state
429 .cfi_def_cfa_offset 4
430 @ sp needed
431 0018 5DF804FB ldr pc, [sp], #4
432 .LVL17:
433 .L37:
434 .LCFI13:
435 .cfi_restore_state
212:Core/Src/stm32f1xx_hal_msp.c ****
436 .loc 1 212 5 is_stmt 1 view .LVU87
437 .LBB9:
212:Core/Src/stm32f1xx_hal_msp.c ****
438 .loc 1 212 5 view .LVU88
ARM GAS C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s page 13
212:Core/Src/stm32f1xx_hal_msp.c ****
439 .loc 1 212 5 view .LVU89
440 001c 03F56043 add r3, r3, #57344
441 0020 9A69 ldr r2, [r3, #24]
442 0022 42F48052 orr r2, r2, #4096
443 0026 9A61 str r2, [r3, #24]
212:Core/Src/stm32f1xx_hal_msp.c ****
444 .loc 1 212 5 view .LVU90
445 0028 9A69 ldr r2, [r3, #24]
446 002a 02F48052 and r2, r2, #4096
447 002e 0092 str r2, [sp]
212:Core/Src/stm32f1xx_hal_msp.c ****
448 .loc 1 212 5 view .LVU91
449 0030 009A ldr r2, [sp]
450 .LBE9:
214:Core/Src/stm32f1xx_hal_msp.c **** /**SPI1 GPIO Configuration
451 .loc 1 214 5 view .LVU92
452 .LBB10:
214:Core/Src/stm32f1xx_hal_msp.c **** /**SPI1 GPIO Configuration
453 .loc 1 214 5 view .LVU93
214:Core/Src/stm32f1xx_hal_msp.c **** /**SPI1 GPIO Configuration
454 .loc 1 214 5 view .LVU94
455 0032 9A69 ldr r2, [r3, #24]
456 0034 42F00402 orr r2, r2, #4
457 0038 9A61 str r2, [r3, #24]
214:Core/Src/stm32f1xx_hal_msp.c **** /**SPI1 GPIO Configuration
458 .loc 1 214 5 view .LVU95
459 003a 9B69 ldr r3, [r3, #24]
460 003c 03F00403 and r3, r3, #4
461 0040 0193 str r3, [sp, #4]
214:Core/Src/stm32f1xx_hal_msp.c **** /**SPI1 GPIO Configuration
462 .loc 1 214 5 view .LVU96
463 0042 019B ldr r3, [sp, #4]
464 .LBE10:
219:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
465 .loc 1 219 5 view .LVU97
219:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
466 .loc 1 219 25 is_stmt 0 view .LVU98
467 0044 A023 movs r3, #160
468 0046 0293 str r3, [sp, #8]
220:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
469 .loc 1 220 5 is_stmt 1 view .LVU99
220:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
470 .loc 1 220 26 is_stmt 0 view .LVU100
471 0048 0223 movs r3, #2
472 004a 0393 str r3, [sp, #12]
221:Core/Src/stm32f1xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
473 .loc 1 221 5 is_stmt 1 view .LVU101
221:Core/Src/stm32f1xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
474 .loc 1 221 27 is_stmt 0 view .LVU102
475 004c 0323 movs r3, #3
476 004e 0593 str r3, [sp, #20]
222:Core/Src/stm32f1xx_hal_msp.c ****
477 .loc 1 222 5 is_stmt 1 view .LVU103
478 0050 02A9 add r1, sp, #8
479 0052 0348 ldr r0, .L38+4
480 .LVL18:
ARM GAS C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s page 14
222:Core/Src/stm32f1xx_hal_msp.c ****
481 .loc 1 222 5 is_stmt 0 view .LVU104
482 0054 FFF7FEFF bl HAL_GPIO_Init
483 .LVL19:
484 .loc 1 229 1 view .LVU105
485 0058 DDE7 b .L34
486 .L39:
487 005a 00BF .align 2
488 .L38:
489 005c 00300140 .word 1073819648
490 0060 00080140 .word 1073809408
491 .cfi_endproc
492 .LFE70:
494 .section .text.HAL_SPI_MspDeInit,"ax",%progbits
495 .align 1
496 .global HAL_SPI_MspDeInit
497 .syntax unified
498 .thumb
499 .thumb_func
500 .fpu softvfp
502 HAL_SPI_MspDeInit:
503 .LVL20:
504 .LFB71:
230:Core/Src/stm32f1xx_hal_msp.c ****
231:Core/Src/stm32f1xx_hal_msp.c **** /**
232:Core/Src/stm32f1xx_hal_msp.c **** * @brief SPI MSP De-Initialization
233:Core/Src/stm32f1xx_hal_msp.c **** * This function freeze the hardware resources used in this example
234:Core/Src/stm32f1xx_hal_msp.c **** * @param hspi: SPI handle pointer
235:Core/Src/stm32f1xx_hal_msp.c **** * @retval None
236:Core/Src/stm32f1xx_hal_msp.c **** */
237:Core/Src/stm32f1xx_hal_msp.c **** void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi)
238:Core/Src/stm32f1xx_hal_msp.c **** {
505 .loc 1 238 1 is_stmt 1 view -0
506 .cfi_startproc
507 @ args = 0, pretend = 0, frame = 0
508 @ frame_needed = 0, uses_anonymous_args = 0
509 .loc 1 238 1 is_stmt 0 view .LVU107
510 0000 08B5 push {r3, lr}
511 .LCFI14:
512 .cfi_def_cfa_offset 8
513 .cfi_offset 3, -8
514 .cfi_offset 14, -4
239:Core/Src/stm32f1xx_hal_msp.c **** if(hspi->Instance==SPI1)
515 .loc 1 239 3 is_stmt 1 view .LVU108
516 .loc 1 239 10 is_stmt 0 view .LVU109
517 0002 0268 ldr r2, [r0]
518 .loc 1 239 5 view .LVU110
519 0004 064B ldr r3, .L44
520 0006 9A42 cmp r2, r3
521 0008 00D0 beq .L43
522 .LVL21:
523 .L40:
240:Core/Src/stm32f1xx_hal_msp.c **** {
241:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN SPI1_MspDeInit 0 */
242:Core/Src/stm32f1xx_hal_msp.c ****
243:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END SPI1_MspDeInit 0 */
244:Core/Src/stm32f1xx_hal_msp.c **** /* Peripheral clock disable */
ARM GAS C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s page 15
245:Core/Src/stm32f1xx_hal_msp.c **** __HAL_RCC_SPI1_CLK_DISABLE();
246:Core/Src/stm32f1xx_hal_msp.c ****
247:Core/Src/stm32f1xx_hal_msp.c **** /**SPI1 GPIO Configuration
248:Core/Src/stm32f1xx_hal_msp.c **** PA5 ------> SPI1_SCK
249:Core/Src/stm32f1xx_hal_msp.c **** PA7 ------> SPI1_MOSI
250:Core/Src/stm32f1xx_hal_msp.c **** */
251:Core/Src/stm32f1xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOA, SPI_SCK_Pin|SPI_MOSI_Pin);
252:Core/Src/stm32f1xx_hal_msp.c ****
253:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN SPI1_MspDeInit 1 */
254:Core/Src/stm32f1xx_hal_msp.c ****
255:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END SPI1_MspDeInit 1 */
256:Core/Src/stm32f1xx_hal_msp.c **** }
257:Core/Src/stm32f1xx_hal_msp.c ****
258:Core/Src/stm32f1xx_hal_msp.c **** }
524 .loc 1 258 1 view .LVU111
525 000a 08BD pop {r3, pc}
526 .LVL22:
527 .L43:
245:Core/Src/stm32f1xx_hal_msp.c ****
528 .loc 1 245 5 is_stmt 1 view .LVU112
529 000c 054A ldr r2, .L44+4
530 000e 9369 ldr r3, [r2, #24]
531 0010 23F48053 bic r3, r3, #4096
532 0014 9361 str r3, [r2, #24]
251:Core/Src/stm32f1xx_hal_msp.c ****
533 .loc 1 251 5 view .LVU113
534 0016 A021 movs r1, #160
535 0018 0348 ldr r0, .L44+8
536 .LVL23:
251:Core/Src/stm32f1xx_hal_msp.c ****
537 .loc 1 251 5 is_stmt 0 view .LVU114
538 001a FFF7FEFF bl HAL_GPIO_DeInit
539 .LVL24:
540 .loc 1 258 1 view .LVU115
541 001e F4E7 b .L40
542 .L45:
543 .align 2
544 .L44:
545 0020 00300140 .word 1073819648
546 0024 00100240 .word 1073876992
547 0028 00080140 .word 1073809408
548 .cfi_endproc
549 .LFE71:
551 .section .text.HAL_TIM_OC_MspInit,"ax",%progbits
552 .align 1
553 .global HAL_TIM_OC_MspInit
554 .syntax unified
555 .thumb
556 .thumb_func
557 .fpu softvfp
559 HAL_TIM_OC_MspInit:
560 .LVL25:
561 .LFB72:
259:Core/Src/stm32f1xx_hal_msp.c ****
260:Core/Src/stm32f1xx_hal_msp.c **** /**
261:Core/Src/stm32f1xx_hal_msp.c **** * @brief TIM_OC MSP Initialization
262:Core/Src/stm32f1xx_hal_msp.c **** * This function configures the hardware resources used in this example
ARM GAS C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s page 16
263:Core/Src/stm32f1xx_hal_msp.c **** * @param htim_oc: TIM_OC handle pointer
264:Core/Src/stm32f1xx_hal_msp.c **** * @retval None
265:Core/Src/stm32f1xx_hal_msp.c **** */
266:Core/Src/stm32f1xx_hal_msp.c **** void HAL_TIM_OC_MspInit(TIM_HandleTypeDef* htim_oc)
267:Core/Src/stm32f1xx_hal_msp.c **** {
562 .loc 1 267 1 is_stmt 1 view -0
563 .cfi_startproc
564 @ args = 0, pretend = 0, frame = 8
565 @ frame_needed = 0, uses_anonymous_args = 0
566 @ link register save eliminated.
268:Core/Src/stm32f1xx_hal_msp.c **** if(htim_oc->Instance==TIM3)
567 .loc 1 268 3 view .LVU117
568 .loc 1 268 13 is_stmt 0 view .LVU118
569 0000 0268 ldr r2, [r0]
570 .loc 1 268 5 view .LVU119
571 0002 094B ldr r3, .L53
572 0004 9A42 cmp r2, r3
573 0006 00D0 beq .L52
574 0008 7047 bx lr
575 .L52:
267:Core/Src/stm32f1xx_hal_msp.c **** if(htim_oc->Instance==TIM3)
576 .loc 1 267 1 view .LVU120
577 000a 82B0 sub sp, sp, #8
578 .LCFI15:
579 .cfi_def_cfa_offset 8
269:Core/Src/stm32f1xx_hal_msp.c **** {
270:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN TIM3_MspInit 0 */
271:Core/Src/stm32f1xx_hal_msp.c ****
272:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END TIM3_MspInit 0 */
273:Core/Src/stm32f1xx_hal_msp.c **** /* Peripheral clock enable */
274:Core/Src/stm32f1xx_hal_msp.c **** __HAL_RCC_TIM3_CLK_ENABLE();
580 .loc 1 274 5 is_stmt 1 view .LVU121
581 .LBB11:
582 .loc 1 274 5 view .LVU122
583 .loc 1 274 5 view .LVU123
584 000c 03F50333 add r3, r3, #134144
585 0010 DA69 ldr r2, [r3, #28]
586 0012 42F00202 orr r2, r2, #2
587 0016 DA61 str r2, [r3, #28]
588 .loc 1 274 5 view .LVU124
589 0018 DB69 ldr r3, [r3, #28]
590 001a 03F00203 and r3, r3, #2
591 001e 0193 str r3, [sp, #4]
592 .loc 1 274 5 view .LVU125
593 0020 019B ldr r3, [sp, #4]
594 .LBE11:
275:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN TIM3_MspInit 1 */
276:Core/Src/stm32f1xx_hal_msp.c ****
277:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END TIM3_MspInit 1 */
278:Core/Src/stm32f1xx_hal_msp.c **** }
279:Core/Src/stm32f1xx_hal_msp.c ****
280:Core/Src/stm32f1xx_hal_msp.c **** }
595 .loc 1 280 1 is_stmt 0 view .LVU126
596 0022 02B0 add sp, sp, #8
597 .LCFI16:
598 .cfi_def_cfa_offset 0
599 @ sp needed
ARM GAS C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s page 17
600 0024 7047 bx lr
601 .L54:
602 0026 00BF .align 2
603 .L53:
604 0028 00040040 .word 1073742848
605 .cfi_endproc
606 .LFE72:
608 .section .text.HAL_TIM_Encoder_MspInit,"ax",%progbits
609 .align 1
610 .global HAL_TIM_Encoder_MspInit
611 .syntax unified
612 .thumb
613 .thumb_func
614 .fpu softvfp
616 HAL_TIM_Encoder_MspInit:
617 .LVL26:
618 .LFB73:
281:Core/Src/stm32f1xx_hal_msp.c ****
282:Core/Src/stm32f1xx_hal_msp.c **** /**
283:Core/Src/stm32f1xx_hal_msp.c **** * @brief TIM_Encoder MSP Initialization
284:Core/Src/stm32f1xx_hal_msp.c **** * This function configures the hardware resources used in this example
285:Core/Src/stm32f1xx_hal_msp.c **** * @param htim_encoder: TIM_Encoder handle pointer
286:Core/Src/stm32f1xx_hal_msp.c **** * @retval None
287:Core/Src/stm32f1xx_hal_msp.c **** */
288:Core/Src/stm32f1xx_hal_msp.c **** void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* htim_encoder)
289:Core/Src/stm32f1xx_hal_msp.c **** {
619 .loc 1 289 1 is_stmt 1 view -0
620 .cfi_startproc
621 @ args = 0, pretend = 0, frame = 24
622 @ frame_needed = 0, uses_anonymous_args = 0
623 .loc 1 289 1 is_stmt 0 view .LVU128
624 0000 00B5 push {lr}
625 .LCFI17:
626 .cfi_def_cfa_offset 4
627 .cfi_offset 14, -4
628 0002 87B0 sub sp, sp, #28
629 .LCFI18:
630 .cfi_def_cfa_offset 32
290:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitTypeDef GPIO_InitStruct = {0};
631 .loc 1 290 3 is_stmt 1 view .LVU129
632 .loc 1 290 20 is_stmt 0 view .LVU130
633 0004 0023 movs r3, #0
634 0006 0293 str r3, [sp, #8]
635 0008 0393 str r3, [sp, #12]
636 000a 0493 str r3, [sp, #16]
637 000c 0593 str r3, [sp, #20]
291:Core/Src/stm32f1xx_hal_msp.c **** if(htim_encoder->Instance==TIM4)
638 .loc 1 291 3 is_stmt 1 view .LVU131
639 .loc 1 291 18 is_stmt 0 view .LVU132
640 000e 0268 ldr r2, [r0]
641 .loc 1 291 5 view .LVU133
642 0010 114B ldr r3, .L59
643 0012 9A42 cmp r2, r3
644 0014 02D0 beq .L58
645 .LVL27:
646 .L55:
292:Core/Src/stm32f1xx_hal_msp.c **** {
ARM GAS C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s page 18
293:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspInit 0 */
294:Core/Src/stm32f1xx_hal_msp.c ****
295:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END TIM4_MspInit 0 */
296:Core/Src/stm32f1xx_hal_msp.c **** /* Peripheral clock enable */
297:Core/Src/stm32f1xx_hal_msp.c **** __HAL_RCC_TIM4_CLK_ENABLE();
298:Core/Src/stm32f1xx_hal_msp.c ****
299:Core/Src/stm32f1xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
300:Core/Src/stm32f1xx_hal_msp.c **** /**TIM4 GPIO Configuration
301:Core/Src/stm32f1xx_hal_msp.c **** PB6 ------> TIM4_CH1
302:Core/Src/stm32f1xx_hal_msp.c **** PB7 ------> TIM4_CH2
303:Core/Src/stm32f1xx_hal_msp.c **** */
304:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
305:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
306:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_PULLUP;
307:Core/Src/stm32f1xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
308:Core/Src/stm32f1xx_hal_msp.c ****
309:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspInit 1 */
310:Core/Src/stm32f1xx_hal_msp.c ****
311:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END TIM4_MspInit 1 */
312:Core/Src/stm32f1xx_hal_msp.c **** }
313:Core/Src/stm32f1xx_hal_msp.c ****
314:Core/Src/stm32f1xx_hal_msp.c **** }
647 .loc 1 314 1 view .LVU134
648 0016 07B0 add sp, sp, #28
649 .LCFI19:
650 .cfi_remember_state
651 .cfi_def_cfa_offset 4
652 @ sp needed
653 0018 5DF804FB ldr pc, [sp], #4
654 .LVL28:
655 .L58:
656 .LCFI20:
657 .cfi_restore_state
297:Core/Src/stm32f1xx_hal_msp.c ****
658 .loc 1 297 5 is_stmt 1 view .LVU135
659 .LBB12:
297:Core/Src/stm32f1xx_hal_msp.c ****
660 .loc 1 297 5 view .LVU136
297:Core/Src/stm32f1xx_hal_msp.c ****
661 .loc 1 297 5 view .LVU137
662 001c 03F50233 add r3, r3, #133120
663 0020 DA69 ldr r2, [r3, #28]
664 0022 42F00402 orr r2, r2, #4
665 0026 DA61 str r2, [r3, #28]
297:Core/Src/stm32f1xx_hal_msp.c ****
666 .loc 1 297 5 view .LVU138
667 0028 DA69 ldr r2, [r3, #28]
668 002a 02F00402 and r2, r2, #4
669 002e 0092 str r2, [sp]
297:Core/Src/stm32f1xx_hal_msp.c ****
670 .loc 1 297 5 view .LVU139
671 0030 009A ldr r2, [sp]
672 .LBE12:
299:Core/Src/stm32f1xx_hal_msp.c **** /**TIM4 GPIO Configuration
673 .loc 1 299 5 view .LVU140
674 .LBB13:
299:Core/Src/stm32f1xx_hal_msp.c **** /**TIM4 GPIO Configuration
ARM GAS C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s page 19
675 .loc 1 299 5 view .LVU141
299:Core/Src/stm32f1xx_hal_msp.c **** /**TIM4 GPIO Configuration
676 .loc 1 299 5 view .LVU142
677 0032 9A69 ldr r2, [r3, #24]
678 0034 42F00802 orr r2, r2, #8
679 0038 9A61 str r2, [r3, #24]
299:Core/Src/stm32f1xx_hal_msp.c **** /**TIM4 GPIO Configuration
680 .loc 1 299 5 view .LVU143
681 003a 9B69 ldr r3, [r3, #24]
682 003c 03F00803 and r3, r3, #8
683 0040 0193 str r3, [sp, #4]
299:Core/Src/stm32f1xx_hal_msp.c **** /**TIM4 GPIO Configuration
684 .loc 1 299 5 view .LVU144
685 0042 019B ldr r3, [sp, #4]
686 .LBE13:
304:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
687 .loc 1 304 5 view .LVU145
304:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
688 .loc 1 304 25 is_stmt 0 view .LVU146
689 0044 C023 movs r3, #192
690 0046 0293 str r3, [sp, #8]
305:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_PULLUP;
691 .loc 1 305 5 is_stmt 1 view .LVU147
306:Core/Src/stm32f1xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
692 .loc 1 306 5 view .LVU148
306:Core/Src/stm32f1xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
693 .loc 1 306 26 is_stmt 0 view .LVU149
694 0048 0123 movs r3, #1
695 004a 0493 str r3, [sp, #16]
307:Core/Src/stm32f1xx_hal_msp.c ****
696 .loc 1 307 5 is_stmt 1 view .LVU150
697 004c 02A9 add r1, sp, #8
698 004e 0348 ldr r0, .L59+4
699 .LVL29:
307:Core/Src/stm32f1xx_hal_msp.c ****
700 .loc 1 307 5 is_stmt 0 view .LVU151
701 0050 FFF7FEFF bl HAL_GPIO_Init
702 .LVL30:
703 .loc 1 314 1 view .LVU152
704 0054 DFE7 b .L55
705 .L60:
706 0056 00BF .align 2
707 .L59:
708 0058 00080040 .word 1073743872
709 005c 000C0140 .word 1073810432
710 .cfi_endproc
711 .LFE73:
713 .section .text.HAL_TIM_OC_MspDeInit,"ax",%progbits
714 .align 1
715 .global HAL_TIM_OC_MspDeInit
716 .syntax unified
717 .thumb
718 .thumb_func
719 .fpu softvfp
721 HAL_TIM_OC_MspDeInit:
722 .LVL31:
723 .LFB74:
ARM GAS C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s page 20
315:Core/Src/stm32f1xx_hal_msp.c ****
316:Core/Src/stm32f1xx_hal_msp.c **** /**
317:Core/Src/stm32f1xx_hal_msp.c **** * @brief TIM_OC MSP De-Initialization
318:Core/Src/stm32f1xx_hal_msp.c **** * This function freeze the hardware resources used in this example
319:Core/Src/stm32f1xx_hal_msp.c **** * @param htim_oc: TIM_OC handle pointer
320:Core/Src/stm32f1xx_hal_msp.c **** * @retval None
321:Core/Src/stm32f1xx_hal_msp.c **** */
322:Core/Src/stm32f1xx_hal_msp.c **** void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef* htim_oc)
323:Core/Src/stm32f1xx_hal_msp.c **** {
724 .loc 1 323 1 is_stmt 1 view -0
725 .cfi_startproc
726 @ args = 0, pretend = 0, frame = 0
727 @ frame_needed = 0, uses_anonymous_args = 0
728 @ link register save eliminated.
324:Core/Src/stm32f1xx_hal_msp.c **** if(htim_oc->Instance==TIM3)
729 .loc 1 324 3 view .LVU154
730 .loc 1 324 13 is_stmt 0 view .LVU155
731 0000 0268 ldr r2, [r0]
732 .loc 1 324 5 view .LVU156
733 0002 054B ldr r3, .L64
734 0004 9A42 cmp r2, r3
735 0006 00D0 beq .L63
736 .L61:
325:Core/Src/stm32f1xx_hal_msp.c **** {
326:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN TIM3_MspDeInit 0 */
327:Core/Src/stm32f1xx_hal_msp.c ****
328:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END TIM3_MspDeInit 0 */
329:Core/Src/stm32f1xx_hal_msp.c **** /* Peripheral clock disable */
330:Core/Src/stm32f1xx_hal_msp.c **** __HAL_RCC_TIM3_CLK_DISABLE();
331:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN TIM3_MspDeInit 1 */
332:Core/Src/stm32f1xx_hal_msp.c ****
333:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END TIM3_MspDeInit 1 */
334:Core/Src/stm32f1xx_hal_msp.c **** }
335:Core/Src/stm32f1xx_hal_msp.c ****
336:Core/Src/stm32f1xx_hal_msp.c **** }
737 .loc 1 336 1 view .LVU157
738 0008 7047 bx lr
739 .L63:
330:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN TIM3_MspDeInit 1 */
740 .loc 1 330 5 is_stmt 1 view .LVU158
741 000a 044A ldr r2, .L64+4
742 000c D369 ldr r3, [r2, #28]
743 000e 23F00203 bic r3, r3, #2
744 0012 D361 str r3, [r2, #28]
745 .loc 1 336 1 is_stmt 0 view .LVU159
746 0014 F8E7 b .L61
747 .L65:
748 0016 00BF .align 2
749 .L64:
750 0018 00040040 .word 1073742848
751 001c 00100240 .word 1073876992
752 .cfi_endproc
753 .LFE74:
755 .section .text.HAL_TIM_Encoder_MspDeInit,"ax",%progbits
756 .align 1
757 .global HAL_TIM_Encoder_MspDeInit
758 .syntax unified
ARM GAS C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s page 21
759 .thumb
760 .thumb_func
761 .fpu softvfp
763 HAL_TIM_Encoder_MspDeInit:
764 .LVL32:
765 .LFB75:
337:Core/Src/stm32f1xx_hal_msp.c ****
338:Core/Src/stm32f1xx_hal_msp.c **** /**
339:Core/Src/stm32f1xx_hal_msp.c **** * @brief TIM_Encoder MSP De-Initialization
340:Core/Src/stm32f1xx_hal_msp.c **** * This function freeze the hardware resources used in this example
341:Core/Src/stm32f1xx_hal_msp.c **** * @param htim_encoder: TIM_Encoder handle pointer
342:Core/Src/stm32f1xx_hal_msp.c **** * @retval None
343:Core/Src/stm32f1xx_hal_msp.c **** */
344:Core/Src/stm32f1xx_hal_msp.c **** void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef* htim_encoder)
345:Core/Src/stm32f1xx_hal_msp.c **** {
766 .loc 1 345 1 is_stmt 1 view -0
767 .cfi_startproc
768 @ args = 0, pretend = 0, frame = 0
769 @ frame_needed = 0, uses_anonymous_args = 0
770 .loc 1 345 1 is_stmt 0 view .LVU161
771 0000 08B5 push {r3, lr}
772 .LCFI21:
773 .cfi_def_cfa_offset 8
774 .cfi_offset 3, -8
775 .cfi_offset 14, -4
346:Core/Src/stm32f1xx_hal_msp.c **** if(htim_encoder->Instance==TIM4)
776 .loc 1 346 3 is_stmt 1 view .LVU162
777 .loc 1 346 18 is_stmt 0 view .LVU163
778 0002 0268 ldr r2, [r0]
779 .loc 1 346 5 view .LVU164
780 0004 064B ldr r3, .L70
781 0006 9A42 cmp r2, r3
782 0008 00D0 beq .L69
783 .LVL33:
784 .L66:
347:Core/Src/stm32f1xx_hal_msp.c **** {
348:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspDeInit 0 */
349:Core/Src/stm32f1xx_hal_msp.c ****
350:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END TIM4_MspDeInit 0 */
351:Core/Src/stm32f1xx_hal_msp.c **** /* Peripheral clock disable */
352:Core/Src/stm32f1xx_hal_msp.c **** __HAL_RCC_TIM4_CLK_DISABLE();
353:Core/Src/stm32f1xx_hal_msp.c ****
354:Core/Src/stm32f1xx_hal_msp.c **** /**TIM4 GPIO Configuration
355:Core/Src/stm32f1xx_hal_msp.c **** PB6 ------> TIM4_CH1
356:Core/Src/stm32f1xx_hal_msp.c **** PB7 ------> TIM4_CH2
357:Core/Src/stm32f1xx_hal_msp.c **** */
358:Core/Src/stm32f1xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6|GPIO_PIN_7);
359:Core/Src/stm32f1xx_hal_msp.c ****
360:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspDeInit 1 */
361:Core/Src/stm32f1xx_hal_msp.c ****
362:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END TIM4_MspDeInit 1 */
363:Core/Src/stm32f1xx_hal_msp.c **** }
364:Core/Src/stm32f1xx_hal_msp.c ****
365:Core/Src/stm32f1xx_hal_msp.c **** }
785 .loc 1 365 1 view .LVU165
786 000a 08BD pop {r3, pc}
787 .LVL34:
ARM GAS C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s page 22
788 .L69:
352:Core/Src/stm32f1xx_hal_msp.c ****
789 .loc 1 352 5 is_stmt 1 view .LVU166
790 000c 054A ldr r2, .L70+4
791 000e D369 ldr r3, [r2, #28]
792 0010 23F00403 bic r3, r3, #4
793 0014 D361 str r3, [r2, #28]
358:Core/Src/stm32f1xx_hal_msp.c ****
794 .loc 1 358 5 view .LVU167
795 0016 C021 movs r1, #192
796 0018 0348 ldr r0, .L70+8
797 .LVL35:
358:Core/Src/stm32f1xx_hal_msp.c ****
798 .loc 1 358 5 is_stmt 0 view .LVU168
799 001a FFF7FEFF bl HAL_GPIO_DeInit
800 .LVL36:
801 .loc 1 365 1 view .LVU169
802 001e F4E7 b .L66
803 .L71:
804 .align 2
805 .L70:
806 0020 00080040 .word 1073743872
807 0024 00100240 .word 1073876992
808 0028 000C0140 .word 1073810432
809 .cfi_endproc
810 .LFE75:
812 .section .text.HAL_UART_MspInit,"ax",%progbits
813 .align 1
814 .global HAL_UART_MspInit
815 .syntax unified
816 .thumb
817 .thumb_func
818 .fpu softvfp
820 HAL_UART_MspInit:
821 .LVL37:
822 .LFB76:
366:Core/Src/stm32f1xx_hal_msp.c ****
367:Core/Src/stm32f1xx_hal_msp.c **** /**
368:Core/Src/stm32f1xx_hal_msp.c **** * @brief UART MSP Initialization
369:Core/Src/stm32f1xx_hal_msp.c **** * This function configures the hardware resources used in this example
370:Core/Src/stm32f1xx_hal_msp.c **** * @param huart: UART handle pointer
371:Core/Src/stm32f1xx_hal_msp.c **** * @retval None
372:Core/Src/stm32f1xx_hal_msp.c **** */
373:Core/Src/stm32f1xx_hal_msp.c **** void HAL_UART_MspInit(UART_HandleTypeDef* huart)
374:Core/Src/stm32f1xx_hal_msp.c **** {
823 .loc 1 374 1 is_stmt 1 view -0
824 .cfi_startproc
825 @ args = 0, pretend = 0, frame = 24
826 @ frame_needed = 0, uses_anonymous_args = 0
827 .loc 1 374 1 is_stmt 0 view .LVU171
828 0000 30B5 push {r4, r5, lr}
829 .LCFI22:
830 .cfi_def_cfa_offset 12
831 .cfi_offset 4, -12
832 .cfi_offset 5, -8
833 .cfi_offset 14, -4
834 0002 87B0 sub sp, sp, #28
ARM GAS C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s page 23
835 .LCFI23:
836 .cfi_def_cfa_offset 40
375:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitTypeDef GPIO_InitStruct = {0};
837 .loc 1 375 3 is_stmt 1 view .LVU172
838 .loc 1 375 20 is_stmt 0 view .LVU173
839 0004 0023 movs r3, #0
840 0006 0293 str r3, [sp, #8]
841 0008 0393 str r3, [sp, #12]
842 000a 0493 str r3, [sp, #16]
843 000c 0593 str r3, [sp, #20]
376:Core/Src/stm32f1xx_hal_msp.c **** if(huart->Instance==USART1)
844 .loc 1 376 3 is_stmt 1 view .LVU174
845 .loc 1 376 11 is_stmt 0 view .LVU175
846 000e 0268 ldr r2, [r0]
847 .loc 1 376 5 view .LVU176
848 0010 1B4B ldr r3, .L76
849 0012 9A42 cmp r2, r3
850 0014 01D0 beq .L75
851 .LVL38:
852 .L72:
377:Core/Src/stm32f1xx_hal_msp.c **** {
378:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN USART1_MspInit 0 */
379:Core/Src/stm32f1xx_hal_msp.c ****
380:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END USART1_MspInit 0 */
381:Core/Src/stm32f1xx_hal_msp.c **** /* Peripheral clock enable */
382:Core/Src/stm32f1xx_hal_msp.c **** __HAL_RCC_USART1_CLK_ENABLE();
383:Core/Src/stm32f1xx_hal_msp.c ****
384:Core/Src/stm32f1xx_hal_msp.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
385:Core/Src/stm32f1xx_hal_msp.c **** /**USART1 GPIO Configuration
386:Core/Src/stm32f1xx_hal_msp.c **** PA9 ------> USART1_TX
387:Core/Src/stm32f1xx_hal_msp.c **** PA10 ------> USART1_RX
388:Core/Src/stm32f1xx_hal_msp.c **** */
389:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_9;
390:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
391:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
392:Core/Src/stm32f1xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
393:Core/Src/stm32f1xx_hal_msp.c ****
394:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_10;
395:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
396:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
397:Core/Src/stm32f1xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
398:Core/Src/stm32f1xx_hal_msp.c ****
399:Core/Src/stm32f1xx_hal_msp.c **** /* USART1 interrupt Init */
400:Core/Src/stm32f1xx_hal_msp.c **** HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
401:Core/Src/stm32f1xx_hal_msp.c **** HAL_NVIC_EnableIRQ(USART1_IRQn);
402:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN USART1_MspInit 1 */
403:Core/Src/stm32f1xx_hal_msp.c ****
404:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END USART1_MspInit 1 */
405:Core/Src/stm32f1xx_hal_msp.c **** }
406:Core/Src/stm32f1xx_hal_msp.c ****
407:Core/Src/stm32f1xx_hal_msp.c **** }
853 .loc 1 407 1 view .LVU177
854 0016 07B0 add sp, sp, #28
855 .LCFI24:
856 .cfi_remember_state
857 .cfi_def_cfa_offset 12
858 @ sp needed
ARM GAS C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s page 24
859 0018 30BD pop {r4, r5, pc}
860 .LVL39:
861 .L75:
862 .LCFI25:
863 .cfi_restore_state
382:Core/Src/stm32f1xx_hal_msp.c ****
864 .loc 1 382 5 is_stmt 1 view .LVU178
865 .LBB14:
382:Core/Src/stm32f1xx_hal_msp.c ****
866 .loc 1 382 5 view .LVU179
382:Core/Src/stm32f1xx_hal_msp.c ****
867 .loc 1 382 5 view .LVU180
868 001a 03F55843 add r3, r3, #55296
869 001e 9A69 ldr r2, [r3, #24]
870 0020 42F48042 orr r2, r2, #16384
871 0024 9A61 str r2, [r3, #24]
382:Core/Src/stm32f1xx_hal_msp.c ****
872 .loc 1 382 5 view .LVU181
873 0026 9A69 ldr r2, [r3, #24]
874 0028 02F48042 and r2, r2, #16384
875 002c 0092 str r2, [sp]
382:Core/Src/stm32f1xx_hal_msp.c ****
876 .loc 1 382 5 view .LVU182
877 002e 009A ldr r2, [sp]
878 .LBE14:
384:Core/Src/stm32f1xx_hal_msp.c **** /**USART1 GPIO Configuration
879 .loc 1 384 5 view .LVU183
880 .LBB15:
384:Core/Src/stm32f1xx_hal_msp.c **** /**USART1 GPIO Configuration
881 .loc 1 384 5 view .LVU184
384:Core/Src/stm32f1xx_hal_msp.c **** /**USART1 GPIO Configuration
882 .loc 1 384 5 view .LVU185
883 0030 9A69 ldr r2, [r3, #24]
884 0032 42F00402 orr r2, r2, #4
885 0036 9A61 str r2, [r3, #24]
384:Core/Src/stm32f1xx_hal_msp.c **** /**USART1 GPIO Configuration
886 .loc 1 384 5 view .LVU186
887 0038 9B69 ldr r3, [r3, #24]
888 003a 03F00403 and r3, r3, #4
889 003e 0193 str r3, [sp, #4]
384:Core/Src/stm32f1xx_hal_msp.c **** /**USART1 GPIO Configuration
890 .loc 1 384 5 view .LVU187
891 0040 019B ldr r3, [sp, #4]
892 .LBE15:
389:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
893 .loc 1 389 5 view .LVU188
389:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
894 .loc 1 389 25 is_stmt 0 view .LVU189
895 0042 4FF40073 mov r3, #512
896 0046 0293 str r3, [sp, #8]
390:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
897 .loc 1 390 5 is_stmt 1 view .LVU190
390:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
898 .loc 1 390 26 is_stmt 0 view .LVU191
899 0048 0223 movs r3, #2
900 004a 0393 str r3, [sp, #12]
391:Core/Src/stm32f1xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
ARM GAS C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s page 25
901 .loc 1 391 5 is_stmt 1 view .LVU192
391:Core/Src/stm32f1xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
902 .loc 1 391 27 is_stmt 0 view .LVU193
903 004c 0323 movs r3, #3
904 004e 0593 str r3, [sp, #20]
392:Core/Src/stm32f1xx_hal_msp.c ****
905 .loc 1 392 5 is_stmt 1 view .LVU194
906 0050 0C4D ldr r5, .L76+4
907 0052 02A9 add r1, sp, #8
908 0054 2846 mov r0, r5
909 .LVL40:
392:Core/Src/stm32f1xx_hal_msp.c ****
910 .loc 1 392 5 is_stmt 0 view .LVU195
911 0056 FFF7FEFF bl HAL_GPIO_Init
912 .LVL41:
394:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
913 .loc 1 394 5 is_stmt 1 view .LVU196
394:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
914 .loc 1 394 25 is_stmt 0 view .LVU197
915 005a 4FF48063 mov r3, #1024
916 005e 0293 str r3, [sp, #8]
395:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
917 .loc 1 395 5 is_stmt 1 view .LVU198
395:Core/Src/stm32f1xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
918 .loc 1 395 26 is_stmt 0 view .LVU199
919 0060 0024 movs r4, #0
920 0062 0394 str r4, [sp, #12]
396:Core/Src/stm32f1xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
921 .loc 1 396 5 is_stmt 1 view .LVU200
396:Core/Src/stm32f1xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
922 .loc 1 396 26 is_stmt 0 view .LVU201
923 0064 0494 str r4, [sp, #16]
397:Core/Src/stm32f1xx_hal_msp.c ****
924 .loc 1 397 5 is_stmt 1 view .LVU202
925 0066 02A9 add r1, sp, #8
926 0068 2846 mov r0, r5
927 006a FFF7FEFF bl HAL_GPIO_Init
928 .LVL42:
400:Core/Src/stm32f1xx_hal_msp.c **** HAL_NVIC_EnableIRQ(USART1_IRQn);
929 .loc 1 400 5 view .LVU203
930 006e 2246 mov r2, r4
931 0070 2146 mov r1, r4
932 0072 2520 movs r0, #37
933 0074 FFF7FEFF bl HAL_NVIC_SetPriority
934 .LVL43:
401:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN USART1_MspInit 1 */
935 .loc 1 401 5 view .LVU204
936 0078 2520 movs r0, #37
937 007a FFF7FEFF bl HAL_NVIC_EnableIRQ
938 .LVL44:
939 .loc 1 407 1 is_stmt 0 view .LVU205
940 007e CAE7 b .L72
941 .L77:
942 .align 2
943 .L76:
944 0080 00380140 .word 1073821696
945 0084 00080140 .word 1073809408
ARM GAS C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s page 26
946 .cfi_endproc
947 .LFE76:
949 .section .text.HAL_UART_MspDeInit,"ax",%progbits
950 .align 1
951 .global HAL_UART_MspDeInit
952 .syntax unified
953 .thumb
954 .thumb_func
955 .fpu softvfp
957 HAL_UART_MspDeInit:
958 .LVL45:
959 .LFB77:
408:Core/Src/stm32f1xx_hal_msp.c ****
409:Core/Src/stm32f1xx_hal_msp.c **** /**
410:Core/Src/stm32f1xx_hal_msp.c **** * @brief UART MSP De-Initialization
411:Core/Src/stm32f1xx_hal_msp.c **** * This function freeze the hardware resources used in this example
412:Core/Src/stm32f1xx_hal_msp.c **** * @param huart: UART handle pointer
413:Core/Src/stm32f1xx_hal_msp.c **** * @retval None
414:Core/Src/stm32f1xx_hal_msp.c **** */
415:Core/Src/stm32f1xx_hal_msp.c **** void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
416:Core/Src/stm32f1xx_hal_msp.c **** {
960 .loc 1 416 1 is_stmt 1 view -0
961 .cfi_startproc
962 @ args = 0, pretend = 0, frame = 0
963 @ frame_needed = 0, uses_anonymous_args = 0
964 .loc 1 416 1 is_stmt 0 view .LVU207
965 0000 08B5 push {r3, lr}
966 .LCFI26:
967 .cfi_def_cfa_offset 8
968 .cfi_offset 3, -8
969 .cfi_offset 14, -4
417:Core/Src/stm32f1xx_hal_msp.c **** if(huart->Instance==USART1)
970 .loc 1 417 3 is_stmt 1 view .LVU208
971 .loc 1 417 11 is_stmt 0 view .LVU209
972 0002 0268 ldr r2, [r0]
973 .loc 1 417 5 view .LVU210
974 0004 084B ldr r3, .L82
975 0006 9A42 cmp r2, r3
976 0008 00D0 beq .L81
977 .LVL46:
978 .L78:
418:Core/Src/stm32f1xx_hal_msp.c **** {
419:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN USART1_MspDeInit 0 */
420:Core/Src/stm32f1xx_hal_msp.c ****
421:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END USART1_MspDeInit 0 */
422:Core/Src/stm32f1xx_hal_msp.c **** /* Peripheral clock disable */
423:Core/Src/stm32f1xx_hal_msp.c **** __HAL_RCC_USART1_CLK_DISABLE();
424:Core/Src/stm32f1xx_hal_msp.c ****
425:Core/Src/stm32f1xx_hal_msp.c **** /**USART1 GPIO Configuration
426:Core/Src/stm32f1xx_hal_msp.c **** PA9 ------> USART1_TX
427:Core/Src/stm32f1xx_hal_msp.c **** PA10 ------> USART1_RX
428:Core/Src/stm32f1xx_hal_msp.c **** */
429:Core/Src/stm32f1xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10);
430:Core/Src/stm32f1xx_hal_msp.c ****
431:Core/Src/stm32f1xx_hal_msp.c **** /* USART1 interrupt DeInit */
432:Core/Src/stm32f1xx_hal_msp.c **** HAL_NVIC_DisableIRQ(USART1_IRQn);
433:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN USART1_MspDeInit 1 */
ARM GAS C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s page 27
434:Core/Src/stm32f1xx_hal_msp.c ****
435:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE END USART1_MspDeInit 1 */
436:Core/Src/stm32f1xx_hal_msp.c **** }
437:Core/Src/stm32f1xx_hal_msp.c ****
438:Core/Src/stm32f1xx_hal_msp.c **** }
979 .loc 1 438 1 view .LVU211
980 000a 08BD pop {r3, pc}
981 .LVL47:
982 .L81:
423:Core/Src/stm32f1xx_hal_msp.c ****
983 .loc 1 423 5 is_stmt 1 view .LVU212
984 000c 074A ldr r2, .L82+4
985 000e 9369 ldr r3, [r2, #24]
986 0010 23F48043 bic r3, r3, #16384
987 0014 9361 str r3, [r2, #24]
429:Core/Src/stm32f1xx_hal_msp.c ****
988 .loc 1 429 5 view .LVU213
989 0016 4FF4C061 mov r1, #1536
990 001a 0548 ldr r0, .L82+8
991 .LVL48:
429:Core/Src/stm32f1xx_hal_msp.c ****
992 .loc 1 429 5 is_stmt 0 view .LVU214
993 001c FFF7FEFF bl HAL_GPIO_DeInit
994 .LVL49:
432:Core/Src/stm32f1xx_hal_msp.c **** /* USER CODE BEGIN USART1_MspDeInit 1 */
995 .loc 1 432 5 is_stmt 1 view .LVU215
996 0020 2520 movs r0, #37
997 0022 FFF7FEFF bl HAL_NVIC_DisableIRQ
998 .LVL50:
999 .loc 1 438 1 is_stmt 0 view .LVU216
1000 0026 F0E7 b .L78
1001 .L83:
1002 .align 2
1003 .L82:
1004 0028 00380140 .word 1073821696
1005 002c 00100240 .word 1073876992
1006 0030 00080140 .word 1073809408
1007 .cfi_endproc
1008 .LFE77:
1010 .text
1011 .Letext0:
1012 .file 2 "c:\\users\\mike\\appdata\\roaming\\xpacks\\@gnu-mcu-eclipse\\arm-none-eabi-gcc\\8.2.1-1.7
1013 .file 3 "c:\\users\\mike\\appdata\\roaming\\xpacks\\@gnu-mcu-eclipse\\arm-none-eabi-gcc\\8.2.1-1.7
1014 .file 4 "Drivers/CMSIS/Include/core_cm3.h"
1015 .file 5 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h"
1016 .file 6 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h"
1017 .file 7 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h"
1018 .file 8 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h"
1019 .file 9 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h"
1020 .file 10 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h"
1021 .file 11 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h"
1022 .file 12 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc.h"
1023 .file 13 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h"
1024 .file 14 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h"
1025 .file 15 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h"
1026 .file 16 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h"
1027 .file 17 "Core/Inc/main.h"
ARM GAS C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s page 28
1028 .file 18 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h"
1029 .file 19 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h"
ARM GAS C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s page 29
DEFINED SYMBOLS
*ABS*:0000000000000000 stm32f1xx_hal_msp.c
C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s:16 .text.HAL_MspInit:0000000000000000 $t
C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s:24 .text.HAL_MspInit:0000000000000000 HAL_MspInit
C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s:88 .text.HAL_MspInit:000000000000003c $d
C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s:94 .text.HAL_I2C_MspInit:0000000000000000 $t
C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s:101 .text.HAL_I2C_MspInit:0000000000000000 HAL_I2C_MspInit
C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s:211 .text.HAL_I2C_MspInit:000000000000006c $d
C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s:218 .text.HAL_I2C_MspDeInit:0000000000000000 $t
C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s:225 .text.HAL_I2C_MspDeInit:0000000000000000 HAL_I2C_MspDeInit
C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s:270 .text.HAL_I2C_MspDeInit:0000000000000030 $d
C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s:277 .text.HAL_RTC_MspInit:0000000000000000 $t
C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s:284 .text.HAL_RTC_MspInit:0000000000000000 HAL_RTC_MspInit
C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s:339 .text.HAL_RTC_MspInit:0000000000000034 $d
C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s:346 .text.HAL_RTC_MspDeInit:0000000000000000 $t
C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s:353 .text.HAL_RTC_MspDeInit:0000000000000000 HAL_RTC_MspDeInit
C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s:381 .text.HAL_RTC_MspDeInit:0000000000000014 $d
C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s:387 .text.HAL_SPI_MspInit:0000000000000000 $t
C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s:394 .text.HAL_SPI_MspInit:0000000000000000 HAL_SPI_MspInit
C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s:489 .text.HAL_SPI_MspInit:000000000000005c $d
C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s:495 .text.HAL_SPI_MspDeInit:0000000000000000 $t
C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s:502 .text.HAL_SPI_MspDeInit:0000000000000000 HAL_SPI_MspDeInit
C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s:545 .text.HAL_SPI_MspDeInit:0000000000000020 $d
C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s:552 .text.HAL_TIM_OC_MspInit:0000000000000000 $t
C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s:559 .text.HAL_TIM_OC_MspInit:0000000000000000 HAL_TIM_OC_MspInit
C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s:604 .text.HAL_TIM_OC_MspInit:0000000000000028 $d
C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s:609 .text.HAL_TIM_Encoder_MspInit:0000000000000000 $t
C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s:616 .text.HAL_TIM_Encoder_MspInit:0000000000000000 HAL_TIM_Encoder_MspInit
C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s:708 .text.HAL_TIM_Encoder_MspInit:0000000000000058 $d
C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s:714 .text.HAL_TIM_OC_MspDeInit:0000000000000000 $t
C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s:721 .text.HAL_TIM_OC_MspDeInit:0000000000000000 HAL_TIM_OC_MspDeInit
C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s:750 .text.HAL_TIM_OC_MspDeInit:0000000000000018 $d
C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s:756 .text.HAL_TIM_Encoder_MspDeInit:0000000000000000 $t
C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s:763 .text.HAL_TIM_Encoder_MspDeInit:0000000000000000 HAL_TIM_Encoder_MspDeInit
C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s:806 .text.HAL_TIM_Encoder_MspDeInit:0000000000000020 $d
C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s:813 .text.HAL_UART_MspInit:0000000000000000 $t
C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s:820 .text.HAL_UART_MspInit:0000000000000000 HAL_UART_MspInit
C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s:944 .text.HAL_UART_MspInit:0000000000000080 $d
C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s:950 .text.HAL_UART_MspDeInit:0000000000000000 $t
C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s:957 .text.HAL_UART_MspDeInit:0000000000000000 HAL_UART_MspDeInit
C:\Users\mike\AppData\Local\Temp\ccTBnoyG.s:1004 .text.HAL_UART_MspDeInit:0000000000000028 $d
UNDEFINED SYMBOLS
HAL_GPIO_Init
HAL_GPIO_DeInit
HAL_PWR_EnableBkUpAccess
HAL_NVIC_SetPriority
HAL_NVIC_EnableIRQ
HAL_NVIC_DisableIRQ