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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32f1xx_ll_wwdg.h
  4.   * @author  MCD Application Team
  5.   * @brief   Header file of WWDG LL module.
  6.   ******************************************************************************
  7.   * @attention
  8.   *
  9.   * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
  10.   * All rights reserved.</center></h2>
  11.   *
  12.   * This software component is licensed by ST under BSD 3-Clause license,
  13.   * the "License"; You may not use this file except in compliance with the
  14.   * License. You may obtain a copy of the License at:
  15.   *                        opensource.org/licenses/BSD-3-Clause
  16.   *
  17.   ******************************************************************************
  18.   */
  19.  
  20. /* Define to prevent recursive inclusion -------------------------------------*/
  21. #ifndef STM32F1xx_LL_WWDG_H
  22. #define STM32F1xx_LL_WWDG_H
  23.  
  24. #ifdef __cplusplus
  25. extern "C" {
  26. #endif
  27.  
  28. /* Includes ------------------------------------------------------------------*/
  29. #include "stm32f1xx.h"
  30.  
  31. /** @addtogroup STM32F1xx_LL_Driver
  32.   * @{
  33.   */
  34.  
  35. #if defined (WWDG)
  36. /** @defgroup WWDG_LL WWDG
  37.   * @{
  38.   */
  39.  
  40. /* Private types -------------------------------------------------------------*/
  41. /* Private variables ---------------------------------------------------------*/
  42. /* Private constants ---------------------------------------------------------*/
  43. /* Private macros ------------------------------------------------------------*/
  44. /* Exported types ------------------------------------------------------------*/
  45. /* Exported constants --------------------------------------------------------*/
  46. /** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
  47.   * @{
  48.   */
  49.  
  50. /** @defgroup WWDG_LL_EC_IT IT Defines
  51.   * @brief    IT defines which can be used with LL_WWDG_ReadReg and  LL_WWDG_WriteReg functions
  52.   * @{
  53.   */
  54. #define LL_WWDG_CFR_EWI                    WWDG_CFR_EWI
  55. /**
  56.   * @}
  57.   */
  58.  
  59. /** @defgroup WWDG_LL_EC_PRESCALER  PRESCALER
  60. * @{
  61. */
  62. #define LL_WWDG_PRESCALER_1                0x00000000U                                             /*!< WWDG counter clock = (PCLK1/4096)/1 */
  63. #define LL_WWDG_PRESCALER_2                WWDG_CFR_WDGTB_0                                        /*!< WWDG counter clock = (PCLK1/4096)/2 */
  64. #define LL_WWDG_PRESCALER_4                WWDG_CFR_WDGTB_1                                        /*!< WWDG counter clock = (PCLK1/4096)/4 */
  65. #define LL_WWDG_PRESCALER_8                (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1)                   /*!< WWDG counter clock = (PCLK1/4096)/8 */
  66. /**
  67.   * @}
  68.   */
  69.  
  70. /**
  71.   * @}
  72.   */
  73.  
  74. /* Exported macro ------------------------------------------------------------*/
  75. /** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
  76.   * @{
  77.   */
  78. /** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
  79.   * @{
  80.   */
  81. /**
  82.   * @brief  Write a value in WWDG register
  83.   * @param  __INSTANCE__ WWDG Instance
  84.   * @param  __REG__ Register to be written
  85.   * @param  __VALUE__ Value to be written in the register
  86.   * @retval None
  87.   */
  88. #define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
  89.  
  90. /**
  91.   * @brief  Read a value in WWDG register
  92.   * @param  __INSTANCE__ WWDG Instance
  93.   * @param  __REG__ Register to be read
  94.   * @retval Register value
  95.   */
  96. #define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
  97. /**
  98.   * @}
  99.   */
  100.  
  101. /**
  102.   * @}
  103.   */
  104.  
  105. /* Exported functions --------------------------------------------------------*/
  106. /** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
  107.   * @{
  108.   */
  109.  
  110. /** @defgroup WWDG_LL_EF_Configuration Configuration
  111.   * @{
  112.   */
  113. /**
  114.   * @brief  Enable Window Watchdog. The watchdog is always disabled after a reset.
  115.   * @note   It is enabled by setting the WDGA bit in the WWDG_CR register,
  116.   *         then it cannot be disabled again except by a reset.
  117.   *         This bit is set by software and only cleared by hardware after a reset.
  118.   *         When WDGA = 1, the watchdog can generate a reset.
  119.   * @rmtoll CR           WDGA          LL_WWDG_Enable
  120.   * @param  WWDGx WWDG Instance
  121.   * @retval None
  122.   */
  123. __STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
  124. {
  125.   SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
  126. }
  127.  
  128. /**
  129.   * @brief  Checks if Window Watchdog is enabled
  130.   * @rmtoll CR           WDGA          LL_WWDG_IsEnabled
  131.   * @param  WWDGx WWDG Instance
  132.   * @retval State of bit (1 or 0).
  133.   */
  134. __STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
  135. {
  136.   return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL);
  137. }
  138.  
  139. /**
  140.   * @brief  Set the Watchdog counter value to provided value (7-bits T[6:0])
  141.   * @note   When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
  142.   *         This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
  143.   *         A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
  144.   *         Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
  145.   * @rmtoll CR           T             LL_WWDG_SetCounter
  146.   * @param  WWDGx WWDG Instance
  147.   * @param  Counter 0..0x7F (7 bit counter value)
  148.   * @retval None
  149.   */
  150. __STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
  151. {
  152.   MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
  153. }
  154.  
  155. /**
  156.   * @brief  Return current Watchdog Counter Value (7 bits counter value)
  157.   * @rmtoll CR           T             LL_WWDG_GetCounter
  158.   * @param  WWDGx WWDG Instance
  159.   * @retval 7 bit Watchdog Counter value
  160.   */
  161. __STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
  162. {
  163.   return (READ_BIT(WWDGx->CR, WWDG_CR_T));
  164. }
  165.  
  166. /**
  167.   * @brief  Set the time base of the prescaler (WDGTB).
  168.   * @note   Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
  169.   *         is decremented every (4096 x 2expWDGTB) PCLK cycles
  170.   * @rmtoll CFR          WDGTB         LL_WWDG_SetPrescaler
  171.   * @param  WWDGx WWDG Instance
  172.   * @param  Prescaler This parameter can be one of the following values:
  173.   *         @arg @ref LL_WWDG_PRESCALER_1
  174.   *         @arg @ref LL_WWDG_PRESCALER_2
  175.   *         @arg @ref LL_WWDG_PRESCALER_4
  176.   *         @arg @ref LL_WWDG_PRESCALER_8
  177.   * @retval None
  178.   */
  179. __STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
  180. {
  181.   MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
  182. }
  183.  
  184. /**
  185.   * @brief  Return current Watchdog Prescaler Value
  186.   * @rmtoll CFR          WDGTB         LL_WWDG_GetPrescaler
  187.   * @param  WWDGx WWDG Instance
  188.   * @retval Returned value can be one of the following values:
  189.   *         @arg @ref LL_WWDG_PRESCALER_1
  190.   *         @arg @ref LL_WWDG_PRESCALER_2
  191.   *         @arg @ref LL_WWDG_PRESCALER_4
  192.   *         @arg @ref LL_WWDG_PRESCALER_8
  193.   */
  194. __STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
  195. {
  196.   return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
  197. }
  198.  
  199. /**
  200.   * @brief  Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
  201.   * @note   This window value defines when write in the WWDG_CR register
  202.   *         to program Watchdog counter is allowed.
  203.   *         Watchdog counter value update must occur only when the counter value
  204.   *         is lower than the Watchdog window register value.
  205.   *         Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
  206.   *         (in the control register) is refreshed before the downcounter has reached
  207.   *         the watchdog window register value.
  208.   *         Physically is possible to set the Window lower then 0x40 but it is not recommended.
  209.   *         To generate an immediate reset, it is possible to set the Counter lower than 0x40.
  210.   * @rmtoll CFR          W             LL_WWDG_SetWindow
  211.   * @param  WWDGx WWDG Instance
  212.   * @param  Window 0x00..0x7F (7 bit Window value)
  213.   * @retval None
  214.   */
  215. __STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
  216. {
  217.   MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
  218. }
  219.  
  220. /**
  221.   * @brief  Return current Watchdog Window Value (7 bits value)
  222.   * @rmtoll CFR          W             LL_WWDG_GetWindow
  223.   * @param  WWDGx WWDG Instance
  224.   * @retval 7 bit Watchdog Window value
  225.   */
  226. __STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
  227. {
  228.   return (READ_BIT(WWDGx->CFR, WWDG_CFR_W));
  229. }
  230.  
  231. /**
  232.   * @}
  233.   */
  234.  
  235. /** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
  236.   * @{
  237.   */
  238. /**
  239.   * @brief  Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
  240.   * @note   This bit is set by hardware when the counter has reached the value 0x40.
  241.   *         It must be cleared by software by writing 0.
  242.   *         A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
  243.   * @rmtoll SR           EWIF          LL_WWDG_IsActiveFlag_EWKUP
  244.   * @param  WWDGx WWDG Instance
  245.   * @retval State of bit (1 or 0).
  246.   */
  247. __STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
  248. {
  249.   return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL);  
  250. }
  251.  
  252. /**
  253.   * @brief  Clear WWDG Early Wakeup Interrupt Flag (EWIF)
  254.   * @rmtoll SR           EWIF          LL_WWDG_ClearFlag_EWKUP
  255.   * @param  WWDGx WWDG Instance
  256.   * @retval None
  257.   */
  258. __STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
  259. {
  260.   WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
  261. }
  262.  
  263. /**
  264.   * @}
  265.   */
  266.  
  267. /** @defgroup WWDG_LL_EF_IT_Management IT_Management
  268.   * @{
  269.   */
  270. /**
  271.   * @brief  Enable the Early Wakeup Interrupt.
  272.   * @note   When set, an interrupt occurs whenever the counter reaches value 0x40.
  273.   *         This interrupt is only cleared by hardware after a reset
  274.   * @rmtoll CFR          EWI           LL_WWDG_EnableIT_EWKUP
  275.   * @param  WWDGx WWDG Instance
  276.   * @retval None
  277.   */
  278. __STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
  279. {
  280.   SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
  281. }
  282.  
  283. /**
  284.   * @brief  Check if Early Wakeup Interrupt is enabled
  285.   * @rmtoll CFR          EWI           LL_WWDG_IsEnabledIT_EWKUP
  286.   * @param  WWDGx WWDG Instance
  287.   * @retval State of bit (1 or 0).
  288.   */
  289. __STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
  290. {
  291.   return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL);
  292. }
  293.  
  294. /**
  295.   * @}
  296.   */
  297.  
  298. /**
  299.   * @}
  300.   */
  301.  
  302. /**
  303.   * @}
  304.   */
  305.  
  306. #endif /* WWDG */
  307.  
  308. /**
  309.   * @}
  310.   */
  311.  
  312. #ifdef __cplusplus
  313. }
  314. #endif
  315.  
  316. #endif /* STM32F1xx_LL_WWDG_H */
  317.  
  318. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  319.