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  1. /*
  2.  * hardware.c
  3.  *
  4.  *  Created on: 19 Aug 2017
  5.  *      Author: Mike
  6.  */
  7. #include "ch.h"
  8. #include "hal.h"
  9. #include "hardware.h"
  10.  
  11. uint16_t timerSamples[timerSampleSize];
  12.  
  13. uint8_t timerInIndex;
  14. uint8_t timerOutIndex;
  15.  
  16.  
  17.  
  18. void TIM1_UP_IRQHandler(void) {
  19. // we have an interrupt here .
  20.         if (TIM1->SR & TIM_SR_CC1IF) {
  21.                 TIM1->SR &= ~TIM_SR_CC1IF;
  22.                 timerSamples[timerInIndex++] = TIM1->CCMR1;
  23.                 if (timerInIndex == timerSampleSize) {
  24.                         timerInIndex = 0;
  25.                 }
  26.  
  27.         }
  28.  
  29. }
  30.  
  31. void initTimer(void) {
  32.         rccEnableTIM1(FALSE);
  33.         rccResetTIM1();
  34.         nvicEnableVector(TIM1_UP_IRQn,
  35.                         CORTEX_PRIORITY_MASK(STM32_GPT_TIM1_IRQ_PRIORITY));
  36.         //gptp->clock = STM32_TIMCLK2;
  37.  
  38.         TIM1->CR1 = 0; /* Initially stopped.           */
  39.         TIM1->CR2 = TIM_CR2_CCDS; /* DMA on UE (if any).          */
  40.         TIM1->PSC = 72 * 3; /* Prescaler value : 3 uS tick timer .             */
  41.         TIM1->DIER = 0;
  42.  
  43. }
  44.  
  45. void stopTimer(void) {
  46.         nvicDisableVector(TIM1_UP_IRQn);
  47.         rccDisableTIM1(FALSE);
  48. }
  49.  
  50. void startTimer(void) {
  51.           TIM1->ARR  = 0xFFFF;                 /* Time constant.               */
  52.           TIM1->EGR  = TIM_EGR_UG;             /* Update event.                */
  53.           TIM1->CNT  = 0;                      /* Reset counter.               */
  54.           /* NOTE: After generating the UG event it takes several clock cycles before
  55.              SR bit 0 goes to 1. This is because the clearing of CNT has been inserted
  56.              before the clearing of SR, to give it some time.*/
  57.           TIM1->SR   = 0;                      /* Clear pending IRQs (if any). */
  58.           TIM1->DIER = TIM_DIER_UIE;           /* Update Event IRQ enabled.    */
  59.           TIM1->CR1  = TIM_CR1_URS | TIM_CR1_CEN;
  60.  
  61.           TIM1->CCMR1 = 3344;
  62. }
  63.