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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32l1xx_ll_tim.c
  4.   * @author  MCD Application Team
  5.   * @brief   TIM LL module driver.
  6.   ******************************************************************************
  7.   * @attention
  8.   *
  9.   * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
  10.   * All rights reserved.</center></h2>
  11.   *
  12.   * This software component is licensed by ST under BSD 3-Clause license,
  13.   * the "License"; You may not use this file except in compliance with the
  14.   * License. You may obtain a copy of the License at:
  15.   *                        opensource.org/licenses/BSD-3-Clause
  16.   *
  17.   ******************************************************************************
  18.   */
  19. #if defined(USE_FULL_LL_DRIVER)
  20.  
  21. /* Includes ------------------------------------------------------------------*/
  22. #include "stm32l1xx_ll_tim.h"
  23. #include "stm32l1xx_ll_bus.h"
  24.  
  25. #ifdef  USE_FULL_ASSERT
  26. #include "stm32_assert.h"
  27. #else
  28. #define assert_param(expr) ((void)0U)
  29. #endif /* USE_FULL_ASSERT */
  30.  
  31. /** @addtogroup STM32L1xx_LL_Driver
  32.   * @{
  33.   */
  34.  
  35. #if defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM6) || defined (TIM7)
  36.  
  37. /** @addtogroup TIM_LL
  38.   * @{
  39.   */
  40.  
  41. /* Private types -------------------------------------------------------------*/
  42. /* Private variables ---------------------------------------------------------*/
  43. /* Private constants ---------------------------------------------------------*/
  44. /* Private macros ------------------------------------------------------------*/
  45. /** @addtogroup TIM_LL_Private_Macros
  46.   * @{
  47.   */
  48. #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
  49.                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
  50.                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
  51.                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
  52.                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
  53.  
  54. #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
  55.                                             || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
  56.                                             || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
  57.  
  58. #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
  59.                                      || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
  60.                                      || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
  61.                                      || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
  62.                                      || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
  63.                                      || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
  64.                                      || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
  65.                                      || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
  66.  
  67. #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
  68.                                       || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
  69.  
  70. #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
  71.                                          || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
  72.  
  73. #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
  74.                                           || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
  75.                                           || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
  76.  
  77. #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
  78.                                     || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
  79.                                     || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
  80.                                     || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
  81.  
  82. #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
  83.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
  84.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
  85.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
  86.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
  87.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
  88.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
  89.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
  90.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
  91.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
  92.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
  93.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
  94.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
  95.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
  96.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
  97.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
  98.  
  99. #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
  100.                                           || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
  101.                                           || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
  102.  
  103. #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
  104.                                           || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
  105.                                           || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
  106.  
  107. #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
  108.                                                   || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
  109. /**
  110.   * @}
  111.   */
  112.  
  113.  
  114. /* Private function prototypes -----------------------------------------------*/
  115. /** @defgroup TIM_LL_Private_Functions TIM Private Functions
  116.   * @{
  117.   */
  118. static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
  119. static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
  120. static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
  121. static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
  122. static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
  123. static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
  124. static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
  125. static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
  126. /**
  127.   * @}
  128.   */
  129.  
  130. /* Exported functions --------------------------------------------------------*/
  131. /** @addtogroup TIM_LL_Exported_Functions
  132.   * @{
  133.   */
  134.  
  135. /** @addtogroup TIM_LL_EF_Init
  136.   * @{
  137.   */
  138.  
  139. /**
  140.   * @brief  Set TIMx registers to their reset values.
  141.   * @param  TIMx Timer instance
  142.   * @retval An ErrorStatus enumeration value:
  143.   *          - SUCCESS: TIMx registers are de-initialized
  144.   *          - ERROR: invalid TIMx instance
  145.   */
  146. ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
  147. {
  148.   ErrorStatus result = SUCCESS;
  149.  
  150.   /* Check the parameters */
  151.   assert_param(IS_TIM_INSTANCE(TIMx));
  152.  
  153.   if (TIMx == TIM2)
  154.   {
  155.     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
  156.     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
  157.   }
  158. #if defined(TIM3)
  159.   else if (TIMx == TIM3)
  160.   {
  161.     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
  162.     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
  163.   }
  164. #endif /* TIM3 */
  165. #if defined(TIM4)
  166.   else if (TIMx == TIM4)
  167.   {
  168.     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
  169.     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
  170.   }
  171. #endif /* TIM4 */
  172. #if defined(TIM5)
  173.   else if (TIMx == TIM5)
  174.   {
  175.     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
  176.     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
  177.   }
  178. #endif /* TIM5 */
  179. #if defined(TIM6)
  180.   else if (TIMx == TIM6)
  181.   {
  182.     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
  183.     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
  184.   }
  185. #endif /* TIM6 */
  186. #if defined(TIM7)
  187.   else if (TIMx == TIM7)
  188.   {
  189.     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
  190.     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
  191.   }
  192. #endif /* TIM7 */
  193. #if defined(TIM9)
  194.   else if (TIMx == TIM9)
  195.   {
  196.     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9);
  197.     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9);
  198.   }
  199. #endif /* TIM9 */
  200. #if defined(TIM10)
  201.   else if (TIMx == TIM10)
  202.   {
  203.     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10);
  204.     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10);
  205.   }
  206. #endif /* TIM10 */
  207. #if defined(TIM11)
  208.   else if (TIMx == TIM11)
  209.   {
  210.     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11);
  211.     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11);
  212.   }
  213. #endif /* TIM11 */
  214.   else
  215.   {
  216.     result = ERROR;
  217.   }
  218.  
  219.   return result;
  220. }
  221.  
  222. /**
  223.   * @brief  Set the fields of the time base unit configuration data structure
  224.   *         to their default values.
  225.   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
  226.   * @retval None
  227.   */
  228. void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
  229. {
  230.   /* Set the default configuration */
  231.   TIM_InitStruct->Prescaler         = (uint16_t)0x0000;
  232.   TIM_InitStruct->CounterMode       = LL_TIM_COUNTERMODE_UP;
  233.   TIM_InitStruct->Autoreload        = 0xFFFFFFFFU;
  234.   TIM_InitStruct->ClockDivision     = LL_TIM_CLOCKDIVISION_DIV1;
  235. }
  236.  
  237. /**
  238.   * @brief  Configure the TIMx time base unit.
  239.   * @param  TIMx Timer Instance
  240.   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
  241.   * @retval An ErrorStatus enumeration value:
  242.   *          - SUCCESS: TIMx registers are de-initialized
  243.   *          - ERROR: not applicable
  244.   */
  245. ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
  246. {
  247.   uint32_t tmpcr1;
  248.  
  249.   /* Check the parameters */
  250.   assert_param(IS_TIM_INSTANCE(TIMx));
  251.   assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
  252.   assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
  253.  
  254.   tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
  255.  
  256.   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
  257.   {
  258.     /* Select the Counter Mode */
  259.     MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
  260.   }
  261.  
  262.   if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
  263.   {
  264.     /* Set the clock division */
  265.     MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
  266.   }
  267.  
  268.   /* Write to TIMx CR1 */
  269.   LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
  270.  
  271.   /* Set the Autoreload value */
  272.   LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
  273.  
  274.   /* Set the Prescaler value */
  275.   LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
  276.   /* Generate an update event to reload the Prescaler
  277.      and the repetition counter value (if applicable) immediately */
  278.   LL_TIM_GenerateEvent_UPDATE(TIMx);
  279.  
  280.   return SUCCESS;
  281. }
  282.  
  283. /**
  284.   * @brief  Set the fields of the TIMx output channel configuration data
  285.   *         structure to their default values.
  286.   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
  287.   * @retval None
  288.   */
  289. void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
  290. {
  291.   /* Set the default configuration */
  292.   TIM_OC_InitStruct->OCMode       = LL_TIM_OCMODE_FROZEN;
  293.   TIM_OC_InitStruct->OCState      = LL_TIM_OCSTATE_DISABLE;
  294.   TIM_OC_InitStruct->CompareValue = 0x00000000U;
  295.   TIM_OC_InitStruct->OCPolarity   = LL_TIM_OCPOLARITY_HIGH;
  296. }
  297.  
  298. /**
  299.   * @brief  Configure the TIMx output channel.
  300.   * @param  TIMx Timer Instance
  301.   * @param  Channel This parameter can be one of the following values:
  302.   *         @arg @ref LL_TIM_CHANNEL_CH1
  303.   *         @arg @ref LL_TIM_CHANNEL_CH2
  304.   *         @arg @ref LL_TIM_CHANNEL_CH3
  305.   *         @arg @ref LL_TIM_CHANNEL_CH4
  306.   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
  307.   * @retval An ErrorStatus enumeration value:
  308.   *          - SUCCESS: TIMx output channel is initialized
  309.   *          - ERROR: TIMx output channel is not initialized
  310.   */
  311. ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
  312. {
  313.   ErrorStatus result = ERROR;
  314.  
  315.   switch (Channel)
  316.   {
  317.     case LL_TIM_CHANNEL_CH1:
  318.       result = OC1Config(TIMx, TIM_OC_InitStruct);
  319.       break;
  320.     case LL_TIM_CHANNEL_CH2:
  321.       result = OC2Config(TIMx, TIM_OC_InitStruct);
  322.       break;
  323.     case LL_TIM_CHANNEL_CH3:
  324.       result = OC3Config(TIMx, TIM_OC_InitStruct);
  325.       break;
  326.     case LL_TIM_CHANNEL_CH4:
  327.       result = OC4Config(TIMx, TIM_OC_InitStruct);
  328.       break;
  329.     default:
  330.       break;
  331.   }
  332.  
  333.   return result;
  334. }
  335.  
  336. /**
  337.   * @brief  Set the fields of the TIMx input channel configuration data
  338.   *         structure to their default values.
  339.   * @param  TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
  340.   * @retval None
  341.   */
  342. void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
  343. {
  344.   /* Set the default configuration */
  345.   TIM_ICInitStruct->ICPolarity    = LL_TIM_IC_POLARITY_RISING;
  346.   TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
  347.   TIM_ICInitStruct->ICPrescaler   = LL_TIM_ICPSC_DIV1;
  348.   TIM_ICInitStruct->ICFilter      = LL_TIM_IC_FILTER_FDIV1;
  349. }
  350.  
  351. /**
  352.   * @brief  Configure the TIMx input channel.
  353.   * @param  TIMx Timer Instance
  354.   * @param  Channel This parameter can be one of the following values:
  355.   *         @arg @ref LL_TIM_CHANNEL_CH1
  356.   *         @arg @ref LL_TIM_CHANNEL_CH2
  357.   *         @arg @ref LL_TIM_CHANNEL_CH3
  358.   *         @arg @ref LL_TIM_CHANNEL_CH4
  359.   * @param  TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
  360.   * @retval An ErrorStatus enumeration value:
  361.   *          - SUCCESS: TIMx output channel is initialized
  362.   *          - ERROR: TIMx output channel is not initialized
  363.   */
  364. ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
  365. {
  366.   ErrorStatus result = ERROR;
  367.  
  368.   switch (Channel)
  369.   {
  370.     case LL_TIM_CHANNEL_CH1:
  371.       result = IC1Config(TIMx, TIM_IC_InitStruct);
  372.       break;
  373.     case LL_TIM_CHANNEL_CH2:
  374.       result = IC2Config(TIMx, TIM_IC_InitStruct);
  375.       break;
  376.     case LL_TIM_CHANNEL_CH3:
  377.       result = IC3Config(TIMx, TIM_IC_InitStruct);
  378.       break;
  379.     case LL_TIM_CHANNEL_CH4:
  380.       result = IC4Config(TIMx, TIM_IC_InitStruct);
  381.       break;
  382.     default:
  383.       break;
  384.   }
  385.  
  386.   return result;
  387. }
  388.  
  389. /**
  390.   * @brief  Fills each TIM_EncoderInitStruct field with its default value
  391.   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
  392.   * @retval None
  393.   */
  394. void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
  395. {
  396.   /* Set the default configuration */
  397.   TIM_EncoderInitStruct->EncoderMode    = LL_TIM_ENCODERMODE_X2_TI1;
  398.   TIM_EncoderInitStruct->IC1Polarity    = LL_TIM_IC_POLARITY_RISING;
  399.   TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
  400.   TIM_EncoderInitStruct->IC1Prescaler   = LL_TIM_ICPSC_DIV1;
  401.   TIM_EncoderInitStruct->IC1Filter      = LL_TIM_IC_FILTER_FDIV1;
  402.   TIM_EncoderInitStruct->IC2Polarity    = LL_TIM_IC_POLARITY_RISING;
  403.   TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
  404.   TIM_EncoderInitStruct->IC2Prescaler   = LL_TIM_ICPSC_DIV1;
  405.   TIM_EncoderInitStruct->IC2Filter      = LL_TIM_IC_FILTER_FDIV1;
  406. }
  407.  
  408. /**
  409.   * @brief  Configure the encoder interface of the timer instance.
  410.   * @param  TIMx Timer Instance
  411.   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
  412.   * @retval An ErrorStatus enumeration value:
  413.   *          - SUCCESS: TIMx registers are de-initialized
  414.   *          - ERROR: not applicable
  415.   */
  416. ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
  417. {
  418.   uint32_t tmpccmr1;
  419.   uint32_t tmpccer;
  420.  
  421.   /* Check the parameters */
  422.   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
  423.   assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
  424.   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
  425.   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
  426.   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
  427.   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
  428.   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
  429.   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
  430.   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
  431.   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
  432.  
  433.   /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
  434.   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
  435.  
  436.   /* Get the TIMx CCMR1 register value */
  437.   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
  438.  
  439.   /* Get the TIMx CCER register value */
  440.   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
  441.  
  442.   /* Configure TI1 */
  443.   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
  444.   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
  445.   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
  446.   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
  447.  
  448.   /* Configure TI2 */
  449.   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F  | TIM_CCMR1_IC2PSC);
  450.   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
  451.   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
  452.   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
  453.  
  454.   /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
  455.   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
  456.   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
  457.   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
  458.   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
  459.  
  460.   /* Set encoder mode */
  461.   LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
  462.  
  463.   /* Write to TIMx CCMR1 */
  464.   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
  465.  
  466.   /* Write to TIMx CCER */
  467.   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
  468.  
  469.   return SUCCESS;
  470. }
  471.  
  472. /**
  473.   * @}
  474.   */
  475.  
  476. /**
  477.   * @}
  478.   */
  479.  
  480. /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
  481.   *  @brief   Private functions
  482.   * @{
  483.   */
  484. /**
  485.   * @brief  Configure the TIMx output channel 1.
  486.   * @param  TIMx Timer Instance
  487.   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
  488.   * @retval An ErrorStatus enumeration value:
  489.   *          - SUCCESS: TIMx registers are de-initialized
  490.   *          - ERROR: not applicable
  491.   */
  492. static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
  493. {
  494.   uint32_t tmpccmr1;
  495.   uint32_t tmpccer;
  496.   uint32_t tmpcr2;
  497.  
  498.   /* Check the parameters */
  499.   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
  500.   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
  501.   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
  502.   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
  503.  
  504.   /* Disable the Channel 1: Reset the CC1E Bit */
  505.   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
  506.  
  507.   /* Get the TIMx CCER register value */
  508.   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
  509.  
  510.   /* Get the TIMx CR2 register value */
  511.   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
  512.  
  513.   /* Get the TIMx CCMR1 register value */
  514.   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
  515.  
  516.   /* Reset Capture/Compare selection Bits */
  517.   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
  518.  
  519.   /* Set the Output Compare Mode */
  520.   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
  521.  
  522.   /* Set the Output Compare Polarity */
  523.   MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
  524.  
  525.   /* Set the Output State */
  526.   MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
  527.  
  528.   /* Write to TIMx CR2 */
  529.   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
  530.  
  531.   /* Write to TIMx CCMR1 */
  532.   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
  533.  
  534.   /* Set the Capture Compare Register value */
  535.   LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
  536.  
  537.   /* Write to TIMx CCER */
  538.   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
  539.  
  540.   return SUCCESS;
  541. }
  542.  
  543. /**
  544.   * @brief  Configure the TIMx output channel 2.
  545.   * @param  TIMx Timer Instance
  546.   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
  547.   * @retval An ErrorStatus enumeration value:
  548.   *          - SUCCESS: TIMx registers are de-initialized
  549.   *          - ERROR: not applicable
  550.   */
  551. static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
  552. {
  553.   uint32_t tmpccmr1;
  554.   uint32_t tmpccer;
  555.   uint32_t tmpcr2;
  556.  
  557.   /* Check the parameters */
  558.   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
  559.   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
  560.   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
  561.   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
  562.  
  563.   /* Disable the Channel 2: Reset the CC2E Bit */
  564.   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
  565.  
  566.   /* Get the TIMx CCER register value */
  567.   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
  568.  
  569.   /* Get the TIMx CR2 register value */
  570.   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
  571.  
  572.   /* Get the TIMx CCMR1 register value */
  573.   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
  574.  
  575.   /* Reset Capture/Compare selection Bits */
  576.   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
  577.  
  578.   /* Select the Output Compare Mode */
  579.   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
  580.  
  581.   /* Set the Output Compare Polarity */
  582.   MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
  583.  
  584.   /* Set the Output State */
  585.   MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
  586.  
  587.   /* Write to TIMx CR2 */
  588.   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
  589.  
  590.   /* Write to TIMx CCMR1 */
  591.   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
  592.  
  593.   /* Set the Capture Compare Register value */
  594.   LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
  595.  
  596.   /* Write to TIMx CCER */
  597.   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
  598.  
  599.   return SUCCESS;
  600. }
  601.  
  602. /**
  603.   * @brief  Configure the TIMx output channel 3.
  604.   * @param  TIMx Timer Instance
  605.   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
  606.   * @retval An ErrorStatus enumeration value:
  607.   *          - SUCCESS: TIMx registers are de-initialized
  608.   *          - ERROR: not applicable
  609.   */
  610. static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
  611. {
  612.   uint32_t tmpccmr2;
  613.   uint32_t tmpccer;
  614.   uint32_t tmpcr2;
  615.  
  616.   /* Check the parameters */
  617.   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
  618.   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
  619.   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
  620.   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
  621.  
  622.   /* Disable the Channel 3: Reset the CC3E Bit */
  623.   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
  624.  
  625.   /* Get the TIMx CCER register value */
  626.   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
  627.  
  628.   /* Get the TIMx CR2 register value */
  629.   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
  630.  
  631.   /* Get the TIMx CCMR2 register value */
  632.   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
  633.  
  634.   /* Reset Capture/Compare selection Bits */
  635.   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
  636.  
  637.   /* Select the Output Compare Mode */
  638.   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
  639.  
  640.   /* Set the Output Compare Polarity */
  641.   MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
  642.  
  643.   /* Set the Output State */
  644.   MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
  645.  
  646.   /* Write to TIMx CR2 */
  647.   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
  648.  
  649.   /* Write to TIMx CCMR2 */
  650.   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
  651.  
  652.   /* Set the Capture Compare Register value */
  653.   LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
  654.  
  655.   /* Write to TIMx CCER */
  656.   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
  657.  
  658.   return SUCCESS;
  659. }
  660.  
  661. /**
  662.   * @brief  Configure the TIMx output channel 4.
  663.   * @param  TIMx Timer Instance
  664.   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
  665.   * @retval An ErrorStatus enumeration value:
  666.   *          - SUCCESS: TIMx registers are de-initialized
  667.   *          - ERROR: not applicable
  668.   */
  669. static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
  670. {
  671.   uint32_t tmpccmr2;
  672.   uint32_t tmpccer;
  673.   uint32_t tmpcr2;
  674.  
  675.   /* Check the parameters */
  676.   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
  677.   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
  678.   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
  679.   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
  680.  
  681.   /* Disable the Channel 4: Reset the CC4E Bit */
  682.   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
  683.  
  684.   /* Get the TIMx CCER register value */
  685.   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
  686.  
  687.   /* Get the TIMx CR2 register value */
  688.   tmpcr2 =  LL_TIM_ReadReg(TIMx, CR2);
  689.  
  690.   /* Get the TIMx CCMR2 register value */
  691.   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
  692.  
  693.   /* Reset Capture/Compare selection Bits */
  694.   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
  695.  
  696.   /* Select the Output Compare Mode */
  697.   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
  698.  
  699.   /* Set the Output Compare Polarity */
  700.   MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
  701.  
  702.   /* Set the Output State */
  703.   MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
  704.  
  705.   /* Write to TIMx CR2 */
  706.   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
  707.  
  708.   /* Write to TIMx CCMR2 */
  709.   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
  710.  
  711.   /* Set the Capture Compare Register value */
  712.   LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
  713.  
  714.   /* Write to TIMx CCER */
  715.   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
  716.  
  717.   return SUCCESS;
  718. }
  719.  
  720.  
  721. /**
  722.   * @brief  Configure the TIMx input channel 1.
  723.   * @param  TIMx Timer Instance
  724.   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
  725.   * @retval An ErrorStatus enumeration value:
  726.   *          - SUCCESS: TIMx registers are de-initialized
  727.   *          - ERROR: not applicable
  728.   */
  729. static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
  730. {
  731.   /* Check the parameters */
  732.   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
  733.   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
  734.   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
  735.   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
  736.   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
  737.  
  738.   /* Disable the Channel 1: Reset the CC1E Bit */
  739.   TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
  740.  
  741.   /* Select the Input and set the filter and the prescaler value */
  742.   MODIFY_REG(TIMx->CCMR1,
  743.              (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
  744.              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
  745.  
  746.   /* Select the Polarity and set the CC1E Bit */
  747.   MODIFY_REG(TIMx->CCER,
  748.              (TIM_CCER_CC1P | TIM_CCER_CC1NP),
  749.              (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
  750.  
  751.   return SUCCESS;
  752. }
  753.  
  754. /**
  755.   * @brief  Configure the TIMx input channel 2.
  756.   * @param  TIMx Timer Instance
  757.   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
  758.   * @retval An ErrorStatus enumeration value:
  759.   *          - SUCCESS: TIMx registers are de-initialized
  760.   *          - ERROR: not applicable
  761.   */
  762. static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
  763. {
  764.   /* Check the parameters */
  765.   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
  766.   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
  767.   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
  768.   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
  769.   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
  770.  
  771.   /* Disable the Channel 2: Reset the CC2E Bit */
  772.   TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
  773.  
  774.   /* Select the Input and set the filter and the prescaler value */
  775.   MODIFY_REG(TIMx->CCMR1,
  776.              (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
  777.              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
  778.  
  779.   /* Select the Polarity and set the CC2E Bit */
  780.   MODIFY_REG(TIMx->CCER,
  781.              (TIM_CCER_CC2P | TIM_CCER_CC2NP),
  782.              ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
  783.  
  784.   return SUCCESS;
  785. }
  786.  
  787. /**
  788.   * @brief  Configure the TIMx input channel 3.
  789.   * @param  TIMx Timer Instance
  790.   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
  791.   * @retval An ErrorStatus enumeration value:
  792.   *          - SUCCESS: TIMx registers are de-initialized
  793.   *          - ERROR: not applicable
  794.   */
  795. static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
  796. {
  797.   /* Check the parameters */
  798.   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
  799.   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
  800.   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
  801.   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
  802.   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
  803.  
  804.   /* Disable the Channel 3: Reset the CC3E Bit */
  805.   TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
  806.  
  807.   /* Select the Input and set the filter and the prescaler value */
  808.   MODIFY_REG(TIMx->CCMR2,
  809.              (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
  810.              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
  811.  
  812.   /* Select the Polarity and set the CC3E Bit */
  813.   MODIFY_REG(TIMx->CCER,
  814.              (TIM_CCER_CC3P | TIM_CCER_CC3NP),
  815.              ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
  816.  
  817.   return SUCCESS;
  818. }
  819.  
  820. /**
  821.   * @brief  Configure the TIMx input channel 4.
  822.   * @param  TIMx Timer Instance
  823.   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
  824.   * @retval An ErrorStatus enumeration value:
  825.   *          - SUCCESS: TIMx registers are de-initialized
  826.   *          - ERROR: not applicable
  827.   */
  828. static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
  829. {
  830.   /* Check the parameters */
  831.   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
  832.   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
  833.   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
  834.   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
  835.   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
  836.  
  837.   /* Disable the Channel 4: Reset the CC4E Bit */
  838.   TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
  839.  
  840.   /* Select the Input and set the filter and the prescaler value */
  841.   MODIFY_REG(TIMx->CCMR2,
  842.              (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
  843.              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
  844.  
  845.   /* Select the Polarity and set the CC2E Bit */
  846.   MODIFY_REG(TIMx->CCER,
  847.              (TIM_CCER_CC4P | TIM_CCER_CC4NP),
  848.              ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
  849.  
  850.   return SUCCESS;
  851. }
  852.  
  853.  
  854. /**
  855.   * @}
  856.   */
  857.  
  858. /**
  859.   * @}
  860.   */
  861.  
  862. #endif /* TIM2 || TIM3 || TIM4 || TIM5 || TIM9 || TIM10 || TIM11 TIM6 || TIM7 */
  863.  
  864. /**
  865.   * @}
  866.   */
  867.  
  868. #endif /* USE_FULL_LL_DRIVER */
  869.  
  870. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  871.