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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32l1xx_hal_tim.c
  4.   * @author  MCD Application Team
  5.   * @brief   TIM HAL module driver.
  6.   *          This file provides firmware functions to manage the following
  7.   *          functionalities of the Timer (TIM) peripheral:
  8.   *           + TIM Time Base Initialization
  9.   *           + TIM Time Base Start
  10.   *           + TIM Time Base Start Interruption
  11.   *           + TIM Time Base Start DMA
  12.   *           + TIM Output Compare/PWM Initialization
  13.   *           + TIM Output Compare/PWM Channel Configuration
  14.   *           + TIM Output Compare/PWM  Start
  15.   *           + TIM Output Compare/PWM  Start Interruption
  16.   *           + TIM Output Compare/PWM Start DMA
  17.   *           + TIM Input Capture Initialization
  18.   *           + TIM Input Capture Channel Configuration
  19.   *           + TIM Input Capture Start
  20.   *           + TIM Input Capture Start Interruption
  21.   *           + TIM Input Capture Start DMA
  22.   *           + TIM One Pulse Initialization
  23.   *           + TIM One Pulse Channel Configuration
  24.   *           + TIM One Pulse Start
  25.   *           + TIM Encoder Interface Initialization
  26.   *           + TIM Encoder Interface Start
  27.   *           + TIM Encoder Interface Start Interruption
  28.   *           + TIM Encoder Interface Start DMA
  29.   *           + Commutation Event configuration with Interruption and DMA
  30.   *           + TIM OCRef clear configuration
  31.   *           + TIM External Clock configuration
  32.   @verbatim
  33.   ==============================================================================
  34.                       ##### TIMER Generic features #####
  35.   ==============================================================================
  36.   [..] The Timer features include:
  37.        (#) 16-bit up, down, up/down auto-reload counter.
  38.        (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
  39.            counter clock frequency either by any factor between 1 and 65536.
  40.        (#) Up to 4 independent channels for:
  41.            (++) Input Capture
  42.            (++) Output Compare
  43.            (++) PWM generation (Edge and Center-aligned Mode)
  44.            (++) One-pulse mode output
  45.        (#) Synchronization circuit to control the timer with external signals and to interconnect
  46.             several timers together.
  47.        (#) Supports incremental encoder for positioning purposes
  48.  
  49.             ##### How to use this driver #####
  50.   ==============================================================================
  51.     [..]
  52.      (#) Initialize the TIM low level resources by implementing the following functions
  53.          depending on the selected feature:
  54.            (++) Time Base : HAL_TIM_Base_MspInit()
  55.            (++) Input Capture : HAL_TIM_IC_MspInit()
  56.            (++) Output Compare : HAL_TIM_OC_MspInit()
  57.            (++) PWM generation : HAL_TIM_PWM_MspInit()
  58.            (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
  59.            (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
  60.  
  61.      (#) Initialize the TIM low level resources :
  62.         (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
  63.         (##) TIM pins configuration
  64.             (+++) Enable the clock for the TIM GPIOs using the following function:
  65.              __HAL_RCC_GPIOx_CLK_ENABLE();
  66.             (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
  67.  
  68.      (#) The external Clock can be configured, if needed (the default clock is the
  69.          internal clock from the APBx), using the following function:
  70.          HAL_TIM_ConfigClockSource, the clock configuration should be done before
  71.          any start function.
  72.  
  73.      (#) Configure the TIM in the desired functioning mode using one of the
  74.        Initialization function of this driver:
  75.        (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
  76.        (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
  77.             Output Compare signal.
  78.        (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
  79.             PWM signal.
  80.        (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
  81.             external signal.
  82.        (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
  83.             in One Pulse Mode.
  84.        (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
  85.  
  86.      (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
  87.            (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
  88.            (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
  89.            (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
  90.            (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
  91.            (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
  92.            (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
  93.  
  94.      (#) The DMA Burst is managed with the two following functions:
  95.          HAL_TIM_DMABurst_WriteStart()
  96.          HAL_TIM_DMABurst_ReadStart()
  97.  
  98.     *** Callback registration ***
  99.   =============================================
  100.  
  101.   [..]
  102.   The compilation define  USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
  103.   allows the user to configure dynamically the driver callbacks.
  104.  
  105.   [..]
  106.   Use Function @ref HAL_TIM_RegisterCallback() to register a callback.
  107.   @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
  108.   the Callback ID and a pointer to the user callback function.
  109.  
  110.   [..]
  111.   Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default
  112.   weak function.
  113.   @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
  114.   and the Callback ID.
  115.  
  116.   [..]
  117.   These functions allow to register/unregister following callbacks:
  118.     (+) Base_MspInitCallback              : TIM Base Msp Init Callback.
  119.     (+) Base_MspDeInitCallback            : TIM Base Msp DeInit Callback.
  120.     (+) IC_MspInitCallback                : TIM IC Msp Init Callback.
  121.     (+) IC_MspDeInitCallback              : TIM IC Msp DeInit Callback.
  122.     (+) OC_MspInitCallback                : TIM OC Msp Init Callback.
  123.     (+) OC_MspDeInitCallback              : TIM OC Msp DeInit Callback.
  124.     (+) PWM_MspInitCallback               : TIM PWM Msp Init Callback.
  125.     (+) PWM_MspDeInitCallback             : TIM PWM Msp DeInit Callback.
  126.     (+) OnePulse_MspInitCallback          : TIM One Pulse Msp Init Callback.
  127.     (+) OnePulse_MspDeInitCallback        : TIM One Pulse Msp DeInit Callback.
  128.     (+) Encoder_MspInitCallback           : TIM Encoder Msp Init Callback.
  129.     (+) Encoder_MspDeInitCallback         : TIM Encoder Msp DeInit Callback.
  130.     (+) PeriodElapsedCallback             : TIM Period Elapsed Callback.
  131.     (+) PeriodElapsedHalfCpltCallback     : TIM Period Elapsed half complete Callback.
  132.     (+) TriggerCallback                   : TIM Trigger Callback.
  133.     (+) TriggerHalfCpltCallback           : TIM Trigger half complete Callback.
  134.     (+) IC_CaptureCallback                : TIM Input Capture Callback.
  135.     (+) IC_CaptureHalfCpltCallback        : TIM Input Capture half complete Callback.
  136.     (+) OC_DelayElapsedCallback           : TIM Output Compare Delay Elapsed Callback.
  137.     (+) PWM_PulseFinishedCallback         : TIM PWM Pulse Finished Callback.
  138.     (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
  139.     (+) ErrorCallback                     : TIM Error Callback.
  140.  
  141.   [..]
  142. By default, after the Init and when the state is HAL_TIM_STATE_RESET
  143. all interrupt callbacks are set to the corresponding weak functions:
  144.   examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().
  145.  
  146.   [..]
  147.   Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
  148.   functionalities in the Init / DeInit only when these callbacks are null
  149.   (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
  150.     keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
  151.  
  152.   [..]
  153.     Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
  154.     Exception done MspInit / MspDeInit that can be registered / unregistered
  155.     in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
  156.     thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
  157.   In that case first register the MspInit/MspDeInit user callbacks
  158.       using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.
  159.  
  160.   [..]
  161.       When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
  162.       not defined, the callback registration feature is not available and all callbacks
  163.       are set to the corresponding weak functions.
  164.  
  165.   @endverbatim
  166.   ******************************************************************************
  167.   * @attention
  168.   *
  169.   * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
  170.   * All rights reserved.</center></h2>
  171.   *
  172.   * This software component is licensed by ST under BSD 3-Clause license,
  173.   * the "License"; You may not use this file except in compliance with the
  174.   * License. You may obtain a copy of the License at:
  175.   *                        opensource.org/licenses/BSD-3-Clause
  176.   *
  177.   ******************************************************************************
  178.   */
  179.  
  180. /* Includes ------------------------------------------------------------------*/
  181. #include "stm32l1xx_hal.h"
  182.  
  183. /** @addtogroup STM32L1xx_HAL_Driver
  184.   * @{
  185.   */
  186.  
  187. /** @defgroup TIM TIM
  188.   * @brief TIM HAL module driver
  189.   * @{
  190.   */
  191.  
  192. #ifdef HAL_TIM_MODULE_ENABLED
  193.  
  194. /* Private typedef -----------------------------------------------------------*/
  195. /* Private define ------------------------------------------------------------*/
  196. /* Private macros ------------------------------------------------------------*/
  197. /* Private variables ---------------------------------------------------------*/
  198. /* Private function prototypes -----------------------------------------------*/
  199. /** @addtogroup TIM_Private_Functions
  200.   * @{
  201.   */
  202. static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
  203. static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
  204. static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
  205. static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
  206. static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
  207. static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
  208.                               uint32_t TIM_ICFilter);
  209. static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
  210. static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
  211.                               uint32_t TIM_ICFilter);
  212. static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
  213. static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
  214.                               uint32_t TIM_ICFilter);
  215. static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
  216.                               uint32_t TIM_ICFilter);
  217. static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
  218. static void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
  219.                               uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
  220. static void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
  221. static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
  222. static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
  223. static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
  224. static void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
  225. static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
  226. static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
  227. static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
  228.                                                   TIM_SlaveConfigTypeDef *sSlaveConfig);
  229. /**
  230.   * @}
  231.   */
  232. /* Exported functions --------------------------------------------------------*/
  233.  
  234. /** @defgroup TIM_Exported_Functions TIM Exported Functions
  235.   * @{
  236.   */
  237.  
  238. /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
  239.   *  @brief    Time Base functions
  240.   *
  241. @verbatim
  242.   ==============================================================================
  243.               ##### Time Base functions #####
  244.   ==============================================================================
  245.   [..]
  246.     This section provides functions allowing to:
  247.     (+) Initialize and configure the TIM base.
  248.     (+) De-initialize the TIM base.
  249.     (+) Start the Time Base.
  250.     (+) Stop the Time Base.
  251.     (+) Start the Time Base and enable interrupt.
  252.     (+) Stop the Time Base and disable interrupt.
  253.     (+) Start the Time Base and enable DMA transfer.
  254.     (+) Stop the Time Base and disable DMA transfer.
  255.  
  256. @endverbatim
  257.   * @{
  258.   */
  259. /**
  260.   * @brief  Initializes the TIM Time base Unit according to the specified
  261.   *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
  262.   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
  263.   *         requires a timer reset to avoid unexpected direction
  264.   *         due to DIR bit readonly in center aligned mode.
  265.   *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
  266.   * @param  htim TIM Base handle
  267.   * @retval HAL status
  268.   */
  269. HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
  270. {
  271.   /* Check the TIM handle allocation */
  272.   if (htim == NULL)
  273.   {
  274.     return HAL_ERROR;
  275.   }
  276.  
  277.   /* Check the parameters */
  278.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  279.   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  280.   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  281.   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
  282.  
  283.   if (htim->State == HAL_TIM_STATE_RESET)
  284.   {
  285.     /* Allocate lock resource and initialize it */
  286.     htim->Lock = HAL_UNLOCKED;
  287.  
  288. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  289.     /* Reset interrupt callbacks to legacy weak callbacks */
  290.     TIM_ResetCallback(htim);
  291.  
  292.     if (htim->Base_MspInitCallback == NULL)
  293.     {
  294.       htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
  295.     }
  296.     /* Init the low level hardware : GPIO, CLOCK, NVIC */
  297.     htim->Base_MspInitCallback(htim);
  298. #else
  299.     /* Init the low level hardware : GPIO, CLOCK, NVIC */
  300.     HAL_TIM_Base_MspInit(htim);
  301. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  302.   }
  303.  
  304.   /* Set the TIM state */
  305.   htim->State = HAL_TIM_STATE_BUSY;
  306.  
  307.   /* Set the Time Base configuration */
  308.   TIM_Base_SetConfig(htim->Instance, &htim->Init);
  309.  
  310.   /* Initialize the DMA burst operation state */
  311.   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  312.  
  313.   /* Initialize the TIM channels state */
  314.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  315.  
  316.   /* Initialize the TIM state*/
  317.   htim->State = HAL_TIM_STATE_READY;
  318.  
  319.   return HAL_OK;
  320. }
  321.  
  322. /**
  323.   * @brief  DeInitializes the TIM Base peripheral
  324.   * @param  htim TIM Base handle
  325.   * @retval HAL status
  326.   */
  327. HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
  328. {
  329.   /* Check the parameters */
  330.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  331.  
  332.   htim->State = HAL_TIM_STATE_BUSY;
  333.  
  334.   /* Disable the TIM Peripheral Clock */
  335.   __HAL_TIM_DISABLE(htim);
  336.  
  337. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  338.   if (htim->Base_MspDeInitCallback == NULL)
  339.   {
  340.     htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
  341.   }
  342.   /* DeInit the low level hardware */
  343.   htim->Base_MspDeInitCallback(htim);
  344. #else
  345.   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
  346.   HAL_TIM_Base_MspDeInit(htim);
  347. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  348.  
  349.   /* Change the DMA burst operation state */
  350.   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
  351.  
  352.   /* Change the TIM channels state */
  353.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
  354.  
  355.   /* Change TIM state */
  356.   htim->State = HAL_TIM_STATE_RESET;
  357.  
  358.   /* Release Lock */
  359.   __HAL_UNLOCK(htim);
  360.  
  361.   return HAL_OK;
  362. }
  363.  
  364. /**
  365.   * @brief  Initializes the TIM Base MSP.
  366.   * @param  htim TIM Base handle
  367.   * @retval None
  368.   */
  369. __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
  370. {
  371.   /* Prevent unused argument(s) compilation warning */
  372.   UNUSED(htim);
  373.  
  374.   /* NOTE : This function should not be modified, when the callback is needed,
  375.             the HAL_TIM_Base_MspInit could be implemented in the user file
  376.    */
  377. }
  378.  
  379. /**
  380.   * @brief  DeInitializes TIM Base MSP.
  381.   * @param  htim TIM Base handle
  382.   * @retval None
  383.   */
  384. __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
  385. {
  386.   /* Prevent unused argument(s) compilation warning */
  387.   UNUSED(htim);
  388.  
  389.   /* NOTE : This function should not be modified, when the callback is needed,
  390.             the HAL_TIM_Base_MspDeInit could be implemented in the user file
  391.    */
  392. }
  393.  
  394.  
  395. /**
  396.   * @brief  Starts the TIM Base generation.
  397.   * @param  htim TIM Base handle
  398.   * @retval HAL status
  399.   */
  400. HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
  401. {
  402.   uint32_t tmpsmcr;
  403.  
  404.   /* Check the parameters */
  405.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  406.  
  407.   /* Check the TIM state */
  408.   if (htim->State != HAL_TIM_STATE_READY)
  409.   {
  410.     return HAL_ERROR;
  411.   }
  412.  
  413.   /* Set the TIM state */
  414.   htim->State = HAL_TIM_STATE_BUSY;
  415.  
  416.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  417.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  418.   {
  419.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  420.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  421.     {
  422.       __HAL_TIM_ENABLE(htim);
  423.     }
  424.   }
  425.   else
  426.   {
  427.     __HAL_TIM_ENABLE(htim);
  428.   }
  429.  
  430.   /* Return function status */
  431.   return HAL_OK;
  432. }
  433.  
  434. /**
  435.   * @brief  Stops the TIM Base generation.
  436.   * @param  htim TIM Base handle
  437.   * @retval HAL status
  438.   */
  439. HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
  440. {
  441.   /* Check the parameters */
  442.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  443.  
  444.   /* Disable the Peripheral */
  445.   __HAL_TIM_DISABLE(htim);
  446.  
  447.   /* Set the TIM state */
  448.   htim->State = HAL_TIM_STATE_READY;
  449.  
  450.   /* Return function status */
  451.   return HAL_OK;
  452. }
  453.  
  454. /**
  455.   * @brief  Starts the TIM Base generation in interrupt mode.
  456.   * @param  htim TIM Base handle
  457.   * @retval HAL status
  458.   */
  459. HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
  460. {
  461.   uint32_t tmpsmcr;
  462.  
  463.   /* Check the parameters */
  464.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  465.  
  466.   /* Check the TIM state */
  467.   if (htim->State != HAL_TIM_STATE_READY)
  468.   {
  469.     return HAL_ERROR;
  470.   }
  471.  
  472.   /* Set the TIM state */
  473.   htim->State = HAL_TIM_STATE_BUSY;
  474.  
  475.   /* Enable the TIM Update interrupt */
  476.   __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
  477.  
  478.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  479.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  480.   {
  481.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  482.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  483.     {
  484.       __HAL_TIM_ENABLE(htim);
  485.     }
  486.   }
  487.   else
  488.   {
  489.     __HAL_TIM_ENABLE(htim);
  490.   }
  491.  
  492.   /* Return function status */
  493.   return HAL_OK;
  494. }
  495.  
  496. /**
  497.   * @brief  Stops the TIM Base generation in interrupt mode.
  498.   * @param  htim TIM Base handle
  499.   * @retval HAL status
  500.   */
  501. HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
  502. {
  503.   /* Check the parameters */
  504.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  505.  
  506.   /* Disable the TIM Update interrupt */
  507.   __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
  508.  
  509.   /* Disable the Peripheral */
  510.   __HAL_TIM_DISABLE(htim);
  511.  
  512.   /* Set the TIM state */
  513.   htim->State = HAL_TIM_STATE_READY;
  514.  
  515.   /* Return function status */
  516.   return HAL_OK;
  517. }
  518.  
  519. /**
  520.   * @brief  Starts the TIM Base generation in DMA mode.
  521.   * @param  htim TIM Base handle
  522.   * @param  pData The source Buffer address.
  523.   * @param  Length The length of data to be transferred from memory to peripheral.
  524.   * @retval HAL status
  525.   */
  526. HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
  527. {
  528.   uint32_t tmpsmcr;
  529.  
  530.   /* Check the parameters */
  531.   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
  532.  
  533.   /* Set the TIM state */
  534.   if (htim->State == HAL_TIM_STATE_BUSY)
  535.   {
  536.     return HAL_BUSY;
  537.   }
  538.   else if (htim->State == HAL_TIM_STATE_READY)
  539.   {
  540.     if ((pData == NULL) && (Length > 0U))
  541.     {
  542.       return HAL_ERROR;
  543.     }
  544.     else
  545.     {
  546.       htim->State = HAL_TIM_STATE_BUSY;
  547.     }
  548.   }
  549.   else
  550.   {
  551.     return HAL_ERROR;
  552.   }
  553.  
  554.   /* Set the DMA Period elapsed callbacks */
  555.   htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
  556.   htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
  557.  
  558.   /* Set the DMA error callback */
  559.   htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
  560.  
  561.   /* Enable the DMA channel */
  562.   if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR,
  563.                      Length) != HAL_OK)
  564.   {
  565.     /* Return error status */
  566.     return HAL_ERROR;
  567.   }
  568.  
  569.   /* Enable the TIM Update DMA request */
  570.   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
  571.  
  572.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  573.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  574.   {
  575.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  576.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  577.     {
  578.       __HAL_TIM_ENABLE(htim);
  579.     }
  580.   }
  581.   else
  582.   {
  583.     __HAL_TIM_ENABLE(htim);
  584.   }
  585.  
  586.   /* Return function status */
  587.   return HAL_OK;
  588. }
  589.  
  590. /**
  591.   * @brief  Stops the TIM Base generation in DMA mode.
  592.   * @param  htim TIM Base handle
  593.   * @retval HAL status
  594.   */
  595. HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
  596. {
  597.   /* Check the parameters */
  598.   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
  599.  
  600.   /* Disable the TIM Update DMA request */
  601.   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
  602.  
  603.   (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
  604.  
  605.   /* Disable the Peripheral */
  606.   __HAL_TIM_DISABLE(htim);
  607.  
  608.   /* Set the TIM state */
  609.   htim->State = HAL_TIM_STATE_READY;
  610.  
  611.   /* Return function status */
  612.   return HAL_OK;
  613. }
  614.  
  615. /**
  616.   * @}
  617.   */
  618.  
  619. /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
  620.   *  @brief    TIM Output Compare functions
  621.   *
  622. @verbatim
  623.   ==============================================================================
  624.                   ##### TIM Output Compare functions #####
  625.   ==============================================================================
  626.   [..]
  627.     This section provides functions allowing to:
  628.     (+) Initialize and configure the TIM Output Compare.
  629.     (+) De-initialize the TIM Output Compare.
  630.     (+) Start the TIM Output Compare.
  631.     (+) Stop the TIM Output Compare.
  632.     (+) Start the TIM Output Compare and enable interrupt.
  633.     (+) Stop the TIM Output Compare and disable interrupt.
  634.     (+) Start the TIM Output Compare and enable DMA transfer.
  635.     (+) Stop the TIM Output Compare and disable DMA transfer.
  636.  
  637. @endverbatim
  638.   * @{
  639.   */
  640. /**
  641.   * @brief  Initializes the TIM Output Compare according to the specified
  642.   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
  643.   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
  644.   *         requires a timer reset to avoid unexpected direction
  645.   *         due to DIR bit readonly in center aligned mode.
  646.   *         Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
  647.   * @param  htim TIM Output Compare handle
  648.   * @retval HAL status
  649.   */
  650. HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
  651. {
  652.   /* Check the TIM handle allocation */
  653.   if (htim == NULL)
  654.   {
  655.     return HAL_ERROR;
  656.   }
  657.  
  658.   /* Check the parameters */
  659.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  660.   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  661.   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  662.   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
  663.  
  664.   if (htim->State == HAL_TIM_STATE_RESET)
  665.   {
  666.     /* Allocate lock resource and initialize it */
  667.     htim->Lock = HAL_UNLOCKED;
  668.  
  669. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  670.     /* Reset interrupt callbacks to legacy weak callbacks */
  671.     TIM_ResetCallback(htim);
  672.  
  673.     if (htim->OC_MspInitCallback == NULL)
  674.     {
  675.       htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
  676.     }
  677.     /* Init the low level hardware : GPIO, CLOCK, NVIC */
  678.     htim->OC_MspInitCallback(htim);
  679. #else
  680.     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
  681.     HAL_TIM_OC_MspInit(htim);
  682. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  683.   }
  684.  
  685.   /* Set the TIM state */
  686.   htim->State = HAL_TIM_STATE_BUSY;
  687.  
  688.   /* Init the base time for the Output Compare */
  689.   TIM_Base_SetConfig(htim->Instance,  &htim->Init);
  690.  
  691.   /* Initialize the DMA burst operation state */
  692.   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  693.  
  694.   /* Initialize the TIM channels state */
  695.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  696.  
  697.   /* Initialize the TIM state*/
  698.   htim->State = HAL_TIM_STATE_READY;
  699.  
  700.   return HAL_OK;
  701. }
  702.  
  703. /**
  704.   * @brief  DeInitializes the TIM peripheral
  705.   * @param  htim TIM Output Compare handle
  706.   * @retval HAL status
  707.   */
  708. HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
  709. {
  710.   /* Check the parameters */
  711.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  712.  
  713.   htim->State = HAL_TIM_STATE_BUSY;
  714.  
  715.   /* Disable the TIM Peripheral Clock */
  716.   __HAL_TIM_DISABLE(htim);
  717.  
  718. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  719.   if (htim->OC_MspDeInitCallback == NULL)
  720.   {
  721.     htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
  722.   }
  723.   /* DeInit the low level hardware */
  724.   htim->OC_MspDeInitCallback(htim);
  725. #else
  726.   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
  727.   HAL_TIM_OC_MspDeInit(htim);
  728. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  729.  
  730.   /* Change the DMA burst operation state */
  731.   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
  732.  
  733.   /* Change the TIM channels state */
  734.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
  735.  
  736.   /* Change TIM state */
  737.   htim->State = HAL_TIM_STATE_RESET;
  738.  
  739.   /* Release Lock */
  740.   __HAL_UNLOCK(htim);
  741.  
  742.   return HAL_OK;
  743. }
  744.  
  745. /**
  746.   * @brief  Initializes the TIM Output Compare MSP.
  747.   * @param  htim TIM Output Compare handle
  748.   * @retval None
  749.   */
  750. __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
  751. {
  752.   /* Prevent unused argument(s) compilation warning */
  753.   UNUSED(htim);
  754.  
  755.   /* NOTE : This function should not be modified, when the callback is needed,
  756.             the HAL_TIM_OC_MspInit could be implemented in the user file
  757.    */
  758. }
  759.  
  760. /**
  761.   * @brief  DeInitializes TIM Output Compare MSP.
  762.   * @param  htim TIM Output Compare handle
  763.   * @retval None
  764.   */
  765. __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
  766. {
  767.   /* Prevent unused argument(s) compilation warning */
  768.   UNUSED(htim);
  769.  
  770.   /* NOTE : This function should not be modified, when the callback is needed,
  771.             the HAL_TIM_OC_MspDeInit could be implemented in the user file
  772.    */
  773. }
  774.  
  775. /**
  776.   * @brief  Starts the TIM Output Compare signal generation.
  777.   * @param  htim TIM Output Compare handle
  778.   * @param  Channel TIM Channel to be enabled
  779.   *          This parameter can be one of the following values:
  780.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  781.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  782.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  783.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  784.   * @retval HAL status
  785.   */
  786. HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
  787. {
  788.   uint32_t tmpsmcr;
  789.  
  790.   /* Check the parameters */
  791.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  792.  
  793.   /* Check the TIM channel state */
  794.   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
  795.   {
  796.     return HAL_ERROR;
  797.   }
  798.  
  799.   /* Set the TIM channel state */
  800.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  801.  
  802.   /* Enable the Output compare channel */
  803.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  804.  
  805.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  806.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  807.   {
  808.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  809.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  810.     {
  811.       __HAL_TIM_ENABLE(htim);
  812.     }
  813.   }
  814.   else
  815.   {
  816.     __HAL_TIM_ENABLE(htim);
  817.   }
  818.  
  819.   /* Return function status */
  820.   return HAL_OK;
  821. }
  822.  
  823. /**
  824.   * @brief  Stops the TIM Output Compare signal generation.
  825.   * @param  htim TIM Output Compare handle
  826.   * @param  Channel TIM Channel to be disabled
  827.   *          This parameter can be one of the following values:
  828.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  829.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  830.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  831.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  832.   * @retval HAL status
  833.   */
  834. HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
  835. {
  836.   /* Check the parameters */
  837.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  838.  
  839.   /* Disable the Output compare channel */
  840.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  841.  
  842.   /* Disable the Peripheral */
  843.   __HAL_TIM_DISABLE(htim);
  844.  
  845.   /* Set the TIM channel state */
  846.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  847.  
  848.   /* Return function status */
  849.   return HAL_OK;
  850. }
  851.  
  852. /**
  853.   * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
  854.   * @param  htim TIM Output Compare handle
  855.   * @param  Channel TIM Channel to be enabled
  856.   *          This parameter can be one of the following values:
  857.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  858.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  859.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  860.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  861.   * @retval HAL status
  862.   */
  863. HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  864. {
  865.   uint32_t tmpsmcr;
  866.  
  867.   /* Check the parameters */
  868.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  869.  
  870.   /* Check the TIM channel state */
  871.   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
  872.   {
  873.     return HAL_ERROR;
  874.   }
  875.  
  876.   /* Set the TIM channel state */
  877.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  878.  
  879.   switch (Channel)
  880.   {
  881.     case TIM_CHANNEL_1:
  882.     {
  883.       /* Enable the TIM Capture/Compare 1 interrupt */
  884.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
  885.       break;
  886.     }
  887.  
  888.     case TIM_CHANNEL_2:
  889.     {
  890.       /* Enable the TIM Capture/Compare 2 interrupt */
  891.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
  892.       break;
  893.     }
  894.  
  895.     case TIM_CHANNEL_3:
  896.     {
  897.       /* Enable the TIM Capture/Compare 3 interrupt */
  898.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
  899.       break;
  900.     }
  901.  
  902.     case TIM_CHANNEL_4:
  903.     {
  904.       /* Enable the TIM Capture/Compare 4 interrupt */
  905.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
  906.       break;
  907.     }
  908.  
  909.     default:
  910.       break;
  911.   }
  912.  
  913.   /* Enable the Output compare channel */
  914.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  915.  
  916.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  917.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  918.   {
  919.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  920.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  921.     {
  922.       __HAL_TIM_ENABLE(htim);
  923.     }
  924.   }
  925.   else
  926.   {
  927.     __HAL_TIM_ENABLE(htim);
  928.   }
  929.  
  930.   /* Return function status */
  931.   return HAL_OK;
  932. }
  933.  
  934. /**
  935.   * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
  936.   * @param  htim TIM Output Compare handle
  937.   * @param  Channel TIM Channel to be disabled
  938.   *          This parameter can be one of the following values:
  939.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  940.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  941.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  942.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  943.   * @retval HAL status
  944.   */
  945. HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  946. {
  947.   /* Check the parameters */
  948.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  949.  
  950.   switch (Channel)
  951.   {
  952.     case TIM_CHANNEL_1:
  953.     {
  954.       /* Disable the TIM Capture/Compare 1 interrupt */
  955.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
  956.       break;
  957.     }
  958.  
  959.     case TIM_CHANNEL_2:
  960.     {
  961.       /* Disable the TIM Capture/Compare 2 interrupt */
  962.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
  963.       break;
  964.     }
  965.  
  966.     case TIM_CHANNEL_3:
  967.     {
  968.       /* Disable the TIM Capture/Compare 3 interrupt */
  969.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
  970.       break;
  971.     }
  972.  
  973.     case TIM_CHANNEL_4:
  974.     {
  975.       /* Disable the TIM Capture/Compare 4 interrupt */
  976.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
  977.       break;
  978.     }
  979.  
  980.     default:
  981.       break;
  982.   }
  983.  
  984.   /* Disable the Output compare channel */
  985.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  986.  
  987.   /* Disable the Peripheral */
  988.   __HAL_TIM_DISABLE(htim);
  989.  
  990.   /* Set the TIM channel state */
  991.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  992.  
  993.   /* Return function status */
  994.   return HAL_OK;
  995. }
  996.  
  997. /**
  998.   * @brief  Starts the TIM Output Compare signal generation in DMA mode.
  999.   * @param  htim TIM Output Compare handle
  1000.   * @param  Channel TIM Channel to be enabled
  1001.   *          This parameter can be one of the following values:
  1002.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1003.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1004.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1005.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1006.   * @param  pData The source Buffer address.
  1007.   * @param  Length The length of data to be transferred from memory to TIM peripheral
  1008.   * @retval HAL status
  1009.   */
  1010. HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
  1011. {
  1012.   uint32_t tmpsmcr;
  1013.  
  1014.   /* Check the parameters */
  1015.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1016.  
  1017.   /* Set the TIM channel state */
  1018.   if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
  1019.   {
  1020.     return HAL_BUSY;
  1021.   }
  1022.   else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
  1023.   {
  1024.     if ((pData == NULL) && (Length > 0U))
  1025.     {
  1026.       return HAL_ERROR;
  1027.     }
  1028.     else
  1029.     {
  1030.       TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  1031.     }
  1032.   }
  1033.   else
  1034.   {
  1035.     return HAL_ERROR;
  1036.   }
  1037.  
  1038.   switch (Channel)
  1039.   {
  1040.     case TIM_CHANNEL_1:
  1041.     {
  1042.       /* Set the DMA compare callbacks */
  1043.       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1044.       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1045.  
  1046.       /* Set the DMA error callback */
  1047.       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
  1048.  
  1049.       /* Enable the DMA channel */
  1050.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
  1051.                          Length) != HAL_OK)
  1052.       {
  1053.         /* Return error status */
  1054.         return HAL_ERROR;
  1055.       }
  1056.  
  1057.       /* Enable the TIM Capture/Compare 1 DMA request */
  1058.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
  1059.       break;
  1060.     }
  1061.  
  1062.     case TIM_CHANNEL_2:
  1063.     {
  1064.       /* Set the DMA compare callbacks */
  1065.       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1066.       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1067.  
  1068.       /* Set the DMA error callback */
  1069.       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
  1070.  
  1071.       /* Enable the DMA channel */
  1072.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
  1073.                          Length) != HAL_OK)
  1074.       {
  1075.         /* Return error status */
  1076.         return HAL_ERROR;
  1077.       }
  1078.  
  1079.       /* Enable the TIM Capture/Compare 2 DMA request */
  1080.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
  1081.       break;
  1082.     }
  1083.  
  1084.     case TIM_CHANNEL_3:
  1085.     {
  1086.       /* Set the DMA compare callbacks */
  1087.       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1088.       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1089.  
  1090.       /* Set the DMA error callback */
  1091.       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
  1092.  
  1093.       /* Enable the DMA channel */
  1094.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
  1095.                          Length) != HAL_OK)
  1096.       {
  1097.         /* Return error status */
  1098.         return HAL_ERROR;
  1099.       }
  1100.       /* Enable the TIM Capture/Compare 3 DMA request */
  1101.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
  1102.       break;
  1103.     }
  1104.  
  1105.     case TIM_CHANNEL_4:
  1106.     {
  1107.       /* Set the DMA compare callbacks */
  1108.       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1109.       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1110.  
  1111.       /* Set the DMA error callback */
  1112.       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
  1113.  
  1114.       /* Enable the DMA channel */
  1115.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
  1116.                          Length) != HAL_OK)
  1117.       {
  1118.         /* Return error status */
  1119.         return HAL_ERROR;
  1120.       }
  1121.       /* Enable the TIM Capture/Compare 4 DMA request */
  1122.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
  1123.       break;
  1124.     }
  1125.  
  1126.     default:
  1127.       break;
  1128.   }
  1129.  
  1130.   /* Enable the Output compare channel */
  1131.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  1132.  
  1133.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  1134.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  1135.   {
  1136.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  1137.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  1138.     {
  1139.       __HAL_TIM_ENABLE(htim);
  1140.     }
  1141.   }
  1142.   else
  1143.   {
  1144.     __HAL_TIM_ENABLE(htim);
  1145.   }
  1146.  
  1147.   /* Return function status */
  1148.   return HAL_OK;
  1149. }
  1150.  
  1151. /**
  1152.   * @brief  Stops the TIM Output Compare signal generation in DMA mode.
  1153.   * @param  htim TIM Output Compare handle
  1154.   * @param  Channel TIM Channel to be disabled
  1155.   *          This parameter can be one of the following values:
  1156.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1157.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1158.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1159.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1160.   * @retval HAL status
  1161.   */
  1162. HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
  1163. {
  1164.   /* Check the parameters */
  1165.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1166.  
  1167.   switch (Channel)
  1168.   {
  1169.     case TIM_CHANNEL_1:
  1170.     {
  1171.       /* Disable the TIM Capture/Compare 1 DMA request */
  1172.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
  1173.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
  1174.       break;
  1175.     }
  1176.  
  1177.     case TIM_CHANNEL_2:
  1178.     {
  1179.       /* Disable the TIM Capture/Compare 2 DMA request */
  1180.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
  1181.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
  1182.       break;
  1183.     }
  1184.  
  1185.     case TIM_CHANNEL_3:
  1186.     {
  1187.       /* Disable the TIM Capture/Compare 3 DMA request */
  1188.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
  1189.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
  1190.       break;
  1191.     }
  1192.  
  1193.     case TIM_CHANNEL_4:
  1194.     {
  1195.       /* Disable the TIM Capture/Compare 4 interrupt */
  1196.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
  1197.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
  1198.       break;
  1199.     }
  1200.  
  1201.     default:
  1202.       break;
  1203.   }
  1204.  
  1205.   /* Disable the Output compare channel */
  1206.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  1207.  
  1208.   /* Disable the Peripheral */
  1209.   __HAL_TIM_DISABLE(htim);
  1210.  
  1211.   /* Set the TIM channel state */
  1212.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  1213.  
  1214.   /* Return function status */
  1215.   return HAL_OK;
  1216. }
  1217.  
  1218. /**
  1219.   * @}
  1220.   */
  1221.  
  1222. /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
  1223.   *  @brief    TIM PWM functions
  1224.   *
  1225. @verbatim
  1226.   ==============================================================================
  1227.                           ##### TIM PWM functions #####
  1228.   ==============================================================================
  1229.   [..]
  1230.     This section provides functions allowing to:
  1231.     (+) Initialize and configure the TIM PWM.
  1232.     (+) De-initialize the TIM PWM.
  1233.     (+) Start the TIM PWM.
  1234.     (+) Stop the TIM PWM.
  1235.     (+) Start the TIM PWM and enable interrupt.
  1236.     (+) Stop the TIM PWM and disable interrupt.
  1237.     (+) Start the TIM PWM and enable DMA transfer.
  1238.     (+) Stop the TIM PWM and disable DMA transfer.
  1239.  
  1240. @endverbatim
  1241.   * @{
  1242.   */
  1243. /**
  1244.   * @brief  Initializes the TIM PWM Time Base according to the specified
  1245.   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
  1246.   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
  1247.   *         requires a timer reset to avoid unexpected direction
  1248.   *         due to DIR bit readonly in center aligned mode.
  1249.   *         Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
  1250.   * @param  htim TIM PWM handle
  1251.   * @retval HAL status
  1252.   */
  1253. HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
  1254. {
  1255.   /* Check the TIM handle allocation */
  1256.   if (htim == NULL)
  1257.   {
  1258.     return HAL_ERROR;
  1259.   }
  1260.  
  1261.   /* Check the parameters */
  1262.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  1263.   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  1264.   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  1265.   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
  1266.  
  1267.   if (htim->State == HAL_TIM_STATE_RESET)
  1268.   {
  1269.     /* Allocate lock resource and initialize it */
  1270.     htim->Lock = HAL_UNLOCKED;
  1271.  
  1272. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  1273.     /* Reset interrupt callbacks to legacy weak callbacks */
  1274.     TIM_ResetCallback(htim);
  1275.  
  1276.     if (htim->PWM_MspInitCallback == NULL)
  1277.     {
  1278.       htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
  1279.     }
  1280.     /* Init the low level hardware : GPIO, CLOCK, NVIC */
  1281.     htim->PWM_MspInitCallback(htim);
  1282. #else
  1283.     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
  1284.     HAL_TIM_PWM_MspInit(htim);
  1285. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  1286.   }
  1287.  
  1288.   /* Set the TIM state */
  1289.   htim->State = HAL_TIM_STATE_BUSY;
  1290.  
  1291.   /* Init the base time for the PWM */
  1292.   TIM_Base_SetConfig(htim->Instance, &htim->Init);
  1293.  
  1294.   /* Initialize the DMA burst operation state */
  1295.   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  1296.  
  1297.   /* Initialize the TIM channels state */
  1298.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  1299.  
  1300.   /* Initialize the TIM state*/
  1301.   htim->State = HAL_TIM_STATE_READY;
  1302.  
  1303.   return HAL_OK;
  1304. }
  1305.  
  1306. /**
  1307.   * @brief  DeInitializes the TIM peripheral
  1308.   * @param  htim TIM PWM handle
  1309.   * @retval HAL status
  1310.   */
  1311. HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
  1312. {
  1313.   /* Check the parameters */
  1314.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  1315.  
  1316.   htim->State = HAL_TIM_STATE_BUSY;
  1317.  
  1318.   /* Disable the TIM Peripheral Clock */
  1319.   __HAL_TIM_DISABLE(htim);
  1320.  
  1321. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  1322.   if (htim->PWM_MspDeInitCallback == NULL)
  1323.   {
  1324.     htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
  1325.   }
  1326.   /* DeInit the low level hardware */
  1327.   htim->PWM_MspDeInitCallback(htim);
  1328. #else
  1329.   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
  1330.   HAL_TIM_PWM_MspDeInit(htim);
  1331. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  1332.  
  1333.   /* Change the DMA burst operation state */
  1334.   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
  1335.  
  1336.   /* Change the TIM channels state */
  1337.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
  1338.  
  1339.   /* Change TIM state */
  1340.   htim->State = HAL_TIM_STATE_RESET;
  1341.  
  1342.   /* Release Lock */
  1343.   __HAL_UNLOCK(htim);
  1344.  
  1345.   return HAL_OK;
  1346. }
  1347.  
  1348. /**
  1349.   * @brief  Initializes the TIM PWM MSP.
  1350.   * @param  htim TIM PWM handle
  1351.   * @retval None
  1352.   */
  1353. __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
  1354. {
  1355.   /* Prevent unused argument(s) compilation warning */
  1356.   UNUSED(htim);
  1357.  
  1358.   /* NOTE : This function should not be modified, when the callback is needed,
  1359.             the HAL_TIM_PWM_MspInit could be implemented in the user file
  1360.    */
  1361. }
  1362.  
  1363. /**
  1364.   * @brief  DeInitializes TIM PWM MSP.
  1365.   * @param  htim TIM PWM handle
  1366.   * @retval None
  1367.   */
  1368. __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
  1369. {
  1370.   /* Prevent unused argument(s) compilation warning */
  1371.   UNUSED(htim);
  1372.  
  1373.   /* NOTE : This function should not be modified, when the callback is needed,
  1374.             the HAL_TIM_PWM_MspDeInit could be implemented in the user file
  1375.    */
  1376. }
  1377.  
  1378. /**
  1379.   * @brief  Starts the PWM signal generation.
  1380.   * @param  htim TIM handle
  1381.   * @param  Channel TIM Channels to be enabled
  1382.   *          This parameter can be one of the following values:
  1383.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1384.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1385.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1386.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1387.   * @retval HAL status
  1388.   */
  1389. HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
  1390. {
  1391.   uint32_t tmpsmcr;
  1392.  
  1393.   /* Check the parameters */
  1394.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1395.  
  1396.   /* Check the TIM channel state */
  1397.   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
  1398.   {
  1399.     return HAL_ERROR;
  1400.   }
  1401.  
  1402.   /* Set the TIM channel state */
  1403.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  1404.  
  1405.   /* Enable the Capture compare channel */
  1406.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  1407.  
  1408.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  1409.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  1410.   {
  1411.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  1412.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  1413.     {
  1414.       __HAL_TIM_ENABLE(htim);
  1415.     }
  1416.   }
  1417.   else
  1418.   {
  1419.     __HAL_TIM_ENABLE(htim);
  1420.   }
  1421.  
  1422.   /* Return function status */
  1423.   return HAL_OK;
  1424. }
  1425.  
  1426. /**
  1427.   * @brief  Stops the PWM signal generation.
  1428.   * @param  htim TIM PWM handle
  1429.   * @param  Channel TIM Channels to be disabled
  1430.   *          This parameter can be one of the following values:
  1431.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1432.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1433.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1434.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1435.   * @retval HAL status
  1436.   */
  1437. HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
  1438. {
  1439.   /* Check the parameters */
  1440.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1441.  
  1442.   /* Disable the Capture compare channel */
  1443.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  1444.  
  1445.   /* Disable the Peripheral */
  1446.   __HAL_TIM_DISABLE(htim);
  1447.  
  1448.   /* Set the TIM channel state */
  1449.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  1450.  
  1451.   /* Return function status */
  1452.   return HAL_OK;
  1453. }
  1454.  
  1455. /**
  1456.   * @brief  Starts the PWM signal generation in interrupt mode.
  1457.   * @param  htim TIM PWM handle
  1458.   * @param  Channel TIM Channel to be enabled
  1459.   *          This parameter can be one of the following values:
  1460.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1461.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1462.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1463.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1464.   * @retval HAL status
  1465.   */
  1466. HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  1467. {
  1468.   uint32_t tmpsmcr;
  1469.   /* Check the parameters */
  1470.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1471.  
  1472.   /* Check the TIM channel state */
  1473.   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
  1474.   {
  1475.     return HAL_ERROR;
  1476.   }
  1477.  
  1478.   /* Set the TIM channel state */
  1479.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  1480.  
  1481.   switch (Channel)
  1482.   {
  1483.     case TIM_CHANNEL_1:
  1484.     {
  1485.       /* Enable the TIM Capture/Compare 1 interrupt */
  1486.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
  1487.       break;
  1488.     }
  1489.  
  1490.     case TIM_CHANNEL_2:
  1491.     {
  1492.       /* Enable the TIM Capture/Compare 2 interrupt */
  1493.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
  1494.       break;
  1495.     }
  1496.  
  1497.     case TIM_CHANNEL_3:
  1498.     {
  1499.       /* Enable the TIM Capture/Compare 3 interrupt */
  1500.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
  1501.       break;
  1502.     }
  1503.  
  1504.     case TIM_CHANNEL_4:
  1505.     {
  1506.       /* Enable the TIM Capture/Compare 4 interrupt */
  1507.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
  1508.       break;
  1509.     }
  1510.  
  1511.     default:
  1512.       break;
  1513.   }
  1514.  
  1515.   /* Enable the Capture compare channel */
  1516.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  1517.  
  1518.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  1519.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  1520.   {
  1521.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  1522.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  1523.     {
  1524.       __HAL_TIM_ENABLE(htim);
  1525.     }
  1526.   }
  1527.   else
  1528.   {
  1529.     __HAL_TIM_ENABLE(htim);
  1530.   }
  1531.  
  1532.   /* Return function status */
  1533.   return HAL_OK;
  1534. }
  1535.  
  1536. /**
  1537.   * @brief  Stops the PWM signal generation in interrupt mode.
  1538.   * @param  htim TIM PWM handle
  1539.   * @param  Channel TIM Channels to be disabled
  1540.   *          This parameter can be one of the following values:
  1541.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1542.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1543.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1544.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1545.   * @retval HAL status
  1546.   */
  1547. HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  1548. {
  1549.   /* Check the parameters */
  1550.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1551.  
  1552.   switch (Channel)
  1553.   {
  1554.     case TIM_CHANNEL_1:
  1555.     {
  1556.       /* Disable the TIM Capture/Compare 1 interrupt */
  1557.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
  1558.       break;
  1559.     }
  1560.  
  1561.     case TIM_CHANNEL_2:
  1562.     {
  1563.       /* Disable the TIM Capture/Compare 2 interrupt */
  1564.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
  1565.       break;
  1566.     }
  1567.  
  1568.     case TIM_CHANNEL_3:
  1569.     {
  1570.       /* Disable the TIM Capture/Compare 3 interrupt */
  1571.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
  1572.       break;
  1573.     }
  1574.  
  1575.     case TIM_CHANNEL_4:
  1576.     {
  1577.       /* Disable the TIM Capture/Compare 4 interrupt */
  1578.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
  1579.       break;
  1580.     }
  1581.  
  1582.     default:
  1583.       break;
  1584.   }
  1585.  
  1586.   /* Disable the Capture compare channel */
  1587.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  1588.  
  1589.   /* Disable the Peripheral */
  1590.   __HAL_TIM_DISABLE(htim);
  1591.  
  1592.   /* Set the TIM channel state */
  1593.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  1594.  
  1595.   /* Return function status */
  1596.   return HAL_OK;
  1597. }
  1598.  
  1599. /**
  1600.   * @brief  Starts the TIM PWM signal generation in DMA mode.
  1601.   * @param  htim TIM PWM handle
  1602.   * @param  Channel TIM Channels to be enabled
  1603.   *          This parameter can be one of the following values:
  1604.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1605.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1606.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1607.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1608.   * @param  pData The source Buffer address.
  1609.   * @param  Length The length of data to be transferred from memory to TIM peripheral
  1610.   * @retval HAL status
  1611.   */
  1612. HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
  1613. {
  1614.   uint32_t tmpsmcr;
  1615.  
  1616.   /* Check the parameters */
  1617.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1618.  
  1619.   /* Set the TIM channel state */
  1620.   if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
  1621.   {
  1622.     return HAL_BUSY;
  1623.   }
  1624.   else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
  1625.   {
  1626.     if ((pData == NULL) && (Length > 0U))
  1627.     {
  1628.       return HAL_ERROR;
  1629.     }
  1630.     else
  1631.     {
  1632.       TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  1633.     }
  1634.   }
  1635.   else
  1636.   {
  1637.     return HAL_ERROR;
  1638.   }
  1639.  
  1640.   switch (Channel)
  1641.   {
  1642.     case TIM_CHANNEL_1:
  1643.     {
  1644.       /* Set the DMA compare callbacks */
  1645.       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1646.       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1647.  
  1648.       /* Set the DMA error callback */
  1649.       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
  1650.  
  1651.       /* Enable the DMA channel */
  1652.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
  1653.                          Length) != HAL_OK)
  1654.       {
  1655.         /* Return error status */
  1656.         return HAL_ERROR;
  1657.       }
  1658.  
  1659.       /* Enable the TIM Capture/Compare 1 DMA request */
  1660.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
  1661.       break;
  1662.     }
  1663.  
  1664.     case TIM_CHANNEL_2:
  1665.     {
  1666.       /* Set the DMA compare callbacks */
  1667.       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1668.       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1669.  
  1670.       /* Set the DMA error callback */
  1671.       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
  1672.  
  1673.       /* Enable the DMA channel */
  1674.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
  1675.                          Length) != HAL_OK)
  1676.       {
  1677.         /* Return error status */
  1678.         return HAL_ERROR;
  1679.       }
  1680.       /* Enable the TIM Capture/Compare 2 DMA request */
  1681.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
  1682.       break;
  1683.     }
  1684.  
  1685.     case TIM_CHANNEL_3:
  1686.     {
  1687.       /* Set the DMA compare callbacks */
  1688.       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1689.       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1690.  
  1691.       /* Set the DMA error callback */
  1692.       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
  1693.  
  1694.       /* Enable the DMA channel */
  1695.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
  1696.                          Length) != HAL_OK)
  1697.       {
  1698.         /* Return error status */
  1699.         return HAL_ERROR;
  1700.       }
  1701.       /* Enable the TIM Output Capture/Compare 3 request */
  1702.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
  1703.       break;
  1704.     }
  1705.  
  1706.     case TIM_CHANNEL_4:
  1707.     {
  1708.       /* Set the DMA compare callbacks */
  1709.       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
  1710.       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  1711.  
  1712.       /* Set the DMA error callback */
  1713.       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
  1714.  
  1715.       /* Enable the DMA channel */
  1716.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
  1717.                          Length) != HAL_OK)
  1718.       {
  1719.         /* Return error status */
  1720.         return HAL_ERROR;
  1721.       }
  1722.       /* Enable the TIM Capture/Compare 4 DMA request */
  1723.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
  1724.       break;
  1725.     }
  1726.  
  1727.     default:
  1728.       break;
  1729.   }
  1730.  
  1731.   /* Enable the Capture compare channel */
  1732.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  1733.  
  1734.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  1735.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  1736.   {
  1737.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  1738.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  1739.     {
  1740.       __HAL_TIM_ENABLE(htim);
  1741.     }
  1742.   }
  1743.   else
  1744.   {
  1745.     __HAL_TIM_ENABLE(htim);
  1746.   }
  1747.  
  1748.   /* Return function status */
  1749.   return HAL_OK;
  1750. }
  1751.  
  1752. /**
  1753.   * @brief  Stops the TIM PWM signal generation in DMA mode.
  1754.   * @param  htim TIM PWM handle
  1755.   * @param  Channel TIM Channels to be disabled
  1756.   *          This parameter can be one of the following values:
  1757.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1758.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1759.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1760.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1761.   * @retval HAL status
  1762.   */
  1763. HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
  1764. {
  1765.   /* Check the parameters */
  1766.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1767.  
  1768.   switch (Channel)
  1769.   {
  1770.     case TIM_CHANNEL_1:
  1771.     {
  1772.       /* Disable the TIM Capture/Compare 1 DMA request */
  1773.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
  1774.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
  1775.       break;
  1776.     }
  1777.  
  1778.     case TIM_CHANNEL_2:
  1779.     {
  1780.       /* Disable the TIM Capture/Compare 2 DMA request */
  1781.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
  1782.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
  1783.       break;
  1784.     }
  1785.  
  1786.     case TIM_CHANNEL_3:
  1787.     {
  1788.       /* Disable the TIM Capture/Compare 3 DMA request */
  1789.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
  1790.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
  1791.       break;
  1792.     }
  1793.  
  1794.     case TIM_CHANNEL_4:
  1795.     {
  1796.       /* Disable the TIM Capture/Compare 4 interrupt */
  1797.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
  1798.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
  1799.       break;
  1800.     }
  1801.  
  1802.     default:
  1803.       break;
  1804.   }
  1805.  
  1806.   /* Disable the Capture compare channel */
  1807.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  1808.  
  1809.   /* Disable the Peripheral */
  1810.   __HAL_TIM_DISABLE(htim);
  1811.  
  1812.   /* Set the TIM channel state */
  1813.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  1814.  
  1815.   /* Return function status */
  1816.   return HAL_OK;
  1817. }
  1818.  
  1819. /**
  1820.   * @}
  1821.   */
  1822.  
  1823. /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
  1824.   *  @brief    TIM Input Capture functions
  1825.   *
  1826. @verbatim
  1827.   ==============================================================================
  1828.               ##### TIM Input Capture functions #####
  1829.   ==============================================================================
  1830.  [..]
  1831.    This section provides functions allowing to:
  1832.    (+) Initialize and configure the TIM Input Capture.
  1833.    (+) De-initialize the TIM Input Capture.
  1834.    (+) Start the TIM Input Capture.
  1835.    (+) Stop the TIM Input Capture.
  1836.    (+) Start the TIM Input Capture and enable interrupt.
  1837.    (+) Stop the TIM Input Capture and disable interrupt.
  1838.    (+) Start the TIM Input Capture and enable DMA transfer.
  1839.    (+) Stop the TIM Input Capture and disable DMA transfer.
  1840.  
  1841. @endverbatim
  1842.   * @{
  1843.   */
  1844. /**
  1845.   * @brief  Initializes the TIM Input Capture Time base according to the specified
  1846.   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
  1847.   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
  1848.   *         requires a timer reset to avoid unexpected direction
  1849.   *         due to DIR bit readonly in center aligned mode.
  1850.   *         Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
  1851.   * @param  htim TIM Input Capture handle
  1852.   * @retval HAL status
  1853.   */
  1854. HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
  1855. {
  1856.   /* Check the TIM handle allocation */
  1857.   if (htim == NULL)
  1858.   {
  1859.     return HAL_ERROR;
  1860.   }
  1861.  
  1862.   /* Check the parameters */
  1863.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  1864.   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  1865.   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  1866.   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
  1867.  
  1868.   if (htim->State == HAL_TIM_STATE_RESET)
  1869.   {
  1870.     /* Allocate lock resource and initialize it */
  1871.     htim->Lock = HAL_UNLOCKED;
  1872.  
  1873. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  1874.     /* Reset interrupt callbacks to legacy weak callbacks */
  1875.     TIM_ResetCallback(htim);
  1876.  
  1877.     if (htim->IC_MspInitCallback == NULL)
  1878.     {
  1879.       htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
  1880.     }
  1881.     /* Init the low level hardware : GPIO, CLOCK, NVIC */
  1882.     htim->IC_MspInitCallback(htim);
  1883. #else
  1884.     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
  1885.     HAL_TIM_IC_MspInit(htim);
  1886. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  1887.   }
  1888.  
  1889.   /* Set the TIM state */
  1890.   htim->State = HAL_TIM_STATE_BUSY;
  1891.  
  1892.   /* Init the base time for the input capture */
  1893.   TIM_Base_SetConfig(htim->Instance, &htim->Init);
  1894.  
  1895.   /* Initialize the DMA burst operation state */
  1896.   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  1897.  
  1898.   /* Initialize the TIM channels state */
  1899.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
  1900.  
  1901.   /* Initialize the TIM state*/
  1902.   htim->State = HAL_TIM_STATE_READY;
  1903.  
  1904.   return HAL_OK;
  1905. }
  1906.  
  1907. /**
  1908.   * @brief  DeInitializes the TIM peripheral
  1909.   * @param  htim TIM Input Capture handle
  1910.   * @retval HAL status
  1911.   */
  1912. HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
  1913. {
  1914.   /* Check the parameters */
  1915.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  1916.  
  1917.   htim->State = HAL_TIM_STATE_BUSY;
  1918.  
  1919.   /* Disable the TIM Peripheral Clock */
  1920.   __HAL_TIM_DISABLE(htim);
  1921.  
  1922. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  1923.   if (htim->IC_MspDeInitCallback == NULL)
  1924.   {
  1925.     htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
  1926.   }
  1927.   /* DeInit the low level hardware */
  1928.   htim->IC_MspDeInitCallback(htim);
  1929. #else
  1930.   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
  1931.   HAL_TIM_IC_MspDeInit(htim);
  1932. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  1933.  
  1934.   /* Change the DMA burst operation state */
  1935.   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
  1936.  
  1937.   /* Change the TIM channels state */
  1938.   TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
  1939.  
  1940.   /* Change TIM state */
  1941.   htim->State = HAL_TIM_STATE_RESET;
  1942.  
  1943.   /* Release Lock */
  1944.   __HAL_UNLOCK(htim);
  1945.  
  1946.   return HAL_OK;
  1947. }
  1948.  
  1949. /**
  1950.   * @brief  Initializes the TIM Input Capture MSP.
  1951.   * @param  htim TIM Input Capture handle
  1952.   * @retval None
  1953.   */
  1954. __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
  1955. {
  1956.   /* Prevent unused argument(s) compilation warning */
  1957.   UNUSED(htim);
  1958.  
  1959.   /* NOTE : This function should not be modified, when the callback is needed,
  1960.             the HAL_TIM_IC_MspInit could be implemented in the user file
  1961.    */
  1962. }
  1963.  
  1964. /**
  1965.   * @brief  DeInitializes TIM Input Capture MSP.
  1966.   * @param  htim TIM handle
  1967.   * @retval None
  1968.   */
  1969. __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
  1970. {
  1971.   /* Prevent unused argument(s) compilation warning */
  1972.   UNUSED(htim);
  1973.  
  1974.   /* NOTE : This function should not be modified, when the callback is needed,
  1975.             the HAL_TIM_IC_MspDeInit could be implemented in the user file
  1976.    */
  1977. }
  1978.  
  1979. /**
  1980.   * @brief  Starts the TIM Input Capture measurement.
  1981.   * @param  htim TIM Input Capture handle
  1982.   * @param  Channel TIM Channels to be enabled
  1983.   *          This parameter can be one of the following values:
  1984.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1985.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1986.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1987.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1988.   * @retval HAL status
  1989.   */
  1990. HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
  1991. {
  1992.   uint32_t tmpsmcr;
  1993.   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
  1994.  
  1995.   /* Check the parameters */
  1996.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  1997.  
  1998.   /* Check the TIM channel state */
  1999.   if (channel_state != HAL_TIM_CHANNEL_STATE_READY)
  2000.   {
  2001.     return HAL_ERROR;
  2002.   }
  2003.  
  2004.   /* Set the TIM channel state */
  2005.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  2006.  
  2007.   /* Enable the Input Capture channel */
  2008.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  2009.  
  2010.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  2011.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  2012.   {
  2013.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  2014.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  2015.     {
  2016.       __HAL_TIM_ENABLE(htim);
  2017.     }
  2018.   }
  2019.   else
  2020.   {
  2021.     __HAL_TIM_ENABLE(htim);
  2022.   }
  2023.  
  2024.   /* Return function status */
  2025.   return HAL_OK;
  2026. }
  2027.  
  2028. /**
  2029.   * @brief  Stops the TIM Input Capture measurement.
  2030.   * @param  htim TIM Input Capture handle
  2031.   * @param  Channel TIM Channels to be disabled
  2032.   *          This parameter can be one of the following values:
  2033.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  2034.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  2035.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  2036.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  2037.   * @retval HAL status
  2038.   */
  2039. HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
  2040. {
  2041.   /* Check the parameters */
  2042.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  2043.  
  2044.   /* Disable the Input Capture channel */
  2045.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  2046.  
  2047.   /* Disable the Peripheral */
  2048.   __HAL_TIM_DISABLE(htim);
  2049.  
  2050.   /* Set the TIM channel state */
  2051.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  2052.  
  2053.   /* Return function status */
  2054.   return HAL_OK;
  2055. }
  2056.  
  2057. /**
  2058.   * @brief  Starts the TIM Input Capture measurement in interrupt mode.
  2059.   * @param  htim TIM Input Capture handle
  2060.   * @param  Channel TIM Channels to be enabled
  2061.   *          This parameter can be one of the following values:
  2062.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  2063.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  2064.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  2065.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  2066.   * @retval HAL status
  2067.   */
  2068. HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  2069. {
  2070.   uint32_t tmpsmcr;
  2071.   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
  2072.  
  2073.   /* Check the parameters */
  2074.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  2075.  
  2076.   /* Check the TIM channel state */
  2077.   if (channel_state != HAL_TIM_CHANNEL_STATE_READY)
  2078.   {
  2079.     return HAL_ERROR;
  2080.   }
  2081.  
  2082.   /* Set the TIM channel state */
  2083.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  2084.  
  2085.   switch (Channel)
  2086.   {
  2087.     case TIM_CHANNEL_1:
  2088.     {
  2089.       /* Enable the TIM Capture/Compare 1 interrupt */
  2090.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
  2091.       break;
  2092.     }
  2093.  
  2094.     case TIM_CHANNEL_2:
  2095.     {
  2096.       /* Enable the TIM Capture/Compare 2 interrupt */
  2097.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
  2098.       break;
  2099.     }
  2100.  
  2101.     case TIM_CHANNEL_3:
  2102.     {
  2103.       /* Enable the TIM Capture/Compare 3 interrupt */
  2104.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
  2105.       break;
  2106.     }
  2107.  
  2108.     case TIM_CHANNEL_4:
  2109.     {
  2110.       /* Enable the TIM Capture/Compare 4 interrupt */
  2111.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
  2112.       break;
  2113.     }
  2114.  
  2115.     default:
  2116.       break;
  2117.   }
  2118.   /* Enable the Input Capture channel */
  2119.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  2120.  
  2121.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  2122.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  2123.   {
  2124.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  2125.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  2126.     {
  2127.       __HAL_TIM_ENABLE(htim);
  2128.     }
  2129.   }
  2130.   else
  2131.   {
  2132.     __HAL_TIM_ENABLE(htim);
  2133.   }
  2134.  
  2135.   /* Return function status */
  2136.   return HAL_OK;
  2137. }
  2138.  
  2139. /**
  2140.   * @brief  Stops the TIM Input Capture measurement in interrupt mode.
  2141.   * @param  htim TIM Input Capture handle
  2142.   * @param  Channel TIM Channels to be disabled
  2143.   *          This parameter can be one of the following values:
  2144.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  2145.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  2146.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  2147.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  2148.   * @retval HAL status
  2149.   */
  2150. HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  2151. {
  2152.   /* Check the parameters */
  2153.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  2154.  
  2155.   switch (Channel)
  2156.   {
  2157.     case TIM_CHANNEL_1:
  2158.     {
  2159.       /* Disable the TIM Capture/Compare 1 interrupt */
  2160.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
  2161.       break;
  2162.     }
  2163.  
  2164.     case TIM_CHANNEL_2:
  2165.     {
  2166.       /* Disable the TIM Capture/Compare 2 interrupt */
  2167.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
  2168.       break;
  2169.     }
  2170.  
  2171.     case TIM_CHANNEL_3:
  2172.     {
  2173.       /* Disable the TIM Capture/Compare 3 interrupt */
  2174.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
  2175.       break;
  2176.     }
  2177.  
  2178.     case TIM_CHANNEL_4:
  2179.     {
  2180.       /* Disable the TIM Capture/Compare 4 interrupt */
  2181.       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
  2182.       break;
  2183.     }
  2184.  
  2185.     default:
  2186.       break;
  2187.   }
  2188.  
  2189.   /* Disable the Input Capture channel */
  2190.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  2191.  
  2192.   /* Disable the Peripheral */
  2193.   __HAL_TIM_DISABLE(htim);
  2194.  
  2195.   /* Set the TIM channel state */
  2196.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  2197.  
  2198.   /* Return function status */
  2199.   return HAL_OK;
  2200. }
  2201.  
  2202. /**
  2203.   * @brief  Starts the TIM Input Capture measurement in DMA mode.
  2204.   * @param  htim TIM Input Capture handle
  2205.   * @param  Channel TIM Channels to be enabled
  2206.   *          This parameter can be one of the following values:
  2207.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  2208.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  2209.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  2210.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  2211.   * @param  pData The destination Buffer address.
  2212.   * @param  Length The length of data to be transferred from TIM peripheral to memory.
  2213.   * @retval HAL status
  2214.   */
  2215. HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
  2216. {
  2217.   uint32_t tmpsmcr;
  2218.   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
  2219.  
  2220.   /* Check the parameters */
  2221.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  2222.   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
  2223.  
  2224.   /* Set the TIM channel state */
  2225.   if (channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
  2226.   {
  2227.     return HAL_BUSY;
  2228.   }
  2229.   if (channel_state == HAL_TIM_CHANNEL_STATE_READY)
  2230.   {
  2231.     if ((pData == NULL) && (Length > 0U))
  2232.     {
  2233.       return HAL_ERROR;
  2234.     }
  2235.     else
  2236.     {
  2237.       TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
  2238.     }
  2239.   }
  2240.   else
  2241.   {
  2242.     return HAL_ERROR;
  2243.   }
  2244.  
  2245.   /* Enable the Input Capture channel */
  2246.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
  2247.  
  2248.   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  2249.   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
  2250.   {
  2251.     tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
  2252.     if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
  2253.     {
  2254.       __HAL_TIM_ENABLE(htim);
  2255.     }
  2256.   }
  2257.   else
  2258.   {
  2259.     __HAL_TIM_ENABLE(htim);
  2260.   }
  2261.  
  2262.   switch (Channel)
  2263.   {
  2264.     case TIM_CHANNEL_1:
  2265.     {
  2266.       /* Set the DMA capture callbacks */
  2267.       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
  2268.       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  2269.  
  2270.       /* Set the DMA error callback */
  2271.       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
  2272.  
  2273.       /* Enable the DMA channel */
  2274.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
  2275.                          Length) != HAL_OK)
  2276.       {
  2277.         /* Return error status */
  2278.         return HAL_ERROR;
  2279.       }
  2280.       /* Enable the TIM Capture/Compare 1 DMA request */
  2281.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
  2282.       break;
  2283.     }
  2284.  
  2285.     case TIM_CHANNEL_2:
  2286.     {
  2287.       /* Set the DMA capture callbacks */
  2288.       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
  2289.       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  2290.  
  2291.       /* Set the DMA error callback */
  2292.       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
  2293.  
  2294.       /* Enable the DMA channel */
  2295.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
  2296.                          Length) != HAL_OK)
  2297.       {
  2298.         /* Return error status */
  2299.         return HAL_ERROR;
  2300.       }
  2301.       /* Enable the TIM Capture/Compare 2  DMA request */
  2302.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
  2303.       break;
  2304.     }
  2305.  
  2306.     case TIM_CHANNEL_3:
  2307.     {
  2308.       /* Set the DMA capture callbacks */
  2309.       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
  2310.       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  2311.  
  2312.       /* Set the DMA error callback */
  2313.       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
  2314.  
  2315.       /* Enable the DMA channel */
  2316.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
  2317.                          Length) != HAL_OK)
  2318.       {
  2319.         /* Return error status */
  2320.         return HAL_ERROR;
  2321.       }
  2322.       /* Enable the TIM Capture/Compare 3  DMA request */
  2323.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
  2324.       break;
  2325.     }
  2326.  
  2327.     case TIM_CHANNEL_4:
  2328.     {
  2329.       /* Set the DMA capture callbacks */
  2330.       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
  2331.       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  2332.  
  2333.       /* Set the DMA error callback */
  2334.       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
  2335.  
  2336.       /* Enable the DMA channel */
  2337.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
  2338.                          Length) != HAL_OK)
  2339.       {
  2340.         /* Return error status */
  2341.         return HAL_ERROR;
  2342.       }
  2343.       /* Enable the TIM Capture/Compare 4  DMA request */
  2344.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
  2345.       break;
  2346.     }
  2347.  
  2348.     default:
  2349.       break;
  2350.   }
  2351.  
  2352.   /* Return function status */
  2353.   return HAL_OK;
  2354. }
  2355.  
  2356. /**
  2357.   * @brief  Stops the TIM Input Capture measurement in DMA mode.
  2358.   * @param  htim TIM Input Capture handle
  2359.   * @param  Channel TIM Channels to be disabled
  2360.   *          This parameter can be one of the following values:
  2361.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  2362.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  2363.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  2364.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  2365.   * @retval HAL status
  2366.   */
  2367. HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
  2368. {
  2369.   /* Check the parameters */
  2370.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  2371.   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
  2372.  
  2373.   /* Disable the Input Capture channel */
  2374.   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
  2375.  
  2376.   switch (Channel)
  2377.   {
  2378.     case TIM_CHANNEL_1:
  2379.     {
  2380.       /* Disable the TIM Capture/Compare 1 DMA request */
  2381.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
  2382.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
  2383.       break;
  2384.     }
  2385.  
  2386.     case TIM_CHANNEL_2:
  2387.     {
  2388.       /* Disable the TIM Capture/Compare 2 DMA request */
  2389.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
  2390.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
  2391.       break;
  2392.     }
  2393.  
  2394.     case TIM_CHANNEL_3:
  2395.     {
  2396.       /* Disable the TIM Capture/Compare 3  DMA request */
  2397.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
  2398.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
  2399.       break;
  2400.     }
  2401.  
  2402.     case TIM_CHANNEL_4:
  2403.     {
  2404.       /* Disable the TIM Capture/Compare 4  DMA request */
  2405.       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
  2406.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
  2407.       break;
  2408.     }
  2409.  
  2410.     default:
  2411.       break;
  2412.   }
  2413.  
  2414.   /* Disable the Peripheral */
  2415.   __HAL_TIM_DISABLE(htim);
  2416.  
  2417.   /* Set the TIM channel state */
  2418.   TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  2419.  
  2420.   /* Return function status */
  2421.   return HAL_OK;
  2422. }
  2423. /**
  2424.   * @}
  2425.   */
  2426.  
  2427. /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
  2428.   *  @brief    TIM One Pulse functions
  2429.   *
  2430. @verbatim
  2431.   ==============================================================================
  2432.                         ##### TIM One Pulse functions #####
  2433.   ==============================================================================
  2434.   [..]
  2435.     This section provides functions allowing to:
  2436.     (+) Initialize and configure the TIM One Pulse.
  2437.     (+) De-initialize the TIM One Pulse.
  2438.     (+) Start the TIM One Pulse.
  2439.     (+) Stop the TIM One Pulse.
  2440.     (+) Start the TIM One Pulse and enable interrupt.
  2441.     (+) Stop the TIM One Pulse and disable interrupt.
  2442.     (+) Start the TIM One Pulse and enable DMA transfer.
  2443.     (+) Stop the TIM One Pulse and disable DMA transfer.
  2444.  
  2445. @endverbatim
  2446.   * @{
  2447.   */
  2448. /**
  2449.   * @brief  Initializes the TIM One Pulse Time Base according to the specified
  2450.   *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
  2451.   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
  2452.   *         requires a timer reset to avoid unexpected direction
  2453.   *         due to DIR bit readonly in center aligned mode.
  2454.   *         Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
  2455.   * @note   When the timer instance is initialized in One Pulse mode, timer
  2456.   *         channels 1 and channel 2 are reserved and cannot be used for other
  2457.   *         purpose.
  2458.   * @param  htim TIM One Pulse handle
  2459.   * @param  OnePulseMode Select the One pulse mode.
  2460.   *         This parameter can be one of the following values:
  2461.   *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
  2462.   *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
  2463.   * @retval HAL status
  2464.   */
  2465. HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
  2466. {
  2467.   /* Check the TIM handle allocation */
  2468.   if (htim == NULL)
  2469.   {
  2470.     return HAL_ERROR;
  2471.   }
  2472.  
  2473.   /* Check the parameters */
  2474.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  2475.   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  2476.   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  2477.   assert_param(IS_TIM_OPM_MODE(OnePulseMode));
  2478.   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
  2479.  
  2480.   if (htim->State == HAL_TIM_STATE_RESET)
  2481.   {
  2482.     /* Allocate lock resource and initialize it */
  2483.     htim->Lock = HAL_UNLOCKED;
  2484.  
  2485. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  2486.     /* Reset interrupt callbacks to legacy weak callbacks */
  2487.     TIM_ResetCallback(htim);
  2488.  
  2489.     if (htim->OnePulse_MspInitCallback == NULL)
  2490.     {
  2491.       htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
  2492.     }
  2493.     /* Init the low level hardware : GPIO, CLOCK, NVIC */
  2494.     htim->OnePulse_MspInitCallback(htim);
  2495. #else
  2496.     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
  2497.     HAL_TIM_OnePulse_MspInit(htim);
  2498. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  2499.   }
  2500.  
  2501.   /* Set the TIM state */
  2502.   htim->State = HAL_TIM_STATE_BUSY;
  2503.  
  2504.   /* Configure the Time base in the One Pulse Mode */
  2505.   TIM_Base_SetConfig(htim->Instance, &htim->Init);
  2506.  
  2507.   /* Reset the OPM Bit */
  2508.   htim->Instance->CR1 &= ~TIM_CR1_OPM;
  2509.  
  2510.   /* Configure the OPM Mode */
  2511.   htim->Instance->CR1 |= OnePulseMode;
  2512.  
  2513.   /* Initialize the DMA burst operation state */
  2514.   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  2515.  
  2516.   /* Initialize the TIM channels state */
  2517.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  2518.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  2519.  
  2520.   /* Initialize the TIM state*/
  2521.   htim->State = HAL_TIM_STATE_READY;
  2522.  
  2523.   return HAL_OK;
  2524. }
  2525.  
  2526. /**
  2527.   * @brief  DeInitializes the TIM One Pulse
  2528.   * @param  htim TIM One Pulse handle
  2529.   * @retval HAL status
  2530.   */
  2531. HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
  2532. {
  2533.   /* Check the parameters */
  2534.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  2535.  
  2536.   htim->State = HAL_TIM_STATE_BUSY;
  2537.  
  2538.   /* Disable the TIM Peripheral Clock */
  2539.   __HAL_TIM_DISABLE(htim);
  2540.  
  2541. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  2542.   if (htim->OnePulse_MspDeInitCallback == NULL)
  2543.   {
  2544.     htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
  2545.   }
  2546.   /* DeInit the low level hardware */
  2547.   htim->OnePulse_MspDeInitCallback(htim);
  2548. #else
  2549.   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
  2550.   HAL_TIM_OnePulse_MspDeInit(htim);
  2551. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  2552.  
  2553.   /* Change the DMA burst operation state */
  2554.   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
  2555.  
  2556.   /* Set the TIM channel state */
  2557.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
  2558.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
  2559.  
  2560.   /* Change TIM state */
  2561.   htim->State = HAL_TIM_STATE_RESET;
  2562.  
  2563.   /* Release Lock */
  2564.   __HAL_UNLOCK(htim);
  2565.  
  2566.   return HAL_OK;
  2567. }
  2568.  
  2569. /**
  2570.   * @brief  Initializes the TIM One Pulse MSP.
  2571.   * @param  htim TIM One Pulse handle
  2572.   * @retval None
  2573.   */
  2574. __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
  2575. {
  2576.   /* Prevent unused argument(s) compilation warning */
  2577.   UNUSED(htim);
  2578.  
  2579.   /* NOTE : This function should not be modified, when the callback is needed,
  2580.             the HAL_TIM_OnePulse_MspInit could be implemented in the user file
  2581.    */
  2582. }
  2583.  
  2584. /**
  2585.   * @brief  DeInitializes TIM One Pulse MSP.
  2586.   * @param  htim TIM One Pulse handle
  2587.   * @retval None
  2588.   */
  2589. __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
  2590. {
  2591.   /* Prevent unused argument(s) compilation warning */
  2592.   UNUSED(htim);
  2593.  
  2594.   /* NOTE : This function should not be modified, when the callback is needed,
  2595.             the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
  2596.    */
  2597. }
  2598.  
  2599. /**
  2600.   * @brief  Starts the TIM One Pulse signal generation.
  2601.   * @note Though OutputChannel parameter is deprecated and ignored by the function
  2602.   *        it has been kept to avoid HAL_TIM API compatibility break.
  2603.   * @note The pulse output channel is determined when calling
  2604.   *       @ref HAL_TIM_OnePulse_ConfigChannel().
  2605.   * @param  htim TIM One Pulse handle
  2606.   * @param  OutputChannel See note above
  2607.   * @retval HAL status
  2608.   */
  2609. HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
  2610. {
  2611.   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
  2612.   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
  2613.  
  2614.   /* Prevent unused argument(s) compilation warning */
  2615.   UNUSED(OutputChannel);
  2616.  
  2617.   /* Check the TIM channels state */
  2618.   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  2619.       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
  2620.   {
  2621.     return HAL_ERROR;
  2622.   }
  2623.  
  2624.   /* Set the TIM channels state */
  2625.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  2626.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  2627.  
  2628.   /* Enable the Capture compare and the Input Capture channels
  2629.     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
  2630.     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
  2631.     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
  2632.     whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
  2633.  
  2634.     No need to enable the counter, it's enabled automatically by hardware
  2635.     (the counter starts in response to a stimulus and generate a pulse */
  2636.  
  2637.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  2638.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  2639.  
  2640.   /* Return function status */
  2641.   return HAL_OK;
  2642. }
  2643.  
  2644. /**
  2645.   * @brief  Stops the TIM One Pulse signal generation.
  2646.   * @note Though OutputChannel parameter is deprecated and ignored by the function
  2647.   *        it has been kept to avoid HAL_TIM API compatibility break.
  2648.   * @note The pulse output channel is determined when calling
  2649.   *       @ref HAL_TIM_OnePulse_ConfigChannel().
  2650.   * @param  htim TIM One Pulse handle
  2651.   * @param  OutputChannel See note above
  2652.   * @retval HAL status
  2653.   */
  2654. HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
  2655. {
  2656.   /* Prevent unused argument(s) compilation warning */
  2657.   UNUSED(OutputChannel);
  2658.  
  2659.   /* Disable the Capture compare and the Input Capture channels
  2660.   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
  2661.   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
  2662.   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
  2663.   whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
  2664.  
  2665.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  2666.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  2667.  
  2668.   /* Disable the Peripheral */
  2669.   __HAL_TIM_DISABLE(htim);
  2670.  
  2671.   /* Set the TIM channels state */
  2672.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  2673.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  2674.  
  2675.   /* Return function status */
  2676.   return HAL_OK;
  2677. }
  2678.  
  2679. /**
  2680.   * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
  2681.   * @note Though OutputChannel parameter is deprecated and ignored by the function
  2682.   *        it has been kept to avoid HAL_TIM API compatibility break.
  2683.   * @note The pulse output channel is determined when calling
  2684.   *       @ref HAL_TIM_OnePulse_ConfigChannel().
  2685.   * @param  htim TIM One Pulse handle
  2686.   * @param  OutputChannel See note above
  2687.   * @retval HAL status
  2688.   */
  2689. HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
  2690. {
  2691.   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
  2692.   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
  2693.  
  2694.   /* Prevent unused argument(s) compilation warning */
  2695.   UNUSED(OutputChannel);
  2696.  
  2697.   /* Check the TIM channels state */
  2698.   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  2699.       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
  2700.   {
  2701.     return HAL_ERROR;
  2702.   }
  2703.  
  2704.   /* Set the TIM channels state */
  2705.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  2706.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  2707.  
  2708.   /* Enable the Capture compare and the Input Capture channels
  2709.     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
  2710.     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
  2711.     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
  2712.     whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
  2713.  
  2714.     No need to enable the counter, it's enabled automatically by hardware
  2715.     (the counter starts in response to a stimulus and generate a pulse */
  2716.  
  2717.   /* Enable the TIM Capture/Compare 1 interrupt */
  2718.   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
  2719.  
  2720.   /* Enable the TIM Capture/Compare 2 interrupt */
  2721.   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
  2722.  
  2723.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  2724.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  2725.  
  2726.   /* Return function status */
  2727.   return HAL_OK;
  2728. }
  2729.  
  2730. /**
  2731.   * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
  2732.   * @note Though OutputChannel parameter is deprecated and ignored by the function
  2733.   *        it has been kept to avoid HAL_TIM API compatibility break.
  2734.   * @note The pulse output channel is determined when calling
  2735.   *       @ref HAL_TIM_OnePulse_ConfigChannel().
  2736.   * @param  htim TIM One Pulse handle
  2737.   * @param  OutputChannel See note above
  2738.   * @retval HAL status
  2739.   */
  2740. HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
  2741. {
  2742.   /* Prevent unused argument(s) compilation warning */
  2743.   UNUSED(OutputChannel);
  2744.  
  2745.   /* Disable the TIM Capture/Compare 1 interrupt */
  2746.   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
  2747.  
  2748.   /* Disable the TIM Capture/Compare 2 interrupt */
  2749.   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
  2750.  
  2751.   /* Disable the Capture compare and the Input Capture channels
  2752.   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
  2753.   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
  2754.   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
  2755.   whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
  2756.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  2757.   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  2758.  
  2759.   /* Disable the Peripheral */
  2760.   __HAL_TIM_DISABLE(htim);
  2761.  
  2762.   /* Set the TIM channels state */
  2763.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  2764.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  2765.  
  2766.   /* Return function status */
  2767.   return HAL_OK;
  2768. }
  2769.  
  2770. /**
  2771.   * @}
  2772.   */
  2773.  
  2774. /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
  2775.   *  @brief    TIM Encoder functions
  2776.   *
  2777. @verbatim
  2778.   ==============================================================================
  2779.                           ##### TIM Encoder functions #####
  2780.   ==============================================================================
  2781.   [..]
  2782.     This section provides functions allowing to:
  2783.     (+) Initialize and configure the TIM Encoder.
  2784.     (+) De-initialize the TIM Encoder.
  2785.     (+) Start the TIM Encoder.
  2786.     (+) Stop the TIM Encoder.
  2787.     (+) Start the TIM Encoder and enable interrupt.
  2788.     (+) Stop the TIM Encoder and disable interrupt.
  2789.     (+) Start the TIM Encoder and enable DMA transfer.
  2790.     (+) Stop the TIM Encoder and disable DMA transfer.
  2791.  
  2792. @endverbatim
  2793.   * @{
  2794.   */
  2795. /**
  2796.   * @brief  Initializes the TIM Encoder Interface and initialize the associated handle.
  2797.   * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
  2798.   *         requires a timer reset to avoid unexpected direction
  2799.   *         due to DIR bit readonly in center aligned mode.
  2800.   *         Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
  2801.   * @note   Encoder mode and External clock mode 2 are not compatible and must not be selected together
  2802.   *         Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
  2803.   *         using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
  2804.   * @note   When the timer instance is initialized in Encoder mode, timer
  2805.   *         channels 1 and channel 2 are reserved and cannot be used for other
  2806.   *         purpose.
  2807.   * @param  htim TIM Encoder Interface handle
  2808.   * @param  sConfig TIM Encoder Interface configuration structure
  2809.   * @retval HAL status
  2810.   */
  2811. HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig)
  2812. {
  2813.   uint32_t tmpsmcr;
  2814.   uint32_t tmpccmr1;
  2815.   uint32_t tmpccer;
  2816.  
  2817.   /* Check the TIM handle allocation */
  2818.   if (htim == NULL)
  2819.   {
  2820.     return HAL_ERROR;
  2821.   }
  2822.  
  2823.   /* Check the parameters */
  2824.   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
  2825.   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  2826.   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  2827.   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
  2828.   assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
  2829.   assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
  2830.   assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
  2831.   assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
  2832.   assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
  2833.   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
  2834.   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
  2835.   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
  2836.   assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
  2837.  
  2838.   if (htim->State == HAL_TIM_STATE_RESET)
  2839.   {
  2840.     /* Allocate lock resource and initialize it */
  2841.     htim->Lock = HAL_UNLOCKED;
  2842.  
  2843. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  2844.     /* Reset interrupt callbacks to legacy weak callbacks */
  2845.     TIM_ResetCallback(htim);
  2846.  
  2847.     if (htim->Encoder_MspInitCallback == NULL)
  2848.     {
  2849.       htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
  2850.     }
  2851.     /* Init the low level hardware : GPIO, CLOCK, NVIC */
  2852.     htim->Encoder_MspInitCallback(htim);
  2853. #else
  2854.     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
  2855.     HAL_TIM_Encoder_MspInit(htim);
  2856. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  2857.   }
  2858.  
  2859.   /* Set the TIM state */
  2860.   htim->State = HAL_TIM_STATE_BUSY;
  2861.  
  2862.   /* Reset the SMS and ECE bits */
  2863.   htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
  2864.  
  2865.   /* Configure the Time base in the Encoder Mode */
  2866.   TIM_Base_SetConfig(htim->Instance, &htim->Init);
  2867.  
  2868.   /* Get the TIMx SMCR register value */
  2869.   tmpsmcr = htim->Instance->SMCR;
  2870.  
  2871.   /* Get the TIMx CCMR1 register value */
  2872.   tmpccmr1 = htim->Instance->CCMR1;
  2873.  
  2874.   /* Get the TIMx CCER register value */
  2875.   tmpccer = htim->Instance->CCER;
  2876.  
  2877.   /* Set the encoder Mode */
  2878.   tmpsmcr |= sConfig->EncoderMode;
  2879.  
  2880.   /* Select the Capture Compare 1 and the Capture Compare 2 as input */
  2881.   tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
  2882.   tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
  2883.  
  2884.   /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
  2885.   tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
  2886.   tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
  2887.   tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
  2888.   tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
  2889.  
  2890.   /* Set the TI1 and the TI2 Polarities */
  2891.   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
  2892.   tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
  2893.   tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
  2894.  
  2895.   /* Write to TIMx SMCR */
  2896.   htim->Instance->SMCR = tmpsmcr;
  2897.  
  2898.   /* Write to TIMx CCMR1 */
  2899.   htim->Instance->CCMR1 = tmpccmr1;
  2900.  
  2901.   /* Write to TIMx CCER */
  2902.   htim->Instance->CCER = tmpccer;
  2903.  
  2904.   /* Initialize the DMA burst operation state */
  2905.   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  2906.  
  2907.   /* Set the TIM channels state */
  2908.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  2909.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  2910.  
  2911.   /* Initialize the TIM state*/
  2912.   htim->State = HAL_TIM_STATE_READY;
  2913.  
  2914.   return HAL_OK;
  2915. }
  2916.  
  2917.  
  2918. /**
  2919.   * @brief  DeInitializes the TIM Encoder interface
  2920.   * @param  htim TIM Encoder Interface handle
  2921.   * @retval HAL status
  2922.   */
  2923. HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
  2924. {
  2925.   /* Check the parameters */
  2926.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  2927.  
  2928.   htim->State = HAL_TIM_STATE_BUSY;
  2929.  
  2930.   /* Disable the TIM Peripheral Clock */
  2931.   __HAL_TIM_DISABLE(htim);
  2932.  
  2933. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  2934.   if (htim->Encoder_MspDeInitCallback == NULL)
  2935.   {
  2936.     htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
  2937.   }
  2938.   /* DeInit the low level hardware */
  2939.   htim->Encoder_MspDeInitCallback(htim);
  2940. #else
  2941.   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
  2942.   HAL_TIM_Encoder_MspDeInit(htim);
  2943. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  2944.  
  2945.   /* Change the DMA burst operation state */
  2946.   htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
  2947.  
  2948.   /* Set the TIM channels state */
  2949.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
  2950.   TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
  2951.  
  2952.   /* Change TIM state */
  2953.   htim->State = HAL_TIM_STATE_RESET;
  2954.  
  2955.   /* Release Lock */
  2956.   __HAL_UNLOCK(htim);
  2957.  
  2958.   return HAL_OK;
  2959. }
  2960.  
  2961. /**
  2962.   * @brief  Initializes the TIM Encoder Interface MSP.
  2963.   * @param  htim TIM Encoder Interface handle
  2964.   * @retval None
  2965.   */
  2966. __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
  2967. {
  2968.   /* Prevent unused argument(s) compilation warning */
  2969.   UNUSED(htim);
  2970.  
  2971.   /* NOTE : This function should not be modified, when the callback is needed,
  2972.             the HAL_TIM_Encoder_MspInit could be implemented in the user file
  2973.    */
  2974. }
  2975.  
  2976. /**
  2977.   * @brief  DeInitializes TIM Encoder Interface MSP.
  2978.   * @param  htim TIM Encoder Interface handle
  2979.   * @retval None
  2980.   */
  2981. __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
  2982. {
  2983.   /* Prevent unused argument(s) compilation warning */
  2984.   UNUSED(htim);
  2985.  
  2986.   /* NOTE : This function should not be modified, when the callback is needed,
  2987.             the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
  2988.    */
  2989. }
  2990.  
  2991. /**
  2992.   * @brief  Starts the TIM Encoder Interface.
  2993.   * @param  htim TIM Encoder Interface handle
  2994.   * @param  Channel TIM Channels to be enabled
  2995.   *          This parameter can be one of the following values:
  2996.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  2997.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  2998.   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
  2999.   * @retval HAL status
  3000.   */
  3001. HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
  3002. {
  3003.   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
  3004.   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
  3005.  
  3006.   /* Check the parameters */
  3007.   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
  3008.  
  3009.   /* Set the TIM channel(s) state */
  3010.   if (Channel == TIM_CHANNEL_1)
  3011.   {
  3012.     if (channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  3013.     {
  3014.       return HAL_ERROR;
  3015.     }
  3016.     else
  3017.     {
  3018.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3019.     }
  3020.   }
  3021.   else if (Channel == TIM_CHANNEL_2)
  3022.   {
  3023.     if (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
  3024.     {
  3025.       return HAL_ERROR;
  3026.     }
  3027.     else
  3028.     {
  3029.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3030.     }
  3031.   }
  3032.   else
  3033.   {
  3034.     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  3035.         || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
  3036.     {
  3037.       return HAL_ERROR;
  3038.     }
  3039.     else
  3040.     {
  3041.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3042.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3043.     }
  3044.   }
  3045.  
  3046.   /* Enable the encoder interface channels */
  3047.   switch (Channel)
  3048.   {
  3049.     case TIM_CHANNEL_1:
  3050.     {
  3051.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  3052.       break;
  3053.     }
  3054.  
  3055.     case TIM_CHANNEL_2:
  3056.     {
  3057.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  3058.       break;
  3059.     }
  3060.  
  3061.     default :
  3062.     {
  3063.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  3064.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  3065.       break;
  3066.     }
  3067.   }
  3068.   /* Enable the Peripheral */
  3069.   __HAL_TIM_ENABLE(htim);
  3070.  
  3071.   /* Return function status */
  3072.   return HAL_OK;
  3073. }
  3074.  
  3075. /**
  3076.   * @brief  Stops the TIM Encoder Interface.
  3077.   * @param  htim TIM Encoder Interface handle
  3078.   * @param  Channel TIM Channels to be disabled
  3079.   *          This parameter can be one of the following values:
  3080.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  3081.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  3082.   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
  3083.   * @retval HAL status
  3084.   */
  3085. HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
  3086. {
  3087.   /* Check the parameters */
  3088.   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
  3089.  
  3090.   /* Disable the Input Capture channels 1 and 2
  3091.     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
  3092.   switch (Channel)
  3093.   {
  3094.     case TIM_CHANNEL_1:
  3095.     {
  3096.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  3097.       break;
  3098.     }
  3099.  
  3100.     case TIM_CHANNEL_2:
  3101.     {
  3102.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  3103.       break;
  3104.     }
  3105.  
  3106.     default :
  3107.     {
  3108.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  3109.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  3110.       break;
  3111.     }
  3112.   }
  3113.  
  3114.   /* Disable the Peripheral */
  3115.   __HAL_TIM_DISABLE(htim);
  3116.  
  3117.   /* Set the TIM channel(s) state */
  3118.   if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
  3119.   {
  3120.     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  3121.   }
  3122.   else
  3123.   {
  3124.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  3125.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  3126.   }
  3127.  
  3128.   /* Return function status */
  3129.   return HAL_OK;
  3130. }
  3131.  
  3132. /**
  3133.   * @brief  Starts the TIM Encoder Interface in interrupt mode.
  3134.   * @param  htim TIM Encoder Interface handle
  3135.   * @param  Channel TIM Channels to be enabled
  3136.   *          This parameter can be one of the following values:
  3137.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  3138.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  3139.   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
  3140.   * @retval HAL status
  3141.   */
  3142. HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  3143. {
  3144.   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
  3145.   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
  3146.  
  3147.   /* Check the parameters */
  3148.   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
  3149.  
  3150.   /* Set the TIM channel(s) state */
  3151.   if (Channel == TIM_CHANNEL_1)
  3152.   {
  3153.     if (channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  3154.     {
  3155.       return HAL_ERROR;
  3156.     }
  3157.     else
  3158.     {
  3159.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3160.     }
  3161.   }
  3162.   else if (Channel == TIM_CHANNEL_2)
  3163.   {
  3164.     if (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
  3165.     {
  3166.       return HAL_ERROR;
  3167.     }
  3168.     else
  3169.     {
  3170.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3171.     }
  3172.   }
  3173.   else
  3174.   {
  3175.     if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
  3176.         || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
  3177.     {
  3178.       return HAL_ERROR;
  3179.     }
  3180.     else
  3181.     {
  3182.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3183.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3184.     }
  3185.   }
  3186.  
  3187.   /* Enable the encoder interface channels */
  3188.   /* Enable the capture compare Interrupts 1 and/or 2 */
  3189.   switch (Channel)
  3190.   {
  3191.     case TIM_CHANNEL_1:
  3192.     {
  3193.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  3194.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
  3195.       break;
  3196.     }
  3197.  
  3198.     case TIM_CHANNEL_2:
  3199.     {
  3200.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  3201.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
  3202.       break;
  3203.     }
  3204.  
  3205.     default :
  3206.     {
  3207.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  3208.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  3209.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
  3210.       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
  3211.       break;
  3212.     }
  3213.   }
  3214.  
  3215.   /* Enable the Peripheral */
  3216.   __HAL_TIM_ENABLE(htim);
  3217.  
  3218.   /* Return function status */
  3219.   return HAL_OK;
  3220. }
  3221.  
  3222. /**
  3223.   * @brief  Stops the TIM Encoder Interface in interrupt mode.
  3224.   * @param  htim TIM Encoder Interface handle
  3225.   * @param  Channel TIM Channels to be disabled
  3226.   *          This parameter can be one of the following values:
  3227.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  3228.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  3229.   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
  3230.   * @retval HAL status
  3231.   */
  3232. HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
  3233. {
  3234.   /* Check the parameters */
  3235.   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
  3236.  
  3237.   /* Disable the Input Capture channels 1 and 2
  3238.     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
  3239.   if (Channel == TIM_CHANNEL_1)
  3240.   {
  3241.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  3242.  
  3243.     /* Disable the capture compare Interrupts 1 */
  3244.     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
  3245.   }
  3246.   else if (Channel == TIM_CHANNEL_2)
  3247.   {
  3248.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  3249.  
  3250.     /* Disable the capture compare Interrupts 2 */
  3251.     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
  3252.   }
  3253.   else
  3254.   {
  3255.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  3256.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  3257.  
  3258.     /* Disable the capture compare Interrupts 1 and 2 */
  3259.     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
  3260.     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
  3261.   }
  3262.  
  3263.   /* Disable the Peripheral */
  3264.   __HAL_TIM_DISABLE(htim);
  3265.  
  3266.   /* Set the TIM channel(s) state */
  3267.   if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
  3268.   {
  3269.     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  3270.   }
  3271.   else
  3272.   {
  3273.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  3274.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  3275.   }
  3276.  
  3277.   /* Return function status */
  3278.   return HAL_OK;
  3279. }
  3280.  
  3281. /**
  3282.   * @brief  Starts the TIM Encoder Interface in DMA mode.
  3283.   * @param  htim TIM Encoder Interface handle
  3284.   * @param  Channel TIM Channels to be enabled
  3285.   *          This parameter can be one of the following values:
  3286.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  3287.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  3288.   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
  3289.   * @param  pData1 The destination Buffer address for IC1.
  3290.   * @param  pData2 The destination Buffer address for IC2.
  3291.   * @param  Length The length of data to be transferred from TIM peripheral to memory.
  3292.   * @retval HAL status
  3293.   */
  3294. HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
  3295.                                             uint32_t *pData2, uint16_t Length)
  3296. {
  3297.   HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
  3298.   HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
  3299.  
  3300.   /* Check the parameters */
  3301.   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
  3302.  
  3303.   /* Set the TIM channel(s) state */
  3304.   if (Channel == TIM_CHANNEL_1)
  3305.   {
  3306.     if (channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
  3307.     {
  3308.       return HAL_BUSY;
  3309.     }
  3310.     else if (channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
  3311.     {
  3312.       if ((pData1 == NULL) && (Length > 0U))
  3313.       {
  3314.         return HAL_ERROR;
  3315.       }
  3316.       else
  3317.       {
  3318.         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3319.       }
  3320.     }
  3321.     else
  3322.     {
  3323.       return HAL_ERROR;
  3324.     }
  3325.   }
  3326.   else if (Channel == TIM_CHANNEL_2)
  3327.   {
  3328.     if (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
  3329.     {
  3330.       return HAL_BUSY;
  3331.     }
  3332.     else if (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
  3333.     {
  3334.       if ((pData2 == NULL) && (Length > 0U))
  3335.       {
  3336.         return HAL_ERROR;
  3337.       }
  3338.       else
  3339.       {
  3340.         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3341.       }
  3342.     }
  3343.     else
  3344.     {
  3345.       return HAL_ERROR;
  3346.     }
  3347.   }
  3348.   else
  3349.   {
  3350.     if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
  3351.         || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
  3352.     {
  3353.       return HAL_BUSY;
  3354.     }
  3355.     else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
  3356.              && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
  3357.     {
  3358.       if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
  3359.       {
  3360.         return HAL_ERROR;
  3361.       }
  3362.       else
  3363.       {
  3364.         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
  3365.         TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
  3366.       }
  3367.     }
  3368.     else
  3369.     {
  3370.       return HAL_ERROR;
  3371.     }
  3372.   }
  3373.  
  3374.   switch (Channel)
  3375.   {
  3376.     case TIM_CHANNEL_1:
  3377.     {
  3378.       /* Set the DMA capture callbacks */
  3379.       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
  3380.       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  3381.  
  3382.       /* Set the DMA error callback */
  3383.       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
  3384.  
  3385.       /* Enable the DMA channel */
  3386.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
  3387.                          Length) != HAL_OK)
  3388.       {
  3389.         /* Return error status */
  3390.         return HAL_ERROR;
  3391.       }
  3392.       /* Enable the TIM Input Capture DMA request */
  3393.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
  3394.  
  3395.       /* Enable the Peripheral */
  3396.       __HAL_TIM_ENABLE(htim);
  3397.  
  3398.       /* Enable the Capture compare channel */
  3399.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  3400.       break;
  3401.     }
  3402.  
  3403.     case TIM_CHANNEL_2:
  3404.     {
  3405.       /* Set the DMA capture callbacks */
  3406.       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
  3407.       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  3408.  
  3409.       /* Set the DMA error callback */
  3410.       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
  3411.       /* Enable the DMA channel */
  3412.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
  3413.                          Length) != HAL_OK)
  3414.       {
  3415.         /* Return error status */
  3416.         return HAL_ERROR;
  3417.       }
  3418.       /* Enable the TIM Input Capture  DMA request */
  3419.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
  3420.  
  3421.       /* Enable the Peripheral */
  3422.       __HAL_TIM_ENABLE(htim);
  3423.  
  3424.       /* Enable the Capture compare channel */
  3425.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  3426.       break;
  3427.     }
  3428.  
  3429.     case TIM_CHANNEL_ALL:
  3430.     {
  3431.       /* Set the DMA capture callbacks */
  3432.       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
  3433.       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  3434.  
  3435.       /* Set the DMA error callback */
  3436.       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
  3437.  
  3438.       /* Enable the DMA channel */
  3439.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
  3440.                          Length) != HAL_OK)
  3441.       {
  3442.         /* Return error status */
  3443.         return HAL_ERROR;
  3444.       }
  3445.  
  3446.       /* Set the DMA capture callbacks */
  3447.       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
  3448.       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  3449.  
  3450.       /* Set the DMA error callback */
  3451.       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
  3452.  
  3453.       /* Enable the DMA channel */
  3454.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
  3455.                          Length) != HAL_OK)
  3456.       {
  3457.         /* Return error status */
  3458.         return HAL_ERROR;
  3459.       }
  3460.       /* Enable the Peripheral */
  3461.       __HAL_TIM_ENABLE(htim);
  3462.  
  3463.       /* Enable the Capture compare channel */
  3464.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
  3465.       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
  3466.  
  3467.       /* Enable the TIM Input Capture  DMA request */
  3468.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
  3469.       /* Enable the TIM Input Capture  DMA request */
  3470.       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
  3471.       break;
  3472.     }
  3473.  
  3474.     default:
  3475.       break;
  3476.   }
  3477.  
  3478.   /* Return function status */
  3479.   return HAL_OK;
  3480. }
  3481.  
  3482. /**
  3483.   * @brief  Stops the TIM Encoder Interface in DMA mode.
  3484.   * @param  htim TIM Encoder Interface handle
  3485.   * @param  Channel TIM Channels to be enabled
  3486.   *          This parameter can be one of the following values:
  3487.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  3488.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  3489.   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
  3490.   * @retval HAL status
  3491.   */
  3492. HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
  3493. {
  3494.   /* Check the parameters */
  3495.   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
  3496.  
  3497.   /* Disable the Input Capture channels 1 and 2
  3498.     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
  3499.   if (Channel == TIM_CHANNEL_1)
  3500.   {
  3501.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  3502.  
  3503.     /* Disable the capture compare DMA Request 1 */
  3504.     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
  3505.     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
  3506.   }
  3507.   else if (Channel == TIM_CHANNEL_2)
  3508.   {
  3509.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  3510.  
  3511.     /* Disable the capture compare DMA Request 2 */
  3512.     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
  3513.     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
  3514.   }
  3515.   else
  3516.   {
  3517.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
  3518.     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
  3519.  
  3520.     /* Disable the capture compare DMA Request 1 and 2 */
  3521.     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
  3522.     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
  3523.     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
  3524.     (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
  3525.   }
  3526.  
  3527.   /* Disable the Peripheral */
  3528.   __HAL_TIM_DISABLE(htim);
  3529.  
  3530.   /* Set the TIM channel(s) state */
  3531.   if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
  3532.   {
  3533.     TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
  3534.   }
  3535.   else
  3536.   {
  3537.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  3538.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  3539.   }
  3540.  
  3541.   /* Return function status */
  3542.   return HAL_OK;
  3543. }
  3544.  
  3545. /**
  3546.   * @}
  3547.   */
  3548. /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
  3549.   *  @brief    TIM IRQ handler management
  3550.   *
  3551. @verbatim
  3552.   ==============================================================================
  3553.                         ##### IRQ handler management #####
  3554.   ==============================================================================
  3555.   [..]
  3556.     This section provides Timer IRQ handler function.
  3557.  
  3558. @endverbatim
  3559.   * @{
  3560.   */
  3561. /**
  3562.   * @brief  This function handles TIM interrupts requests.
  3563.   * @param  htim TIM  handle
  3564.   * @retval None
  3565.   */
  3566. void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
  3567. {
  3568.   /* Capture compare 1 event */
  3569.   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
  3570.   {
  3571.     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
  3572.     {
  3573.       {
  3574.         __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
  3575.         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  3576.  
  3577.         /* Input capture event */
  3578.         if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
  3579.         {
  3580. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3581.           htim->IC_CaptureCallback(htim);
  3582. #else
  3583.           HAL_TIM_IC_CaptureCallback(htim);
  3584. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3585.         }
  3586.         /* Output compare event */
  3587.         else
  3588.         {
  3589. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3590.           htim->OC_DelayElapsedCallback(htim);
  3591.           htim->PWM_PulseFinishedCallback(htim);
  3592. #else
  3593.           HAL_TIM_OC_DelayElapsedCallback(htim);
  3594.           HAL_TIM_PWM_PulseFinishedCallback(htim);
  3595. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3596.         }
  3597.         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  3598.       }
  3599.     }
  3600.   }
  3601.   /* Capture compare 2 event */
  3602.   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
  3603.   {
  3604.     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
  3605.     {
  3606.       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
  3607.       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  3608.       /* Input capture event */
  3609.       if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
  3610.       {
  3611. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3612.         htim->IC_CaptureCallback(htim);
  3613. #else
  3614.         HAL_TIM_IC_CaptureCallback(htim);
  3615. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3616.       }
  3617.       /* Output compare event */
  3618.       else
  3619.       {
  3620. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3621.         htim->OC_DelayElapsedCallback(htim);
  3622.         htim->PWM_PulseFinishedCallback(htim);
  3623. #else
  3624.         HAL_TIM_OC_DelayElapsedCallback(htim);
  3625.         HAL_TIM_PWM_PulseFinishedCallback(htim);
  3626. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3627.       }
  3628.       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  3629.     }
  3630.   }
  3631.   /* Capture compare 3 event */
  3632.   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
  3633.   {
  3634.     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
  3635.     {
  3636.       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
  3637.       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  3638.       /* Input capture event */
  3639.       if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
  3640.       {
  3641. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3642.         htim->IC_CaptureCallback(htim);
  3643. #else
  3644.         HAL_TIM_IC_CaptureCallback(htim);
  3645. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3646.       }
  3647.       /* Output compare event */
  3648.       else
  3649.       {
  3650. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3651.         htim->OC_DelayElapsedCallback(htim);
  3652.         htim->PWM_PulseFinishedCallback(htim);
  3653. #else
  3654.         HAL_TIM_OC_DelayElapsedCallback(htim);
  3655.         HAL_TIM_PWM_PulseFinishedCallback(htim);
  3656. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3657.       }
  3658.       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  3659.     }
  3660.   }
  3661.   /* Capture compare 4 event */
  3662.   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
  3663.   {
  3664.     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
  3665.     {
  3666.       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
  3667.       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  3668.       /* Input capture event */
  3669.       if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
  3670.       {
  3671. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3672.         htim->IC_CaptureCallback(htim);
  3673. #else
  3674.         HAL_TIM_IC_CaptureCallback(htim);
  3675. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3676.       }
  3677.       /* Output compare event */
  3678.       else
  3679.       {
  3680. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3681.         htim->OC_DelayElapsedCallback(htim);
  3682.         htim->PWM_PulseFinishedCallback(htim);
  3683. #else
  3684.         HAL_TIM_OC_DelayElapsedCallback(htim);
  3685.         HAL_TIM_PWM_PulseFinishedCallback(htim);
  3686. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3687.       }
  3688.       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  3689.     }
  3690.   }
  3691.   /* TIM Update event */
  3692.   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
  3693.   {
  3694.     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
  3695.     {
  3696.       __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
  3697. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3698.       htim->PeriodElapsedCallback(htim);
  3699. #else
  3700.       HAL_TIM_PeriodElapsedCallback(htim);
  3701. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3702.     }
  3703.   }
  3704.   /* TIM Trigger detection event */
  3705.   if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
  3706.   {
  3707.     if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
  3708.     {
  3709.       __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
  3710. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  3711.       htim->TriggerCallback(htim);
  3712. #else
  3713.       HAL_TIM_TriggerCallback(htim);
  3714. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  3715.     }
  3716.   }
  3717. }
  3718.  
  3719. /**
  3720.   * @}
  3721.   */
  3722.  
  3723. /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
  3724.   *  @brief    TIM Peripheral Control functions
  3725.   *
  3726. @verbatim
  3727.   ==============================================================================
  3728.                    ##### Peripheral Control functions #####
  3729.   ==============================================================================
  3730.  [..]
  3731.    This section provides functions allowing to:
  3732.       (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
  3733.       (+) Configure External Clock source.
  3734.       (+) Configure Master and the Slave synchronization.
  3735.       (+) Configure the DMA Burst Mode.
  3736.  
  3737. @endverbatim
  3738.   * @{
  3739.   */
  3740.  
  3741. /**
  3742.   * @brief  Initializes the TIM Output Compare Channels according to the specified
  3743.   *         parameters in the TIM_OC_InitTypeDef.
  3744.   * @param  htim TIM Output Compare handle
  3745.   * @param  sConfig TIM Output Compare configuration structure
  3746.   * @param  Channel TIM Channels to configure
  3747.   *          This parameter can be one of the following values:
  3748.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  3749.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  3750.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  3751.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  3752.   * @retval HAL status
  3753.   */
  3754. HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
  3755.                                            TIM_OC_InitTypeDef *sConfig,
  3756.                                            uint32_t Channel)
  3757. {
  3758.   /* Check the parameters */
  3759.   assert_param(IS_TIM_CHANNELS(Channel));
  3760.   assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
  3761.   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
  3762.  
  3763.   /* Process Locked */
  3764.   __HAL_LOCK(htim);
  3765.  
  3766.   switch (Channel)
  3767.   {
  3768.     case TIM_CHANNEL_1:
  3769.     {
  3770.       /* Check the parameters */
  3771.       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  3772.  
  3773.       /* Configure the TIM Channel 1 in Output Compare */
  3774.       TIM_OC1_SetConfig(htim->Instance, sConfig);
  3775.       break;
  3776.     }
  3777.  
  3778.     case TIM_CHANNEL_2:
  3779.     {
  3780.       /* Check the parameters */
  3781.       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  3782.  
  3783.       /* Configure the TIM Channel 2 in Output Compare */
  3784.       TIM_OC2_SetConfig(htim->Instance, sConfig);
  3785.       break;
  3786.     }
  3787.  
  3788.     case TIM_CHANNEL_3:
  3789.     {
  3790.       /* Check the parameters */
  3791.       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
  3792.  
  3793.       /* Configure the TIM Channel 3 in Output Compare */
  3794.       TIM_OC3_SetConfig(htim->Instance, sConfig);
  3795.       break;
  3796.     }
  3797.  
  3798.     case TIM_CHANNEL_4:
  3799.     {
  3800.       /* Check the parameters */
  3801.       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
  3802.  
  3803.       /* Configure the TIM Channel 4 in Output Compare */
  3804.       TIM_OC4_SetConfig(htim->Instance, sConfig);
  3805.       break;
  3806.     }
  3807.  
  3808.     default:
  3809.       break;
  3810.   }
  3811.  
  3812.   __HAL_UNLOCK(htim);
  3813.  
  3814.   return HAL_OK;
  3815. }
  3816.  
  3817. /**
  3818.   * @brief  Initializes the TIM Input Capture Channels according to the specified
  3819.   *         parameters in the TIM_IC_InitTypeDef.
  3820.   * @param  htim TIM IC handle
  3821.   * @param  sConfig TIM Input Capture configuration structure
  3822.   * @param  Channel TIM Channel to configure
  3823.   *          This parameter can be one of the following values:
  3824.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  3825.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  3826.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  3827.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  3828.   * @retval HAL status
  3829.   */
  3830. HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
  3831. {
  3832.   /* Check the parameters */
  3833.   assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  3834.   assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
  3835.   assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
  3836.   assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
  3837.   assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
  3838.  
  3839.   /* Process Locked */
  3840.   __HAL_LOCK(htim);
  3841.  
  3842.   if (Channel == TIM_CHANNEL_1)
  3843.   {
  3844.     /* TI1 Configuration */
  3845.     TIM_TI1_SetConfig(htim->Instance,
  3846.                       sConfig->ICPolarity,
  3847.                       sConfig->ICSelection,
  3848.                       sConfig->ICFilter);
  3849.  
  3850.     /* Reset the IC1PSC Bits */
  3851.     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
  3852.  
  3853.     /* Set the IC1PSC value */
  3854.     htim->Instance->CCMR1 |= sConfig->ICPrescaler;
  3855.   }
  3856.   else if (Channel == TIM_CHANNEL_2)
  3857.   {
  3858.     /* TI2 Configuration */
  3859.     assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  3860.  
  3861.     TIM_TI2_SetConfig(htim->Instance,
  3862.                       sConfig->ICPolarity,
  3863.                       sConfig->ICSelection,
  3864.                       sConfig->ICFilter);
  3865.  
  3866.     /* Reset the IC2PSC Bits */
  3867.     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
  3868.  
  3869.     /* Set the IC2PSC value */
  3870.     htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
  3871.   }
  3872.   else if (Channel == TIM_CHANNEL_3)
  3873.   {
  3874.     /* TI3 Configuration */
  3875.     assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
  3876.  
  3877.     TIM_TI3_SetConfig(htim->Instance,
  3878.                       sConfig->ICPolarity,
  3879.                       sConfig->ICSelection,
  3880.                       sConfig->ICFilter);
  3881.  
  3882.     /* Reset the IC3PSC Bits */
  3883.     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
  3884.  
  3885.     /* Set the IC3PSC value */
  3886.     htim->Instance->CCMR2 |= sConfig->ICPrescaler;
  3887.   }
  3888.   else
  3889.   {
  3890.     /* TI4 Configuration */
  3891.     assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
  3892.  
  3893.     TIM_TI4_SetConfig(htim->Instance,
  3894.                       sConfig->ICPolarity,
  3895.                       sConfig->ICSelection,
  3896.                       sConfig->ICFilter);
  3897.  
  3898.     /* Reset the IC4PSC Bits */
  3899.     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
  3900.  
  3901.     /* Set the IC4PSC value */
  3902.     htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
  3903.   }
  3904.  
  3905.   __HAL_UNLOCK(htim);
  3906.  
  3907.   return HAL_OK;
  3908. }
  3909.  
  3910. /**
  3911.   * @brief  Initializes the TIM PWM  channels according to the specified
  3912.   *         parameters in the TIM_OC_InitTypeDef.
  3913.   * @param  htim TIM PWM handle
  3914.   * @param  sConfig TIM PWM configuration structure
  3915.   * @param  Channel TIM Channels to be configured
  3916.   *          This parameter can be one of the following values:
  3917.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  3918.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  3919.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  3920.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  3921.   * @retval HAL status
  3922.   */
  3923. HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
  3924.                                             TIM_OC_InitTypeDef *sConfig,
  3925.                                             uint32_t Channel)
  3926. {
  3927.   /* Check the parameters */
  3928.   assert_param(IS_TIM_CHANNELS(Channel));
  3929.   assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
  3930.   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
  3931.   assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
  3932.  
  3933.   /* Process Locked */
  3934.   __HAL_LOCK(htim);
  3935.  
  3936.   switch (Channel)
  3937.   {
  3938.     case TIM_CHANNEL_1:
  3939.     {
  3940.       /* Check the parameters */
  3941.       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  3942.  
  3943.       /* Configure the Channel 1 in PWM mode */
  3944.       TIM_OC1_SetConfig(htim->Instance, sConfig);
  3945.  
  3946.       /* Set the Preload enable bit for channel1 */
  3947.       htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
  3948.  
  3949.       /* Configure the Output Fast mode */
  3950.       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
  3951.       htim->Instance->CCMR1 |= sConfig->OCFastMode;
  3952.       break;
  3953.     }
  3954.  
  3955.     case TIM_CHANNEL_2:
  3956.     {
  3957.       /* Check the parameters */
  3958.       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  3959.  
  3960.       /* Configure the Channel 2 in PWM mode */
  3961.       TIM_OC2_SetConfig(htim->Instance, sConfig);
  3962.  
  3963.       /* Set the Preload enable bit for channel2 */
  3964.       htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
  3965.  
  3966.       /* Configure the Output Fast mode */
  3967.       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
  3968.       htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
  3969.       break;
  3970.     }
  3971.  
  3972.     case TIM_CHANNEL_3:
  3973.     {
  3974.       /* Check the parameters */
  3975.       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
  3976.  
  3977.       /* Configure the Channel 3 in PWM mode */
  3978.       TIM_OC3_SetConfig(htim->Instance, sConfig);
  3979.  
  3980.       /* Set the Preload enable bit for channel3 */
  3981.       htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
  3982.  
  3983.       /* Configure the Output Fast mode */
  3984.       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
  3985.       htim->Instance->CCMR2 |= sConfig->OCFastMode;
  3986.       break;
  3987.     }
  3988.  
  3989.     case TIM_CHANNEL_4:
  3990.     {
  3991.       /* Check the parameters */
  3992.       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
  3993.  
  3994.       /* Configure the Channel 4 in PWM mode */
  3995.       TIM_OC4_SetConfig(htim->Instance, sConfig);
  3996.  
  3997.       /* Set the Preload enable bit for channel4 */
  3998.       htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
  3999.  
  4000.       /* Configure the Output Fast mode */
  4001.       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
  4002.       htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
  4003.       break;
  4004.     }
  4005.  
  4006.     default:
  4007.       break;
  4008.   }
  4009.  
  4010.   __HAL_UNLOCK(htim);
  4011.  
  4012.   return HAL_OK;
  4013. }
  4014.  
  4015. /**
  4016.   * @brief  Initializes the TIM One Pulse Channels according to the specified
  4017.   *         parameters in the TIM_OnePulse_InitTypeDef.
  4018.   * @param  htim TIM One Pulse handle
  4019.   * @param  sConfig TIM One Pulse configuration structure
  4020.   * @param  OutputChannel TIM output channel to configure
  4021.   *          This parameter can be one of the following values:
  4022.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  4023.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  4024.   * @param  InputChannel TIM input Channel to configure
  4025.   *          This parameter can be one of the following values:
  4026.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  4027.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  4028.   * @note  To output a waveform with a minimum delay user can enable the fast
  4029.   *        mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
  4030.   *        output is forced in response to the edge detection on TIx input,
  4031.   *        without taking in account the comparison.
  4032.   * @retval HAL status
  4033.   */
  4034. HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef *sConfig,
  4035.                                                  uint32_t OutputChannel,  uint32_t InputChannel)
  4036. {
  4037.   TIM_OC_InitTypeDef temp1;
  4038.  
  4039.   /* Check the parameters */
  4040.   assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
  4041.   assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
  4042.  
  4043.   if (OutputChannel != InputChannel)
  4044.   {
  4045.     /* Process Locked */
  4046.     __HAL_LOCK(htim);
  4047.  
  4048.     htim->State = HAL_TIM_STATE_BUSY;
  4049.  
  4050.     /* Extract the Output compare configuration from sConfig structure */
  4051.     temp1.OCMode = sConfig->OCMode;
  4052.     temp1.Pulse = sConfig->Pulse;
  4053.     temp1.OCPolarity = sConfig->OCPolarity;
  4054.  
  4055.     switch (OutputChannel)
  4056.     {
  4057.       case TIM_CHANNEL_1:
  4058.       {
  4059.         assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  4060.  
  4061.         TIM_OC1_SetConfig(htim->Instance, &temp1);
  4062.         break;
  4063.       }
  4064.       case TIM_CHANNEL_2:
  4065.       {
  4066.         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  4067.  
  4068.         TIM_OC2_SetConfig(htim->Instance, &temp1);
  4069.         break;
  4070.       }
  4071.       default:
  4072.         break;
  4073.     }
  4074.  
  4075.     switch (InputChannel)
  4076.     {
  4077.       case TIM_CHANNEL_1:
  4078.       {
  4079.         assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  4080.  
  4081.         TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
  4082.                           sConfig->ICSelection, sConfig->ICFilter);
  4083.  
  4084.         /* Reset the IC1PSC Bits */
  4085.         htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
  4086.  
  4087.         /* Select the Trigger source */
  4088.         htim->Instance->SMCR &= ~TIM_SMCR_TS;
  4089.         htim->Instance->SMCR |= TIM_TS_TI1FP1;
  4090.  
  4091.         /* Select the Slave Mode */
  4092.         htim->Instance->SMCR &= ~TIM_SMCR_SMS;
  4093.         htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
  4094.         break;
  4095.       }
  4096.       case TIM_CHANNEL_2:
  4097.       {
  4098.         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  4099.  
  4100.         TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
  4101.                           sConfig->ICSelection, sConfig->ICFilter);
  4102.  
  4103.         /* Reset the IC2PSC Bits */
  4104.         htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
  4105.  
  4106.         /* Select the Trigger source */
  4107.         htim->Instance->SMCR &= ~TIM_SMCR_TS;
  4108.         htim->Instance->SMCR |= TIM_TS_TI2FP2;
  4109.  
  4110.         /* Select the Slave Mode */
  4111.         htim->Instance->SMCR &= ~TIM_SMCR_SMS;
  4112.         htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
  4113.         break;
  4114.       }
  4115.  
  4116.       default:
  4117.         break;
  4118.     }
  4119.  
  4120.     htim->State = HAL_TIM_STATE_READY;
  4121.  
  4122.     __HAL_UNLOCK(htim);
  4123.  
  4124.     return HAL_OK;
  4125.   }
  4126.   else
  4127.   {
  4128.     return HAL_ERROR;
  4129.   }
  4130. }
  4131.  
  4132. /**
  4133.   * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
  4134.   * @param  htim TIM handle
  4135.   * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data write
  4136.   *         This parameter can be one of the following values:
  4137.   *            @arg TIM_DMABASE_CR1
  4138.   *            @arg TIM_DMABASE_CR2
  4139.   *            @arg TIM_DMABASE_SMCR
  4140.   *            @arg TIM_DMABASE_DIER
  4141.   *            @arg TIM_DMABASE_SR
  4142.   *            @arg TIM_DMABASE_EGR
  4143.   *            @arg TIM_DMABASE_CCMR1
  4144.   *            @arg TIM_DMABASE_CCMR2
  4145.   *            @arg TIM_DMABASE_CCER
  4146.   *            @arg TIM_DMABASE_CNT
  4147.   *            @arg TIM_DMABASE_PSC
  4148.   *            @arg TIM_DMABASE_ARR
  4149.   *            @arg TIM_DMABASE_CCR1
  4150.   *            @arg TIM_DMABASE_CCR2
  4151.   *            @arg TIM_DMABASE_CCR3
  4152.   *            @arg TIM_DMABASE_CCR4
  4153.   *            @arg TIM_DMABASE_OR
  4154.   * @param  BurstRequestSrc TIM DMA Request sources
  4155.   *         This parameter can be one of the following values:
  4156.   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
  4157.   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  4158.   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  4159.   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  4160.   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  4161.   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
  4162.   * @param  BurstBuffer The Buffer address.
  4163.   * @param  BurstLength DMA Burst length. This parameter can be one value
  4164.   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
  4165.   * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
  4166.   * @retval HAL status
  4167.   */
  4168. HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
  4169.                                               uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t  BurstLength)
  4170. {
  4171.   return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
  4172.                                           ((BurstLength) >> 8U) + 1U);
  4173. }
  4174.  
  4175. /**
  4176.   * @brief  Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
  4177.   * @param  htim TIM handle
  4178.   * @param  BurstBaseAddress TIM Base address from where the DMA will start the Data write
  4179.   *         This parameter can be one of the following values:
  4180.   *            @arg TIM_DMABASE_CR1
  4181.   *            @arg TIM_DMABASE_CR2
  4182.   *            @arg TIM_DMABASE_SMCR
  4183.   *            @arg TIM_DMABASE_DIER
  4184.   *            @arg TIM_DMABASE_SR
  4185.   *            @arg TIM_DMABASE_EGR
  4186.   *            @arg TIM_DMABASE_CCMR1
  4187.   *            @arg TIM_DMABASE_CCMR2
  4188.   *            @arg TIM_DMABASE_CCER
  4189.   *            @arg TIM_DMABASE_CNT
  4190.   *            @arg TIM_DMABASE_PSC
  4191.   *            @arg TIM_DMABASE_ARR
  4192.   *            @arg TIM_DMABASE_CCR1
  4193.   *            @arg TIM_DMABASE_CCR2
  4194.   *            @arg TIM_DMABASE_CCR3
  4195.   *            @arg TIM_DMABASE_CCR4
  4196.   *            @arg TIM_DMABASE_OR
  4197.   * @param  BurstRequestSrc TIM DMA Request sources
  4198.   *         This parameter can be one of the following values:
  4199.   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
  4200.   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  4201.   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  4202.   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  4203.   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  4204.   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
  4205.   * @param  BurstBuffer The Buffer address.
  4206.   * @param  BurstLength DMA Burst length. This parameter can be one value
  4207.   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
  4208.   * @param  DataLength Data length. This parameter can be one value
  4209.   *         between 1 and 0xFFFF.
  4210.   * @retval HAL status
  4211.   */
  4212. HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
  4213.                                                    uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
  4214.                                                    uint32_t  BurstLength,  uint32_t  DataLength)
  4215. {
  4216.   /* Check the parameters */
  4217.   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
  4218.   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
  4219.   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
  4220.   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
  4221.   assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
  4222.  
  4223.   if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
  4224.   {
  4225.     return HAL_BUSY;
  4226.   }
  4227.   else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
  4228.   {
  4229.     if ((BurstBuffer == NULL) && (BurstLength > 0U))
  4230.     {
  4231.       return HAL_ERROR;
  4232.     }
  4233.     else
  4234.     {
  4235.       htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
  4236.     }
  4237.   }
  4238.   else
  4239.   {
  4240.     /* nothing to do */
  4241.   }
  4242.   switch (BurstRequestSrc)
  4243.   {
  4244.     case TIM_DMA_UPDATE:
  4245.     {
  4246.       /* Set the DMA Period elapsed callbacks */
  4247.       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
  4248.       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
  4249.  
  4250.       /* Set the DMA error callback */
  4251.       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
  4252.  
  4253.       /* Enable the DMA channel */
  4254.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
  4255.                          (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
  4256.       {
  4257.         /* Return error status */
  4258.         return HAL_ERROR;
  4259.       }
  4260.       break;
  4261.     }
  4262.     case TIM_DMA_CC1:
  4263.     {
  4264.       /* Set the DMA compare callbacks */
  4265.       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
  4266.       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  4267.  
  4268.       /* Set the DMA error callback */
  4269.       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
  4270.  
  4271.       /* Enable the DMA channel */
  4272.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
  4273.                          (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
  4274.       {
  4275.         /* Return error status */
  4276.         return HAL_ERROR;
  4277.       }
  4278.       break;
  4279.     }
  4280.     case TIM_DMA_CC2:
  4281.     {
  4282.       /* Set the DMA compare callbacks */
  4283.       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
  4284.       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  4285.  
  4286.       /* Set the DMA error callback */
  4287.       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
  4288.  
  4289.       /* Enable the DMA channel */
  4290.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
  4291.                          (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
  4292.       {
  4293.         /* Return error status */
  4294.         return HAL_ERROR;
  4295.       }
  4296.       break;
  4297.     }
  4298.     case TIM_DMA_CC3:
  4299.     {
  4300.       /* Set the DMA compare callbacks */
  4301.       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
  4302.       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  4303.  
  4304.       /* Set the DMA error callback */
  4305.       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
  4306.  
  4307.       /* Enable the DMA channel */
  4308.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
  4309.                          (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
  4310.       {
  4311.         /* Return error status */
  4312.         return HAL_ERROR;
  4313.       }
  4314.       break;
  4315.     }
  4316.     case TIM_DMA_CC4:
  4317.     {
  4318.       /* Set the DMA compare callbacks */
  4319.       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
  4320.       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
  4321.  
  4322.       /* Set the DMA error callback */
  4323.       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
  4324.  
  4325.       /* Enable the DMA channel */
  4326.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
  4327.                          (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
  4328.       {
  4329.         /* Return error status */
  4330.         return HAL_ERROR;
  4331.       }
  4332.       break;
  4333.     }
  4334.     case TIM_DMA_TRIGGER:
  4335.     {
  4336.       /* Set the DMA trigger callbacks */
  4337.       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
  4338.       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
  4339.  
  4340.       /* Set the DMA error callback */
  4341.       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
  4342.  
  4343.       /* Enable the DMA channel */
  4344.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
  4345.                          (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
  4346.       {
  4347.         /* Return error status */
  4348.         return HAL_ERROR;
  4349.       }
  4350.       break;
  4351.     }
  4352.     default:
  4353.       break;
  4354.   }
  4355.  
  4356.   /* Configure the DMA Burst Mode */
  4357.   htim->Instance->DCR = (BurstBaseAddress | BurstLength);
  4358.   /* Enable the TIM DMA Request */
  4359.   __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
  4360.  
  4361.   /* Return function status */
  4362.   return HAL_OK;
  4363. }
  4364.  
  4365. /**
  4366.   * @brief  Stops the TIM DMA Burst mode
  4367.   * @param  htim TIM handle
  4368.   * @param  BurstRequestSrc TIM DMA Request sources to disable
  4369.   * @retval HAL status
  4370.   */
  4371. HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
  4372. {
  4373.   /* Check the parameters */
  4374.   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
  4375.  
  4376.   /* Abort the DMA transfer (at least disable the DMA channel) */
  4377.   switch (BurstRequestSrc)
  4378.   {
  4379.     case TIM_DMA_UPDATE:
  4380.     {
  4381.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
  4382.       break;
  4383.     }
  4384.     case TIM_DMA_CC1:
  4385.     {
  4386.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
  4387.       break;
  4388.     }
  4389.     case TIM_DMA_CC2:
  4390.     {
  4391.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
  4392.       break;
  4393.     }
  4394.     case TIM_DMA_CC3:
  4395.     {
  4396.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
  4397.       break;
  4398.     }
  4399.     case TIM_DMA_CC4:
  4400.     {
  4401.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
  4402.       break;
  4403.     }
  4404.     case TIM_DMA_TRIGGER:
  4405.     {
  4406.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
  4407.       break;
  4408.     }
  4409.     default:
  4410.       break;
  4411.   }
  4412.  
  4413.   /* Disable the TIM Update DMA request */
  4414.   __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
  4415.  
  4416.   /* Change the DMA burst operation state */
  4417.   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  4418.  
  4419.   /* Return function status */
  4420.   return HAL_OK;
  4421. }
  4422.  
  4423. /**
  4424.   * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
  4425.   * @param  htim TIM handle
  4426.   * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
  4427.   *         This parameter can be one of the following values:
  4428.   *            @arg TIM_DMABASE_CR1
  4429.   *            @arg TIM_DMABASE_CR2
  4430.   *            @arg TIM_DMABASE_SMCR
  4431.   *            @arg TIM_DMABASE_DIER
  4432.   *            @arg TIM_DMABASE_SR
  4433.   *            @arg TIM_DMABASE_EGR
  4434.   *            @arg TIM_DMABASE_CCMR1
  4435.   *            @arg TIM_DMABASE_CCMR2
  4436.   *            @arg TIM_DMABASE_CCER
  4437.   *            @arg TIM_DMABASE_CNT
  4438.   *            @arg TIM_DMABASE_PSC
  4439.   *            @arg TIM_DMABASE_ARR
  4440.   *            @arg TIM_DMABASE_CCR1
  4441.   *            @arg TIM_DMABASE_CCR2
  4442.   *            @arg TIM_DMABASE_CCR3
  4443.   *            @arg TIM_DMABASE_CCR4
  4444.   *            @arg TIM_DMABASE_OR
  4445.   * @param  BurstRequestSrc TIM DMA Request sources
  4446.   *         This parameter can be one of the following values:
  4447.   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
  4448.   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  4449.   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  4450.   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  4451.   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  4452.   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
  4453.   * @param  BurstBuffer The Buffer address.
  4454.   * @param  BurstLength DMA Burst length. This parameter can be one value
  4455.   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
  4456.   * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
  4457.   * @retval HAL status
  4458.   */
  4459. HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
  4460.                                              uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength)
  4461. {
  4462.   return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
  4463.                                          ((BurstLength) >> 8U) + 1U);
  4464. }
  4465.  
  4466. /**
  4467.   * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
  4468.   * @param  htim TIM handle
  4469.   * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
  4470.   *         This parameter can be one of the following values:
  4471.   *            @arg TIM_DMABASE_CR1
  4472.   *            @arg TIM_DMABASE_CR2
  4473.   *            @arg TIM_DMABASE_SMCR
  4474.   *            @arg TIM_DMABASE_DIER
  4475.   *            @arg TIM_DMABASE_SR
  4476.   *            @arg TIM_DMABASE_EGR
  4477.   *            @arg TIM_DMABASE_CCMR1
  4478.   *            @arg TIM_DMABASE_CCMR2
  4479.   *            @arg TIM_DMABASE_CCER
  4480.   *            @arg TIM_DMABASE_CNT
  4481.   *            @arg TIM_DMABASE_PSC
  4482.   *            @arg TIM_DMABASE_ARR
  4483.   *            @arg TIM_DMABASE_CCR1
  4484.   *            @arg TIM_DMABASE_CCR2
  4485.   *            @arg TIM_DMABASE_CCR3
  4486.   *            @arg TIM_DMABASE_CCR4
  4487.   *            @arg TIM_DMABASE_OR
  4488.   * @param  BurstRequestSrc TIM DMA Request sources
  4489.   *         This parameter can be one of the following values:
  4490.   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
  4491.   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  4492.   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  4493.   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  4494.   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  4495.   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
  4496.   * @param  BurstBuffer The Buffer address.
  4497.   * @param  BurstLength DMA Burst length. This parameter can be one value
  4498.   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
  4499.   * @param  DataLength Data length. This parameter can be one value
  4500.   *         between 1 and 0xFFFF.
  4501.   * @retval HAL status
  4502.   */
  4503. HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
  4504.                                                   uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,
  4505.                                                   uint32_t  BurstLength, uint32_t  DataLength)
  4506. {
  4507.   /* Check the parameters */
  4508.   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
  4509.   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
  4510.   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
  4511.   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
  4512.   assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
  4513.  
  4514.   if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
  4515.   {
  4516.     return HAL_BUSY;
  4517.   }
  4518.   else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
  4519.   {
  4520.     if ((BurstBuffer == NULL) && (BurstLength > 0U))
  4521.     {
  4522.       return HAL_ERROR;
  4523.     }
  4524.     else
  4525.     {
  4526.       htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
  4527.     }
  4528.   }
  4529.   else
  4530.   {
  4531.     /* nothing to do */
  4532.   }
  4533.   switch (BurstRequestSrc)
  4534.   {
  4535.     case TIM_DMA_UPDATE:
  4536.     {
  4537.       /* Set the DMA Period elapsed callbacks */
  4538.       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
  4539.       htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
  4540.  
  4541.       /* Set the DMA error callback */
  4542.       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
  4543.  
  4544.       /* Enable the DMA channel */
  4545.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
  4546.                          DataLength) != HAL_OK)
  4547.       {
  4548.         /* Return error status */
  4549.         return HAL_ERROR;
  4550.       }
  4551.       break;
  4552.     }
  4553.     case TIM_DMA_CC1:
  4554.     {
  4555.       /* Set the DMA capture callbacks */
  4556.       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
  4557.       htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  4558.  
  4559.       /* Set the DMA error callback */
  4560.       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
  4561.  
  4562.       /* Enable the DMA channel */
  4563.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
  4564.                          DataLength) != HAL_OK)
  4565.       {
  4566.         /* Return error status */
  4567.         return HAL_ERROR;
  4568.       }
  4569.       break;
  4570.     }
  4571.     case TIM_DMA_CC2:
  4572.     {
  4573.       /* Set the DMA capture callbacks */
  4574.       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
  4575.       htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  4576.  
  4577.       /* Set the DMA error callback */
  4578.       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
  4579.  
  4580.       /* Enable the DMA channel */
  4581.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
  4582.                          DataLength) != HAL_OK)
  4583.       {
  4584.         /* Return error status */
  4585.         return HAL_ERROR;
  4586.       }
  4587.       break;
  4588.     }
  4589.     case TIM_DMA_CC3:
  4590.     {
  4591.       /* Set the DMA capture callbacks */
  4592.       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
  4593.       htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  4594.  
  4595.       /* Set the DMA error callback */
  4596.       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
  4597.  
  4598.       /* Enable the DMA channel */
  4599.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
  4600.                          DataLength) != HAL_OK)
  4601.       {
  4602.         /* Return error status */
  4603.         return HAL_ERROR;
  4604.       }
  4605.       break;
  4606.     }
  4607.     case TIM_DMA_CC4:
  4608.     {
  4609.       /* Set the DMA capture callbacks */
  4610.       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
  4611.       htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
  4612.  
  4613.       /* Set the DMA error callback */
  4614.       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
  4615.  
  4616.       /* Enable the DMA channel */
  4617.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
  4618.                          DataLength) != HAL_OK)
  4619.       {
  4620.         /* Return error status */
  4621.         return HAL_ERROR;
  4622.       }
  4623.       break;
  4624.     }
  4625.     case TIM_DMA_TRIGGER:
  4626.     {
  4627.       /* Set the DMA trigger callbacks */
  4628.       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
  4629.       htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
  4630.  
  4631.       /* Set the DMA error callback */
  4632.       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
  4633.  
  4634.       /* Enable the DMA channel */
  4635.       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
  4636.                          DataLength) != HAL_OK)
  4637.       {
  4638.         /* Return error status */
  4639.         return HAL_ERROR;
  4640.       }
  4641.       break;
  4642.     }
  4643.     default:
  4644.       break;
  4645.   }
  4646.  
  4647.   /* Configure the DMA Burst Mode */
  4648.   htim->Instance->DCR = (BurstBaseAddress | BurstLength);
  4649.  
  4650.   /* Enable the TIM DMA Request */
  4651.   __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
  4652.  
  4653.   /* Return function status */
  4654.   return HAL_OK;
  4655. }
  4656.  
  4657. /**
  4658.   * @brief  Stop the DMA burst reading
  4659.   * @param  htim TIM handle
  4660.   * @param  BurstRequestSrc TIM DMA Request sources to disable.
  4661.   * @retval HAL status
  4662.   */
  4663. HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
  4664. {
  4665.   /* Check the parameters */
  4666.   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
  4667.  
  4668.   /* Abort the DMA transfer (at least disable the DMA channel) */
  4669.   switch (BurstRequestSrc)
  4670.   {
  4671.     case TIM_DMA_UPDATE:
  4672.     {
  4673.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
  4674.       break;
  4675.     }
  4676.     case TIM_DMA_CC1:
  4677.     {
  4678.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
  4679.       break;
  4680.     }
  4681.     case TIM_DMA_CC2:
  4682.     {
  4683.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
  4684.       break;
  4685.     }
  4686.     case TIM_DMA_CC3:
  4687.     {
  4688.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
  4689.       break;
  4690.     }
  4691.     case TIM_DMA_CC4:
  4692.     {
  4693.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
  4694.       break;
  4695.     }
  4696.     case TIM_DMA_TRIGGER:
  4697.     {
  4698.       (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
  4699.       break;
  4700.     }
  4701.     default:
  4702.       break;
  4703.   }
  4704.  
  4705.   /* Disable the TIM Update DMA request */
  4706.   __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
  4707.  
  4708.   /* Change the DMA burst operation state */
  4709.   htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
  4710.  
  4711.   /* Return function status */
  4712.   return HAL_OK;
  4713. }
  4714.  
  4715. /**
  4716.   * @brief  Generate a software event
  4717.   * @param  htim TIM handle
  4718.   * @param  EventSource specifies the event source.
  4719.   *          This parameter can be one of the following values:
  4720.   *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
  4721.   *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
  4722.   *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
  4723.   *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
  4724.   *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
  4725.   *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
  4726.   * @note   Basic timers can only generate an update event.
  4727.   * @retval HAL status
  4728.   */
  4729.  
  4730. HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
  4731. {
  4732.   /* Check the parameters */
  4733.   assert_param(IS_TIM_INSTANCE(htim->Instance));
  4734.   assert_param(IS_TIM_EVENT_SOURCE(EventSource));
  4735.  
  4736.   /* Process Locked */
  4737.   __HAL_LOCK(htim);
  4738.  
  4739.   /* Change the TIM state */
  4740.   htim->State = HAL_TIM_STATE_BUSY;
  4741.  
  4742.   /* Set the event sources */
  4743.   htim->Instance->EGR = EventSource;
  4744.  
  4745.   /* Change the TIM state */
  4746.   htim->State = HAL_TIM_STATE_READY;
  4747.  
  4748.   __HAL_UNLOCK(htim);
  4749.  
  4750.   /* Return function status */
  4751.   return HAL_OK;
  4752. }
  4753.  
  4754. /**
  4755.   * @brief  Configures the OCRef clear feature
  4756.   * @param  htim TIM handle
  4757.   * @param  sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
  4758.   *         contains the OCREF clear feature and parameters for the TIM peripheral.
  4759.   * @param  Channel specifies the TIM Channel
  4760.   *          This parameter can be one of the following values:
  4761.   *            @arg TIM_CHANNEL_1: TIM Channel 1
  4762.   *            @arg TIM_CHANNEL_2: TIM Channel 2
  4763.   *            @arg TIM_CHANNEL_3: TIM Channel 3
  4764.   *            @arg TIM_CHANNEL_4: TIM Channel 4
  4765.   * @retval HAL status
  4766.   */
  4767. HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
  4768.                                            TIM_ClearInputConfigTypeDef *sClearInputConfig,
  4769.                                            uint32_t Channel)
  4770. {
  4771.   /* Check the parameters */
  4772.   assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
  4773.   assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
  4774.  
  4775.   /* Process Locked */
  4776.   __HAL_LOCK(htim);
  4777.  
  4778.   htim->State = HAL_TIM_STATE_BUSY;
  4779.  
  4780.   switch (sClearInputConfig->ClearInputSource)
  4781.   {
  4782.     case TIM_CLEARINPUTSOURCE_NONE:
  4783.     {
  4784.       /* Clear the OCREF clear selection bit and the the ETR Bits */
  4785.       CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
  4786.       break;
  4787.     }
  4788.     case TIM_CLEARINPUTSOURCE_OCREFCLR:
  4789.     {
  4790.       /* Clear the OCREF clear selection bit */
  4791.       CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
  4792.     }
  4793.     break;
  4794.  
  4795.     case TIM_CLEARINPUTSOURCE_ETR:
  4796.     {
  4797.       /* Check the parameters */
  4798.       assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
  4799.       assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
  4800.       assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
  4801.  
  4802.       /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
  4803.       if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
  4804.       {
  4805.         htim->State = HAL_TIM_STATE_READY;
  4806.         __HAL_UNLOCK(htim);
  4807.         return HAL_ERROR;
  4808.       }
  4809.  
  4810.       TIM_ETR_SetConfig(htim->Instance,
  4811.                         sClearInputConfig->ClearInputPrescaler,
  4812.                         sClearInputConfig->ClearInputPolarity,
  4813.                         sClearInputConfig->ClearInputFilter);
  4814.  
  4815.       /* Set the OCREF clear selection bit */
  4816.       SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
  4817.       break;
  4818.     }
  4819.  
  4820.     default:
  4821.       break;
  4822.   }
  4823.  
  4824.   switch (Channel)
  4825.   {
  4826.     case TIM_CHANNEL_1:
  4827.     {
  4828.       if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
  4829.       {
  4830.         /* Enable the OCREF clear feature for Channel 1 */
  4831.         SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
  4832.       }
  4833.       else
  4834.       {
  4835.         /* Disable the OCREF clear feature for Channel 1 */
  4836.         CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
  4837.       }
  4838.       break;
  4839.     }
  4840.     case TIM_CHANNEL_2:
  4841.     {
  4842.       if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
  4843.       {
  4844.         /* Enable the OCREF clear feature for Channel 2 */
  4845.         SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
  4846.       }
  4847.       else
  4848.       {
  4849.         /* Disable the OCREF clear feature for Channel 2 */
  4850.         CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
  4851.       }
  4852.       break;
  4853.     }
  4854.     case TIM_CHANNEL_3:
  4855.     {
  4856.       if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
  4857.       {
  4858.         /* Enable the OCREF clear feature for Channel 3 */
  4859.         SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
  4860.       }
  4861.       else
  4862.       {
  4863.         /* Disable the OCREF clear feature for Channel 3 */
  4864.         CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
  4865.       }
  4866.       break;
  4867.     }
  4868.     case TIM_CHANNEL_4:
  4869.     {
  4870.       if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
  4871.       {
  4872.         /* Enable the OCREF clear feature for Channel 4 */
  4873.         SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
  4874.       }
  4875.       else
  4876.       {
  4877.         /* Disable the OCREF clear feature for Channel 4 */
  4878.         CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
  4879.       }
  4880.       break;
  4881.     }
  4882.     default:
  4883.       break;
  4884.   }
  4885.  
  4886.   htim->State = HAL_TIM_STATE_READY;
  4887.  
  4888.   __HAL_UNLOCK(htim);
  4889.  
  4890.   return HAL_OK;
  4891. }
  4892.  
  4893. /**
  4894.   * @brief   Configures the clock source to be used
  4895.   * @param  htim TIM handle
  4896.   * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
  4897.   *         contains the clock source information for the TIM peripheral.
  4898.   * @retval HAL status
  4899.   */
  4900. HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
  4901. {
  4902.   uint32_t tmpsmcr;
  4903.  
  4904.   /* Process Locked */
  4905.   __HAL_LOCK(htim);
  4906.  
  4907.   htim->State = HAL_TIM_STATE_BUSY;
  4908.  
  4909.   /* Check the parameters */
  4910.   assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
  4911.  
  4912.   /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
  4913.   tmpsmcr = htim->Instance->SMCR;
  4914.   tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
  4915.   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
  4916.   htim->Instance->SMCR = tmpsmcr;
  4917.  
  4918.   switch (sClockSourceConfig->ClockSource)
  4919.   {
  4920.     case TIM_CLOCKSOURCE_INTERNAL:
  4921.     {
  4922.       assert_param(IS_TIM_INSTANCE(htim->Instance));
  4923.       break;
  4924.     }
  4925.  
  4926.     case TIM_CLOCKSOURCE_ETRMODE1:
  4927.     {
  4928.       /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
  4929.       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
  4930.  
  4931.       /* Check ETR input conditioning related parameters */
  4932.       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
  4933.       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
  4934.       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
  4935.  
  4936.       /* Configure the ETR Clock source */
  4937.       TIM_ETR_SetConfig(htim->Instance,
  4938.                         sClockSourceConfig->ClockPrescaler,
  4939.                         sClockSourceConfig->ClockPolarity,
  4940.                         sClockSourceConfig->ClockFilter);
  4941.  
  4942.       /* Select the External clock mode1 and the ETRF trigger */
  4943.       tmpsmcr = htim->Instance->SMCR;
  4944.       tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
  4945.       /* Write to TIMx SMCR */
  4946.       htim->Instance->SMCR = tmpsmcr;
  4947.       break;
  4948.     }
  4949.  
  4950.     case TIM_CLOCKSOURCE_ETRMODE2:
  4951.     {
  4952.       /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
  4953.       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
  4954.  
  4955.       /* Check ETR input conditioning related parameters */
  4956.       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
  4957.       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
  4958.       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
  4959.  
  4960.       /* Configure the ETR Clock source */
  4961.       TIM_ETR_SetConfig(htim->Instance,
  4962.                         sClockSourceConfig->ClockPrescaler,
  4963.                         sClockSourceConfig->ClockPolarity,
  4964.                         sClockSourceConfig->ClockFilter);
  4965.       /* Enable the External clock mode2 */
  4966.       htim->Instance->SMCR |= TIM_SMCR_ECE;
  4967.       break;
  4968.     }
  4969.  
  4970.     case TIM_CLOCKSOURCE_TI1:
  4971.     {
  4972.       /* Check whether or not the timer instance supports external clock mode 1 */
  4973.       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
  4974.  
  4975.       /* Check TI1 input conditioning related parameters */
  4976.       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
  4977.       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
  4978.  
  4979.       TIM_TI1_ConfigInputStage(htim->Instance,
  4980.                                sClockSourceConfig->ClockPolarity,
  4981.                                sClockSourceConfig->ClockFilter);
  4982.       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
  4983.       break;
  4984.     }
  4985.  
  4986.     case TIM_CLOCKSOURCE_TI2:
  4987.     {
  4988.       /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
  4989.       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
  4990.  
  4991.       /* Check TI2 input conditioning related parameters */
  4992.       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
  4993.       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
  4994.  
  4995.       TIM_TI2_ConfigInputStage(htim->Instance,
  4996.                                sClockSourceConfig->ClockPolarity,
  4997.                                sClockSourceConfig->ClockFilter);
  4998.       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
  4999.       break;
  5000.     }
  5001.  
  5002.     case TIM_CLOCKSOURCE_TI1ED:
  5003.     {
  5004.       /* Check whether or not the timer instance supports external clock mode 1 */
  5005.       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
  5006.  
  5007.       /* Check TI1 input conditioning related parameters */
  5008.       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
  5009.       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
  5010.  
  5011.       TIM_TI1_ConfigInputStage(htim->Instance,
  5012.                                sClockSourceConfig->ClockPolarity,
  5013.                                sClockSourceConfig->ClockFilter);
  5014.       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
  5015.       break;
  5016.     }
  5017.  
  5018.     case TIM_CLOCKSOURCE_ITR0:
  5019.     case TIM_CLOCKSOURCE_ITR1:
  5020.     case TIM_CLOCKSOURCE_ITR2:
  5021.     case TIM_CLOCKSOURCE_ITR3:
  5022.       {
  5023.         /* Check whether or not the timer instance supports internal trigger input */
  5024.         assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
  5025.  
  5026.         TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
  5027.         break;
  5028.       }
  5029.  
  5030.     default:
  5031.       break;
  5032.   }
  5033.   htim->State = HAL_TIM_STATE_READY;
  5034.  
  5035.   __HAL_UNLOCK(htim);
  5036.  
  5037.   return HAL_OK;
  5038. }
  5039.  
  5040. /**
  5041.   * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
  5042.   *         or a XOR combination between CH1_input, CH2_input & CH3_input
  5043.   * @param  htim TIM handle.
  5044.   * @param  TI1_Selection Indicate whether or not channel 1 is connected to the
  5045.   *         output of a XOR gate.
  5046.   *          This parameter can be one of the following values:
  5047.   *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
  5048.   *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
  5049.   *            pins are connected to the TI1 input (XOR combination)
  5050.   * @retval HAL status
  5051.   */
  5052. HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
  5053. {
  5054.   uint32_t tmpcr2;
  5055.  
  5056.   /* Check the parameters */
  5057.   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
  5058.   assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
  5059.  
  5060.   /* Get the TIMx CR2 register value */
  5061.   tmpcr2 = htim->Instance->CR2;
  5062.  
  5063.   /* Reset the TI1 selection */
  5064.   tmpcr2 &= ~TIM_CR2_TI1S;
  5065.  
  5066.   /* Set the TI1 selection */
  5067.   tmpcr2 |= TI1_Selection;
  5068.  
  5069.   /* Write to TIMxCR2 */
  5070.   htim->Instance->CR2 = tmpcr2;
  5071.  
  5072.   return HAL_OK;
  5073. }
  5074.  
  5075. /**
  5076.   * @brief  Configures the TIM in Slave mode
  5077.   * @param  htim TIM handle.
  5078.   * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
  5079.   *         contains the selected trigger (internal trigger input, filtered
  5080.   *         timer input or external trigger input) and the Slave mode
  5081.   *         (Disable, Reset, Gated, Trigger, External clock mode 1).
  5082.   * @retval HAL status
  5083.   */
  5084. HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
  5085. {
  5086.   /* Check the parameters */
  5087.   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
  5088.   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
  5089.   assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
  5090.  
  5091.   __HAL_LOCK(htim);
  5092.  
  5093.   htim->State = HAL_TIM_STATE_BUSY;
  5094.  
  5095.   if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
  5096.   {
  5097.     htim->State = HAL_TIM_STATE_READY;
  5098.     __HAL_UNLOCK(htim);
  5099.     return HAL_ERROR;
  5100.   }
  5101.  
  5102.   /* Disable Trigger Interrupt */
  5103.   __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
  5104.  
  5105.   /* Disable Trigger DMA request */
  5106.   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
  5107.  
  5108.   htim->State = HAL_TIM_STATE_READY;
  5109.  
  5110.   __HAL_UNLOCK(htim);
  5111.  
  5112.   return HAL_OK;
  5113. }
  5114.  
  5115. /**
  5116.   * @brief  Configures the TIM in Slave mode in interrupt mode
  5117.   * @param  htim TIM handle.
  5118.   * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
  5119.   *         contains the selected trigger (internal trigger input, filtered
  5120.   *         timer input or external trigger input) and the Slave mode
  5121.   *         (Disable, Reset, Gated, Trigger, External clock mode 1).
  5122.   * @retval HAL status
  5123.   */
  5124. HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
  5125.                                                 TIM_SlaveConfigTypeDef *sSlaveConfig)
  5126. {
  5127.   /* Check the parameters */
  5128.   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
  5129.   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
  5130.   assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
  5131.  
  5132.   __HAL_LOCK(htim);
  5133.  
  5134.   htim->State = HAL_TIM_STATE_BUSY;
  5135.  
  5136.   if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
  5137.   {
  5138.     htim->State = HAL_TIM_STATE_READY;
  5139.     __HAL_UNLOCK(htim);
  5140.     return HAL_ERROR;
  5141.   }
  5142.  
  5143.   /* Enable Trigger Interrupt */
  5144.   __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
  5145.  
  5146.   /* Disable Trigger DMA request */
  5147.   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
  5148.  
  5149.   htim->State = HAL_TIM_STATE_READY;
  5150.  
  5151.   __HAL_UNLOCK(htim);
  5152.  
  5153.   return HAL_OK;
  5154. }
  5155.  
  5156. /**
  5157.   * @brief  Read the captured value from Capture Compare unit
  5158.   * @param  htim TIM handle.
  5159.   * @param  Channel TIM Channels to be enabled
  5160.   *          This parameter can be one of the following values:
  5161.   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
  5162.   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
  5163.   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
  5164.   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
  5165.   * @retval Captured value
  5166.   */
  5167. uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
  5168. {
  5169.   uint32_t tmpreg = 0U;
  5170.  
  5171.   switch (Channel)
  5172.   {
  5173.     case TIM_CHANNEL_1:
  5174.     {
  5175.       /* Check the parameters */
  5176.       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  5177.  
  5178.       /* Return the capture 1 value */
  5179.       tmpreg =  htim->Instance->CCR1;
  5180.  
  5181.       break;
  5182.     }
  5183.     case TIM_CHANNEL_2:
  5184.     {
  5185.       /* Check the parameters */
  5186.       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  5187.  
  5188.       /* Return the capture 2 value */
  5189.       tmpreg =   htim->Instance->CCR2;
  5190.  
  5191.       break;
  5192.     }
  5193.  
  5194.     case TIM_CHANNEL_3:
  5195.     {
  5196.       /* Check the parameters */
  5197.       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
  5198.  
  5199.       /* Return the capture 3 value */
  5200.       tmpreg =   htim->Instance->CCR3;
  5201.  
  5202.       break;
  5203.     }
  5204.  
  5205.     case TIM_CHANNEL_4:
  5206.     {
  5207.       /* Check the parameters */
  5208.       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
  5209.  
  5210.       /* Return the capture 4 value */
  5211.       tmpreg =   htim->Instance->CCR4;
  5212.  
  5213.       break;
  5214.     }
  5215.  
  5216.     default:
  5217.       break;
  5218.   }
  5219.  
  5220.   return tmpreg;
  5221. }
  5222.  
  5223. /**
  5224.   * @}
  5225.   */
  5226.  
  5227. /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
  5228.   *  @brief    TIM Callbacks functions
  5229.   *
  5230. @verbatim
  5231.   ==============================================================================
  5232.                         ##### TIM Callbacks functions #####
  5233.   ==============================================================================
  5234.  [..]
  5235.    This section provides TIM callback functions:
  5236.    (+) TIM Period elapsed callback
  5237.    (+) TIM Output Compare callback
  5238.    (+) TIM Input capture callback
  5239.    (+) TIM Trigger callback
  5240.    (+) TIM Error callback
  5241.  
  5242. @endverbatim
  5243.   * @{
  5244.   */
  5245.  
  5246. /**
  5247.   * @brief  Period elapsed callback in non-blocking mode
  5248.   * @param  htim TIM handle
  5249.   * @retval None
  5250.   */
  5251. __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
  5252. {
  5253.   /* Prevent unused argument(s) compilation warning */
  5254.   UNUSED(htim);
  5255.  
  5256.   /* NOTE : This function should not be modified, when the callback is needed,
  5257.             the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
  5258.    */
  5259. }
  5260.  
  5261. /**
  5262.   * @brief  Period elapsed half complete callback in non-blocking mode
  5263.   * @param  htim TIM handle
  5264.   * @retval None
  5265.   */
  5266. __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
  5267. {
  5268.   /* Prevent unused argument(s) compilation warning */
  5269.   UNUSED(htim);
  5270.  
  5271.   /* NOTE : This function should not be modified, when the callback is needed,
  5272.             the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
  5273.    */
  5274. }
  5275.  
  5276. /**
  5277.   * @brief  Output Compare callback in non-blocking mode
  5278.   * @param  htim TIM OC handle
  5279.   * @retval None
  5280.   */
  5281. __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
  5282. {
  5283.   /* Prevent unused argument(s) compilation warning */
  5284.   UNUSED(htim);
  5285.  
  5286.   /* NOTE : This function should not be modified, when the callback is needed,
  5287.             the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
  5288.    */
  5289. }
  5290.  
  5291. /**
  5292.   * @brief  Input Capture callback in non-blocking mode
  5293.   * @param  htim TIM IC handle
  5294.   * @retval None
  5295.   */
  5296. __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
  5297. {
  5298.   /* Prevent unused argument(s) compilation warning */
  5299.   UNUSED(htim);
  5300.  
  5301.   /* NOTE : This function should not be modified, when the callback is needed,
  5302.             the HAL_TIM_IC_CaptureCallback could be implemented in the user file
  5303.    */
  5304. }
  5305.  
  5306. /**
  5307.   * @brief  Input Capture half complete callback in non-blocking mode
  5308.   * @param  htim TIM IC handle
  5309.   * @retval None
  5310.   */
  5311. __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
  5312. {
  5313.   /* Prevent unused argument(s) compilation warning */
  5314.   UNUSED(htim);
  5315.  
  5316.   /* NOTE : This function should not be modified, when the callback is needed,
  5317.             the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
  5318.    */
  5319. }
  5320.  
  5321. /**
  5322.   * @brief  PWM Pulse finished callback in non-blocking mode
  5323.   * @param  htim TIM handle
  5324.   * @retval None
  5325.   */
  5326. __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
  5327. {
  5328.   /* Prevent unused argument(s) compilation warning */
  5329.   UNUSED(htim);
  5330.  
  5331.   /* NOTE : This function should not be modified, when the callback is needed,
  5332.             the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
  5333.    */
  5334. }
  5335.  
  5336. /**
  5337.   * @brief  PWM Pulse finished half complete callback in non-blocking mode
  5338.   * @param  htim TIM handle
  5339.   * @retval None
  5340.   */
  5341. __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
  5342. {
  5343.   /* Prevent unused argument(s) compilation warning */
  5344.   UNUSED(htim);
  5345.  
  5346.   /* NOTE : This function should not be modified, when the callback is needed,
  5347.             the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
  5348.    */
  5349. }
  5350.  
  5351. /**
  5352.   * @brief  Hall Trigger detection callback in non-blocking mode
  5353.   * @param  htim TIM handle
  5354.   * @retval None
  5355.   */
  5356. __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
  5357. {
  5358.   /* Prevent unused argument(s) compilation warning */
  5359.   UNUSED(htim);
  5360.  
  5361.   /* NOTE : This function should not be modified, when the callback is needed,
  5362.             the HAL_TIM_TriggerCallback could be implemented in the user file
  5363.    */
  5364. }
  5365.  
  5366. /**
  5367.   * @brief  Hall Trigger detection half complete callback in non-blocking mode
  5368.   * @param  htim TIM handle
  5369.   * @retval None
  5370.   */
  5371. __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
  5372. {
  5373.   /* Prevent unused argument(s) compilation warning */
  5374.   UNUSED(htim);
  5375.  
  5376.   /* NOTE : This function should not be modified, when the callback is needed,
  5377.             the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
  5378.    */
  5379. }
  5380.  
  5381. /**
  5382.   * @brief  Timer error callback in non-blocking mode
  5383.   * @param  htim TIM handle
  5384.   * @retval None
  5385.   */
  5386. __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
  5387. {
  5388.   /* Prevent unused argument(s) compilation warning */
  5389.   UNUSED(htim);
  5390.  
  5391.   /* NOTE : This function should not be modified, when the callback is needed,
  5392.             the HAL_TIM_ErrorCallback could be implemented in the user file
  5393.    */
  5394. }
  5395.  
  5396. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  5397. /**
  5398.   * @brief  Register a User TIM callback to be used instead of the weak predefined callback
  5399.   * @param htim tim handle
  5400.   * @param CallbackID ID of the callback to be registered
  5401.   *        This parameter can be one of the following values:
  5402.   *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
  5403.   *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
  5404.   *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
  5405.   *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
  5406.   *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
  5407.   *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
  5408.   *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
  5409.   *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
  5410.   *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
  5411.   *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
  5412.   *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
  5413.   *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
  5414.   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
  5415.   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
  5416.   *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
  5417.   *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
  5418.   *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
  5419.   *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
  5420.   *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
  5421.   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
  5422.   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
  5423.   *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
  5424.   *          @param pCallback pointer to the callback function
  5425.   *          @retval status
  5426.   */
  5427. HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
  5428.                                            pTIM_CallbackTypeDef pCallback)
  5429. {
  5430.   HAL_StatusTypeDef status = HAL_OK;
  5431.  
  5432.   if (pCallback == NULL)
  5433.   {
  5434.     return HAL_ERROR;
  5435.   }
  5436.   /* Process locked */
  5437.   __HAL_LOCK(htim);
  5438.  
  5439.   if (htim->State == HAL_TIM_STATE_READY)
  5440.   {
  5441.     switch (CallbackID)
  5442.     {
  5443.       case HAL_TIM_BASE_MSPINIT_CB_ID :
  5444.         htim->Base_MspInitCallback                 = pCallback;
  5445.         break;
  5446.  
  5447.       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
  5448.         htim->Base_MspDeInitCallback               = pCallback;
  5449.         break;
  5450.  
  5451.       case HAL_TIM_IC_MSPINIT_CB_ID :
  5452.         htim->IC_MspInitCallback                   = pCallback;
  5453.         break;
  5454.  
  5455.       case HAL_TIM_IC_MSPDEINIT_CB_ID :
  5456.         htim->IC_MspDeInitCallback                 = pCallback;
  5457.         break;
  5458.  
  5459.       case HAL_TIM_OC_MSPINIT_CB_ID :
  5460.         htim->OC_MspInitCallback                   = pCallback;
  5461.         break;
  5462.  
  5463.       case HAL_TIM_OC_MSPDEINIT_CB_ID :
  5464.         htim->OC_MspDeInitCallback                 = pCallback;
  5465.         break;
  5466.  
  5467.       case HAL_TIM_PWM_MSPINIT_CB_ID :
  5468.         htim->PWM_MspInitCallback                  = pCallback;
  5469.         break;
  5470.  
  5471.       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
  5472.         htim->PWM_MspDeInitCallback                = pCallback;
  5473.         break;
  5474.  
  5475.       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
  5476.         htim->OnePulse_MspInitCallback             = pCallback;
  5477.         break;
  5478.  
  5479.       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
  5480.         htim->OnePulse_MspDeInitCallback           = pCallback;
  5481.         break;
  5482.  
  5483.       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
  5484.         htim->Encoder_MspInitCallback              = pCallback;
  5485.         break;
  5486.  
  5487.       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
  5488.         htim->Encoder_MspDeInitCallback            = pCallback;
  5489.         break;
  5490.  
  5491.       case HAL_TIM_PERIOD_ELAPSED_CB_ID :
  5492.         htim->PeriodElapsedCallback                = pCallback;
  5493.         break;
  5494.  
  5495.       case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
  5496.         htim->PeriodElapsedHalfCpltCallback        = pCallback;
  5497.         break;
  5498.  
  5499.       case HAL_TIM_TRIGGER_CB_ID :
  5500.         htim->TriggerCallback                      = pCallback;
  5501.         break;
  5502.  
  5503.       case HAL_TIM_TRIGGER_HALF_CB_ID :
  5504.         htim->TriggerHalfCpltCallback              = pCallback;
  5505.         break;
  5506.  
  5507.       case HAL_TIM_IC_CAPTURE_CB_ID :
  5508.         htim->IC_CaptureCallback                   = pCallback;
  5509.         break;
  5510.  
  5511.       case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
  5512.         htim->IC_CaptureHalfCpltCallback           = pCallback;
  5513.         break;
  5514.  
  5515.       case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
  5516.         htim->OC_DelayElapsedCallback              = pCallback;
  5517.         break;
  5518.  
  5519.       case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
  5520.         htim->PWM_PulseFinishedCallback            = pCallback;
  5521.         break;
  5522.  
  5523.       case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
  5524.         htim->PWM_PulseFinishedHalfCpltCallback    = pCallback;
  5525.         break;
  5526.  
  5527.       case HAL_TIM_ERROR_CB_ID :
  5528.         htim->ErrorCallback                        = pCallback;
  5529.         break;
  5530.  
  5531.       default :
  5532.         /* Return error status */
  5533.         status =  HAL_ERROR;
  5534.         break;
  5535.     }
  5536.   }
  5537.   else if (htim->State == HAL_TIM_STATE_RESET)
  5538.   {
  5539.     switch (CallbackID)
  5540.     {
  5541.       case HAL_TIM_BASE_MSPINIT_CB_ID :
  5542.         htim->Base_MspInitCallback         = pCallback;
  5543.         break;
  5544.  
  5545.       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
  5546.         htim->Base_MspDeInitCallback       = pCallback;
  5547.         break;
  5548.  
  5549.       case HAL_TIM_IC_MSPINIT_CB_ID :
  5550.         htim->IC_MspInitCallback           = pCallback;
  5551.         break;
  5552.  
  5553.       case HAL_TIM_IC_MSPDEINIT_CB_ID :
  5554.         htim->IC_MspDeInitCallback         = pCallback;
  5555.         break;
  5556.  
  5557.       case HAL_TIM_OC_MSPINIT_CB_ID :
  5558.         htim->OC_MspInitCallback           = pCallback;
  5559.         break;
  5560.  
  5561.       case HAL_TIM_OC_MSPDEINIT_CB_ID :
  5562.         htim->OC_MspDeInitCallback         = pCallback;
  5563.         break;
  5564.  
  5565.       case HAL_TIM_PWM_MSPINIT_CB_ID :
  5566.         htim->PWM_MspInitCallback          = pCallback;
  5567.         break;
  5568.  
  5569.       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
  5570.         htim->PWM_MspDeInitCallback        = pCallback;
  5571.         break;
  5572.  
  5573.       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
  5574.         htim->OnePulse_MspInitCallback     = pCallback;
  5575.         break;
  5576.  
  5577.       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
  5578.         htim->OnePulse_MspDeInitCallback   = pCallback;
  5579.         break;
  5580.  
  5581.       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
  5582.         htim->Encoder_MspInitCallback      = pCallback;
  5583.         break;
  5584.  
  5585.       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
  5586.         htim->Encoder_MspDeInitCallback    = pCallback;
  5587.         break;
  5588.  
  5589.       default :
  5590.         /* Return error status */
  5591.         status =  HAL_ERROR;
  5592.         break;
  5593.     }
  5594.   }
  5595.   else
  5596.   {
  5597.     /* Return error status */
  5598.     status =  HAL_ERROR;
  5599.   }
  5600.  
  5601.   /* Release Lock */
  5602.   __HAL_UNLOCK(htim);
  5603.  
  5604.   return status;
  5605. }
  5606.  
  5607. /**
  5608.   * @brief  Unregister a TIM callback
  5609.   *         TIM callback is redirected to the weak predefined callback
  5610.   * @param htim tim handle
  5611.   * @param CallbackID ID of the callback to be unregistered
  5612.   *        This parameter can be one of the following values:
  5613.   *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
  5614.   *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
  5615.   *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
  5616.   *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
  5617.   *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
  5618.   *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
  5619.   *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
  5620.   *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
  5621.   *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
  5622.   *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
  5623.   *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
  5624.   *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
  5625.   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
  5626.   *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
  5627.   *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
  5628.   *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
  5629.   *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
  5630.   *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
  5631.   *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
  5632.   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
  5633.   *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
  5634.   *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
  5635.   *          @retval status
  5636.   */
  5637. HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
  5638. {
  5639.   HAL_StatusTypeDef status = HAL_OK;
  5640.  
  5641.   /* Process locked */
  5642.   __HAL_LOCK(htim);
  5643.  
  5644.   if (htim->State == HAL_TIM_STATE_READY)
  5645.   {
  5646.     switch (CallbackID)
  5647.     {
  5648.       case HAL_TIM_BASE_MSPINIT_CB_ID :
  5649.         /* Legacy weak Base MspInit Callback */
  5650.         htim->Base_MspInitCallback              = HAL_TIM_Base_MspInit;
  5651.         break;
  5652.  
  5653.       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
  5654.         /* Legacy weak Base Msp DeInit Callback */
  5655.         htim->Base_MspDeInitCallback            = HAL_TIM_Base_MspDeInit;
  5656.         break;
  5657.  
  5658.       case HAL_TIM_IC_MSPINIT_CB_ID :
  5659.         /* Legacy weak IC Msp Init Callback */
  5660.         htim->IC_MspInitCallback                = HAL_TIM_IC_MspInit;
  5661.         break;
  5662.  
  5663.       case HAL_TIM_IC_MSPDEINIT_CB_ID :
  5664.         /* Legacy weak IC Msp DeInit Callback */
  5665.         htim->IC_MspDeInitCallback              = HAL_TIM_IC_MspDeInit;
  5666.         break;
  5667.  
  5668.       case HAL_TIM_OC_MSPINIT_CB_ID :
  5669.         /* Legacy weak OC Msp Init Callback */
  5670.         htim->OC_MspInitCallback                = HAL_TIM_OC_MspInit;
  5671.         break;
  5672.  
  5673.       case HAL_TIM_OC_MSPDEINIT_CB_ID :
  5674.         /* Legacy weak OC Msp DeInit Callback */
  5675.         htim->OC_MspDeInitCallback              = HAL_TIM_OC_MspDeInit;
  5676.         break;
  5677.  
  5678.       case HAL_TIM_PWM_MSPINIT_CB_ID :
  5679.         /* Legacy weak PWM Msp Init Callback */
  5680.         htim->PWM_MspInitCallback               = HAL_TIM_PWM_MspInit;
  5681.         break;
  5682.  
  5683.       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
  5684.         /* Legacy weak PWM Msp DeInit Callback */
  5685.         htim->PWM_MspDeInitCallback             = HAL_TIM_PWM_MspDeInit;
  5686.         break;
  5687.  
  5688.       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
  5689.         /* Legacy weak One Pulse Msp Init Callback */
  5690.         htim->OnePulse_MspInitCallback          = HAL_TIM_OnePulse_MspInit;
  5691.         break;
  5692.  
  5693.       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
  5694.         /* Legacy weak One Pulse Msp DeInit Callback */
  5695.         htim->OnePulse_MspDeInitCallback        = HAL_TIM_OnePulse_MspDeInit;
  5696.         break;
  5697.  
  5698.       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
  5699.         /* Legacy weak Encoder Msp Init Callback */
  5700.         htim->Encoder_MspInitCallback           = HAL_TIM_Encoder_MspInit;
  5701.         break;
  5702.  
  5703.       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
  5704.         /* Legacy weak Encoder Msp DeInit Callback */
  5705.         htim->Encoder_MspDeInitCallback         = HAL_TIM_Encoder_MspDeInit;
  5706.         break;
  5707.  
  5708.       case HAL_TIM_PERIOD_ELAPSED_CB_ID :
  5709.         /* Legacy weak Period Elapsed Callback */
  5710.         htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;
  5711.         break;
  5712.  
  5713.       case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
  5714.         /* Legacy weak Period Elapsed half complete Callback */
  5715.         htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;
  5716.         break;
  5717.  
  5718.       case HAL_TIM_TRIGGER_CB_ID :
  5719.         /* Legacy weak Trigger Callback */
  5720.         htim->TriggerCallback                   = HAL_TIM_TriggerCallback;
  5721.         break;
  5722.  
  5723.       case HAL_TIM_TRIGGER_HALF_CB_ID :
  5724.         /* Legacy weak Trigger half complete Callback */
  5725.         htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;
  5726.         break;
  5727.  
  5728.       case HAL_TIM_IC_CAPTURE_CB_ID :
  5729.         /* Legacy weak IC Capture Callback */
  5730.         htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;
  5731.         break;
  5732.  
  5733.       case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
  5734.         /* Legacy weak IC Capture half complete Callback */
  5735.         htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;
  5736.         break;
  5737.  
  5738.       case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
  5739.         /* Legacy weak OC Delay Elapsed Callback */
  5740.         htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;
  5741.         break;
  5742.  
  5743.       case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
  5744.         /* Legacy weak PWM Pulse Finished Callback */
  5745.         htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;
  5746.         break;
  5747.  
  5748.       case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
  5749.         /* Legacy weak PWM Pulse Finished half complete Callback */
  5750.         htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
  5751.         break;
  5752.  
  5753.       case HAL_TIM_ERROR_CB_ID :
  5754.         /* Legacy weak Error Callback */
  5755.         htim->ErrorCallback                     = HAL_TIM_ErrorCallback;
  5756.         break;
  5757.  
  5758.       default :
  5759.         /* Return error status */
  5760.         status =  HAL_ERROR;
  5761.         break;
  5762.     }
  5763.   }
  5764.   else if (htim->State == HAL_TIM_STATE_RESET)
  5765.   {
  5766.     switch (CallbackID)
  5767.     {
  5768.       case HAL_TIM_BASE_MSPINIT_CB_ID :
  5769.         /* Legacy weak Base MspInit Callback */
  5770.         htim->Base_MspInitCallback         = HAL_TIM_Base_MspInit;
  5771.         break;
  5772.  
  5773.       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
  5774.         /* Legacy weak Base Msp DeInit Callback */
  5775.         htim->Base_MspDeInitCallback       = HAL_TIM_Base_MspDeInit;
  5776.         break;
  5777.  
  5778.       case HAL_TIM_IC_MSPINIT_CB_ID :
  5779.         /* Legacy weak IC Msp Init Callback */
  5780.         htim->IC_MspInitCallback           = HAL_TIM_IC_MspInit;
  5781.         break;
  5782.  
  5783.       case HAL_TIM_IC_MSPDEINIT_CB_ID :
  5784.         /* Legacy weak IC Msp DeInit Callback */
  5785.         htim->IC_MspDeInitCallback         = HAL_TIM_IC_MspDeInit;
  5786.         break;
  5787.  
  5788.       case HAL_TIM_OC_MSPINIT_CB_ID :
  5789.         /* Legacy weak OC Msp Init Callback */
  5790.         htim->OC_MspInitCallback           = HAL_TIM_OC_MspInit;
  5791.         break;
  5792.  
  5793.       case HAL_TIM_OC_MSPDEINIT_CB_ID :
  5794.         /* Legacy weak OC Msp DeInit Callback */
  5795.         htim->OC_MspDeInitCallback         = HAL_TIM_OC_MspDeInit;
  5796.         break;
  5797.  
  5798.       case HAL_TIM_PWM_MSPINIT_CB_ID :
  5799.         /* Legacy weak PWM Msp Init Callback */
  5800.         htim->PWM_MspInitCallback          = HAL_TIM_PWM_MspInit;
  5801.         break;
  5802.  
  5803.       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
  5804.         /* Legacy weak PWM Msp DeInit Callback */
  5805.         htim->PWM_MspDeInitCallback        = HAL_TIM_PWM_MspDeInit;
  5806.         break;
  5807.  
  5808.       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
  5809.         /* Legacy weak One Pulse Msp Init Callback */
  5810.         htim->OnePulse_MspInitCallback     = HAL_TIM_OnePulse_MspInit;
  5811.         break;
  5812.  
  5813.       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
  5814.         /* Legacy weak One Pulse Msp DeInit Callback */
  5815.         htim->OnePulse_MspDeInitCallback   = HAL_TIM_OnePulse_MspDeInit;
  5816.         break;
  5817.  
  5818.       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
  5819.         /* Legacy weak Encoder Msp Init Callback */
  5820.         htim->Encoder_MspInitCallback      = HAL_TIM_Encoder_MspInit;
  5821.         break;
  5822.  
  5823.       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
  5824.         /* Legacy weak Encoder Msp DeInit Callback */
  5825.         htim->Encoder_MspDeInitCallback    = HAL_TIM_Encoder_MspDeInit;
  5826.         break;
  5827.  
  5828.       default :
  5829.         /* Return error status */
  5830.         status =  HAL_ERROR;
  5831.         break;
  5832.     }
  5833.   }
  5834.   else
  5835.   {
  5836.     /* Return error status */
  5837.     status =  HAL_ERROR;
  5838.   }
  5839.  
  5840.   /* Release Lock */
  5841.   __HAL_UNLOCK(htim);
  5842.  
  5843.   return status;
  5844. }
  5845. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  5846.  
  5847. /**
  5848.   * @}
  5849.   */
  5850.  
  5851. /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
  5852.   *  @brief   TIM Peripheral State functions
  5853.   *
  5854. @verbatim
  5855.   ==============================================================================
  5856.                         ##### Peripheral State functions #####
  5857.   ==============================================================================
  5858.     [..]
  5859.     This subsection permits to get in run-time the status of the peripheral
  5860.     and the data flow.
  5861.  
  5862. @endverbatim
  5863.   * @{
  5864.   */
  5865.  
  5866. /**
  5867.   * @brief  Return the TIM Base handle state.
  5868.   * @param  htim TIM Base handle
  5869.   * @retval HAL state
  5870.   */
  5871. HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
  5872. {
  5873.   return htim->State;
  5874. }
  5875.  
  5876. /**
  5877.   * @brief  Return the TIM OC handle state.
  5878.   * @param  htim TIM Output Compare handle
  5879.   * @retval HAL state
  5880.   */
  5881. HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
  5882. {
  5883.   return htim->State;
  5884. }
  5885.  
  5886. /**
  5887.   * @brief  Return the TIM PWM handle state.
  5888.   * @param  htim TIM handle
  5889.   * @retval HAL state
  5890.   */
  5891. HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
  5892. {
  5893.   return htim->State;
  5894. }
  5895.  
  5896. /**
  5897.   * @brief  Return the TIM Input Capture handle state.
  5898.   * @param  htim TIM IC handle
  5899.   * @retval HAL state
  5900.   */
  5901. HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
  5902. {
  5903.   return htim->State;
  5904. }
  5905.  
  5906. /**
  5907.   * @brief  Return the TIM One Pulse Mode handle state.
  5908.   * @param  htim TIM OPM handle
  5909.   * @retval HAL state
  5910.   */
  5911. HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
  5912. {
  5913.   return htim->State;
  5914. }
  5915.  
  5916. /**
  5917.   * @brief  Return the TIM Encoder Mode handle state.
  5918.   * @param  htim TIM Encoder Interface handle
  5919.   * @retval HAL state
  5920.   */
  5921. HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
  5922. {
  5923.   return htim->State;
  5924. }
  5925.  
  5926. /**
  5927.   * @brief  Return the TIM Encoder Mode handle state.
  5928.   * @param  htim TIM handle
  5929.   * @retval Active channel
  5930.   */
  5931. HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim)
  5932. {
  5933.   return htim->Channel;
  5934. }
  5935.  
  5936. /**
  5937.   * @brief  Return actual state of the TIM channel.
  5938.   * @param  htim TIM handle
  5939.   * @param  Channel TIM Channel
  5940.   *          This parameter can be one of the following values:
  5941.   *            @arg TIM_CHANNEL_1: TIM Channel 1
  5942.   *            @arg TIM_CHANNEL_2: TIM Channel 2
  5943.   *            @arg TIM_CHANNEL_3: TIM Channel 3
  5944.   *            @arg TIM_CHANNEL_4: TIM Channel 4
  5945.   *            @arg TIM_CHANNEL_5: TIM Channel 5
  5946.   *            @arg TIM_CHANNEL_6: TIM Channel 6
  5947.   * @retval TIM Channel state
  5948.   */
  5949. HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim,  uint32_t Channel)
  5950. {
  5951.   HAL_TIM_ChannelStateTypeDef channel_state;
  5952.  
  5953.   /* Check the parameters */
  5954.   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
  5955.  
  5956.   channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
  5957.  
  5958.   return channel_state;
  5959. }
  5960.  
  5961. /**
  5962.   * @brief  Return actual state of a DMA burst operation.
  5963.   * @param  htim TIM handle
  5964.   * @retval DMA burst state
  5965.   */
  5966. HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim)
  5967. {
  5968.   /* Check the parameters */
  5969.   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
  5970.  
  5971.   return htim->DMABurstState;
  5972. }
  5973.  
  5974. /**
  5975.   * @}
  5976.   */
  5977.  
  5978. /**
  5979.   * @}
  5980.   */
  5981.  
  5982. /** @defgroup TIM_Private_Functions TIM Private Functions
  5983.   * @{
  5984.   */
  5985.  
  5986. /**
  5987.   * @brief  TIM DMA error callback
  5988.   * @param  hdma pointer to DMA handle.
  5989.   * @retval None
  5990.   */
  5991. void TIM_DMAError(DMA_HandleTypeDef *hdma)
  5992. {
  5993.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  5994.  
  5995.   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
  5996.   {
  5997.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  5998.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  5999.   }
  6000.   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
  6001.   {
  6002.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  6003.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  6004.   }
  6005.   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
  6006.   {
  6007.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  6008.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
  6009.   }
  6010.   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
  6011.   {
  6012.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  6013.     TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
  6014.   }
  6015.   else
  6016.   {
  6017.     htim->State = HAL_TIM_STATE_READY;
  6018.   }
  6019.  
  6020. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6021.   htim->ErrorCallback(htim);
  6022. #else
  6023.   HAL_TIM_ErrorCallback(htim);
  6024. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6025.  
  6026.   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  6027. }
  6028.  
  6029. /**
  6030.   * @brief  TIM DMA Delay Pulse complete callback.
  6031.   * @param  hdma pointer to DMA handle.
  6032.   * @retval None
  6033.   */
  6034. static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
  6035. {
  6036.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6037.  
  6038.   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
  6039.   {
  6040.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  6041.  
  6042.     if (hdma->Init.Mode == DMA_NORMAL)
  6043.     {
  6044.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  6045.     }
  6046.   }
  6047.   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
  6048.   {
  6049.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  6050.  
  6051.     if (hdma->Init.Mode == DMA_NORMAL)
  6052.     {
  6053.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  6054.     }
  6055.   }
  6056.   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
  6057.   {
  6058.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  6059.  
  6060.     if (hdma->Init.Mode == DMA_NORMAL)
  6061.     {
  6062.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
  6063.     }
  6064.   }
  6065.   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
  6066.   {
  6067.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  6068.  
  6069.     if (hdma->Init.Mode == DMA_NORMAL)
  6070.     {
  6071.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
  6072.     }
  6073.   }
  6074.   else
  6075.   {
  6076.     /* nothing to do */
  6077.   }
  6078.  
  6079. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6080.   htim->PWM_PulseFinishedCallback(htim);
  6081. #else
  6082.   HAL_TIM_PWM_PulseFinishedCallback(htim);
  6083. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6084.  
  6085.   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  6086. }
  6087.  
  6088. /**
  6089.   * @brief  TIM DMA Delay Pulse half complete callback.
  6090.   * @param  hdma pointer to DMA handle.
  6091.   * @retval None
  6092.   */
  6093. static void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
  6094. {
  6095.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6096.  
  6097.   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
  6098.   {
  6099.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  6100.   }
  6101.   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
  6102.   {
  6103.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  6104.   }
  6105.   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
  6106.   {
  6107.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  6108.   }
  6109.   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
  6110.   {
  6111.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  6112.   }
  6113.   else
  6114.   {
  6115.     /* nothing to do */
  6116.   }
  6117.  
  6118. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6119.   htim->PWM_PulseFinishedHalfCpltCallback(htim);
  6120. #else
  6121.   HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
  6122. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6123.  
  6124.   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  6125. }
  6126.  
  6127. /**
  6128.   * @brief  TIM DMA Capture complete callback.
  6129.   * @param  hdma pointer to DMA handle.
  6130.   * @retval None
  6131.   */
  6132. void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
  6133. {
  6134.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6135.  
  6136.   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
  6137.   {
  6138.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  6139.  
  6140.     if (hdma->Init.Mode == DMA_NORMAL)
  6141.     {
  6142.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
  6143.     }
  6144.   }
  6145.   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
  6146.   {
  6147.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  6148.  
  6149.     if (hdma->Init.Mode == DMA_NORMAL)
  6150.     {
  6151.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
  6152.     }
  6153.   }
  6154.   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
  6155.   {
  6156.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  6157.  
  6158.     if (hdma->Init.Mode == DMA_NORMAL)
  6159.     {
  6160.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
  6161.     }
  6162.   }
  6163.   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
  6164.   {
  6165.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  6166.  
  6167.     if (hdma->Init.Mode == DMA_NORMAL)
  6168.     {
  6169.       TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
  6170.     }
  6171.   }
  6172.   else
  6173.   {
  6174.     /* nothing to do */
  6175.   }
  6176.  
  6177. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6178.   htim->IC_CaptureCallback(htim);
  6179. #else
  6180.   HAL_TIM_IC_CaptureCallback(htim);
  6181. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6182.  
  6183.   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  6184. }
  6185.  
  6186. /**
  6187.   * @brief  TIM DMA Capture half complete callback.
  6188.   * @param  hdma pointer to DMA handle.
  6189.   * @retval None
  6190.   */
  6191. void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
  6192. {
  6193.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6194.  
  6195.   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
  6196.   {
  6197.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  6198.   }
  6199.   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
  6200.   {
  6201.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  6202.   }
  6203.   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
  6204.   {
  6205.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  6206.   }
  6207.   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
  6208.   {
  6209.     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  6210.   }
  6211.   else
  6212.   {
  6213.     /* nothing to do */
  6214.   }
  6215.  
  6216. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6217.   htim->IC_CaptureHalfCpltCallback(htim);
  6218. #else
  6219.   HAL_TIM_IC_CaptureHalfCpltCallback(htim);
  6220. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6221.  
  6222.   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  6223. }
  6224.  
  6225. /**
  6226.   * @brief  TIM DMA Period Elapse complete callback.
  6227.   * @param  hdma pointer to DMA handle.
  6228.   * @retval None
  6229.   */
  6230. static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
  6231. {
  6232.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6233.  
  6234.   if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
  6235.   {
  6236.     htim->State = HAL_TIM_STATE_READY;
  6237.   }
  6238.  
  6239. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6240.   htim->PeriodElapsedCallback(htim);
  6241. #else
  6242.   HAL_TIM_PeriodElapsedCallback(htim);
  6243. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6244. }
  6245.  
  6246. /**
  6247.   * @brief  TIM DMA Period Elapse half complete callback.
  6248.   * @param  hdma pointer to DMA handle.
  6249.   * @retval None
  6250.   */
  6251. static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
  6252. {
  6253.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6254.  
  6255. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6256.   htim->PeriodElapsedHalfCpltCallback(htim);
  6257. #else
  6258.   HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
  6259. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6260. }
  6261.  
  6262. /**
  6263.   * @brief  TIM DMA Trigger callback.
  6264.   * @param  hdma pointer to DMA handle.
  6265.   * @retval None
  6266.   */
  6267. static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
  6268. {
  6269.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6270.  
  6271.   if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)
  6272.   {
  6273.     htim->State = HAL_TIM_STATE_READY;
  6274.   }
  6275.  
  6276. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6277.   htim->TriggerCallback(htim);
  6278. #else
  6279.   HAL_TIM_TriggerCallback(htim);
  6280. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6281. }
  6282.  
  6283. /**
  6284.   * @brief  TIM DMA Trigger half complete callback.
  6285.   * @param  hdma pointer to DMA handle.
  6286.   * @retval None
  6287.   */
  6288. static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
  6289. {
  6290.   TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  6291.  
  6292. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  6293.   htim->TriggerHalfCpltCallback(htim);
  6294. #else
  6295.   HAL_TIM_TriggerHalfCpltCallback(htim);
  6296. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  6297. }
  6298.  
  6299. /**
  6300.   * @brief  Time Base configuration
  6301.   * @param  TIMx TIM peripheral
  6302.   * @param  Structure TIM Base configuration structure
  6303.   * @retval None
  6304.   */
  6305. static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
  6306. {
  6307.   uint32_t tmpcr1;
  6308.   tmpcr1 = TIMx->CR1;
  6309.  
  6310.   /* Set TIM Time Base Unit parameters ---------------------------------------*/
  6311.   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
  6312.   {
  6313.     /* Select the Counter Mode */
  6314.     tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
  6315.     tmpcr1 |= Structure->CounterMode;
  6316.   }
  6317.  
  6318.   if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
  6319.   {
  6320.     /* Set the clock division */
  6321.     tmpcr1 &= ~TIM_CR1_CKD;
  6322.     tmpcr1 |= (uint32_t)Structure->ClockDivision;
  6323.   }
  6324.  
  6325.   /* Set the auto-reload preload */
  6326.   MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
  6327.  
  6328.   TIMx->CR1 = tmpcr1;
  6329.  
  6330.   /* Set the Autoreload value */
  6331.   TIMx->ARR = (uint32_t)Structure->Period ;
  6332.  
  6333.   /* Set the Prescaler value */
  6334.   TIMx->PSC = Structure->Prescaler;
  6335.  
  6336.   /* Generate an update event to reload the Prescaler
  6337.      and the repetition counter (only for advanced timer) value immediately */
  6338.   TIMx->EGR = TIM_EGR_UG;
  6339. }
  6340.  
  6341. /**
  6342.   * @brief  Timer Output Compare 1 configuration
  6343.   * @param  TIMx to select the TIM peripheral
  6344.   * @param  OC_Config The output configuration structure
  6345.   * @retval None
  6346.   */
  6347. static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
  6348. {
  6349.   uint32_t tmpccmrx;
  6350.   uint32_t tmpccer;
  6351.   uint32_t tmpcr2;
  6352.  
  6353.   /* Disable the Channel 1: Reset the CC1E Bit */
  6354.   TIMx->CCER &= ~TIM_CCER_CC1E;
  6355.  
  6356.   /* Get the TIMx CCER register value */
  6357.   tmpccer = TIMx->CCER;
  6358.   /* Get the TIMx CR2 register value */
  6359.   tmpcr2 =  TIMx->CR2;
  6360.  
  6361.   /* Get the TIMx CCMR1 register value */
  6362.   tmpccmrx = TIMx->CCMR1;
  6363.  
  6364.   /* Reset the Output Compare Mode Bits */
  6365.   tmpccmrx &= ~TIM_CCMR1_OC1M;
  6366.   tmpccmrx &= ~TIM_CCMR1_CC1S;
  6367.   /* Select the Output Compare Mode */
  6368.   tmpccmrx |= OC_Config->OCMode;
  6369.  
  6370.   /* Reset the Output Polarity level */
  6371.   tmpccer &= ~TIM_CCER_CC1P;
  6372.   /* Set the Output Compare Polarity */
  6373.   tmpccer |= OC_Config->OCPolarity;
  6374.  
  6375.   /* Write to TIMx CR2 */
  6376.   TIMx->CR2 = tmpcr2;
  6377.  
  6378.   /* Write to TIMx CCMR1 */
  6379.   TIMx->CCMR1 = tmpccmrx;
  6380.  
  6381.   /* Set the Capture Compare Register value */
  6382.   TIMx->CCR1 = OC_Config->Pulse;
  6383.  
  6384.   /* Write to TIMx CCER */
  6385.   TIMx->CCER = tmpccer;
  6386. }
  6387.  
  6388. /**
  6389.   * @brief  Timer Output Compare 2 configuration
  6390.   * @param  TIMx to select the TIM peripheral
  6391.   * @param  OC_Config The output configuration structure
  6392.   * @retval None
  6393.   */
  6394. static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
  6395. {
  6396.   uint32_t tmpccmrx;
  6397.   uint32_t tmpccer;
  6398.   uint32_t tmpcr2;
  6399.  
  6400.   /* Disable the Channel 2: Reset the CC2E Bit */
  6401.   TIMx->CCER &= ~TIM_CCER_CC2E;
  6402.  
  6403.   /* Get the TIMx CCER register value */
  6404.   tmpccer = TIMx->CCER;
  6405.   /* Get the TIMx CR2 register value */
  6406.   tmpcr2 =  TIMx->CR2;
  6407.  
  6408.   /* Get the TIMx CCMR1 register value */
  6409.   tmpccmrx = TIMx->CCMR1;
  6410.  
  6411.   /* Reset the Output Compare mode and Capture/Compare selection Bits */
  6412.   tmpccmrx &= ~TIM_CCMR1_OC2M;
  6413.   tmpccmrx &= ~TIM_CCMR1_CC2S;
  6414.  
  6415.   /* Select the Output Compare Mode */
  6416.   tmpccmrx |= (OC_Config->OCMode << 8U);
  6417.  
  6418.   /* Reset the Output Polarity level */
  6419.   tmpccer &= ~TIM_CCER_CC2P;
  6420.   /* Set the Output Compare Polarity */
  6421.   tmpccer |= (OC_Config->OCPolarity << 4U);
  6422.  
  6423.   /* Write to TIMx CR2 */
  6424.   TIMx->CR2 = tmpcr2;
  6425.  
  6426.   /* Write to TIMx CCMR1 */
  6427.   TIMx->CCMR1 = tmpccmrx;
  6428.  
  6429.   /* Set the Capture Compare Register value */
  6430.   TIMx->CCR2 = OC_Config->Pulse;
  6431.  
  6432.   /* Write to TIMx CCER */
  6433.   TIMx->CCER = tmpccer;
  6434. }
  6435.  
  6436. /**
  6437.   * @brief  Timer Output Compare 3 configuration
  6438.   * @param  TIMx to select the TIM peripheral
  6439.   * @param  OC_Config The output configuration structure
  6440.   * @retval None
  6441.   */
  6442. static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
  6443. {
  6444.   uint32_t tmpccmrx;
  6445.   uint32_t tmpccer;
  6446.   uint32_t tmpcr2;
  6447.  
  6448.   /* Disable the Channel 3: Reset the CC2E Bit */
  6449.   TIMx->CCER &= ~TIM_CCER_CC3E;
  6450.  
  6451.   /* Get the TIMx CCER register value */
  6452.   tmpccer = TIMx->CCER;
  6453.   /* Get the TIMx CR2 register value */
  6454.   tmpcr2 =  TIMx->CR2;
  6455.  
  6456.   /* Get the TIMx CCMR2 register value */
  6457.   tmpccmrx = TIMx->CCMR2;
  6458.  
  6459.   /* Reset the Output Compare mode and Capture/Compare selection Bits */
  6460.   tmpccmrx &= ~TIM_CCMR2_OC3M;
  6461.   tmpccmrx &= ~TIM_CCMR2_CC3S;
  6462.   /* Select the Output Compare Mode */
  6463.   tmpccmrx |= OC_Config->OCMode;
  6464.  
  6465.   /* Reset the Output Polarity level */
  6466.   tmpccer &= ~TIM_CCER_CC3P;
  6467.   /* Set the Output Compare Polarity */
  6468.   tmpccer |= (OC_Config->OCPolarity << 8U);
  6469.  
  6470.   /* Write to TIMx CR2 */
  6471.   TIMx->CR2 = tmpcr2;
  6472.  
  6473.   /* Write to TIMx CCMR2 */
  6474.   TIMx->CCMR2 = tmpccmrx;
  6475.  
  6476.   /* Set the Capture Compare Register value */
  6477.   TIMx->CCR3 = OC_Config->Pulse;
  6478.  
  6479.   /* Write to TIMx CCER */
  6480.   TIMx->CCER = tmpccer;
  6481. }
  6482.  
  6483. /**
  6484.   * @brief  Timer Output Compare 4 configuration
  6485.   * @param  TIMx to select the TIM peripheral
  6486.   * @param  OC_Config The output configuration structure
  6487.   * @retval None
  6488.   */
  6489. static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
  6490. {
  6491.   uint32_t tmpccmrx;
  6492.   uint32_t tmpccer;
  6493.   uint32_t tmpcr2;
  6494.  
  6495.   /* Disable the Channel 4: Reset the CC4E Bit */
  6496.   TIMx->CCER &= ~TIM_CCER_CC4E;
  6497.  
  6498.   /* Get the TIMx CCER register value */
  6499.   tmpccer = TIMx->CCER;
  6500.   /* Get the TIMx CR2 register value */
  6501.   tmpcr2 =  TIMx->CR2;
  6502.  
  6503.   /* Get the TIMx CCMR2 register value */
  6504.   tmpccmrx = TIMx->CCMR2;
  6505.  
  6506.   /* Reset the Output Compare mode and Capture/Compare selection Bits */
  6507.   tmpccmrx &= ~TIM_CCMR2_OC4M;
  6508.   tmpccmrx &= ~TIM_CCMR2_CC4S;
  6509.  
  6510.   /* Select the Output Compare Mode */
  6511.   tmpccmrx |= (OC_Config->OCMode << 8U);
  6512.  
  6513.   /* Reset the Output Polarity level */
  6514.   tmpccer &= ~TIM_CCER_CC4P;
  6515.   /* Set the Output Compare Polarity */
  6516.   tmpccer |= (OC_Config->OCPolarity << 12U);
  6517.  
  6518.   /* Write to TIMx CR2 */
  6519.   TIMx->CR2 = tmpcr2;
  6520.  
  6521.   /* Write to TIMx CCMR2 */
  6522.   TIMx->CCMR2 = tmpccmrx;
  6523.  
  6524.   /* Set the Capture Compare Register value */
  6525.   TIMx->CCR4 = OC_Config->Pulse;
  6526.  
  6527.   /* Write to TIMx CCER */
  6528.   TIMx->CCER = tmpccer;
  6529. }
  6530.  
  6531. /**
  6532.   * @brief  Slave Timer configuration function
  6533.   * @param  htim TIM handle
  6534.   * @param  sSlaveConfig Slave timer configuration
  6535.   * @retval None
  6536.   */
  6537. static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
  6538.                                                   TIM_SlaveConfigTypeDef *sSlaveConfig)
  6539. {
  6540.   uint32_t tmpsmcr;
  6541.   uint32_t tmpccmr1;
  6542.   uint32_t tmpccer;
  6543.  
  6544.   /* Get the TIMx SMCR register value */
  6545.   tmpsmcr = htim->Instance->SMCR;
  6546.  
  6547.   /* Reset the Trigger Selection Bits */
  6548.   tmpsmcr &= ~TIM_SMCR_TS;
  6549.   /* Set the Input Trigger source */
  6550.   tmpsmcr |= sSlaveConfig->InputTrigger;
  6551.  
  6552.   /* Reset the slave mode Bits */
  6553.   tmpsmcr &= ~TIM_SMCR_SMS;
  6554.   /* Set the slave mode */
  6555.   tmpsmcr |= sSlaveConfig->SlaveMode;
  6556.  
  6557.   /* Write to TIMx SMCR */
  6558.   htim->Instance->SMCR = tmpsmcr;
  6559.  
  6560.   /* Configure the trigger prescaler, filter, and polarity */
  6561.   switch (sSlaveConfig->InputTrigger)
  6562.   {
  6563.     case TIM_TS_ETRF:
  6564.     {
  6565.       /* Check the parameters */
  6566.       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
  6567.       assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
  6568.       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
  6569.       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
  6570.       /* Configure the ETR Trigger source */
  6571.       TIM_ETR_SetConfig(htim->Instance,
  6572.                         sSlaveConfig->TriggerPrescaler,
  6573.                         sSlaveConfig->TriggerPolarity,
  6574.                         sSlaveConfig->TriggerFilter);
  6575.       break;
  6576.     }
  6577.  
  6578.     case TIM_TS_TI1F_ED:
  6579.     {
  6580.       /* Check the parameters */
  6581.       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  6582.       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
  6583.  
  6584.       if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
  6585.       {
  6586.         return HAL_ERROR;
  6587.       }
  6588.  
  6589.       /* Disable the Channel 1: Reset the CC1E Bit */
  6590.       tmpccer = htim->Instance->CCER;
  6591.       htim->Instance->CCER &= ~TIM_CCER_CC1E;
  6592.       tmpccmr1 = htim->Instance->CCMR1;
  6593.  
  6594.       /* Set the filter */
  6595.       tmpccmr1 &= ~TIM_CCMR1_IC1F;
  6596.       tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
  6597.  
  6598.       /* Write to TIMx CCMR1 and CCER registers */
  6599.       htim->Instance->CCMR1 = tmpccmr1;
  6600.       htim->Instance->CCER = tmpccer;
  6601.       break;
  6602.     }
  6603.  
  6604.     case TIM_TS_TI1FP1:
  6605.     {
  6606.       /* Check the parameters */
  6607.       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
  6608.       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
  6609.       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
  6610.  
  6611.       /* Configure TI1 Filter and Polarity */
  6612.       TIM_TI1_ConfigInputStage(htim->Instance,
  6613.                                sSlaveConfig->TriggerPolarity,
  6614.                                sSlaveConfig->TriggerFilter);
  6615.       break;
  6616.     }
  6617.  
  6618.     case TIM_TS_TI2FP2:
  6619.     {
  6620.       /* Check the parameters */
  6621.       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  6622.       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
  6623.       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
  6624.  
  6625.       /* Configure TI2 Filter and Polarity */
  6626.       TIM_TI2_ConfigInputStage(htim->Instance,
  6627.                                sSlaveConfig->TriggerPolarity,
  6628.                                sSlaveConfig->TriggerFilter);
  6629.       break;
  6630.     }
  6631.  
  6632.     case TIM_TS_ITR0:
  6633.     case TIM_TS_ITR1:
  6634.     case TIM_TS_ITR2:
  6635.     case TIM_TS_ITR3:
  6636.       {
  6637.         /* Check the parameter */
  6638.         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
  6639.         break;
  6640.       }
  6641.  
  6642.     default:
  6643.       break;
  6644.   }
  6645.   return HAL_OK;
  6646. }
  6647.  
  6648. /**
  6649.   * @brief  Configure the TI1 as Input.
  6650.   * @param  TIMx to select the TIM peripheral.
  6651.   * @param  TIM_ICPolarity The Input Polarity.
  6652.   *          This parameter can be one of the following values:
  6653.   *            @arg TIM_ICPOLARITY_RISING
  6654.   *            @arg TIM_ICPOLARITY_FALLING
  6655.   *            @arg TIM_ICPOLARITY_BOTHEDGE
  6656.   * @param  TIM_ICSelection specifies the input to be used.
  6657.   *          This parameter can be one of the following values:
  6658.   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
  6659.   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
  6660.   *            @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
  6661.   * @param  TIM_ICFilter Specifies the Input Capture Filter.
  6662.   *          This parameter must be a value between 0x00 and 0x0F.
  6663.   * @retval None
  6664.   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
  6665.   *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be
  6666.   *        protected against un-initialized filter and polarity values.
  6667.   */
  6668. static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
  6669.                               uint32_t TIM_ICFilter)
  6670. {
  6671.   uint32_t tmpccmr1;
  6672.   uint32_t tmpccer;
  6673.  
  6674.   /* Disable the Channel 1: Reset the CC1E Bit */
  6675.   TIMx->CCER &= ~TIM_CCER_CC1E;
  6676.   tmpccmr1 = TIMx->CCMR1;
  6677.   tmpccer = TIMx->CCER;
  6678.  
  6679.   /* Select the Input */
  6680.   if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
  6681.   {
  6682.     tmpccmr1 &= ~TIM_CCMR1_CC1S;
  6683.     tmpccmr1 |= TIM_ICSelection;
  6684.   }
  6685.   else
  6686.   {
  6687.     tmpccmr1 |= TIM_CCMR1_CC1S_0;
  6688.   }
  6689.  
  6690.   /* Set the filter */
  6691.   tmpccmr1 &= ~TIM_CCMR1_IC1F;
  6692.   tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
  6693.  
  6694.   /* Select the Polarity and set the CC1E Bit */
  6695.   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
  6696.   tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
  6697.  
  6698.   /* Write to TIMx CCMR1 and CCER registers */
  6699.   TIMx->CCMR1 = tmpccmr1;
  6700.   TIMx->CCER = tmpccer;
  6701. }
  6702.  
  6703. /**
  6704.   * @brief  Configure the Polarity and Filter for TI1.
  6705.   * @param  TIMx to select the TIM peripheral.
  6706.   * @param  TIM_ICPolarity The Input Polarity.
  6707.   *          This parameter can be one of the following values:
  6708.   *            @arg TIM_ICPOLARITY_RISING
  6709.   *            @arg TIM_ICPOLARITY_FALLING
  6710.   *            @arg TIM_ICPOLARITY_BOTHEDGE
  6711.   * @param  TIM_ICFilter Specifies the Input Capture Filter.
  6712.   *          This parameter must be a value between 0x00 and 0x0F.
  6713.   * @retval None
  6714.   */
  6715. static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
  6716. {
  6717.   uint32_t tmpccmr1;
  6718.   uint32_t tmpccer;
  6719.  
  6720.   /* Disable the Channel 1: Reset the CC1E Bit */
  6721.   tmpccer = TIMx->CCER;
  6722.   TIMx->CCER &= ~TIM_CCER_CC1E;
  6723.   tmpccmr1 = TIMx->CCMR1;
  6724.  
  6725.   /* Set the filter */
  6726.   tmpccmr1 &= ~TIM_CCMR1_IC1F;
  6727.   tmpccmr1 |= (TIM_ICFilter << 4U);
  6728.  
  6729.   /* Select the Polarity and set the CC1E Bit */
  6730.   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
  6731.   tmpccer |= TIM_ICPolarity;
  6732.  
  6733.   /* Write to TIMx CCMR1 and CCER registers */
  6734.   TIMx->CCMR1 = tmpccmr1;
  6735.   TIMx->CCER = tmpccer;
  6736. }
  6737.  
  6738. /**
  6739.   * @brief  Configure the TI2 as Input.
  6740.   * @param  TIMx to select the TIM peripheral
  6741.   * @param  TIM_ICPolarity The Input Polarity.
  6742.   *          This parameter can be one of the following values:
  6743.   *            @arg TIM_ICPOLARITY_RISING
  6744.   *            @arg TIM_ICPOLARITY_FALLING
  6745.   *            @arg TIM_ICPOLARITY_BOTHEDGE
  6746.   * @param  TIM_ICSelection specifies the input to be used.
  6747.   *          This parameter can be one of the following values:
  6748.   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
  6749.   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
  6750.   *            @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
  6751.   * @param  TIM_ICFilter Specifies the Input Capture Filter.
  6752.   *          This parameter must be a value between 0x00 and 0x0F.
  6753.   * @retval None
  6754.   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
  6755.   *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be
  6756.   *        protected against un-initialized filter and polarity values.
  6757.   */
  6758. static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
  6759.                               uint32_t TIM_ICFilter)
  6760. {
  6761.   uint32_t tmpccmr1;
  6762.   uint32_t tmpccer;
  6763.  
  6764.   /* Disable the Channel 2: Reset the CC2E Bit */
  6765.   TIMx->CCER &= ~TIM_CCER_CC2E;
  6766.   tmpccmr1 = TIMx->CCMR1;
  6767.   tmpccer = TIMx->CCER;
  6768.  
  6769.   /* Select the Input */
  6770.   tmpccmr1 &= ~TIM_CCMR1_CC2S;
  6771.   tmpccmr1 |= (TIM_ICSelection << 8U);
  6772.  
  6773.   /* Set the filter */
  6774.   tmpccmr1 &= ~TIM_CCMR1_IC2F;
  6775.   tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
  6776.  
  6777.   /* Select the Polarity and set the CC2E Bit */
  6778.   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
  6779.   tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
  6780.  
  6781.   /* Write to TIMx CCMR1 and CCER registers */
  6782.   TIMx->CCMR1 = tmpccmr1 ;
  6783.   TIMx->CCER = tmpccer;
  6784. }
  6785.  
  6786. /**
  6787.   * @brief  Configure the Polarity and Filter for TI2.
  6788.   * @param  TIMx to select the TIM peripheral.
  6789.   * @param  TIM_ICPolarity The Input Polarity.
  6790.   *          This parameter can be one of the following values:
  6791.   *            @arg TIM_ICPOLARITY_RISING
  6792.   *            @arg TIM_ICPOLARITY_FALLING
  6793.   *            @arg TIM_ICPOLARITY_BOTHEDGE
  6794.   * @param  TIM_ICFilter Specifies the Input Capture Filter.
  6795.   *          This parameter must be a value between 0x00 and 0x0F.
  6796.   * @retval None
  6797.   */
  6798. static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
  6799. {
  6800.   uint32_t tmpccmr1;
  6801.   uint32_t tmpccer;
  6802.  
  6803.   /* Disable the Channel 2: Reset the CC2E Bit */
  6804.   TIMx->CCER &= ~TIM_CCER_CC2E;
  6805.   tmpccmr1 = TIMx->CCMR1;
  6806.   tmpccer = TIMx->CCER;
  6807.  
  6808.   /* Set the filter */
  6809.   tmpccmr1 &= ~TIM_CCMR1_IC2F;
  6810.   tmpccmr1 |= (TIM_ICFilter << 12U);
  6811.  
  6812.   /* Select the Polarity and set the CC2E Bit */
  6813.   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
  6814.   tmpccer |= (TIM_ICPolarity << 4U);
  6815.  
  6816.   /* Write to TIMx CCMR1 and CCER registers */
  6817.   TIMx->CCMR1 = tmpccmr1 ;
  6818.   TIMx->CCER = tmpccer;
  6819. }
  6820.  
  6821. /**
  6822.   * @brief  Configure the TI3 as Input.
  6823.   * @param  TIMx to select the TIM peripheral
  6824.   * @param  TIM_ICPolarity The Input Polarity.
  6825.   *          This parameter can be one of the following values:
  6826.   *            @arg TIM_ICPOLARITY_RISING
  6827.   *            @arg TIM_ICPOLARITY_FALLING
  6828.   *            @arg TIM_ICPOLARITY_BOTHEDGE
  6829.   * @param  TIM_ICSelection specifies the input to be used.
  6830.   *          This parameter can be one of the following values:
  6831.   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
  6832.   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
  6833.   *            @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
  6834.   * @param  TIM_ICFilter Specifies the Input Capture Filter.
  6835.   *          This parameter must be a value between 0x00 and 0x0F.
  6836.   * @retval None
  6837.   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
  6838.   *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
  6839.   *        protected against un-initialized filter and polarity values.
  6840.   */
  6841. static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
  6842.                               uint32_t TIM_ICFilter)
  6843. {
  6844.   uint32_t tmpccmr2;
  6845.   uint32_t tmpccer;
  6846.  
  6847.   /* Disable the Channel 3: Reset the CC3E Bit */
  6848.   TIMx->CCER &= ~TIM_CCER_CC3E;
  6849.   tmpccmr2 = TIMx->CCMR2;
  6850.   tmpccer = TIMx->CCER;
  6851.  
  6852.   /* Select the Input */
  6853.   tmpccmr2 &= ~TIM_CCMR2_CC3S;
  6854.   tmpccmr2 |= TIM_ICSelection;
  6855.  
  6856.   /* Set the filter */
  6857.   tmpccmr2 &= ~TIM_CCMR2_IC3F;
  6858.   tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
  6859.  
  6860.   /* Select the Polarity and set the CC3E Bit */
  6861.   tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
  6862.   tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
  6863.  
  6864.   /* Write to TIMx CCMR2 and CCER registers */
  6865.   TIMx->CCMR2 = tmpccmr2;
  6866.   TIMx->CCER = tmpccer;
  6867. }
  6868.  
  6869. /**
  6870.   * @brief  Configure the TI4 as Input.
  6871.   * @param  TIMx to select the TIM peripheral
  6872.   * @param  TIM_ICPolarity The Input Polarity.
  6873.   *          This parameter can be one of the following values:
  6874.   *            @arg TIM_ICPOLARITY_RISING
  6875.   *            @arg TIM_ICPOLARITY_FALLING
  6876.   *            @arg TIM_ICPOLARITY_BOTHEDGE
  6877.   * @param  TIM_ICSelection specifies the input to be used.
  6878.   *          This parameter can be one of the following values:
  6879.   *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
  6880.   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
  6881.   *            @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
  6882.   * @param  TIM_ICFilter Specifies the Input Capture Filter.
  6883.   *          This parameter must be a value between 0x00 and 0x0F.
  6884.   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
  6885.   *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
  6886.   *        protected against un-initialized filter and polarity values.
  6887.   * @retval None
  6888.   */
  6889. static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
  6890.                               uint32_t TIM_ICFilter)
  6891. {
  6892.   uint32_t tmpccmr2;
  6893.   uint32_t tmpccer;
  6894.  
  6895.   /* Disable the Channel 4: Reset the CC4E Bit */
  6896.   TIMx->CCER &= ~TIM_CCER_CC4E;
  6897.   tmpccmr2 = TIMx->CCMR2;
  6898.   tmpccer = TIMx->CCER;
  6899.  
  6900.   /* Select the Input */
  6901.   tmpccmr2 &= ~TIM_CCMR2_CC4S;
  6902.   tmpccmr2 |= (TIM_ICSelection << 8U);
  6903.  
  6904.   /* Set the filter */
  6905.   tmpccmr2 &= ~TIM_CCMR2_IC4F;
  6906.   tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
  6907.  
  6908.   /* Select the Polarity and set the CC4E Bit */
  6909.   tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
  6910.   tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
  6911.  
  6912.   /* Write to TIMx CCMR2 and CCER registers */
  6913.   TIMx->CCMR2 = tmpccmr2;
  6914.   TIMx->CCER = tmpccer ;
  6915. }
  6916.  
  6917. /**
  6918.   * @brief  Selects the Input Trigger source
  6919.   * @param  TIMx to select the TIM peripheral
  6920.   * @param  InputTriggerSource The Input Trigger source.
  6921.   *          This parameter can be one of the following values:
  6922.   *            @arg TIM_TS_ITR0: Internal Trigger 0
  6923.   *            @arg TIM_TS_ITR1: Internal Trigger 1
  6924.   *            @arg TIM_TS_ITR2: Internal Trigger 2
  6925.   *            @arg TIM_TS_ITR3: Internal Trigger 3
  6926.   *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
  6927.   *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
  6928.   *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
  6929.   *            @arg TIM_TS_ETRF: External Trigger input
  6930.   * @retval None
  6931.   */
  6932. static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
  6933. {
  6934.   uint32_t tmpsmcr;
  6935.  
  6936.   /* Get the TIMx SMCR register value */
  6937.   tmpsmcr = TIMx->SMCR;
  6938.   /* Reset the TS Bits */
  6939.   tmpsmcr &= ~TIM_SMCR_TS;
  6940.   /* Set the Input Trigger source and the slave mode*/
  6941.   tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
  6942.   /* Write to TIMx SMCR */
  6943.   TIMx->SMCR = tmpsmcr;
  6944. }
  6945. /**
  6946.   * @brief  Configures the TIMx External Trigger (ETR).
  6947.   * @param  TIMx to select the TIM peripheral
  6948.   * @param  TIM_ExtTRGPrescaler The external Trigger Prescaler.
  6949.   *          This parameter can be one of the following values:
  6950.   *            @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
  6951.   *            @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
  6952.   *            @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
  6953.   *            @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
  6954.   * @param  TIM_ExtTRGPolarity The external Trigger Polarity.
  6955.   *          This parameter can be one of the following values:
  6956.   *            @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
  6957.   *            @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
  6958.   * @param  ExtTRGFilter External Trigger Filter.
  6959.   *          This parameter must be a value between 0x00 and 0x0F
  6960.   * @retval None
  6961.   */
  6962. static void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
  6963.                               uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
  6964. {
  6965.   uint32_t tmpsmcr;
  6966.  
  6967.   tmpsmcr = TIMx->SMCR;
  6968.  
  6969.   /* Reset the ETR Bits */
  6970.   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
  6971.  
  6972.   /* Set the Prescaler, the Filter value and the Polarity */
  6973.   tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
  6974.  
  6975.   /* Write to TIMx SMCR */
  6976.   TIMx->SMCR = tmpsmcr;
  6977. }
  6978.  
  6979. /**
  6980.   * @brief  Enables or disables the TIM Capture Compare Channel x.
  6981.   * @param  TIMx to select the TIM peripheral
  6982.   * @param  Channel specifies the TIM Channel
  6983.   *          This parameter can be one of the following values:
  6984.   *            @arg TIM_CHANNEL_1: TIM Channel 1
  6985.   *            @arg TIM_CHANNEL_2: TIM Channel 2
  6986.   *            @arg TIM_CHANNEL_3: TIM Channel 3
  6987.   *            @arg TIM_CHANNEL_4: TIM Channel 4
  6988.   * @param  ChannelState specifies the TIM Channel CCxE bit new state.
  6989.   *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
  6990.   * @retval None
  6991.   */
  6992. static void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
  6993. {
  6994.   uint32_t tmp;
  6995.  
  6996.   /* Check the parameters */
  6997.   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
  6998.   assert_param(IS_TIM_CHANNELS(Channel));
  6999.  
  7000.   tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
  7001.  
  7002.   /* Reset the CCxE Bit */
  7003.   TIMx->CCER &= ~tmp;
  7004.  
  7005.   /* Set or reset the CCxE Bit */
  7006.   TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
  7007. }
  7008.  
  7009. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  7010. /**
  7011.   * @brief  Reset interrupt callbacks to the legacy weak callbacks.
  7012.   * @param  htim pointer to a TIM_HandleTypeDef structure that contains
  7013.   *                the configuration information for TIM module.
  7014.   * @retval None
  7015.   */
  7016. void TIM_ResetCallback(TIM_HandleTypeDef *htim)
  7017. {
  7018.   /* Reset the TIM callback to the legacy weak callbacks */
  7019.   htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;
  7020.   htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;
  7021.   htim->TriggerCallback                   = HAL_TIM_TriggerCallback;
  7022.   htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;
  7023.   htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;
  7024.   htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;
  7025.   htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;
  7026.   htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;
  7027.   htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
  7028.   htim->ErrorCallback                     = HAL_TIM_ErrorCallback;
  7029. }
  7030. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  7031.  
  7032. /**
  7033.   * @}
  7034.   */
  7035.  
  7036. #endif /* HAL_TIM_MODULE_ENABLED */
  7037. /**
  7038.   * @}
  7039.   */
  7040.  
  7041. /**
  7042.   * @}
  7043.   */
  7044. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  7045.