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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32l1xx_hal_nor.c
  4.   * @author  MCD Application Team
  5.   * @brief   NOR HAL module driver.
  6.   *          This file provides a generic firmware to drive NOR memories mounted
  7.   *          as external device.
  8.   *        
  9.   @verbatim
  10.   ==============================================================================
  11.                      ##### How to use this driver #####
  12.   ==============================================================================      
  13.     [..]
  14.       This driver is a generic layered driver which contains a set of APIs used to
  15.       control NOR flash memories. It uses the FSMC layer functions to interface
  16.       with NOR devices. This driver is used as follows:
  17.    
  18.       (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
  19.           with control and timing parameters for both normal and extended mode.
  20.            
  21.       (+) Read NOR flash memory manufacturer code and device IDs using the function
  22.           HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
  23.           structure declared by the function caller.
  24.        
  25.       (+) Access NOR flash memory by read/write data unit operations using the functions
  26.           HAL_NOR_Read(), HAL_NOR_Program().
  27.        
  28.       (+) Perform NOR flash erase block/chip operations using the functions
  29.           HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
  30.        
  31.       (+) Read the NOR flash CFI (common flash interface) IDs using the function
  32.           HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
  33.           structure declared by the function caller.
  34.        
  35.       (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
  36.           HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation  
  37.        
  38.       (+) You can monitor the NOR device HAL state by calling the function
  39.           HAL_NOR_GetState()
  40.     [..]
  41.      (@) This driver is a set of generic APIs which handle standard NOR flash operations.
  42.          If a NOR flash device contains different operations and/or implementations,
  43.          it should be implemented separately.
  44.  
  45.      *** NOR HAL driver macros list ***
  46.      =============================================
  47.      [..]
  48.        Below the list of most used macros in NOR HAL driver.
  49.        
  50.       (+) NOR_WRITE : NOR memory write data to specified address
  51.  
  52.   @endverbatim
  53.   ******************************************************************************
  54.   * @attention
  55.   *
  56.   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  57.   * All rights reserved.</center></h2>
  58.   *
  59.   * This software component is licensed by ST under BSD 3-Clause license,
  60.   * the "License"; You may not use this file except in compliance with the
  61.   * License. You may obtain a copy of the License at:
  62.   *                        opensource.org/licenses/BSD-3-Clause
  63.   *
  64.   ******************************************************************************
  65.   */
  66.  
  67. /* Includes ------------------------------------------------------------------*/
  68. #include "stm32l1xx_hal.h"
  69.  
  70. /** @addtogroup STM32L1xx_HAL_Driver
  71.   * @{
  72.   */
  73.  
  74. #ifdef HAL_NOR_MODULE_ENABLED
  75. #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
  76.  
  77. /** @defgroup NOR NOR
  78.   * @brief NOR driver modules
  79.   * @{
  80.   */
  81. /* Private typedef -----------------------------------------------------------*/
  82. /* Private define ------------------------------------------------------------*/
  83. /** @defgroup NOR_Private_Constants NOR Private Constants
  84.   * @{
  85.   */
  86.  
  87. /* Constants to define address to set to write a command */
  88. #define NOR_CMD_ADDRESS_FIRST                 (uint16_t)0x0555
  89. #define NOR_CMD_ADDRESS_FIRST_CFI             (uint16_t)0x0055
  90. #define NOR_CMD_ADDRESS_SECOND                (uint16_t)0x02AA
  91. #define NOR_CMD_ADDRESS_THIRD                 (uint16_t)0x0555
  92. #define NOR_CMD_ADDRESS_FOURTH                (uint16_t)0x0555
  93. #define NOR_CMD_ADDRESS_FIFTH                 (uint16_t)0x02AA
  94. #define NOR_CMD_ADDRESS_SIXTH                 (uint16_t)0x0555
  95.  
  96. /* Constants to define data to program a command */
  97. #define NOR_CMD_DATA_READ_RESET               (uint16_t)0x00F0
  98. #define NOR_CMD_DATA_FIRST                    (uint16_t)0x00AA
  99. #define NOR_CMD_DATA_SECOND                   (uint16_t)0x0055
  100. #define NOR_CMD_DATA_AUTO_SELECT              (uint16_t)0x0090
  101. #define NOR_CMD_DATA_PROGRAM                  (uint16_t)0x00A0
  102. #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD   (uint16_t)0x0080
  103. #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH  (uint16_t)0x00AA
  104. #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH   (uint16_t)0x0055
  105. #define NOR_CMD_DATA_CHIP_ERASE               (uint16_t)0x0010
  106. #define NOR_CMD_DATA_CFI                      (uint16_t)0x0098
  107.  
  108. #define NOR_CMD_DATA_BUFFER_AND_PROG          (uint8_t)0x25
  109. #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM  (uint8_t)0x29
  110. #define NOR_CMD_DATA_BLOCK_ERASE              (uint8_t)0x30
  111.  
  112. /* Mask on NOR STATUS REGISTER */
  113. #define NOR_MASK_STATUS_DQ5                   (uint16_t)0x0020
  114. #define NOR_MASK_STATUS_DQ6                   (uint16_t)0x0040
  115.  
  116. /**
  117.   * @}
  118.   */
  119.  
  120. /* Private macro -------------------------------------------------------------*/
  121. /** @defgroup NOR_Private_Macros NOR Private Macros
  122.   * @{
  123.   */
  124.  
  125. /**
  126.   * @}
  127.   */
  128.  
  129. /* Private variables ---------------------------------------------------------*/
  130.  
  131. /** @defgroup NOR_Private_Variables NOR Private Variables
  132.   * @{
  133.   */
  134.  
  135. static uint32_t uwNORMemoryDataWidth  = NOR_MEMORY_8B;
  136.  
  137. /**
  138.   * @}
  139.   */
  140.  
  141. /* Private function prototypes -----------------------------------------------*/
  142. /* Private functions ---------------------------------------------------------*/
  143.  
  144. /** @defgroup NOR_Exported_Functions NOR Exported Functions
  145.   * @{
  146.   */
  147.  
  148. /** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
  149.   * @brief    Initialization and Configuration functions
  150.   *
  151.   @verbatim    
  152.   ==============================================================================
  153.            ##### NOR Initialization and de_initialization functions #####
  154.   ==============================================================================
  155.   [..]  
  156.     This section provides functions allowing to initialize/de-initialize
  157.     the NOR memory
  158.  
  159. @endverbatim
  160.   * @{
  161.   */
  162.    
  163. /**
  164.   * @brief  Perform the NOR memory Initialization sequence
  165.   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
  166.   *                the configuration information for NOR module.
  167.   * @param  Timing pointer to NOR control timing structure
  168.   * @param  ExtTiming pointer to NOR extended mode timing structure    
  169.   * @retval HAL status
  170.   */
  171. HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming)
  172. {
  173.   /* Check the NOR handle parameter */
  174.   if(hnor == NULL)
  175.   {
  176.      return HAL_ERROR;
  177.   }
  178.  
  179.   if(hnor->State == HAL_NOR_STATE_RESET)
  180.   {
  181.     /* Allocate lock resource and initialize it */
  182.     hnor->Lock = HAL_UNLOCKED;
  183.    
  184.     /* Initialize the low level hardware (MSP) */
  185.     HAL_NOR_MspInit(hnor);
  186.   }
  187.  
  188.   /* Initialize NOR control Interface */
  189.   FSMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
  190.  
  191.   /* Initialize NOR timing Interface */
  192.   FSMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
  193.  
  194.   /* Initialize NOR extended mode timing Interface */
  195.   FSMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
  196.  
  197.   /* Enable the NORSRAM device */
  198.   __FSMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);  
  199.  
  200.   /* Initialize NOR Memory Data Width*/
  201.   if (hnor->Init.MemoryDataWidth == FSMC_NORSRAM_MEM_BUS_WIDTH_8)
  202.   {
  203.     uwNORMemoryDataWidth = NOR_MEMORY_8B;
  204.   }
  205.   else
  206.   {
  207.     uwNORMemoryDataWidth = NOR_MEMORY_16B;
  208.   }
  209.  
  210.   /* Check the NOR controller state */
  211.   hnor->State = HAL_NOR_STATE_READY;
  212.  
  213.   return HAL_OK;
  214. }
  215.  
  216. /**
  217.   * @brief  Perform NOR memory De-Initialization sequence
  218.   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
  219.   *                the configuration information for NOR module.
  220.   * @retval HAL status
  221.   */
  222. HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)  
  223. {
  224.   /* De-Initialize the low level hardware (MSP) */
  225.   HAL_NOR_MspDeInit(hnor);
  226.  
  227.   /* Configure the NOR registers with their reset values */
  228.   FSMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
  229.  
  230.   /* Update the NOR controller state */
  231.   hnor->State = HAL_NOR_STATE_RESET;
  232.  
  233.   /* Release Lock */
  234.   __HAL_UNLOCK(hnor);
  235.  
  236.   return HAL_OK;
  237. }
  238.  
  239. /**
  240.   * @brief  NOR MSP Init
  241.   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
  242.   *                the configuration information for NOR module.
  243.   * @retval None
  244.   */
  245. __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
  246. {
  247.   /* Prevent unused argument(s) compilation warning */
  248.   UNUSED(hnor);
  249.  
  250.   /* NOTE : This function Should not be modified, when the callback is needed,
  251.             the HAL_NOR_MspInit could be implemented in the user file
  252.    */
  253. }
  254.  
  255. /**
  256.   * @brief  NOR MSP DeInit
  257.   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
  258.   *                the configuration information for NOR module.
  259.   * @retval None
  260.   */
  261. __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
  262. {
  263.   /* Prevent unused argument(s) compilation warning */
  264.   UNUSED(hnor);
  265.  
  266.   /* NOTE : This function Should not be modified, when the callback is needed,
  267.             the HAL_NOR_MspDeInit could be implemented in the user file
  268.    */
  269. }
  270.  
  271. /**
  272.   * @brief  NOR MSP Wait fro Ready/Busy signal
  273.   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
  274.   *                the configuration information for NOR module.
  275.   * @param  Timeout Maximum timeout value
  276.   * @retval None
  277.   */
  278. __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
  279. {
  280.   /* Prevent unused argument(s) compilation warning */
  281.   UNUSED(hnor);
  282.   UNUSED(Timeout);
  283.  
  284.   /* NOTE : This function Should not be modified, when the callback is needed,
  285.             the HAL_NOR_MspWait could be implemented in the user file
  286.    */
  287. }
  288.  
  289. /**
  290.   * @}
  291.   */
  292.  
  293. /** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
  294.   * @brief    Input Output and memory control functions
  295.   *
  296.   @verbatim    
  297.   ==============================================================================
  298.                 ##### NOR Input and Output functions #####
  299.   ==============================================================================
  300.   [..]  
  301.     This section provides functions allowing to use and control the NOR memory
  302.  
  303. @endverbatim
  304.   * @{
  305.   */
  306.  
  307. /**
  308.   * @brief  Read NOR flash IDs
  309.   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
  310.   *                the configuration information for NOR module.
  311.   * @param  pNOR_ID  pointer to NOR ID structure
  312.   * @retval HAL status
  313.   */
  314. HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
  315. {
  316.   uint32_t deviceaddress = 0;
  317.  
  318.   /* Process Locked */
  319.   __HAL_LOCK(hnor);
  320.  
  321.   /* Check the NOR controller state */
  322.   if(hnor->State == HAL_NOR_STATE_BUSY)
  323.   {
  324.      return HAL_BUSY;
  325.   }
  326.  
  327.   /* Select the NOR device address */
  328.   if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
  329.   {
  330.     deviceaddress = NOR_MEMORY_ADRESS1;
  331.   }
  332.   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
  333.   {
  334.     deviceaddress = NOR_MEMORY_ADRESS2;
  335.   }
  336.   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
  337.   {
  338.     deviceaddress = NOR_MEMORY_ADRESS3;
  339.   }
  340.   else /* FSMC_NORSRAM_BANK4 */
  341.   {
  342.     deviceaddress = NOR_MEMORY_ADRESS4;
  343.   }  
  344.    
  345.   /* Update the NOR controller state */
  346.   hnor->State = HAL_NOR_STATE_BUSY;
  347.  
  348.   /* Send read ID command */
  349.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
  350.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
  351.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
  352.  
  353.   /* Read the NOR IDs */
  354.   pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
  355.   pNOR_ID->Device_Code1      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
  356.   pNOR_ID->Device_Code2      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
  357.   pNOR_ID->Device_Code3      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
  358.  
  359.   /* Check the NOR controller state */
  360.   hnor->State = HAL_NOR_STATE_READY;
  361.  
  362.   /* Process unlocked */
  363.   __HAL_UNLOCK(hnor);  
  364.  
  365.   return HAL_OK;
  366. }
  367.  
  368. /**
  369.   * @brief  Returns the NOR memory to Read mode.
  370.   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
  371.   *                the configuration information for NOR module.
  372.   * @retval HAL status
  373.   */
  374. HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
  375. {
  376.   uint32_t deviceaddress = 0;  
  377.  
  378.   /* Process Locked */
  379.   __HAL_LOCK(hnor);
  380.  
  381.   /* Check the NOR controller state */
  382.   if(hnor->State == HAL_NOR_STATE_BUSY)
  383.   {
  384.      return HAL_BUSY;
  385.   }
  386.  
  387.   /* Select the NOR device address */
  388.   if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
  389.   {
  390.     deviceaddress = NOR_MEMORY_ADRESS1;
  391.   }
  392.   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
  393.   {
  394.     deviceaddress = NOR_MEMORY_ADRESS2;
  395.   }
  396.   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
  397.   {
  398.     deviceaddress = NOR_MEMORY_ADRESS3;
  399.   }
  400.   else /* FSMC_NORSRAM_BANK4 */
  401.   {
  402.     deviceaddress = NOR_MEMORY_ADRESS4;
  403.   }  
  404.  
  405.   NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
  406.  
  407.   /* Check the NOR controller state */
  408.   hnor->State = HAL_NOR_STATE_READY;
  409.  
  410.   /* Process unlocked */
  411.   __HAL_UNLOCK(hnor);  
  412.  
  413.   return HAL_OK;
  414. }
  415.  
  416. /**
  417.   * @brief  Read data from NOR memory
  418.   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
  419.   *                the configuration information for NOR module.
  420.   * @param  pAddress pointer to Device address
  421.   * @param  pData  pointer to read data  
  422.   * @retval HAL status
  423.   */
  424. HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
  425. {
  426.   uint32_t deviceaddress = 0;
  427.  
  428.   /* Process Locked */
  429.   __HAL_LOCK(hnor);
  430.  
  431.   /* Check the NOR controller state */
  432.   if(hnor->State == HAL_NOR_STATE_BUSY)
  433.   {
  434.      return HAL_BUSY;
  435.   }
  436.  
  437.   /* Select the NOR device address */
  438.   if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
  439.   {
  440.     deviceaddress = NOR_MEMORY_ADRESS1;
  441.   }
  442.   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
  443.   {
  444.     deviceaddress = NOR_MEMORY_ADRESS2;
  445.   }
  446.   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
  447.   {
  448.     deviceaddress = NOR_MEMORY_ADRESS3;
  449.   }
  450.   else /* FSMC_NORSRAM_BANK4 */
  451.   {
  452.     deviceaddress = NOR_MEMORY_ADRESS4;
  453.   }
  454.    
  455.   /* Update the NOR controller state */
  456.   hnor->State = HAL_NOR_STATE_BUSY;
  457.  
  458.   /* Send read data command */
  459.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
  460.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);  
  461.   NOR_WRITE((uint32_t)pAddress, NOR_CMD_DATA_READ_RESET);
  462.  
  463.   /* Read the data */
  464.   *pData = *(__IO uint32_t *)(uint32_t)pAddress;
  465.  
  466.   /* Check the NOR controller state */
  467.   hnor->State = HAL_NOR_STATE_READY;
  468.  
  469.   /* Process unlocked */
  470.   __HAL_UNLOCK(hnor);
  471.  
  472.   return HAL_OK;  
  473. }
  474.  
  475. /**
  476.   * @brief  Program data to NOR memory
  477.   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
  478.   *                the configuration information for NOR module.
  479.   * @param  pAddress Device address
  480.   * @param  pData  pointer to the data to write  
  481.   * @retval HAL status
  482.   */
  483. HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
  484. {
  485.   uint32_t deviceaddress = 0;
  486.  
  487.   /* Process Locked */
  488.   __HAL_LOCK(hnor);
  489.  
  490.   /* Check the NOR controller state */
  491.   if(hnor->State == HAL_NOR_STATE_BUSY)
  492.   {
  493.      return HAL_BUSY;
  494.   }
  495.  
  496.   /* Select the NOR device address */
  497.   if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
  498.   {
  499.     deviceaddress = NOR_MEMORY_ADRESS1;
  500.   }
  501.   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
  502.   {
  503.     deviceaddress = NOR_MEMORY_ADRESS2;
  504.   }
  505.   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
  506.   {
  507.     deviceaddress = NOR_MEMORY_ADRESS3;
  508.   }
  509.   else /* FSMC_NORSRAM_BANK4 */
  510.   {
  511.     deviceaddress = NOR_MEMORY_ADRESS4;
  512.   }
  513.    
  514.   /* Update the NOR controller state */
  515.   hnor->State = HAL_NOR_STATE_BUSY;
  516.  
  517.   /* Send program data command */
  518.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
  519.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
  520.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
  521.  
  522.   /* Write the data */
  523.   NOR_WRITE(pAddress, *pData);
  524.  
  525.   /* Check the NOR controller state */
  526.   hnor->State = HAL_NOR_STATE_READY;
  527.  
  528.   /* Process unlocked */
  529.   __HAL_UNLOCK(hnor);
  530.  
  531.   return HAL_OK;  
  532. }
  533.  
  534. /**
  535.   * @brief  Reads a block of data from the FSMC NOR memory.
  536.   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
  537.   *                the configuration information for NOR module.
  538.   * @param  uwAddress NOR memory internal address to read from.
  539.   * @param  pData pointer to the buffer that receives the data read from the
  540.   *         NOR memory.
  541.   * @param  uwBufferSize  number of Half word to read.
  542.   * @retval HAL status
  543.   */
  544. HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
  545. {
  546.   uint32_t deviceaddress = 0;
  547.  
  548.   /* Process Locked */
  549.   __HAL_LOCK(hnor);
  550.  
  551.   /* Check the NOR controller state */
  552.   if(hnor->State == HAL_NOR_STATE_BUSY)
  553.   {
  554.      return HAL_BUSY;
  555.   }
  556.  
  557.   /* Select the NOR device address */
  558.   if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
  559.   {
  560.     deviceaddress = NOR_MEMORY_ADRESS1;
  561.   }
  562.   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
  563.   {
  564.     deviceaddress = NOR_MEMORY_ADRESS2;
  565.   }
  566.   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
  567.   {
  568.     deviceaddress = NOR_MEMORY_ADRESS3;
  569.   }
  570.   else /* FSMC_NORSRAM_BANK4 */
  571.   {
  572.     deviceaddress = NOR_MEMORY_ADRESS4;
  573.   }  
  574.    
  575.   /* Update the NOR controller state */
  576.   hnor->State = HAL_NOR_STATE_BUSY;
  577.  
  578.   /* Send read data command */
  579.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
  580.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);  
  581.   NOR_WRITE(uwAddress, NOR_CMD_DATA_READ_RESET);
  582.  
  583.   /* Read buffer */
  584.   while( uwBufferSize > 0)
  585.   {
  586.     *pData++ = *(__IO uint16_t *)uwAddress;
  587.     uwAddress += 2;
  588.     uwBufferSize--;
  589.   }
  590.  
  591.   /* Check the NOR controller state */
  592.   hnor->State = HAL_NOR_STATE_READY;
  593.  
  594.   /* Process unlocked */
  595.   __HAL_UNLOCK(hnor);
  596.  
  597.   return HAL_OK;  
  598. }
  599.  
  600. /**
  601.   * @brief  Writes a half-word buffer to the FSMC NOR memory. This function
  602.   *         must be used only with S29GL128P NOR memory.
  603.   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
  604.   *                the configuration information for NOR module.
  605.   * @param  uwAddress NOR memory internal address from which the data
  606.   * @note   Some NOR memory need Address aligned to xx bytes (can be aligned to
  607.   *          64 bytes boundary for example).
  608.   * @param  pData pointer to source data buffer.
  609.   * @param  uwBufferSize number of Half words to write.
  610.   * @note   The maximum buffer size allowed is NOR memory dependent
  611.   *         (can be 64 Bytes max for example).
  612.   * @retval HAL status
  613.   */
  614. HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
  615. {
  616.   uint16_t * p_currentaddress = (uint16_t *)NULL;
  617.   uint16_t * p_endaddress = (uint16_t *)NULL;
  618.   uint32_t lastloadedaddress = 0, deviceaddress = 0;
  619.  
  620.   /* Process Locked */
  621.   __HAL_LOCK(hnor);
  622.  
  623.   /* Check the NOR controller state */
  624.   if(hnor->State == HAL_NOR_STATE_BUSY)
  625.   {
  626.      return HAL_BUSY;
  627.   }
  628.  
  629.   /* Select the NOR device address */
  630.   if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
  631.   {
  632.     deviceaddress = NOR_MEMORY_ADRESS1;
  633.   }
  634.   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
  635.   {
  636.     deviceaddress = NOR_MEMORY_ADRESS2;
  637.   }
  638.   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
  639.   {
  640.     deviceaddress = NOR_MEMORY_ADRESS3;
  641.   }
  642.   else /* FSMC_NORSRAM_BANK4 */
  643.   {
  644.     deviceaddress = NOR_MEMORY_ADRESS4;
  645.   }  
  646.    
  647.   /* Update the NOR controller state */
  648.   hnor->State = HAL_NOR_STATE_BUSY;
  649.  
  650.   /* Initialize variables */
  651.   p_currentaddress  = (uint16_t*)((uint32_t)(uwAddress));
  652.   p_endaddress      = p_currentaddress + (uwBufferSize-1);
  653.   lastloadedaddress = (uint32_t)(uwAddress);
  654.  
  655.   /* Issue unlock command sequence */
  656.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
  657.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
  658.  
  659.   /* Write Buffer Load Command */
  660.   NOR_WRITE((uint32_t)(p_currentaddress), NOR_CMD_DATA_BUFFER_AND_PROG);
  661.   NOR_WRITE((uint32_t)(p_currentaddress), (uwBufferSize-1));
  662.  
  663.   /* Load Data into NOR Buffer */
  664.   while(p_currentaddress <= p_endaddress)
  665.   {
  666.     /* Store last loaded address & data value (for polling) */
  667.     lastloadedaddress = (uint32_t)p_currentaddress;
  668.  
  669.     NOR_WRITE(p_currentaddress, *pData++);
  670.    
  671.     p_currentaddress++;
  672.   }
  673.  
  674.   NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
  675.  
  676.   /* Check the NOR controller state */
  677.   hnor->State = HAL_NOR_STATE_READY;
  678.  
  679.   /* Process unlocked */
  680.   __HAL_UNLOCK(hnor);
  681.  
  682.   return HAL_OK;
  683.  
  684. }
  685.  
  686. /**
  687.   * @brief  Erase the specified block of the NOR memory
  688.   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
  689.   *                the configuration information for NOR module.
  690.   * @param  BlockAddress  Block to erase address
  691.   * @param  Address Device address
  692.   * @retval HAL status
  693.   */
  694. HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
  695. {
  696.   uint32_t deviceaddress = 0;
  697.  
  698.   /* Process Locked */
  699.   __HAL_LOCK(hnor);
  700.  
  701.   /* Check the NOR controller state */
  702.   if(hnor->State == HAL_NOR_STATE_BUSY)
  703.   {
  704.      return HAL_BUSY;
  705.   }
  706.  
  707.   /* Select the NOR device address */
  708.   if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
  709.   {
  710.     deviceaddress = NOR_MEMORY_ADRESS1;
  711.   }
  712.   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
  713.   {
  714.     deviceaddress = NOR_MEMORY_ADRESS2;
  715.   }
  716.   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
  717.   {
  718.     deviceaddress = NOR_MEMORY_ADRESS3;
  719.   }
  720.   else /* FSMC_NORSRAM_BANK4 */
  721.   {
  722.     deviceaddress = NOR_MEMORY_ADRESS4;
  723.   }
  724.    
  725.   /* Update the NOR controller state */
  726.   hnor->State = HAL_NOR_STATE_BUSY;
  727.  
  728.   /* Send block erase command sequence */
  729.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
  730.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
  731.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
  732.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
  733.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
  734.   NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
  735.  
  736.   /* Check the NOR memory status and update the controller state */
  737.   hnor->State = HAL_NOR_STATE_READY;
  738.    
  739.   /* Process unlocked */
  740.   __HAL_UNLOCK(hnor);
  741.  
  742.   return HAL_OK;
  743.  
  744. }
  745.  
  746. /**
  747.   * @brief  Erase the entire NOR chip.
  748.   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
  749.   *                the configuration information for NOR module.
  750.   * @param  Address  Device address  
  751.   * @retval HAL status
  752.   */
  753. HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
  754. {
  755.   uint32_t deviceaddress = 0;
  756.  
  757.   /* Process Locked */
  758.   __HAL_LOCK(hnor);
  759.  
  760.   /* Check the NOR controller state */
  761.   if(hnor->State == HAL_NOR_STATE_BUSY)
  762.   {
  763.      return HAL_BUSY;
  764.   }
  765.  
  766.   /* Select the NOR device address */
  767.   if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
  768.   {
  769.     deviceaddress = NOR_MEMORY_ADRESS1;
  770.   }
  771.   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
  772.   {
  773.     deviceaddress = NOR_MEMORY_ADRESS2;
  774.   }
  775.   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
  776.   {
  777.     deviceaddress = NOR_MEMORY_ADRESS3;
  778.   }
  779.   else /* FSMC_NORSRAM_BANK4 */
  780.   {
  781.     deviceaddress = NOR_MEMORY_ADRESS4;
  782.   }
  783.    
  784.   /* Update the NOR controller state */
  785.   hnor->State = HAL_NOR_STATE_BUSY;  
  786.    
  787.   /* Send NOR chip erase command sequence */
  788.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
  789.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
  790.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
  791.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
  792.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);  
  793.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
  794.  
  795.   /* Check the NOR memory status and update the controller state */
  796.   hnor->State = HAL_NOR_STATE_READY;
  797.    
  798.   /* Process unlocked */
  799.   __HAL_UNLOCK(hnor);
  800.  
  801.   return HAL_OK;  
  802. }
  803.  
  804. /**
  805.   * @brief  Read NOR flash CFI IDs
  806.   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
  807.   *                the configuration information for NOR module.
  808.   * @param  pNOR_CFI  pointer to NOR CFI IDs structure  
  809.   * @retval HAL status
  810.   */
  811. HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
  812. {
  813.   uint32_t deviceaddress = 0;
  814.  
  815.   /* Process Locked */
  816.   __HAL_LOCK(hnor);
  817.  
  818.   /* Check the NOR controller state */
  819.   if(hnor->State == HAL_NOR_STATE_BUSY)
  820.   {
  821.      return HAL_BUSY;
  822.   }
  823.  
  824.   /* Select the NOR device address */
  825.   if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
  826.   {
  827.     deviceaddress = NOR_MEMORY_ADRESS1;
  828.   }
  829.   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
  830.   {
  831.     deviceaddress = NOR_MEMORY_ADRESS2;
  832.   }
  833.   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
  834.   {
  835.     deviceaddress = NOR_MEMORY_ADRESS3;
  836.   }
  837.   else /* FSMC_NORSRAM_BANK4 */
  838.   {
  839.     deviceaddress = NOR_MEMORY_ADRESS4;
  840.   }  
  841.    
  842.   /* Update the NOR controller state */
  843.   hnor->State = HAL_NOR_STATE_BUSY;
  844.  
  845.   /* Send read CFI query command */
  846.   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
  847.  
  848.   /* read the NOR CFI information */
  849.   pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
  850.   pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
  851.   pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
  852.   pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
  853.  
  854.   /* Check the NOR controller state */
  855.   hnor->State = HAL_NOR_STATE_READY;
  856.  
  857.   /* Process unlocked */
  858.   __HAL_UNLOCK(hnor);
  859.  
  860.   return HAL_OK;
  861. }
  862.  
  863. /**
  864.   * @}
  865.   */
  866.  
  867. /** @defgroup NOR_Exported_Functions_Group3 Control functions
  868.  *  @brief   management functions
  869.  *
  870. @verbatim  
  871.   ==============================================================================
  872.                         ##### NOR Control functions #####
  873.   ==============================================================================
  874.   [..]
  875.     This subsection provides a set of functions allowing to control dynamically
  876.     the NOR interface.
  877.  
  878. @endverbatim
  879.   * @{
  880.   */
  881.    
  882. /**
  883.   * @brief  Enables dynamically NOR write operation.
  884.   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
  885.   *                the configuration information for NOR module.
  886.   * @retval HAL status
  887.   */
  888. HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
  889. {
  890.   /* Process Locked */
  891.   __HAL_LOCK(hnor);
  892.  
  893.   /* Enable write operation */
  894.   FSMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
  895.  
  896.   /* Update the NOR controller state */
  897.   hnor->State = HAL_NOR_STATE_READY;
  898.  
  899.   /* Process unlocked */
  900.   __HAL_UNLOCK(hnor);
  901.  
  902.   return HAL_OK;  
  903. }
  904.  
  905. /**
  906.   * @brief  Disables dynamically NOR write operation.
  907.   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
  908.   *                the configuration information for NOR module.
  909.   * @retval HAL status
  910.   */
  911. HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
  912. {
  913.   /* Process Locked */
  914.   __HAL_LOCK(hnor);
  915.  
  916.   /* Update the SRAM controller state */
  917.   hnor->State = HAL_NOR_STATE_BUSY;
  918.    
  919.   /* Disable write operation */
  920.   FSMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
  921.  
  922.   /* Update the NOR controller state */
  923.   hnor->State = HAL_NOR_STATE_PROTECTED;
  924.  
  925.   /* Process unlocked */
  926.   __HAL_UNLOCK(hnor);
  927.  
  928.   return HAL_OK;  
  929. }
  930.  
  931. /**
  932.   * @}
  933.   */  
  934.  
  935. /** @defgroup NOR_Exported_Functions_Group4 State functions
  936.  *  @brief   Peripheral State functions
  937.  *
  938. @verbatim  
  939.   ==============================================================================
  940.                       ##### NOR State functions #####
  941.   ==============================================================================  
  942.   [..]
  943.     This subsection permits to get in run-time the status of the NOR controller
  944.     and the data flow.
  945.  
  946. @endverbatim
  947.   * @{
  948.   */
  949.  
  950. /**
  951.   * @brief  return the NOR controller state
  952.   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
  953.   *                the configuration information for NOR module.
  954.   * @retval NOR controller state
  955.   */
  956. HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
  957. {
  958.   return hnor->State;
  959. }
  960.  
  961. /**
  962.   * @brief  Returns the NOR operation status.
  963.   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
  964.   *                the configuration information for NOR module.  
  965.   * @param  Address Device address
  966.   * @param  Timeout NOR progamming Timeout
  967.   * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
  968.   *         or HAL_NOR_STATUS_TIMEOUT
  969.   */
  970. HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
  971. {
  972.   HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
  973.   uint16_t tmp_sr1 = 0, tmp_sr2 = 0;
  974.   uint32_t tickstart = 0;
  975.  
  976.   /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
  977.   HAL_NOR_MspWait(hnor, Timeout);
  978.  
  979.   /* Get tick */
  980.   tickstart = HAL_GetTick();
  981.   while((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
  982.   {
  983.     /* Check for the Timeout */
  984.     if(Timeout != HAL_MAX_DELAY)
  985.     {
  986.       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
  987.       {
  988.         status = HAL_NOR_STATUS_TIMEOUT;
  989.       }  
  990.     }
  991.  
  992.     /* Read NOR status register (DQ6 and DQ5) */
  993.     tmp_sr1 = *(__IO uint16_t *)Address;
  994.     tmp_sr2 = *(__IO uint16_t *)Address;
  995.  
  996.     /* If DQ6 did not toggle between the two reads then return NOR_Success */
  997.     if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
  998.     {
  999.       return HAL_NOR_STATUS_SUCCESS;
  1000.     }
  1001.    
  1002.     if((tmp_sr1 & NOR_MASK_STATUS_DQ5) != NOR_MASK_STATUS_DQ5)
  1003.     {
  1004.       status = HAL_NOR_STATUS_ONGOING;
  1005.     }
  1006.    
  1007.     tmp_sr1 = *(__IO uint16_t *)Address;
  1008.     tmp_sr2 = *(__IO uint16_t *)Address;
  1009.  
  1010.     /* If DQ6 did not toggle between the two reads then return NOR_Success */
  1011.     if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
  1012.     {
  1013.       return HAL_NOR_STATUS_SUCCESS;
  1014.     }
  1015.     else if((tmp_sr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
  1016.     {
  1017.       return HAL_NOR_STATUS_ERROR;
  1018.     }
  1019.   }
  1020.  
  1021.   /* Return the operation status */
  1022.   return status;
  1023. }
  1024.  
  1025. /**
  1026.   * @}
  1027.   */
  1028.  
  1029. /**
  1030.   * @}
  1031.   */
  1032. /**
  1033.   * @}
  1034.   */
  1035. #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
  1036. #endif /* HAL_NOR_MODULE_ENABLED */
  1037.  
  1038. /**
  1039.   * @}
  1040.   */
  1041.  
  1042. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  1043.