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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32l1xx_ll_spi.h
  4.   * @author  MCD Application Team
  5.   * @brief   Header file of SPI LL module.
  6.   ******************************************************************************
  7.   * @attention
  8.   *
  9.   * Copyright (c) 2016 STMicroelectronics.
  10.   * All rights reserved.
  11.   *
  12.   * This software is licensed under terms that can be found in the LICENSE file
  13.   * in the root directory of this software component.
  14.   * If no LICENSE file comes with this software, it is provided AS-IS.
  15.   *
  16.   ******************************************************************************
  17.   */
  18.  
  19. /* Define to prevent recursive inclusion -------------------------------------*/
  20. #ifndef STM32L1xx_LL_SPI_H
  21. #define STM32L1xx_LL_SPI_H
  22.  
  23. #ifdef __cplusplus
  24. extern "C" {
  25. #endif
  26.  
  27. /* Includes ------------------------------------------------------------------*/
  28. #include "stm32l1xx.h"
  29.  
  30. /** @addtogroup STM32L1xx_LL_Driver
  31.   * @{
  32.   */
  33.  
  34. #if defined (SPI1) || defined (SPI2) || defined (SPI3)
  35.  
  36. /** @defgroup SPI_LL SPI
  37.   * @{
  38.   */
  39.  
  40. /* Private types -------------------------------------------------------------*/
  41. /* Private variables ---------------------------------------------------------*/
  42. /* Private macros ------------------------------------------------------------*/
  43.  
  44. /* Exported types ------------------------------------------------------------*/
  45. #if defined(USE_FULL_LL_DRIVER)
  46. /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
  47.   * @{
  48.   */
  49.  
  50. /**
  51.   * @brief  SPI Init structures definition
  52.   */
  53. typedef struct
  54. {
  55.   uint32_t TransferDirection;       /*!< Specifies the SPI unidirectional or bidirectional data mode.
  56.                                          This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
  57.  
  58.                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
  59.  
  60.   uint32_t Mode;                    /*!< Specifies the SPI mode (Master/Slave).
  61.                                          This parameter can be a value of @ref SPI_LL_EC_MODE.
  62.  
  63.                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
  64.  
  65.   uint32_t DataWidth;               /*!< Specifies the SPI data width.
  66.                                          This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
  67.  
  68.                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
  69.  
  70.   uint32_t ClockPolarity;           /*!< Specifies the serial clock steady state.
  71.                                          This parameter can be a value of @ref SPI_LL_EC_POLARITY.
  72.  
  73.                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
  74.  
  75.   uint32_t ClockPhase;              /*!< Specifies the clock active edge for the bit capture.
  76.                                          This parameter can be a value of @ref SPI_LL_EC_PHASE.
  77.  
  78.                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
  79.  
  80.   uint32_t NSS;                     /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
  81.                                          This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
  82.  
  83.                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
  84.  
  85.   uint32_t BaudRate;                /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
  86.                                          This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
  87.                                          @note The communication clock is derived from the master clock. The slave clock does not need to be set.
  88.  
  89.                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
  90.  
  91.   uint32_t BitOrder;                /*!< Specifies whether data transfers start from MSB or LSB bit.
  92.                                          This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
  93.  
  94.                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
  95.  
  96.   uint32_t CRCCalculation;          /*!< Specifies if the CRC calculation is enabled or not.
  97.                                          This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
  98.  
  99.                                          This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
  100.  
  101.   uint32_t CRCPoly;                 /*!< Specifies the polynomial used for the CRC calculation.
  102.                                          This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
  103.  
  104.                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
  105.  
  106. } LL_SPI_InitTypeDef;
  107.  
  108. /**
  109.   * @}
  110.   */
  111. #endif /* USE_FULL_LL_DRIVER */
  112.  
  113. /* Exported constants --------------------------------------------------------*/
  114. /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
  115.   * @{
  116.   */
  117.  
  118. /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
  119.   * @brief    Flags defines which can be used with LL_SPI_ReadReg function
  120.   * @{
  121.   */
  122. #define LL_SPI_SR_RXNE                     SPI_SR_RXNE               /*!< Rx buffer not empty flag         */
  123. #define LL_SPI_SR_TXE                      SPI_SR_TXE                /*!< Tx buffer empty flag             */
  124. #define LL_SPI_SR_BSY                      SPI_SR_BSY                /*!< Busy flag                        */
  125. #define LL_SPI_SR_CRCERR                   SPI_SR_CRCERR             /*!< CRC error flag                   */
  126. #define LL_SPI_SR_MODF                     SPI_SR_MODF               /*!< Mode fault flag                  */
  127. #define LL_SPI_SR_OVR                      SPI_SR_OVR                /*!< Overrun flag                     */
  128. #define LL_SPI_SR_FRE                      SPI_SR_FRE                /*!< TI mode frame format error flag  */
  129. /**
  130.   * @}
  131.   */
  132.  
  133. /** @defgroup SPI_LL_EC_IT IT Defines
  134.   * @brief    IT defines which can be used with LL_SPI_ReadReg and  LL_SPI_WriteReg functions
  135.   * @{
  136.   */
  137. #define LL_SPI_CR2_RXNEIE                  SPI_CR2_RXNEIE            /*!< Rx buffer not empty interrupt enable */
  138. #define LL_SPI_CR2_TXEIE                   SPI_CR2_TXEIE             /*!< Tx buffer empty interrupt enable     */
  139. #define LL_SPI_CR2_ERRIE                   SPI_CR2_ERRIE             /*!< Error interrupt enable               */
  140. /**
  141.   * @}
  142.   */
  143.  
  144. /** @defgroup SPI_LL_EC_MODE Operation Mode
  145.   * @{
  146.   */
  147. #define LL_SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)    /*!< Master configuration  */
  148. #define LL_SPI_MODE_SLAVE                  0x00000000U                     /*!< Slave configuration   */
  149. /**
  150.   * @}
  151.   */
  152.  
  153. /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
  154.   * @brief  SPI TI Mode not supported for Category 1 and 2
  155.   * @{
  156.   */
  157. #define LL_SPI_PROTOCOL_MOTOROLA           0x00000000U               /*!< Motorola mode. Used as default value */
  158. #if defined(SPI_CR2_FRF)
  159. #define LL_SPI_PROTOCOL_TI                 (SPI_CR2_FRF)             /*!< TI mode                              */
  160. #endif /* SPI_CR2_FRF */
  161. /**
  162.   * @}
  163.   */
  164.  
  165. /** @defgroup SPI_LL_EC_PHASE Clock Phase
  166.   * @{
  167.   */
  168. #define LL_SPI_PHASE_1EDGE                 0x00000000U               /*!< First clock transition is the first data capture edge  */
  169. #define LL_SPI_PHASE_2EDGE                 (SPI_CR1_CPHA)            /*!< Second clock transition is the first data capture edge */
  170. /**
  171.   * @}
  172.   */
  173.  
  174. /** @defgroup SPI_LL_EC_POLARITY Clock Polarity
  175.   * @{
  176.   */
  177. #define LL_SPI_POLARITY_LOW                0x00000000U               /*!< Clock to 0 when idle */
  178. #define LL_SPI_POLARITY_HIGH               (SPI_CR1_CPOL)            /*!< Clock to 1 when idle */
  179. /**
  180.   * @}
  181.   */
  182.  
  183. /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
  184.   * @{
  185.   */
  186. #define LL_SPI_BAUDRATEPRESCALER_DIV2      0x00000000U                                    /*!< BaudRate control equal to fPCLK/2   */
  187. #define LL_SPI_BAUDRATEPRESCALER_DIV4      (SPI_CR1_BR_0)                                 /*!< BaudRate control equal to fPCLK/4   */
  188. #define LL_SPI_BAUDRATEPRESCALER_DIV8      (SPI_CR1_BR_1)                                 /*!< BaudRate control equal to fPCLK/8   */
  189. #define LL_SPI_BAUDRATEPRESCALER_DIV16     (SPI_CR1_BR_1 | SPI_CR1_BR_0)                  /*!< BaudRate control equal to fPCLK/16  */
  190. #define LL_SPI_BAUDRATEPRESCALER_DIV32     (SPI_CR1_BR_2)                                 /*!< BaudRate control equal to fPCLK/32  */
  191. #define LL_SPI_BAUDRATEPRESCALER_DIV64     (SPI_CR1_BR_2 | SPI_CR1_BR_0)                  /*!< BaudRate control equal to fPCLK/64  */
  192. #define LL_SPI_BAUDRATEPRESCALER_DIV128    (SPI_CR1_BR_2 | SPI_CR1_BR_1)                  /*!< BaudRate control equal to fPCLK/128 */
  193. #define LL_SPI_BAUDRATEPRESCALER_DIV256    (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)   /*!< BaudRate control equal to fPCLK/256 */
  194. /**
  195.   * @}
  196.   */
  197.  
  198. /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
  199.   * @{
  200.   */
  201. #define LL_SPI_LSB_FIRST                   (SPI_CR1_LSBFIRST)        /*!< Data is transmitted/received with the LSB first */
  202. #define LL_SPI_MSB_FIRST                   0x00000000U               /*!< Data is transmitted/received with the MSB first */
  203. /**
  204.   * @}
  205.   */
  206.  
  207. /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
  208.   * @{
  209.   */
  210. #define LL_SPI_FULL_DUPLEX                 0x00000000U                          /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
  211. #define LL_SPI_SIMPLEX_RX                  (SPI_CR1_RXONLY)                     /*!< Simplex Rx mode.  Rx transfer only on 1 line    */
  212. #define LL_SPI_HALF_DUPLEX_RX              (SPI_CR1_BIDIMODE)                   /*!< Half-Duplex Rx mode. Rx transfer on 1 line      */
  213. #define LL_SPI_HALF_DUPLEX_TX              (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)  /*!< Half-Duplex Tx mode. Tx transfer on 1 line      */
  214. /**
  215.   * @}
  216.   */
  217.  
  218. /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
  219.   * @{
  220.   */
  221. #define LL_SPI_NSS_SOFT                    (SPI_CR1_SSM)                     /*!< NSS managed internally. NSS pin not used and free              */
  222. #define LL_SPI_NSS_HARD_INPUT              0x00000000U                       /*!< NSS pin used in Input. Only used in Master mode                */
  223. #define LL_SPI_NSS_HARD_OUTPUT             (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
  224. /**
  225.   * @}
  226.   */
  227.  
  228. /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
  229.   * @{
  230.   */
  231. #define LL_SPI_DATAWIDTH_8BIT              0x00000000U                       /*!< Data length for SPI transfer:  8 bits */
  232. #define LL_SPI_DATAWIDTH_16BIT             (SPI_CR1_DFF)                     /*!< Data length for SPI transfer:  16 bits */
  233. /**
  234.   * @}
  235.   */
  236. #if defined(USE_FULL_LL_DRIVER)
  237.  
  238. /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
  239.   * @{
  240.   */
  241. #define LL_SPI_CRCCALCULATION_DISABLE      0x00000000U               /*!< CRC calculation disabled */
  242. #define LL_SPI_CRCCALCULATION_ENABLE       (SPI_CR1_CRCEN)           /*!< CRC calculation enabled  */
  243. /**
  244.   * @}
  245.   */
  246. #endif /* USE_FULL_LL_DRIVER */
  247.  
  248. /**
  249.   * @}
  250.   */
  251.  
  252. /* Exported macro ------------------------------------------------------------*/
  253. /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
  254.   * @{
  255.   */
  256.  
  257. /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
  258.   * @{
  259.   */
  260.  
  261. /**
  262.   * @brief  Write a value in SPI register
  263.   * @param  __INSTANCE__ SPI Instance
  264.   * @param  __REG__ Register to be written
  265.   * @param  __VALUE__ Value to be written in the register
  266.   * @retval None
  267.   */
  268. #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
  269.  
  270. /**
  271.   * @brief  Read a value in SPI register
  272.   * @param  __INSTANCE__ SPI Instance
  273.   * @param  __REG__ Register to be read
  274.   * @retval Register value
  275.   */
  276. #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
  277. /**
  278.   * @}
  279.   */
  280.  
  281. /**
  282.   * @}
  283.   */
  284.  
  285. /* Exported functions --------------------------------------------------------*/
  286. /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
  287.   * @{
  288.   */
  289.  
  290. /** @defgroup SPI_LL_EF_Configuration Configuration
  291.   * @{
  292.   */
  293.  
  294. /**
  295.   * @brief  Enable SPI peripheral
  296.   * @rmtoll CR1          SPE           LL_SPI_Enable
  297.   * @param  SPIx SPI Instance
  298.   * @retval None
  299.   */
  300. __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
  301. {
  302.   SET_BIT(SPIx->CR1, SPI_CR1_SPE);
  303. }
  304.  
  305. /**
  306.   * @brief  Disable SPI peripheral
  307.   * @note   When disabling the SPI, follow the procedure described in the Reference Manual.
  308.   * @rmtoll CR1          SPE           LL_SPI_Disable
  309.   * @param  SPIx SPI Instance
  310.   * @retval None
  311.   */
  312. __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
  313. {
  314.   CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
  315. }
  316.  
  317. /**
  318.   * @brief  Check if SPI peripheral is enabled
  319.   * @rmtoll CR1          SPE           LL_SPI_IsEnabled
  320.   * @param  SPIx SPI Instance
  321.   * @retval State of bit (1 or 0).
  322.   */
  323. __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
  324. {
  325.   return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
  326. }
  327.  
  328. /**
  329.   * @brief  Set SPI operation mode to Master or Slave
  330.   * @note   This bit should not be changed when communication is ongoing.
  331.   * @rmtoll CR1          MSTR          LL_SPI_SetMode\n
  332.   *         CR1          SSI           LL_SPI_SetMode
  333.   * @param  SPIx SPI Instance
  334.   * @param  Mode This parameter can be one of the following values:
  335.   *         @arg @ref LL_SPI_MODE_MASTER
  336.   *         @arg @ref LL_SPI_MODE_SLAVE
  337.   * @retval None
  338.   */
  339. __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
  340. {
  341.   MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
  342. }
  343.  
  344. /**
  345.   * @brief  Get SPI operation mode (Master or Slave)
  346.   * @rmtoll CR1          MSTR          LL_SPI_GetMode\n
  347.   *         CR1          SSI           LL_SPI_GetMode
  348.   * @param  SPIx SPI Instance
  349.   * @retval Returned value can be one of the following values:
  350.   *         @arg @ref LL_SPI_MODE_MASTER
  351.   *         @arg @ref LL_SPI_MODE_SLAVE
  352.   */
  353. __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
  354. {
  355.   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
  356. }
  357.  
  358. #if defined(SPI_CR2_FRF)
  359. /**
  360.   * @brief  Set serial protocol used. TI Mode not supported for Category 1 and 2.
  361.   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
  362.   * @rmtoll CR2          FRF           LL_SPI_SetStandard
  363.   * @param  SPIx SPI Instance
  364.   * @param  Standard This parameter can be one of the following values:
  365.   *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA
  366.   *         @arg @ref LL_SPI_PROTOCOL_TI
  367.   * @retval None
  368.   */
  369. __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
  370. {
  371.   MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
  372. }
  373.  
  374. /**
  375.   * @brief  Get serial protocol used
  376.   * @rmtoll CR2          FRF           LL_SPI_GetStandard
  377.   * @param  SPIx SPI Instance
  378.   * @retval Returned value can be one of the following values:
  379.   *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA
  380.   *         @arg @ref LL_SPI_PROTOCOL_TI
  381.   */
  382. __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
  383. {
  384.   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
  385. }
  386. #endif /* SPI_CR2_FRF */
  387.  
  388. /**
  389.   * @brief  Set clock phase
  390.   * @note   This bit should not be changed when communication is ongoing.
  391.   *         This bit is not used in SPI TI mode.
  392.   * @rmtoll CR1          CPHA          LL_SPI_SetClockPhase
  393.   * @param  SPIx SPI Instance
  394.   * @param  ClockPhase This parameter can be one of the following values:
  395.   *         @arg @ref LL_SPI_PHASE_1EDGE
  396.   *         @arg @ref LL_SPI_PHASE_2EDGE
  397.   * @retval None
  398.   */
  399. __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
  400. {
  401.   MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
  402. }
  403.  
  404. /**
  405.   * @brief  Get clock phase
  406.   * @rmtoll CR1          CPHA          LL_SPI_GetClockPhase
  407.   * @param  SPIx SPI Instance
  408.   * @retval Returned value can be one of the following values:
  409.   *         @arg @ref LL_SPI_PHASE_1EDGE
  410.   *         @arg @ref LL_SPI_PHASE_2EDGE
  411.   */
  412. __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
  413. {
  414.   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
  415. }
  416.  
  417. /**
  418.   * @brief  Set clock polarity
  419.   * @note   This bit should not be changed when communication is ongoing.
  420.   *         This bit is not used in SPI TI mode.
  421.   * @rmtoll CR1          CPOL          LL_SPI_SetClockPolarity
  422.   * @param  SPIx SPI Instance
  423.   * @param  ClockPolarity This parameter can be one of the following values:
  424.   *         @arg @ref LL_SPI_POLARITY_LOW
  425.   *         @arg @ref LL_SPI_POLARITY_HIGH
  426.   * @retval None
  427.   */
  428. __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
  429. {
  430.   MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
  431. }
  432.  
  433. /**
  434.   * @brief  Get clock polarity
  435.   * @rmtoll CR1          CPOL          LL_SPI_GetClockPolarity
  436.   * @param  SPIx SPI Instance
  437.   * @retval Returned value can be one of the following values:
  438.   *         @arg @ref LL_SPI_POLARITY_LOW
  439.   *         @arg @ref LL_SPI_POLARITY_HIGH
  440.   */
  441. __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
  442. {
  443.   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
  444. }
  445.  
  446. /**
  447.   * @brief  Set baud rate prescaler
  448.   * @note   These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
  449.   * @rmtoll CR1          BR            LL_SPI_SetBaudRatePrescaler
  450.   * @param  SPIx SPI Instance
  451.   * @param  BaudRate This parameter can be one of the following values:
  452.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
  453.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
  454.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
  455.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
  456.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
  457.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
  458.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
  459.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
  460.   * @retval None
  461.   */
  462. __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
  463. {
  464.   MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
  465. }
  466.  
  467. /**
  468.   * @brief  Get baud rate prescaler
  469.   * @rmtoll CR1          BR            LL_SPI_GetBaudRatePrescaler
  470.   * @param  SPIx SPI Instance
  471.   * @retval Returned value can be one of the following values:
  472.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
  473.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
  474.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
  475.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
  476.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
  477.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
  478.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
  479.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
  480.   */
  481. __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
  482. {
  483.   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
  484. }
  485.  
  486. /**
  487.   * @brief  Set transfer bit order
  488.   * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
  489.   * @rmtoll CR1          LSBFIRST      LL_SPI_SetTransferBitOrder
  490.   * @param  SPIx SPI Instance
  491.   * @param  BitOrder This parameter can be one of the following values:
  492.   *         @arg @ref LL_SPI_LSB_FIRST
  493.   *         @arg @ref LL_SPI_MSB_FIRST
  494.   * @retval None
  495.   */
  496. __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
  497. {
  498.   MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
  499. }
  500.  
  501. /**
  502.   * @brief  Get transfer bit order
  503.   * @rmtoll CR1          LSBFIRST      LL_SPI_GetTransferBitOrder
  504.   * @param  SPIx SPI Instance
  505.   * @retval Returned value can be one of the following values:
  506.   *         @arg @ref LL_SPI_LSB_FIRST
  507.   *         @arg @ref LL_SPI_MSB_FIRST
  508.   */
  509. __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
  510. {
  511.   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
  512. }
  513.  
  514. /**
  515.   * @brief  Set transfer direction mode
  516.   * @note   For Half-Duplex mode, Rx Direction is set by default.
  517.   *         In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
  518.   * @rmtoll CR1          RXONLY        LL_SPI_SetTransferDirection\n
  519.   *         CR1          BIDIMODE      LL_SPI_SetTransferDirection\n
  520.   *         CR1          BIDIOE        LL_SPI_SetTransferDirection
  521.   * @param  SPIx SPI Instance
  522.   * @param  TransferDirection This parameter can be one of the following values:
  523.   *         @arg @ref LL_SPI_FULL_DUPLEX
  524.   *         @arg @ref LL_SPI_SIMPLEX_RX
  525.   *         @arg @ref LL_SPI_HALF_DUPLEX_RX
  526.   *         @arg @ref LL_SPI_HALF_DUPLEX_TX
  527.   * @retval None
  528.   */
  529. __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
  530. {
  531.   MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
  532. }
  533.  
  534. /**
  535.   * @brief  Get transfer direction mode
  536.   * @rmtoll CR1          RXONLY        LL_SPI_GetTransferDirection\n
  537.   *         CR1          BIDIMODE      LL_SPI_GetTransferDirection\n
  538.   *         CR1          BIDIOE        LL_SPI_GetTransferDirection
  539.   * @param  SPIx SPI Instance
  540.   * @retval Returned value can be one of the following values:
  541.   *         @arg @ref LL_SPI_FULL_DUPLEX
  542.   *         @arg @ref LL_SPI_SIMPLEX_RX
  543.   *         @arg @ref LL_SPI_HALF_DUPLEX_RX
  544.   *         @arg @ref LL_SPI_HALF_DUPLEX_TX
  545.   */
  546. __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
  547. {
  548.   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
  549. }
  550.  
  551. /**
  552.   * @brief  Set frame data width
  553.   * @rmtoll CR1          DFF           LL_SPI_SetDataWidth
  554.   * @param  SPIx SPI Instance
  555.   * @param  DataWidth This parameter can be one of the following values:
  556.   *         @arg @ref LL_SPI_DATAWIDTH_8BIT
  557.   *         @arg @ref LL_SPI_DATAWIDTH_16BIT
  558.   * @retval None
  559.   */
  560. __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
  561. {
  562.   MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth);
  563. }
  564.  
  565. /**
  566.   * @brief  Get frame data width
  567.   * @rmtoll CR1          DFF           LL_SPI_GetDataWidth
  568.   * @param  SPIx SPI Instance
  569.   * @retval Returned value can be one of the following values:
  570.   *         @arg @ref LL_SPI_DATAWIDTH_8BIT
  571.   *         @arg @ref LL_SPI_DATAWIDTH_16BIT
  572.   */
  573. __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
  574. {
  575.   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF));
  576. }
  577.  
  578. /**
  579.   * @}
  580.   */
  581.  
  582. /** @defgroup SPI_LL_EF_CRC_Management CRC Management
  583.   * @{
  584.   */
  585.  
  586. /**
  587.   * @brief  Enable CRC
  588.   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
  589.   * @rmtoll CR1          CRCEN         LL_SPI_EnableCRC
  590.   * @param  SPIx SPI Instance
  591.   * @retval None
  592.   */
  593. __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
  594. {
  595.   SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
  596. }
  597.  
  598. /**
  599.   * @brief  Disable CRC
  600.   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
  601.   * @rmtoll CR1          CRCEN         LL_SPI_DisableCRC
  602.   * @param  SPIx SPI Instance
  603.   * @retval None
  604.   */
  605. __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
  606. {
  607.   CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
  608. }
  609.  
  610. /**
  611.   * @brief  Check if CRC is enabled
  612.   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
  613.   * @rmtoll CR1          CRCEN         LL_SPI_IsEnabledCRC
  614.   * @param  SPIx SPI Instance
  615.   * @retval State of bit (1 or 0).
  616.   */
  617. __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
  618. {
  619.   return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
  620. }
  621.  
  622. /**
  623.   * @brief  Set CRCNext to transfer CRC on the line
  624.   * @note   This bit has to be written as soon as the last data is written in the SPIx_DR register.
  625.   * @rmtoll CR1          CRCNEXT       LL_SPI_SetCRCNext
  626.   * @param  SPIx SPI Instance
  627.   * @retval None
  628.   */
  629. __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
  630. {
  631.   SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
  632. }
  633.  
  634. /**
  635.   * @brief  Set polynomial for CRC calculation
  636.   * @rmtoll CRCPR        CRCPOLY       LL_SPI_SetCRCPolynomial
  637.   * @param  SPIx SPI Instance
  638.   * @param  CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
  639.   * @retval None
  640.   */
  641. __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
  642. {
  643.   WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
  644. }
  645.  
  646. /**
  647.   * @brief  Get polynomial for CRC calculation
  648.   * @rmtoll CRCPR        CRCPOLY       LL_SPI_GetCRCPolynomial
  649.   * @param  SPIx SPI Instance
  650.   * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
  651.   */
  652. __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
  653. {
  654.   return (uint32_t)(READ_REG(SPIx->CRCPR));
  655. }
  656.  
  657. /**
  658.   * @brief  Get Rx CRC
  659.   * @rmtoll RXCRCR       RXCRC         LL_SPI_GetRxCRC
  660.   * @param  SPIx SPI Instance
  661.   * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
  662.   */
  663. __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
  664. {
  665.   return (uint32_t)(READ_REG(SPIx->RXCRCR));
  666. }
  667.  
  668. /**
  669.   * @brief  Get Tx CRC
  670.   * @rmtoll TXCRCR       TXCRC         LL_SPI_GetTxCRC
  671.   * @param  SPIx SPI Instance
  672.   * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
  673.   */
  674. __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
  675. {
  676.   return (uint32_t)(READ_REG(SPIx->TXCRCR));
  677. }
  678.  
  679. /**
  680.   * @}
  681.   */
  682.  
  683. /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
  684.   * @{
  685.   */
  686.  
  687. /**
  688.   * @brief  Set NSS mode
  689.   * @note   LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
  690.   * @rmtoll CR1          SSM           LL_SPI_SetNSSMode\n
  691.   * @rmtoll CR2          SSOE          LL_SPI_SetNSSMode
  692.   * @param  SPIx SPI Instance
  693.   * @param  NSS This parameter can be one of the following values:
  694.   *         @arg @ref LL_SPI_NSS_SOFT
  695.   *         @arg @ref LL_SPI_NSS_HARD_INPUT
  696.   *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
  697.   * @retval None
  698.   */
  699. __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
  700. {
  701.   MODIFY_REG(SPIx->CR1, SPI_CR1_SSM,  NSS);
  702.   MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
  703. }
  704.  
  705. /**
  706.   * @brief  Get NSS mode
  707.   * @rmtoll CR1          SSM           LL_SPI_GetNSSMode\n
  708.   * @rmtoll CR2          SSOE          LL_SPI_GetNSSMode
  709.   * @param  SPIx SPI Instance
  710.   * @retval Returned value can be one of the following values:
  711.   *         @arg @ref LL_SPI_NSS_SOFT
  712.   *         @arg @ref LL_SPI_NSS_HARD_INPUT
  713.   *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
  714.   */
  715. __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
  716. {
  717.   uint32_t Ssm  = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
  718.   uint32_t Ssoe = (READ_BIT(SPIx->CR2,  SPI_CR2_SSOE) << 16U);
  719.   return (Ssm | Ssoe);
  720. }
  721.  
  722. /**
  723.   * @}
  724.   */
  725.  
  726. /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
  727.   * @{
  728.   */
  729.  
  730. /**
  731.   * @brief  Check if Rx buffer is not empty
  732.   * @rmtoll SR           RXNE          LL_SPI_IsActiveFlag_RXNE
  733.   * @param  SPIx SPI Instance
  734.   * @retval State of bit (1 or 0).
  735.   */
  736. __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
  737. {
  738.   return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
  739. }
  740.  
  741. /**
  742.   * @brief  Check if Tx buffer is empty
  743.   * @rmtoll SR           TXE           LL_SPI_IsActiveFlag_TXE
  744.   * @param  SPIx SPI Instance
  745.   * @retval State of bit (1 or 0).
  746.   */
  747. __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
  748. {
  749.   return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
  750. }
  751.  
  752. /**
  753.   * @brief  Get CRC error flag
  754.   * @rmtoll SR           CRCERR        LL_SPI_IsActiveFlag_CRCERR
  755.   * @param  SPIx SPI Instance
  756.   * @retval State of bit (1 or 0).
  757.   */
  758. __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
  759. {
  760.   return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
  761. }
  762.  
  763. /**
  764.   * @brief  Get mode fault error flag
  765.   * @rmtoll SR           MODF          LL_SPI_IsActiveFlag_MODF
  766.   * @param  SPIx SPI Instance
  767.   * @retval State of bit (1 or 0).
  768.   */
  769. __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
  770. {
  771.   return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
  772. }
  773.  
  774. /**
  775.   * @brief  Get overrun error flag
  776.   * @rmtoll SR           OVR           LL_SPI_IsActiveFlag_OVR
  777.   * @param  SPIx SPI Instance
  778.   * @retval State of bit (1 or 0).
  779.   */
  780. __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
  781. {
  782.   return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
  783. }
  784.  
  785. /**
  786.   * @brief  Get busy flag
  787.   * @note   The BSY flag is cleared under any one of the following conditions:
  788.   * -When the SPI is correctly disabled
  789.   * -When a fault is detected in Master mode (MODF bit set to 1)
  790.   * -In Master mode, when it finishes a data transmission and no new data is ready to be
  791.   * sent
  792.   * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
  793.   * each data transfer.
  794.   * @rmtoll SR           BSY           LL_SPI_IsActiveFlag_BSY
  795.   * @param  SPIx SPI Instance
  796.   * @retval State of bit (1 or 0).
  797.   */
  798. __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
  799. {
  800.   return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
  801. }
  802.  
  803. #if defined(SPI_CR2_FRF)
  804. /**
  805.   * @brief  Get frame format error flag
  806.   * @rmtoll SR           FRE           LL_SPI_IsActiveFlag_FRE
  807.   * @param  SPIx SPI Instance
  808.   * @retval State of bit (1 or 0).
  809.   */
  810. __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
  811. {
  812.   return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL);
  813. }
  814. #endif /* SPI_CR2_FRF */
  815.  
  816. /**
  817.   * @brief  Clear CRC error flag
  818.   * @rmtoll SR           CRCERR        LL_SPI_ClearFlag_CRCERR
  819.   * @param  SPIx SPI Instance
  820.   * @retval None
  821.   */
  822. __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
  823. {
  824.   CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
  825. }
  826.  
  827. /**
  828.   * @brief  Clear mode fault error flag
  829.   * @note   Clearing this flag is done by a read access to the SPIx_SR
  830.   *         register followed by a write access to the SPIx_CR1 register
  831.   * @rmtoll SR           MODF          LL_SPI_ClearFlag_MODF
  832.   * @param  SPIx SPI Instance
  833.   * @retval None
  834.   */
  835. __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
  836. {
  837.   __IO uint32_t tmpreg_sr;
  838.   tmpreg_sr = SPIx->SR;
  839.   (void) tmpreg_sr;
  840.   CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
  841. }
  842.  
  843. /**
  844.   * @brief  Clear overrun error flag
  845.   * @note   Clearing this flag is done by a read access to the SPIx_DR
  846.   *         register followed by a read access to the SPIx_SR register
  847.   * @rmtoll SR           OVR           LL_SPI_ClearFlag_OVR
  848.   * @param  SPIx SPI Instance
  849.   * @retval None
  850.   */
  851. __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
  852. {
  853.   __IO uint32_t tmpreg;
  854.   tmpreg = SPIx->DR;
  855.   (void) tmpreg;
  856.   tmpreg = SPIx->SR;
  857.   (void) tmpreg;
  858. }
  859.  
  860. /**
  861.   * @brief  Clear frame format error flag
  862.   * @note   Clearing this flag is done by reading SPIx_SR register
  863.   * @rmtoll SR           FRE           LL_SPI_ClearFlag_FRE
  864.   * @param  SPIx SPI Instance
  865.   * @retval None
  866.   */
  867. __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
  868. {
  869.   __IO uint32_t tmpreg;
  870.   tmpreg = SPIx->SR;
  871.   (void) tmpreg;
  872. }
  873.  
  874. /**
  875.   * @}
  876.   */
  877.  
  878. /** @defgroup SPI_LL_EF_IT_Management Interrupt Management
  879.   * @{
  880.   */
  881.  
  882. /**
  883.   * @brief  Enable error interrupt
  884.   * @note   This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
  885.   * @rmtoll CR2          ERRIE         LL_SPI_EnableIT_ERR
  886.   * @param  SPIx SPI Instance
  887.   * @retval None
  888.   */
  889. __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
  890. {
  891.   SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
  892. }
  893.  
  894. /**
  895.   * @brief  Enable Rx buffer not empty interrupt
  896.   * @rmtoll CR2          RXNEIE        LL_SPI_EnableIT_RXNE
  897.   * @param  SPIx SPI Instance
  898.   * @retval None
  899.   */
  900. __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
  901. {
  902.   SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
  903. }
  904.  
  905. /**
  906.   * @brief  Enable Tx buffer empty interrupt
  907.   * @rmtoll CR2          TXEIE         LL_SPI_EnableIT_TXE
  908.   * @param  SPIx SPI Instance
  909.   * @retval None
  910.   */
  911. __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
  912. {
  913.   SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
  914. }
  915.  
  916. /**
  917.   * @brief  Disable error interrupt
  918.   * @note   This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
  919.   * @rmtoll CR2          ERRIE         LL_SPI_DisableIT_ERR
  920.   * @param  SPIx SPI Instance
  921.   * @retval None
  922.   */
  923. __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
  924. {
  925.   CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
  926. }
  927.  
  928. /**
  929.   * @brief  Disable Rx buffer not empty interrupt
  930.   * @rmtoll CR2          RXNEIE        LL_SPI_DisableIT_RXNE
  931.   * @param  SPIx SPI Instance
  932.   * @retval None
  933.   */
  934. __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
  935. {
  936.   CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
  937. }
  938.  
  939. /**
  940.   * @brief  Disable Tx buffer empty interrupt
  941.   * @rmtoll CR2          TXEIE         LL_SPI_DisableIT_TXE
  942.   * @param  SPIx SPI Instance
  943.   * @retval None
  944.   */
  945. __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
  946. {
  947.   CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
  948. }
  949.  
  950. /**
  951.   * @brief  Check if error interrupt is enabled
  952.   * @rmtoll CR2          ERRIE         LL_SPI_IsEnabledIT_ERR
  953.   * @param  SPIx SPI Instance
  954.   * @retval State of bit (1 or 0).
  955.   */
  956. __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
  957. {
  958.   return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
  959. }
  960.  
  961. /**
  962.   * @brief  Check if Rx buffer not empty interrupt is enabled
  963.   * @rmtoll CR2          RXNEIE        LL_SPI_IsEnabledIT_RXNE
  964.   * @param  SPIx SPI Instance
  965.   * @retval State of bit (1 or 0).
  966.   */
  967. __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
  968. {
  969.   return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL);
  970. }
  971.  
  972. /**
  973.   * @brief  Check if Tx buffer empty interrupt
  974.   * @rmtoll CR2          TXEIE         LL_SPI_IsEnabledIT_TXE
  975.   * @param  SPIx SPI Instance
  976.   * @retval State of bit (1 or 0).
  977.   */
  978. __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
  979. {
  980.   return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
  981. }
  982.  
  983. /**
  984.   * @}
  985.   */
  986.  
  987. /** @defgroup SPI_LL_EF_DMA_Management DMA Management
  988.   * @{
  989.   */
  990.  
  991. /**
  992.   * @brief  Enable DMA Rx
  993.   * @rmtoll CR2          RXDMAEN       LL_SPI_EnableDMAReq_RX
  994.   * @param  SPIx SPI Instance
  995.   * @retval None
  996.   */
  997. __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
  998. {
  999.   SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
  1000. }
  1001.  
  1002. /**
  1003.   * @brief  Disable DMA Rx
  1004.   * @rmtoll CR2          RXDMAEN       LL_SPI_DisableDMAReq_RX
  1005.   * @param  SPIx SPI Instance
  1006.   * @retval None
  1007.   */
  1008. __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
  1009. {
  1010.   CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
  1011. }
  1012.  
  1013. /**
  1014.   * @brief  Check if DMA Rx is enabled
  1015.   * @rmtoll CR2          RXDMAEN       LL_SPI_IsEnabledDMAReq_RX
  1016.   * @param  SPIx SPI Instance
  1017.   * @retval State of bit (1 or 0).
  1018.   */
  1019. __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
  1020. {
  1021.   return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL);
  1022. }
  1023.  
  1024. /**
  1025.   * @brief  Enable DMA Tx
  1026.   * @rmtoll CR2          TXDMAEN       LL_SPI_EnableDMAReq_TX
  1027.   * @param  SPIx SPI Instance
  1028.   * @retval None
  1029.   */
  1030. __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
  1031. {
  1032.   SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
  1033. }
  1034.  
  1035. /**
  1036.   * @brief  Disable DMA Tx
  1037.   * @rmtoll CR2          TXDMAEN       LL_SPI_DisableDMAReq_TX
  1038.   * @param  SPIx SPI Instance
  1039.   * @retval None
  1040.   */
  1041. __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
  1042. {
  1043.   CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
  1044. }
  1045.  
  1046. /**
  1047.   * @brief  Check if DMA Tx is enabled
  1048.   * @rmtoll CR2          TXDMAEN       LL_SPI_IsEnabledDMAReq_TX
  1049.   * @param  SPIx SPI Instance
  1050.   * @retval State of bit (1 or 0).
  1051.   */
  1052. __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
  1053. {
  1054.   return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL);
  1055. }
  1056.  
  1057. /**
  1058.   * @brief  Get the data register address used for DMA transfer
  1059.   * @rmtoll DR           DR            LL_SPI_DMA_GetRegAddr
  1060.   * @param  SPIx SPI Instance
  1061.   * @retval Address of data register
  1062.   */
  1063. __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
  1064. {
  1065.   return (uint32_t) &(SPIx->DR);
  1066. }
  1067.  
  1068. /**
  1069.   * @}
  1070.   */
  1071.  
  1072. /** @defgroup SPI_LL_EF_DATA_Management DATA Management
  1073.   * @{
  1074.   */
  1075.  
  1076. /**
  1077.   * @brief  Read 8-Bits in the data register
  1078.   * @rmtoll DR           DR            LL_SPI_ReceiveData8
  1079.   * @param  SPIx SPI Instance
  1080.   * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
  1081.   */
  1082. __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
  1083. {
  1084.   return (*((__IO uint8_t *)&SPIx->DR));
  1085. }
  1086.  
  1087. /**
  1088.   * @brief  Read 16-Bits in the data register
  1089.   * @rmtoll DR           DR            LL_SPI_ReceiveData16
  1090.   * @param  SPIx SPI Instance
  1091.   * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
  1092.   */
  1093. __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
  1094. {
  1095.   return (uint16_t)(READ_REG(SPIx->DR));
  1096. }
  1097.  
  1098. /**
  1099.   * @brief  Write 8-Bits in the data register
  1100.   * @rmtoll DR           DR            LL_SPI_TransmitData8
  1101.   * @param  SPIx SPI Instance
  1102.   * @param  TxData Value between Min_Data=0x00 and Max_Data=0xFF
  1103.   * @retval None
  1104.   */
  1105. __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
  1106. {
  1107. #if defined (__GNUC__)
  1108.   __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
  1109.   *spidr = TxData;
  1110. #else
  1111.   *((__IO uint8_t *)&SPIx->DR) = TxData;
  1112. #endif /* __GNUC__ */
  1113. }
  1114.  
  1115. /**
  1116.   * @brief  Write 16-Bits in the data register
  1117.   * @rmtoll DR           DR            LL_SPI_TransmitData16
  1118.   * @param  SPIx SPI Instance
  1119.   * @param  TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
  1120.   * @retval None
  1121.   */
  1122. __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
  1123. {
  1124. #if defined (__GNUC__)
  1125.   __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
  1126.   *spidr = TxData;
  1127. #else
  1128.   SPIx->DR = TxData;
  1129. #endif /* __GNUC__ */
  1130. }
  1131.  
  1132. /**
  1133.   * @}
  1134.   */
  1135. #if defined(USE_FULL_LL_DRIVER)
  1136. /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
  1137.   * @{
  1138.   */
  1139.  
  1140. ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
  1141. ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
  1142. void        LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
  1143.  
  1144. /**
  1145.   * @}
  1146.   */
  1147. #endif /* USE_FULL_LL_DRIVER */
  1148. /**
  1149.   * @}
  1150.   */
  1151.  
  1152. /**
  1153.   * @}
  1154.   */
  1155.  
  1156. #if defined(SPI_I2S_SUPPORT)
  1157. /** @defgroup I2S_LL I2S
  1158.   * @{
  1159.   */
  1160.  
  1161. /* Private variables ---------------------------------------------------------*/
  1162. /* Private constants ---------------------------------------------------------*/
  1163. /* Private macros ------------------------------------------------------------*/
  1164.  
  1165. /* Exported types ------------------------------------------------------------*/
  1166. #if defined(USE_FULL_LL_DRIVER)
  1167. /** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
  1168.   * @{
  1169.   */
  1170.  
  1171. /**
  1172.   * @brief  I2S Init structure definition
  1173.   */
  1174.  
  1175. typedef struct
  1176. {
  1177.   uint32_t Mode;                    /*!< Specifies the I2S operating mode.
  1178.                                          This parameter can be a value of @ref I2S_LL_EC_MODE
  1179.  
  1180.                                          This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
  1181.  
  1182.   uint32_t Standard;                /*!< Specifies the standard used for the I2S communication.
  1183.                                          This parameter can be a value of @ref I2S_LL_EC_STANDARD
  1184.  
  1185.                                          This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
  1186.  
  1187.  
  1188.   uint32_t DataFormat;              /*!< Specifies the data format for the I2S communication.
  1189.                                          This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
  1190.  
  1191.                                          This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
  1192.  
  1193.  
  1194.   uint32_t MCLKOutput;              /*!< Specifies whether the I2S MCLK output is enabled or not.
  1195.                                          This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
  1196.  
  1197.                                          This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
  1198.  
  1199.  
  1200.   uint32_t AudioFreq;               /*!< Specifies the frequency selected for the I2S communication.
  1201.                                          This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
  1202.  
  1203.                                          Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
  1204.                                          and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
  1205.  
  1206.  
  1207.   uint32_t ClockPolarity;           /*!< Specifies the idle state of the I2S clock.
  1208.                                          This parameter can be a value of @ref I2S_LL_EC_POLARITY
  1209.  
  1210.                                          This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
  1211.  
  1212. } LL_I2S_InitTypeDef;
  1213.  
  1214. /**
  1215.   * @}
  1216.   */
  1217. #endif /*USE_FULL_LL_DRIVER*/
  1218.  
  1219. /* Exported constants --------------------------------------------------------*/
  1220. /** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
  1221.   * @{
  1222.   */
  1223.  
  1224. /** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
  1225.   * @brief    Flags defines which can be used with LL_I2S_ReadReg function
  1226.   * @{
  1227.   */
  1228. #define LL_I2S_SR_RXNE                     LL_SPI_SR_RXNE            /*!< Rx buffer not empty flag         */
  1229. #define LL_I2S_SR_TXE                      LL_SPI_SR_TXE             /*!< Tx buffer empty flag             */
  1230. #define LL_I2S_SR_BSY                      LL_SPI_SR_BSY             /*!< Busy flag                        */
  1231. #define LL_I2S_SR_UDR                      SPI_SR_UDR                /*!< Underrun flag                    */
  1232. #define LL_I2S_SR_OVR                      LL_SPI_SR_OVR             /*!< Overrun flag                     */
  1233. #define LL_I2S_SR_FRE                      LL_SPI_SR_FRE             /*!< TI mode frame format error flag  */
  1234. /**
  1235.   * @}
  1236.   */
  1237.  
  1238. /** @defgroup SPI_LL_EC_IT IT Defines
  1239.   * @brief    IT defines which can be used with LL_SPI_ReadReg and  LL_SPI_WriteReg functions
  1240.   * @{
  1241.   */
  1242. #define LL_I2S_CR2_RXNEIE                  LL_SPI_CR2_RXNEIE         /*!< Rx buffer not empty interrupt enable */
  1243. #define LL_I2S_CR2_TXEIE                   LL_SPI_CR2_TXEIE          /*!< Tx buffer empty interrupt enable     */
  1244. #define LL_I2S_CR2_ERRIE                   LL_SPI_CR2_ERRIE          /*!< Error interrupt enable               */
  1245. /**
  1246.   * @}
  1247.   */
  1248.  
  1249. /** @defgroup I2S_LL_EC_DATA_FORMAT Data format
  1250.   * @{
  1251.   */
  1252. #define LL_I2S_DATAFORMAT_16B              0x00000000U                                   /*!< Data length 16 bits, Channel length 16bit */
  1253. #define LL_I2S_DATAFORMAT_16B_EXTENDED     (SPI_I2SCFGR_CHLEN)                           /*!< Data length 16 bits, Channel length 32bit */
  1254. #define LL_I2S_DATAFORMAT_24B              (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)    /*!< Data length 24 bits, Channel length 32bit */
  1255. #define LL_I2S_DATAFORMAT_32B              (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)    /*!< Data length 16 bits, Channel length 32bit */
  1256. /**
  1257.   * @}
  1258.   */
  1259.  
  1260. /** @defgroup I2S_LL_EC_POLARITY Clock Polarity
  1261.   * @{
  1262.   */
  1263. #define LL_I2S_POLARITY_LOW                0x00000000U               /*!< Clock steady state is low level  */
  1264. #define LL_I2S_POLARITY_HIGH               (SPI_I2SCFGR_CKPOL)       /*!< Clock steady state is high level */
  1265. /**
  1266.   * @}
  1267.   */
  1268.  
  1269. /** @defgroup I2S_LL_EC_STANDARD I2s Standard
  1270.   * @{
  1271.   */
  1272. #define LL_I2S_STANDARD_PHILIPS            0x00000000U                                                         /*!< I2S standard philips                      */
  1273. #define LL_I2S_STANDARD_MSB                (SPI_I2SCFGR_I2SSTD_0)                                              /*!< MSB justified standard (left justified)   */
  1274. #define LL_I2S_STANDARD_LSB                (SPI_I2SCFGR_I2SSTD_1)                                              /*!< LSB justified standard (right justified)  */
  1275. #define LL_I2S_STANDARD_PCM_SHORT          (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)                       /*!< PCM standard, short frame synchronization */
  1276. #define LL_I2S_STANDARD_PCM_LONG           (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization  */
  1277. /**
  1278.   * @}
  1279.   */
  1280.  
  1281. /** @defgroup I2S_LL_EC_MODE Operation Mode
  1282.   * @{
  1283.   */
  1284. #define LL_I2S_MODE_SLAVE_TX               0x00000000U                                   /*!< Slave Tx configuration  */
  1285. #define LL_I2S_MODE_SLAVE_RX               (SPI_I2SCFGR_I2SCFG_0)                        /*!< Slave Rx configuration  */
  1286. #define LL_I2S_MODE_MASTER_TX              (SPI_I2SCFGR_I2SCFG_1)                        /*!< Master Tx configuration */
  1287. #define LL_I2S_MODE_MASTER_RX              (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
  1288. /**
  1289.   * @}
  1290.   */
  1291.  
  1292. /** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
  1293.   * @{
  1294.   */
  1295. #define LL_I2S_PRESCALER_PARITY_EVEN       0x00000000U               /*!< Odd factor: Real divider value is =  I2SDIV * 2    */
  1296. #define LL_I2S_PRESCALER_PARITY_ODD        (SPI_I2SPR_ODD >> 8U)     /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
  1297. /**
  1298.   * @}
  1299.   */
  1300.  
  1301. #if defined(USE_FULL_LL_DRIVER)
  1302.  
  1303. /** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
  1304.   * @{
  1305.   */
  1306. #define LL_I2S_MCLK_OUTPUT_DISABLE         0x00000000U               /*!< Master clock output is disabled */
  1307. #define LL_I2S_MCLK_OUTPUT_ENABLE          (SPI_I2SPR_MCKOE)         /*!< Master clock output is enabled  */
  1308. /**
  1309.   * @}
  1310.   */
  1311.  
  1312. /** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
  1313.   * @{
  1314.   */
  1315.  
  1316. #define LL_I2S_AUDIOFREQ_192K              192000U       /*!< Audio Frequency configuration 192000 Hz       */
  1317. #define LL_I2S_AUDIOFREQ_96K               96000U        /*!< Audio Frequency configuration  96000 Hz       */
  1318. #define LL_I2S_AUDIOFREQ_48K               48000U        /*!< Audio Frequency configuration  48000 Hz       */
  1319. #define LL_I2S_AUDIOFREQ_44K               44100U        /*!< Audio Frequency configuration  44100 Hz       */
  1320. #define LL_I2S_AUDIOFREQ_32K               32000U        /*!< Audio Frequency configuration  32000 Hz       */
  1321. #define LL_I2S_AUDIOFREQ_22K               22050U        /*!< Audio Frequency configuration  22050 Hz       */
  1322. #define LL_I2S_AUDIOFREQ_16K               16000U        /*!< Audio Frequency configuration  16000 Hz       */
  1323. #define LL_I2S_AUDIOFREQ_11K               11025U        /*!< Audio Frequency configuration  11025 Hz       */
  1324. #define LL_I2S_AUDIOFREQ_8K                8000U         /*!< Audio Frequency configuration   8000 Hz       */
  1325. #define LL_I2S_AUDIOFREQ_DEFAULT           2U            /*!< Audio Freq not specified. Register I2SDIV = 2 */
  1326. /**
  1327.   * @}
  1328.   */
  1329. #endif /* USE_FULL_LL_DRIVER */
  1330.  
  1331. /**
  1332.   * @}
  1333.   */
  1334.  
  1335. /* Exported macro ------------------------------------------------------------*/
  1336. /** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
  1337.   * @{
  1338.   */
  1339.  
  1340. /** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
  1341.   * @{
  1342.   */
  1343.  
  1344. /**
  1345.   * @brief  Write a value in I2S register
  1346.   * @param  __INSTANCE__ I2S Instance
  1347.   * @param  __REG__ Register to be written
  1348.   * @param  __VALUE__ Value to be written in the register
  1349.   * @retval None
  1350.   */
  1351. #define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
  1352.  
  1353. /**
  1354.   * @brief  Read a value in I2S register
  1355.   * @param  __INSTANCE__ I2S Instance
  1356.   * @param  __REG__ Register to be read
  1357.   * @retval Register value
  1358.   */
  1359. #define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
  1360. /**
  1361.   * @}
  1362.   */
  1363.  
  1364. /**
  1365.   * @}
  1366.   */
  1367.  
  1368.  
  1369. /* Exported functions --------------------------------------------------------*/
  1370.  
  1371. /** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
  1372.   * @{
  1373.   */
  1374.  
  1375. /** @defgroup I2S_LL_EF_Configuration Configuration
  1376.   * @{
  1377.   */
  1378.  
  1379. /**
  1380.   * @brief  Select I2S mode and Enable I2S peripheral
  1381.   * @rmtoll I2SCFGR      I2SMOD        LL_I2S_Enable\n
  1382.   *         I2SCFGR      I2SE          LL_I2S_Enable
  1383.   * @param  SPIx SPI Instance
  1384.   * @retval None
  1385.   */
  1386. __STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
  1387. {
  1388.   SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
  1389. }
  1390.  
  1391. /**
  1392.   * @brief  Disable I2S peripheral
  1393.   * @rmtoll I2SCFGR      I2SE          LL_I2S_Disable
  1394.   * @param  SPIx SPI Instance
  1395.   * @retval None
  1396.   */
  1397. __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
  1398. {
  1399.   CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
  1400. }
  1401.  
  1402. /**
  1403.   * @brief  Check if I2S peripheral is enabled
  1404.   * @rmtoll I2SCFGR      I2SE          LL_I2S_IsEnabled
  1405.   * @param  SPIx SPI Instance
  1406.   * @retval State of bit (1 or 0).
  1407.   */
  1408. __STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
  1409. {
  1410.   return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL);
  1411. }
  1412.  
  1413. /**
  1414.   * @brief  Set I2S data frame length
  1415.   * @rmtoll I2SCFGR      DATLEN        LL_I2S_SetDataFormat\n
  1416.   *         I2SCFGR      CHLEN         LL_I2S_SetDataFormat
  1417.   * @param  SPIx SPI Instance
  1418.   * @param  DataFormat This parameter can be one of the following values:
  1419.   *         @arg @ref LL_I2S_DATAFORMAT_16B
  1420.   *         @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
  1421.   *         @arg @ref LL_I2S_DATAFORMAT_24B
  1422.   *         @arg @ref LL_I2S_DATAFORMAT_32B
  1423.   * @retval None
  1424.   */
  1425. __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
  1426. {
  1427.   MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
  1428. }
  1429.  
  1430. /**
  1431.   * @brief  Get I2S data frame length
  1432.   * @rmtoll I2SCFGR      DATLEN        LL_I2S_GetDataFormat\n
  1433.   *         I2SCFGR      CHLEN         LL_I2S_GetDataFormat
  1434.   * @param  SPIx SPI Instance
  1435.   * @retval Returned value can be one of the following values:
  1436.   *         @arg @ref LL_I2S_DATAFORMAT_16B
  1437.   *         @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
  1438.   *         @arg @ref LL_I2S_DATAFORMAT_24B
  1439.   *         @arg @ref LL_I2S_DATAFORMAT_32B
  1440.   */
  1441. __STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
  1442. {
  1443.   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
  1444. }
  1445.  
  1446. /**
  1447.   * @brief  Set I2S clock polarity
  1448.   * @rmtoll I2SCFGR      CKPOL         LL_I2S_SetClockPolarity
  1449.   * @param  SPIx SPI Instance
  1450.   * @param  ClockPolarity This parameter can be one of the following values:
  1451.   *         @arg @ref LL_I2S_POLARITY_LOW
  1452.   *         @arg @ref LL_I2S_POLARITY_HIGH
  1453.   * @retval None
  1454.   */
  1455. __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
  1456. {
  1457.   SET_BIT(SPIx->I2SCFGR, ClockPolarity);
  1458. }
  1459.  
  1460. /**
  1461.   * @brief  Get I2S clock polarity
  1462.   * @rmtoll I2SCFGR      CKPOL         LL_I2S_GetClockPolarity
  1463.   * @param  SPIx SPI Instance
  1464.   * @retval Returned value can be one of the following values:
  1465.   *         @arg @ref LL_I2S_POLARITY_LOW
  1466.   *         @arg @ref LL_I2S_POLARITY_HIGH
  1467.   */
  1468. __STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
  1469. {
  1470.   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
  1471. }
  1472.  
  1473. /**
  1474.   * @brief  Set I2S standard protocol
  1475.   * @rmtoll I2SCFGR      I2SSTD        LL_I2S_SetStandard\n
  1476.   *         I2SCFGR      PCMSYNC       LL_I2S_SetStandard
  1477.   * @param  SPIx SPI Instance
  1478.   * @param  Standard This parameter can be one of the following values:
  1479.   *         @arg @ref LL_I2S_STANDARD_PHILIPS
  1480.   *         @arg @ref LL_I2S_STANDARD_MSB
  1481.   *         @arg @ref LL_I2S_STANDARD_LSB
  1482.   *         @arg @ref LL_I2S_STANDARD_PCM_SHORT
  1483.   *         @arg @ref LL_I2S_STANDARD_PCM_LONG
  1484.   * @retval None
  1485.   */
  1486. __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
  1487. {
  1488.   MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
  1489. }
  1490.  
  1491. /**
  1492.   * @brief  Get I2S standard protocol
  1493.   * @rmtoll I2SCFGR      I2SSTD        LL_I2S_GetStandard\n
  1494.   *         I2SCFGR      PCMSYNC       LL_I2S_GetStandard
  1495.   * @param  SPIx SPI Instance
  1496.   * @retval Returned value can be one of the following values:
  1497.   *         @arg @ref LL_I2S_STANDARD_PHILIPS
  1498.   *         @arg @ref LL_I2S_STANDARD_MSB
  1499.   *         @arg @ref LL_I2S_STANDARD_LSB
  1500.   *         @arg @ref LL_I2S_STANDARD_PCM_SHORT
  1501.   *         @arg @ref LL_I2S_STANDARD_PCM_LONG
  1502.   */
  1503. __STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
  1504. {
  1505.   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
  1506. }
  1507.  
  1508. /**
  1509.   * @brief  Set I2S transfer mode
  1510.   * @rmtoll I2SCFGR      I2SCFG        LL_I2S_SetTransferMode
  1511.   * @param  SPIx SPI Instance
  1512.   * @param  Mode This parameter can be one of the following values:
  1513.   *         @arg @ref LL_I2S_MODE_SLAVE_TX
  1514.   *         @arg @ref LL_I2S_MODE_SLAVE_RX
  1515.   *         @arg @ref LL_I2S_MODE_MASTER_TX
  1516.   *         @arg @ref LL_I2S_MODE_MASTER_RX
  1517.   * @retval None
  1518.   */
  1519. __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
  1520. {
  1521.   MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
  1522. }
  1523.  
  1524. /**
  1525.   * @brief  Get I2S transfer mode
  1526.   * @rmtoll I2SCFGR      I2SCFG        LL_I2S_GetTransferMode
  1527.   * @param  SPIx SPI Instance
  1528.   * @retval Returned value can be one of the following values:
  1529.   *         @arg @ref LL_I2S_MODE_SLAVE_TX
  1530.   *         @arg @ref LL_I2S_MODE_SLAVE_RX
  1531.   *         @arg @ref LL_I2S_MODE_MASTER_TX
  1532.   *         @arg @ref LL_I2S_MODE_MASTER_RX
  1533.   */
  1534. __STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
  1535. {
  1536.   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
  1537. }
  1538.  
  1539. /**
  1540.   * @brief  Set I2S linear prescaler
  1541.   * @rmtoll I2SPR        I2SDIV        LL_I2S_SetPrescalerLinear
  1542.   * @param  SPIx SPI Instance
  1543.   * @param  PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
  1544.   * @retval None
  1545.   */
  1546. __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
  1547. {
  1548.   MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
  1549. }
  1550.  
  1551. /**
  1552.   * @brief  Get I2S linear prescaler
  1553.   * @rmtoll I2SPR        I2SDIV        LL_I2S_GetPrescalerLinear
  1554.   * @param  SPIx SPI Instance
  1555.   * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
  1556.   */
  1557. __STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
  1558. {
  1559.   return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
  1560. }
  1561.  
  1562. /**
  1563.   * @brief  Set I2S parity prescaler
  1564.   * @rmtoll I2SPR        ODD           LL_I2S_SetPrescalerParity
  1565.   * @param  SPIx SPI Instance
  1566.   * @param  PrescalerParity This parameter can be one of the following values:
  1567.   *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
  1568.   *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
  1569.   * @retval None
  1570.   */
  1571. __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
  1572. {
  1573.   MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
  1574. }
  1575.  
  1576. /**
  1577.   * @brief  Get I2S parity prescaler
  1578.   * @rmtoll I2SPR        ODD           LL_I2S_GetPrescalerParity
  1579.   * @param  SPIx SPI Instance
  1580.   * @retval Returned value can be one of the following values:
  1581.   *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
  1582.   *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
  1583.   */
  1584. __STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
  1585. {
  1586.   return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
  1587. }
  1588.  
  1589. /**
  1590.   * @brief  Enable the master clock output (Pin MCK)
  1591.   * @rmtoll I2SPR        MCKOE         LL_I2S_EnableMasterClock
  1592.   * @param  SPIx SPI Instance
  1593.   * @retval None
  1594.   */
  1595. __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
  1596. {
  1597.   SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
  1598. }
  1599.  
  1600. /**
  1601.   * @brief  Disable the master clock output (Pin MCK)
  1602.   * @rmtoll I2SPR        MCKOE         LL_I2S_DisableMasterClock
  1603.   * @param  SPIx SPI Instance
  1604.   * @retval None
  1605.   */
  1606. __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
  1607. {
  1608.   CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
  1609. }
  1610.  
  1611. /**
  1612.   * @brief  Check if the master clock output (Pin MCK) is enabled
  1613.   * @rmtoll I2SPR        MCKOE         LL_I2S_IsEnabledMasterClock
  1614.   * @param  SPIx SPI Instance
  1615.   * @retval State of bit (1 or 0).
  1616.   */
  1617. __STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
  1618. {
  1619.   return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL);
  1620. }
  1621.  
  1622. /**
  1623.   * @}
  1624.   */
  1625.  
  1626. /** @defgroup I2S_LL_EF_FLAG FLAG Management
  1627.   * @{
  1628.   */
  1629.  
  1630. /**
  1631.   * @brief  Check if Rx buffer is not empty
  1632.   * @rmtoll SR           RXNE          LL_I2S_IsActiveFlag_RXNE
  1633.   * @param  SPIx SPI Instance
  1634.   * @retval State of bit (1 or 0).
  1635.   */
  1636. __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
  1637. {
  1638.   return LL_SPI_IsActiveFlag_RXNE(SPIx);
  1639. }
  1640.  
  1641. /**
  1642.   * @brief  Check if Tx buffer is empty
  1643.   * @rmtoll SR           TXE           LL_I2S_IsActiveFlag_TXE
  1644.   * @param  SPIx SPI Instance
  1645.   * @retval State of bit (1 or 0).
  1646.   */
  1647. __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
  1648. {
  1649.   return LL_SPI_IsActiveFlag_TXE(SPIx);
  1650. }
  1651.  
  1652. /**
  1653.   * @brief  Get busy flag
  1654.   * @rmtoll SR           BSY           LL_I2S_IsActiveFlag_BSY
  1655.   * @param  SPIx SPI Instance
  1656.   * @retval State of bit (1 or 0).
  1657.   */
  1658. __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
  1659. {
  1660.   return LL_SPI_IsActiveFlag_BSY(SPIx);
  1661. }
  1662.  
  1663. /**
  1664.   * @brief  Get overrun error flag
  1665.   * @rmtoll SR           OVR           LL_I2S_IsActiveFlag_OVR
  1666.   * @param  SPIx SPI Instance
  1667.   * @retval State of bit (1 or 0).
  1668.   */
  1669. __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
  1670. {
  1671.   return LL_SPI_IsActiveFlag_OVR(SPIx);
  1672. }
  1673.  
  1674. /**
  1675.   * @brief  Get underrun error flag
  1676.   * @rmtoll SR           UDR           LL_I2S_IsActiveFlag_UDR
  1677.   * @param  SPIx SPI Instance
  1678.   * @retval State of bit (1 or 0).
  1679.   */
  1680. __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
  1681. {
  1682.   return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
  1683. }
  1684.  
  1685. #if defined(SPI_CR2_FRF)
  1686. /**
  1687.   * @brief  Get frame format error flag
  1688.   * @rmtoll SR           FRE           LL_I2S_IsActiveFlag_FRE
  1689.   * @param  SPIx SPI Instance
  1690.   * @retval State of bit (1 or 0).
  1691.   */
  1692. __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
  1693. {
  1694.   return LL_SPI_IsActiveFlag_FRE(SPIx);
  1695. }
  1696. #endif /* SPI_CR2_FRF */
  1697.  
  1698. /**
  1699.   * @brief  Get channel side flag.
  1700.   * @note   0: Channel Left has to be transmitted or has been received\n
  1701.   *         1: Channel Right has to be transmitted or has been received\n
  1702.   *         It has no significance in PCM mode.
  1703.   * @rmtoll SR           CHSIDE        LL_I2S_IsActiveFlag_CHSIDE
  1704.   * @param  SPIx SPI Instance
  1705.   * @retval State of bit (1 or 0).
  1706.   */
  1707. __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
  1708. {
  1709.   return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL);
  1710. }
  1711.  
  1712. /**
  1713.   * @brief  Clear overrun error flag
  1714.   * @rmtoll SR           OVR           LL_I2S_ClearFlag_OVR
  1715.   * @param  SPIx SPI Instance
  1716.   * @retval None
  1717.   */
  1718. __STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
  1719. {
  1720.   LL_SPI_ClearFlag_OVR(SPIx);
  1721. }
  1722.  
  1723. /**
  1724.   * @brief  Clear underrun error flag
  1725.   * @rmtoll SR           UDR           LL_I2S_ClearFlag_UDR
  1726.   * @param  SPIx SPI Instance
  1727.   * @retval None
  1728.   */
  1729. __STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
  1730. {
  1731.   __IO uint32_t tmpreg;
  1732.   tmpreg = SPIx->SR;
  1733.   (void)tmpreg;
  1734. }
  1735.  
  1736. /**
  1737.   * @brief  Clear frame format error flag
  1738.   * @rmtoll SR           FRE           LL_I2S_ClearFlag_FRE
  1739.   * @param  SPIx SPI Instance
  1740.   * @retval None
  1741.   */
  1742. __STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
  1743. {
  1744.   LL_SPI_ClearFlag_FRE(SPIx);
  1745. }
  1746.  
  1747. /**
  1748.   * @}
  1749.   */
  1750.  
  1751. /** @defgroup I2S_LL_EF_IT Interrupt Management
  1752.   * @{
  1753.   */
  1754.  
  1755. /**
  1756.   * @brief  Enable error IT
  1757.   * @note   This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
  1758.   * @rmtoll CR2          ERRIE         LL_I2S_EnableIT_ERR
  1759.   * @param  SPIx SPI Instance
  1760.   * @retval None
  1761.   */
  1762. __STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
  1763. {
  1764.   LL_SPI_EnableIT_ERR(SPIx);
  1765. }
  1766.  
  1767. /**
  1768.   * @brief  Enable Rx buffer not empty IT
  1769.   * @rmtoll CR2          RXNEIE        LL_I2S_EnableIT_RXNE
  1770.   * @param  SPIx SPI Instance
  1771.   * @retval None
  1772.   */
  1773. __STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
  1774. {
  1775.   LL_SPI_EnableIT_RXNE(SPIx);
  1776. }
  1777.  
  1778. /**
  1779.   * @brief  Enable Tx buffer empty IT
  1780.   * @rmtoll CR2          TXEIE         LL_I2S_EnableIT_TXE
  1781.   * @param  SPIx SPI Instance
  1782.   * @retval None
  1783.   */
  1784. __STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
  1785. {
  1786.   LL_SPI_EnableIT_TXE(SPIx);
  1787. }
  1788.  
  1789. /**
  1790.   * @brief  Disable error IT
  1791.   * @note   This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
  1792.   * @rmtoll CR2          ERRIE         LL_I2S_DisableIT_ERR
  1793.   * @param  SPIx SPI Instance
  1794.   * @retval None
  1795.   */
  1796. __STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
  1797. {
  1798.   LL_SPI_DisableIT_ERR(SPIx);
  1799. }
  1800.  
  1801. /**
  1802.   * @brief  Disable Rx buffer not empty IT
  1803.   * @rmtoll CR2          RXNEIE        LL_I2S_DisableIT_RXNE
  1804.   * @param  SPIx SPI Instance
  1805.   * @retval None
  1806.   */
  1807. __STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
  1808. {
  1809.   LL_SPI_DisableIT_RXNE(SPIx);
  1810. }
  1811.  
  1812. /**
  1813.   * @brief  Disable Tx buffer empty IT
  1814.   * @rmtoll CR2          TXEIE         LL_I2S_DisableIT_TXE
  1815.   * @param  SPIx SPI Instance
  1816.   * @retval None
  1817.   */
  1818. __STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
  1819. {
  1820.   LL_SPI_DisableIT_TXE(SPIx);
  1821. }
  1822.  
  1823. /**
  1824.   * @brief  Check if ERR IT is enabled
  1825.   * @rmtoll CR2          ERRIE         LL_I2S_IsEnabledIT_ERR
  1826.   * @param  SPIx SPI Instance
  1827.   * @retval State of bit (1 or 0).
  1828.   */
  1829. __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
  1830. {
  1831.   return LL_SPI_IsEnabledIT_ERR(SPIx);
  1832. }
  1833.  
  1834. /**
  1835.   * @brief  Check if RXNE IT is enabled
  1836.   * @rmtoll CR2          RXNEIE        LL_I2S_IsEnabledIT_RXNE
  1837.   * @param  SPIx SPI Instance
  1838.   * @retval State of bit (1 or 0).
  1839.   */
  1840. __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
  1841. {
  1842.   return LL_SPI_IsEnabledIT_RXNE(SPIx);
  1843. }
  1844.  
  1845. /**
  1846.   * @brief  Check if TXE IT is enabled
  1847.   * @rmtoll CR2          TXEIE         LL_I2S_IsEnabledIT_TXE
  1848.   * @param  SPIx SPI Instance
  1849.   * @retval State of bit (1 or 0).
  1850.   */
  1851. __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
  1852. {
  1853.   return LL_SPI_IsEnabledIT_TXE(SPIx);
  1854. }
  1855.  
  1856. /**
  1857.   * @}
  1858.   */
  1859.  
  1860. /** @defgroup I2S_LL_EF_DMA DMA Management
  1861.   * @{
  1862.   */
  1863.  
  1864. /**
  1865.   * @brief  Enable DMA Rx
  1866.   * @rmtoll CR2          RXDMAEN       LL_I2S_EnableDMAReq_RX
  1867.   * @param  SPIx SPI Instance
  1868.   * @retval None
  1869.   */
  1870. __STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
  1871. {
  1872.   LL_SPI_EnableDMAReq_RX(SPIx);
  1873. }
  1874.  
  1875. /**
  1876.   * @brief  Disable DMA Rx
  1877.   * @rmtoll CR2          RXDMAEN       LL_I2S_DisableDMAReq_RX
  1878.   * @param  SPIx SPI Instance
  1879.   * @retval None
  1880.   */
  1881. __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
  1882. {
  1883.   LL_SPI_DisableDMAReq_RX(SPIx);
  1884. }
  1885.  
  1886. /**
  1887.   * @brief  Check if DMA Rx is enabled
  1888.   * @rmtoll CR2          RXDMAEN       LL_I2S_IsEnabledDMAReq_RX
  1889.   * @param  SPIx SPI Instance
  1890.   * @retval State of bit (1 or 0).
  1891.   */
  1892. __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
  1893. {
  1894.   return LL_SPI_IsEnabledDMAReq_RX(SPIx);
  1895. }
  1896.  
  1897. /**
  1898.   * @brief  Enable DMA Tx
  1899.   * @rmtoll CR2          TXDMAEN       LL_I2S_EnableDMAReq_TX
  1900.   * @param  SPIx SPI Instance
  1901.   * @retval None
  1902.   */
  1903. __STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
  1904. {
  1905.   LL_SPI_EnableDMAReq_TX(SPIx);
  1906. }
  1907.  
  1908. /**
  1909.   * @brief  Disable DMA Tx
  1910.   * @rmtoll CR2          TXDMAEN       LL_I2S_DisableDMAReq_TX
  1911.   * @param  SPIx SPI Instance
  1912.   * @retval None
  1913.   */
  1914. __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
  1915. {
  1916.   LL_SPI_DisableDMAReq_TX(SPIx);
  1917. }
  1918.  
  1919. /**
  1920.   * @brief  Check if DMA Tx is enabled
  1921.   * @rmtoll CR2          TXDMAEN       LL_I2S_IsEnabledDMAReq_TX
  1922.   * @param  SPIx SPI Instance
  1923.   * @retval State of bit (1 or 0).
  1924.   */
  1925. __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
  1926. {
  1927.   return LL_SPI_IsEnabledDMAReq_TX(SPIx);
  1928. }
  1929.  
  1930. /**
  1931.   * @}
  1932.   */
  1933.  
  1934. /** @defgroup I2S_LL_EF_DATA DATA Management
  1935.   * @{
  1936.   */
  1937.  
  1938. /**
  1939.   * @brief  Read 16-Bits in data register
  1940.   * @rmtoll DR           DR            LL_I2S_ReceiveData16
  1941.   * @param  SPIx SPI Instance
  1942.   * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
  1943.   */
  1944. __STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
  1945. {
  1946.   return LL_SPI_ReceiveData16(SPIx);
  1947. }
  1948.  
  1949. /**
  1950.   * @brief  Write 16-Bits in data register
  1951.   * @rmtoll DR           DR            LL_I2S_TransmitData16
  1952.   * @param  SPIx SPI Instance
  1953.   * @param  TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
  1954.   * @retval None
  1955.   */
  1956. __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
  1957. {
  1958.   LL_SPI_TransmitData16(SPIx, TxData);
  1959. }
  1960.  
  1961. /**
  1962.   * @}
  1963.   */
  1964.  
  1965. #if defined(USE_FULL_LL_DRIVER)
  1966. /** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
  1967.   * @{
  1968.   */
  1969.  
  1970. ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
  1971. ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
  1972. void        LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
  1973. void        LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
  1974.  
  1975. /**
  1976.   * @}
  1977.   */
  1978. #endif /* USE_FULL_LL_DRIVER */
  1979.  
  1980. /**
  1981.   * @}
  1982.   */
  1983.  
  1984. /**
  1985.   * @}
  1986.   */
  1987. #endif /* SPI_I2S_SUPPORT */
  1988.  
  1989. #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
  1990.  
  1991. /**
  1992.   * @}
  1993.   */
  1994.  
  1995. #ifdef __cplusplus
  1996. }
  1997. #endif
  1998.  
  1999. #endif /* STM32L1xx_LL_SPI_H */
  2000.  
  2001.