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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32l1xx_ll_spi.h
  4.   * @author  MCD Application Team
  5.   * @brief   Header file of SPI LL module.
  6.   ******************************************************************************
  7.   * @attention
  8.   *
  9.   * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
  10.   * All rights reserved.</center></h2>
  11.   *
  12.   * This software component is licensed by ST under BSD 3-Clause license,
  13.   * the "License"; You may not use this file except in compliance with the
  14.   * License. You may obtain a copy of the License at:
  15.   *                        opensource.org/licenses/BSD-3-Clause
  16.   *
  17.   ******************************************************************************
  18.   */
  19.  
  20. /* Define to prevent recursive inclusion -------------------------------------*/
  21. #ifndef STM32L1xx_LL_SPI_H
  22. #define STM32L1xx_LL_SPI_H
  23.  
  24. #ifdef __cplusplus
  25. extern "C" {
  26. #endif
  27.  
  28. /* Includes ------------------------------------------------------------------*/
  29. #include "stm32l1xx.h"
  30.  
  31. /** @addtogroup STM32L1xx_LL_Driver
  32.   * @{
  33.   */
  34.  
  35. #if defined (SPI1) || defined (SPI2) || defined (SPI3)
  36.  
  37. /** @defgroup SPI_LL SPI
  38.   * @{
  39.   */
  40.  
  41. /* Private types -------------------------------------------------------------*/
  42. /* Private variables ---------------------------------------------------------*/
  43. /* Private macros ------------------------------------------------------------*/
  44.  
  45. /* Exported types ------------------------------------------------------------*/
  46. #if defined(USE_FULL_LL_DRIVER)
  47. /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
  48.   * @{
  49.   */
  50.  
  51. /**
  52.   * @brief  SPI Init structures definition
  53.   */
  54. typedef struct
  55. {
  56.   uint32_t TransferDirection;       /*!< Specifies the SPI unidirectional or bidirectional data mode.
  57.                                          This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
  58.  
  59.                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
  60.  
  61.   uint32_t Mode;                    /*!< Specifies the SPI mode (Master/Slave).
  62.                                          This parameter can be a value of @ref SPI_LL_EC_MODE.
  63.  
  64.                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
  65.  
  66.   uint32_t DataWidth;               /*!< Specifies the SPI data width.
  67.                                          This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
  68.  
  69.                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
  70.  
  71.   uint32_t ClockPolarity;           /*!< Specifies the serial clock steady state.
  72.                                          This parameter can be a value of @ref SPI_LL_EC_POLARITY.
  73.  
  74.                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
  75.  
  76.   uint32_t ClockPhase;              /*!< Specifies the clock active edge for the bit capture.
  77.                                          This parameter can be a value of @ref SPI_LL_EC_PHASE.
  78.  
  79.                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
  80.  
  81.   uint32_t NSS;                     /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
  82.                                          This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
  83.  
  84.                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
  85.  
  86.   uint32_t BaudRate;                /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
  87.                                          This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
  88.                                          @note The communication clock is derived from the master clock. The slave clock does not need to be set.
  89.  
  90.                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
  91.  
  92.   uint32_t BitOrder;                /*!< Specifies whether data transfers start from MSB or LSB bit.
  93.                                          This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
  94.  
  95.                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
  96.  
  97.   uint32_t CRCCalculation;          /*!< Specifies if the CRC calculation is enabled or not.
  98.                                          This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
  99.  
  100.                                          This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
  101.  
  102.   uint32_t CRCPoly;                 /*!< Specifies the polynomial used for the CRC calculation.
  103.                                          This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
  104.  
  105.                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
  106.  
  107. } LL_SPI_InitTypeDef;
  108.  
  109. /**
  110.   * @}
  111.   */
  112. #endif /* USE_FULL_LL_DRIVER */
  113.  
  114. /* Exported constants --------------------------------------------------------*/
  115. /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
  116.   * @{
  117.   */
  118.  
  119. /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
  120.   * @brief    Flags defines which can be used with LL_SPI_ReadReg function
  121.   * @{
  122.   */
  123. #define LL_SPI_SR_RXNE                     SPI_SR_RXNE               /*!< Rx buffer not empty flag         */
  124. #define LL_SPI_SR_TXE                      SPI_SR_TXE                /*!< Tx buffer empty flag             */
  125. #define LL_SPI_SR_BSY                      SPI_SR_BSY                /*!< Busy flag                        */
  126. #define LL_SPI_SR_CRCERR                   SPI_SR_CRCERR             /*!< CRC error flag                   */
  127. #define LL_SPI_SR_MODF                     SPI_SR_MODF               /*!< Mode fault flag                  */
  128. #define LL_SPI_SR_OVR                      SPI_SR_OVR                /*!< Overrun flag                     */
  129. #define LL_SPI_SR_FRE                      SPI_SR_FRE                /*!< TI mode frame format error flag  */
  130. /**
  131.   * @}
  132.   */
  133.  
  134. /** @defgroup SPI_LL_EC_IT IT Defines
  135.   * @brief    IT defines which can be used with LL_SPI_ReadReg and  LL_SPI_WriteReg functions
  136.   * @{
  137.   */
  138. #define LL_SPI_CR2_RXNEIE                  SPI_CR2_RXNEIE            /*!< Rx buffer not empty interrupt enable */
  139. #define LL_SPI_CR2_TXEIE                   SPI_CR2_TXEIE             /*!< Tx buffer empty interrupt enable     */
  140. #define LL_SPI_CR2_ERRIE                   SPI_CR2_ERRIE             /*!< Error interrupt enable               */
  141. /**
  142.   * @}
  143.   */
  144.  
  145. /** @defgroup SPI_LL_EC_MODE Operation Mode
  146.   * @{
  147.   */
  148. #define LL_SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)    /*!< Master configuration  */
  149. #define LL_SPI_MODE_SLAVE                  0x00000000U                     /*!< Slave configuration   */
  150. /**
  151.   * @}
  152.   */
  153.  
  154. /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
  155.   * @brief  SPI TI Mode not supported for Category 1 and 2
  156.   * @{
  157.   */
  158. #define LL_SPI_PROTOCOL_MOTOROLA           0x00000000U               /*!< Motorola mode. Used as default value */
  159. #if defined(SPI_CR2_FRF)
  160. #define LL_SPI_PROTOCOL_TI                 (SPI_CR2_FRF)             /*!< TI mode                              */
  161. #endif
  162. /**
  163.   * @}
  164.   */
  165.  
  166. /** @defgroup SPI_LL_EC_PHASE Clock Phase
  167.   * @{
  168.   */
  169. #define LL_SPI_PHASE_1EDGE                 0x00000000U               /*!< First clock transition is the first data capture edge  */
  170. #define LL_SPI_PHASE_2EDGE                 (SPI_CR1_CPHA)            /*!< Second clock transition is the first data capture edge */
  171. /**
  172.   * @}
  173.   */
  174.  
  175. /** @defgroup SPI_LL_EC_POLARITY Clock Polarity
  176.   * @{
  177.   */
  178. #define LL_SPI_POLARITY_LOW                0x00000000U               /*!< Clock to 0 when idle */
  179. #define LL_SPI_POLARITY_HIGH               (SPI_CR1_CPOL)            /*!< Clock to 1 when idle */
  180. /**
  181.   * @}
  182.   */
  183.  
  184. /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
  185.   * @{
  186.   */
  187. #define LL_SPI_BAUDRATEPRESCALER_DIV2      0x00000000U                                    /*!< BaudRate control equal to fPCLK/2   */
  188. #define LL_SPI_BAUDRATEPRESCALER_DIV4      (SPI_CR1_BR_0)                                 /*!< BaudRate control equal to fPCLK/4   */
  189. #define LL_SPI_BAUDRATEPRESCALER_DIV8      (SPI_CR1_BR_1)                                 /*!< BaudRate control equal to fPCLK/8   */
  190. #define LL_SPI_BAUDRATEPRESCALER_DIV16     (SPI_CR1_BR_1 | SPI_CR1_BR_0)                  /*!< BaudRate control equal to fPCLK/16  */
  191. #define LL_SPI_BAUDRATEPRESCALER_DIV32     (SPI_CR1_BR_2)                                 /*!< BaudRate control equal to fPCLK/32  */
  192. #define LL_SPI_BAUDRATEPRESCALER_DIV64     (SPI_CR1_BR_2 | SPI_CR1_BR_0)                  /*!< BaudRate control equal to fPCLK/64  */
  193. #define LL_SPI_BAUDRATEPRESCALER_DIV128    (SPI_CR1_BR_2 | SPI_CR1_BR_1)                  /*!< BaudRate control equal to fPCLK/128 */
  194. #define LL_SPI_BAUDRATEPRESCALER_DIV256    (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)   /*!< BaudRate control equal to fPCLK/256 */
  195. /**
  196.   * @}
  197.   */
  198.  
  199. /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
  200.   * @{
  201.   */
  202. #define LL_SPI_LSB_FIRST                   (SPI_CR1_LSBFIRST)        /*!< Data is transmitted/received with the LSB first */
  203. #define LL_SPI_MSB_FIRST                   0x00000000U               /*!< Data is transmitted/received with the MSB first */
  204. /**
  205.   * @}
  206.   */
  207.  
  208. /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
  209.   * @{
  210.   */
  211. #define LL_SPI_FULL_DUPLEX                 0x00000000U                          /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
  212. #define LL_SPI_SIMPLEX_RX                  (SPI_CR1_RXONLY)                     /*!< Simplex Rx mode.  Rx transfer only on 1 line    */
  213. #define LL_SPI_HALF_DUPLEX_RX              (SPI_CR1_BIDIMODE)                   /*!< Half-Duplex Rx mode. Rx transfer on 1 line      */
  214. #define LL_SPI_HALF_DUPLEX_TX              (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)  /*!< Half-Duplex Tx mode. Tx transfer on 1 line      */
  215. /**
  216.   * @}
  217.   */
  218.  
  219. /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
  220.   * @{
  221.   */
  222. #define LL_SPI_NSS_SOFT                    (SPI_CR1_SSM)                     /*!< NSS managed internally. NSS pin not used and free              */
  223. #define LL_SPI_NSS_HARD_INPUT              0x00000000U                       /*!< NSS pin used in Input. Only used in Master mode                */
  224. #define LL_SPI_NSS_HARD_OUTPUT             (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
  225. /**
  226.   * @}
  227.   */
  228.  
  229. /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
  230.   * @{
  231.   */
  232. #define LL_SPI_DATAWIDTH_8BIT              0x00000000U                       /*!< Data length for SPI transfer:  8 bits */
  233. #define LL_SPI_DATAWIDTH_16BIT             (SPI_CR1_DFF)                     /*!< Data length for SPI transfer:  16 bits */
  234. /**
  235.   * @}
  236.   */
  237. #if defined(USE_FULL_LL_DRIVER)
  238.  
  239. /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
  240.   * @{
  241.   */
  242. #define LL_SPI_CRCCALCULATION_DISABLE      0x00000000U               /*!< CRC calculation disabled */
  243. #define LL_SPI_CRCCALCULATION_ENABLE       (SPI_CR1_CRCEN)           /*!< CRC calculation enabled  */
  244. /**
  245.   * @}
  246.   */
  247. #endif /* USE_FULL_LL_DRIVER */
  248.  
  249. /**
  250.   * @}
  251.   */
  252.  
  253. /* Exported macro ------------------------------------------------------------*/
  254. /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
  255.   * @{
  256.   */
  257.  
  258. /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
  259.   * @{
  260.   */
  261.  
  262. /**
  263.   * @brief  Write a value in SPI register
  264.   * @param  __INSTANCE__ SPI Instance
  265.   * @param  __REG__ Register to be written
  266.   * @param  __VALUE__ Value to be written in the register
  267.   * @retval None
  268.   */
  269. #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
  270.  
  271. /**
  272.   * @brief  Read a value in SPI register
  273.   * @param  __INSTANCE__ SPI Instance
  274.   * @param  __REG__ Register to be read
  275.   * @retval Register value
  276.   */
  277. #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
  278. /**
  279.   * @}
  280.   */
  281.  
  282. /**
  283.   * @}
  284.   */
  285.  
  286. /* Exported functions --------------------------------------------------------*/
  287. /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
  288.   * @{
  289.   */
  290.  
  291. /** @defgroup SPI_LL_EF_Configuration Configuration
  292.   * @{
  293.   */
  294.  
  295. /**
  296.   * @brief  Enable SPI peripheral
  297.   * @rmtoll CR1          SPE           LL_SPI_Enable
  298.   * @param  SPIx SPI Instance
  299.   * @retval None
  300.   */
  301. __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
  302. {
  303.   SET_BIT(SPIx->CR1, SPI_CR1_SPE);
  304. }
  305.  
  306. /**
  307.   * @brief  Disable SPI peripheral
  308.   * @note   When disabling the SPI, follow the procedure described in the Reference Manual.
  309.   * @rmtoll CR1          SPE           LL_SPI_Disable
  310.   * @param  SPIx SPI Instance
  311.   * @retval None
  312.   */
  313. __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
  314. {
  315.   CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
  316. }
  317.  
  318. /**
  319.   * @brief  Check if SPI peripheral is enabled
  320.   * @rmtoll CR1          SPE           LL_SPI_IsEnabled
  321.   * @param  SPIx SPI Instance
  322.   * @retval State of bit (1 or 0).
  323.   */
  324. __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
  325. {
  326.   return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
  327. }
  328.  
  329. /**
  330.   * @brief  Set SPI operation mode to Master or Slave
  331.   * @note   This bit should not be changed when communication is ongoing.
  332.   * @rmtoll CR1          MSTR          LL_SPI_SetMode\n
  333.   *         CR1          SSI           LL_SPI_SetMode
  334.   * @param  SPIx SPI Instance
  335.   * @param  Mode This parameter can be one of the following values:
  336.   *         @arg @ref LL_SPI_MODE_MASTER
  337.   *         @arg @ref LL_SPI_MODE_SLAVE
  338.   * @retval None
  339.   */
  340. __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
  341. {
  342.   MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
  343. }
  344.  
  345. /**
  346.   * @brief  Get SPI operation mode (Master or Slave)
  347.   * @rmtoll CR1          MSTR          LL_SPI_GetMode\n
  348.   *         CR1          SSI           LL_SPI_GetMode
  349.   * @param  SPIx SPI Instance
  350.   * @retval Returned value can be one of the following values:
  351.   *         @arg @ref LL_SPI_MODE_MASTER
  352.   *         @arg @ref LL_SPI_MODE_SLAVE
  353.   */
  354. __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
  355. {
  356.   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
  357. }
  358.  
  359. #if defined(SPI_CR2_FRF)
  360. /**
  361.   * @brief  Set serial protocol used. TI Mode not supported for Category 1 and 2.
  362.   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
  363.   * @rmtoll CR2          FRF           LL_SPI_SetStandard
  364.   * @param  SPIx SPI Instance
  365.   * @param  Standard This parameter can be one of the following values:
  366.   *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA
  367.   *         @arg @ref LL_SPI_PROTOCOL_TI
  368.   * @retval None
  369.   */
  370. __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
  371. {
  372.   MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
  373. }
  374.  
  375. /**
  376.   * @brief  Get serial protocol used
  377.   * @rmtoll CR2          FRF           LL_SPI_GetStandard
  378.   * @param  SPIx SPI Instance
  379.   * @retval Returned value can be one of the following values:
  380.   *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA
  381.   *         @arg @ref LL_SPI_PROTOCOL_TI
  382.   */
  383. __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
  384. {
  385.   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
  386. }
  387. #endif
  388.  
  389. /**
  390.   * @brief  Set clock phase
  391.   * @note   This bit should not be changed when communication is ongoing.
  392.   *         This bit is not used in SPI TI mode.
  393.   * @rmtoll CR1          CPHA          LL_SPI_SetClockPhase
  394.   * @param  SPIx SPI Instance
  395.   * @param  ClockPhase This parameter can be one of the following values:
  396.   *         @arg @ref LL_SPI_PHASE_1EDGE
  397.   *         @arg @ref LL_SPI_PHASE_2EDGE
  398.   * @retval None
  399.   */
  400. __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
  401. {
  402.   MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
  403. }
  404.  
  405. /**
  406.   * @brief  Get clock phase
  407.   * @rmtoll CR1          CPHA          LL_SPI_GetClockPhase
  408.   * @param  SPIx SPI Instance
  409.   * @retval Returned value can be one of the following values:
  410.   *         @arg @ref LL_SPI_PHASE_1EDGE
  411.   *         @arg @ref LL_SPI_PHASE_2EDGE
  412.   */
  413. __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
  414. {
  415.   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
  416. }
  417.  
  418. /**
  419.   * @brief  Set clock polarity
  420.   * @note   This bit should not be changed when communication is ongoing.
  421.   *         This bit is not used in SPI TI mode.
  422.   * @rmtoll CR1          CPOL          LL_SPI_SetClockPolarity
  423.   * @param  SPIx SPI Instance
  424.   * @param  ClockPolarity This parameter can be one of the following values:
  425.   *         @arg @ref LL_SPI_POLARITY_LOW
  426.   *         @arg @ref LL_SPI_POLARITY_HIGH
  427.   * @retval None
  428.   */
  429. __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
  430. {
  431.   MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
  432. }
  433.  
  434. /**
  435.   * @brief  Get clock polarity
  436.   * @rmtoll CR1          CPOL          LL_SPI_GetClockPolarity
  437.   * @param  SPIx SPI Instance
  438.   * @retval Returned value can be one of the following values:
  439.   *         @arg @ref LL_SPI_POLARITY_LOW
  440.   *         @arg @ref LL_SPI_POLARITY_HIGH
  441.   */
  442. __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
  443. {
  444.   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
  445. }
  446.  
  447. /**
  448.   * @brief  Set baud rate prescaler
  449.   * @note   These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
  450.   * @rmtoll CR1          BR            LL_SPI_SetBaudRatePrescaler
  451.   * @param  SPIx SPI Instance
  452.   * @param  BaudRate This parameter can be one of the following values:
  453.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
  454.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
  455.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
  456.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
  457.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
  458.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
  459.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
  460.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
  461.   * @retval None
  462.   */
  463. __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
  464. {
  465.   MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
  466. }
  467.  
  468. /**
  469.   * @brief  Get baud rate prescaler
  470.   * @rmtoll CR1          BR            LL_SPI_GetBaudRatePrescaler
  471.   * @param  SPIx SPI Instance
  472.   * @retval Returned value can be one of the following values:
  473.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
  474.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
  475.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
  476.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
  477.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
  478.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
  479.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
  480.   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
  481.   */
  482. __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
  483. {
  484.   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
  485. }
  486.  
  487. /**
  488.   * @brief  Set transfer bit order
  489.   * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
  490.   * @rmtoll CR1          LSBFIRST      LL_SPI_SetTransferBitOrder
  491.   * @param  SPIx SPI Instance
  492.   * @param  BitOrder This parameter can be one of the following values:
  493.   *         @arg @ref LL_SPI_LSB_FIRST
  494.   *         @arg @ref LL_SPI_MSB_FIRST
  495.   * @retval None
  496.   */
  497. __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
  498. {
  499.   MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
  500. }
  501.  
  502. /**
  503.   * @brief  Get transfer bit order
  504.   * @rmtoll CR1          LSBFIRST      LL_SPI_GetTransferBitOrder
  505.   * @param  SPIx SPI Instance
  506.   * @retval Returned value can be one of the following values:
  507.   *         @arg @ref LL_SPI_LSB_FIRST
  508.   *         @arg @ref LL_SPI_MSB_FIRST
  509.   */
  510. __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
  511. {
  512.   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
  513. }
  514.  
  515. /**
  516.   * @brief  Set transfer direction mode
  517.   * @note   For Half-Duplex mode, Rx Direction is set by default.
  518.   *         In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
  519.   * @rmtoll CR1          RXONLY        LL_SPI_SetTransferDirection\n
  520.   *         CR1          BIDIMODE      LL_SPI_SetTransferDirection\n
  521.   *         CR1          BIDIOE        LL_SPI_SetTransferDirection
  522.   * @param  SPIx SPI Instance
  523.   * @param  TransferDirection This parameter can be one of the following values:
  524.   *         @arg @ref LL_SPI_FULL_DUPLEX
  525.   *         @arg @ref LL_SPI_SIMPLEX_RX
  526.   *         @arg @ref LL_SPI_HALF_DUPLEX_RX
  527.   *         @arg @ref LL_SPI_HALF_DUPLEX_TX
  528.   * @retval None
  529.   */
  530. __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
  531. {
  532.   MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
  533. }
  534.  
  535. /**
  536.   * @brief  Get transfer direction mode
  537.   * @rmtoll CR1          RXONLY        LL_SPI_GetTransferDirection\n
  538.   *         CR1          BIDIMODE      LL_SPI_GetTransferDirection\n
  539.   *         CR1          BIDIOE        LL_SPI_GetTransferDirection
  540.   * @param  SPIx SPI Instance
  541.   * @retval Returned value can be one of the following values:
  542.   *         @arg @ref LL_SPI_FULL_DUPLEX
  543.   *         @arg @ref LL_SPI_SIMPLEX_RX
  544.   *         @arg @ref LL_SPI_HALF_DUPLEX_RX
  545.   *         @arg @ref LL_SPI_HALF_DUPLEX_TX
  546.   */
  547. __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
  548. {
  549.   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
  550. }
  551.  
  552. /**
  553.   * @brief  Set frame data width
  554.   * @rmtoll CR1          DFF           LL_SPI_SetDataWidth
  555.   * @param  SPIx SPI Instance
  556.   * @param  DataWidth This parameter can be one of the following values:
  557.   *         @arg @ref LL_SPI_DATAWIDTH_8BIT
  558.   *         @arg @ref LL_SPI_DATAWIDTH_16BIT
  559.   * @retval None
  560.   */
  561. __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
  562. {
  563.   MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth);
  564. }
  565.  
  566. /**
  567.   * @brief  Get frame data width
  568.   * @rmtoll CR1          DFF           LL_SPI_GetDataWidth
  569.   * @param  SPIx SPI Instance
  570.   * @retval Returned value can be one of the following values:
  571.   *         @arg @ref LL_SPI_DATAWIDTH_8BIT
  572.   *         @arg @ref LL_SPI_DATAWIDTH_16BIT
  573.   */
  574. __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
  575. {
  576.   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF));
  577. }
  578.  
  579. /**
  580.   * @}
  581.   */
  582.  
  583. /** @defgroup SPI_LL_EF_CRC_Management CRC Management
  584.   * @{
  585.   */
  586.  
  587. /**
  588.   * @brief  Enable CRC
  589.   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
  590.   * @rmtoll CR1          CRCEN         LL_SPI_EnableCRC
  591.   * @param  SPIx SPI Instance
  592.   * @retval None
  593.   */
  594. __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
  595. {
  596.   SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
  597. }
  598.  
  599. /**
  600.   * @brief  Disable CRC
  601.   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
  602.   * @rmtoll CR1          CRCEN         LL_SPI_DisableCRC
  603.   * @param  SPIx SPI Instance
  604.   * @retval None
  605.   */
  606. __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
  607. {
  608.   CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
  609. }
  610.  
  611. /**
  612.   * @brief  Check if CRC is enabled
  613.   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
  614.   * @rmtoll CR1          CRCEN         LL_SPI_IsEnabledCRC
  615.   * @param  SPIx SPI Instance
  616.   * @retval State of bit (1 or 0).
  617.   */
  618. __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
  619. {
  620.   return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
  621. }
  622.  
  623. /**
  624.   * @brief  Set CRCNext to transfer CRC on the line
  625.   * @note   This bit has to be written as soon as the last data is written in the SPIx_DR register.
  626.   * @rmtoll CR1          CRCNEXT       LL_SPI_SetCRCNext
  627.   * @param  SPIx SPI Instance
  628.   * @retval None
  629.   */
  630. __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
  631. {
  632.   SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
  633. }
  634.  
  635. /**
  636.   * @brief  Set polynomial for CRC calculation
  637.   * @rmtoll CRCPR        CRCPOLY       LL_SPI_SetCRCPolynomial
  638.   * @param  SPIx SPI Instance
  639.   * @param  CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
  640.   * @retval None
  641.   */
  642. __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
  643. {
  644.   WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
  645. }
  646.  
  647. /**
  648.   * @brief  Get polynomial for CRC calculation
  649.   * @rmtoll CRCPR        CRCPOLY       LL_SPI_GetCRCPolynomial
  650.   * @param  SPIx SPI Instance
  651.   * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
  652.   */
  653. __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
  654. {
  655.   return (uint32_t)(READ_REG(SPIx->CRCPR));
  656. }
  657.  
  658. /**
  659.   * @brief  Get Rx CRC
  660.   * @rmtoll RXCRCR       RXCRC         LL_SPI_GetRxCRC
  661.   * @param  SPIx SPI Instance
  662.   * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
  663.   */
  664. __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
  665. {
  666.   return (uint32_t)(READ_REG(SPIx->RXCRCR));
  667. }
  668.  
  669. /**
  670.   * @brief  Get Tx CRC
  671.   * @rmtoll TXCRCR       TXCRC         LL_SPI_GetTxCRC
  672.   * @param  SPIx SPI Instance
  673.   * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
  674.   */
  675. __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
  676. {
  677.   return (uint32_t)(READ_REG(SPIx->TXCRCR));
  678. }
  679.  
  680. /**
  681.   * @}
  682.   */
  683.  
  684. /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
  685.   * @{
  686.   */
  687.  
  688. /**
  689.   * @brief  Set NSS mode
  690.   * @note   LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
  691.   * @rmtoll CR1          SSM           LL_SPI_SetNSSMode\n
  692.   * @rmtoll CR2          SSOE          LL_SPI_SetNSSMode
  693.   * @param  SPIx SPI Instance
  694.   * @param  NSS This parameter can be one of the following values:
  695.   *         @arg @ref LL_SPI_NSS_SOFT
  696.   *         @arg @ref LL_SPI_NSS_HARD_INPUT
  697.   *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
  698.   * @retval None
  699.   */
  700. __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
  701. {
  702.   MODIFY_REG(SPIx->CR1, SPI_CR1_SSM,  NSS);
  703.   MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
  704. }
  705.  
  706. /**
  707.   * @brief  Get NSS mode
  708.   * @rmtoll CR1          SSM           LL_SPI_GetNSSMode\n
  709.   * @rmtoll CR2          SSOE          LL_SPI_GetNSSMode
  710.   * @param  SPIx SPI Instance
  711.   * @retval Returned value can be one of the following values:
  712.   *         @arg @ref LL_SPI_NSS_SOFT
  713.   *         @arg @ref LL_SPI_NSS_HARD_INPUT
  714.   *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
  715.   */
  716. __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
  717. {
  718.   uint32_t Ssm  = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
  719.   uint32_t Ssoe = (READ_BIT(SPIx->CR2,  SPI_CR2_SSOE) << 16U);
  720.   return (Ssm | Ssoe);
  721. }
  722.  
  723. /**
  724.   * @}
  725.   */
  726.  
  727. /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
  728.   * @{
  729.   */
  730.  
  731. /**
  732.   * @brief  Check if Rx buffer is not empty
  733.   * @rmtoll SR           RXNE          LL_SPI_IsActiveFlag_RXNE
  734.   * @param  SPIx SPI Instance
  735.   * @retval State of bit (1 or 0).
  736.   */
  737. __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
  738. {
  739.   return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
  740. }
  741.  
  742. /**
  743.   * @brief  Check if Tx buffer is empty
  744.   * @rmtoll SR           TXE           LL_SPI_IsActiveFlag_TXE
  745.   * @param  SPIx SPI Instance
  746.   * @retval State of bit (1 or 0).
  747.   */
  748. __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
  749. {
  750.   return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
  751. }
  752.  
  753. /**
  754.   * @brief  Get CRC error flag
  755.   * @rmtoll SR           CRCERR        LL_SPI_IsActiveFlag_CRCERR
  756.   * @param  SPIx SPI Instance
  757.   * @retval State of bit (1 or 0).
  758.   */
  759. __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
  760. {
  761.   return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
  762. }
  763.  
  764. /**
  765.   * @brief  Get mode fault error flag
  766.   * @rmtoll SR           MODF          LL_SPI_IsActiveFlag_MODF
  767.   * @param  SPIx SPI Instance
  768.   * @retval State of bit (1 or 0).
  769.   */
  770. __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
  771. {
  772.   return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
  773. }
  774.  
  775. /**
  776.   * @brief  Get overrun error flag
  777.   * @rmtoll SR           OVR           LL_SPI_IsActiveFlag_OVR
  778.   * @param  SPIx SPI Instance
  779.   * @retval State of bit (1 or 0).
  780.   */
  781. __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
  782. {
  783.   return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
  784. }
  785.  
  786. /**
  787.   * @brief  Get busy flag
  788.   * @note   The BSY flag is cleared under any one of the following conditions:
  789.   * -When the SPI is correctly disabled
  790.   * -When a fault is detected in Master mode (MODF bit set to 1)
  791.   * -In Master mode, when it finishes a data transmission and no new data is ready to be
  792.   * sent
  793.   * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
  794.   * each data transfer.
  795.   * @rmtoll SR           BSY           LL_SPI_IsActiveFlag_BSY
  796.   * @param  SPIx SPI Instance
  797.   * @retval State of bit (1 or 0).
  798.   */
  799. __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
  800. {
  801.   return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
  802. }
  803.  
  804. #if defined(SPI_CR2_FRF)
  805. /**
  806.   * @brief  Get frame format error flag
  807.   * @rmtoll SR           FRE           LL_SPI_IsActiveFlag_FRE
  808.   * @param  SPIx SPI Instance
  809.   * @retval State of bit (1 or 0).
  810.   */
  811. __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
  812. {
  813.   return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL);
  814. }
  815. #endif
  816.  
  817. /**
  818.   * @brief  Clear CRC error flag
  819.   * @rmtoll SR           CRCERR        LL_SPI_ClearFlag_CRCERR
  820.   * @param  SPIx SPI Instance
  821.   * @retval None
  822.   */
  823. __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
  824. {
  825.   CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
  826. }
  827.  
  828. /**
  829.   * @brief  Clear mode fault error flag
  830.   * @note   Clearing this flag is done by a read access to the SPIx_SR
  831.   *         register followed by a write access to the SPIx_CR1 register
  832.   * @rmtoll SR           MODF          LL_SPI_ClearFlag_MODF
  833.   * @param  SPIx SPI Instance
  834.   * @retval None
  835.   */
  836. __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
  837. {
  838.   __IO uint32_t tmpreg_sr;
  839.   tmpreg_sr = SPIx->SR;
  840.   (void) tmpreg_sr;
  841.   CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
  842. }
  843.  
  844. /**
  845.   * @brief  Clear overrun error flag
  846.   * @note   Clearing this flag is done by a read access to the SPIx_DR
  847.   *         register followed by a read access to the SPIx_SR register
  848.   * @rmtoll SR           OVR           LL_SPI_ClearFlag_OVR
  849.   * @param  SPIx SPI Instance
  850.   * @retval None
  851.   */
  852. __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
  853. {
  854.   __IO uint32_t tmpreg;
  855.   tmpreg = SPIx->DR;
  856.   (void) tmpreg;
  857.   tmpreg = SPIx->SR;
  858.   (void) tmpreg;
  859. }
  860.  
  861. /**
  862.   * @brief  Clear frame format error flag
  863.   * @note   Clearing this flag is done by reading SPIx_SR register
  864.   * @rmtoll SR           FRE           LL_SPI_ClearFlag_FRE
  865.   * @param  SPIx SPI Instance
  866.   * @retval None
  867.   */
  868. __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
  869. {
  870.   __IO uint32_t tmpreg;
  871.   tmpreg = SPIx->SR;
  872.   (void) tmpreg;
  873. }
  874.  
  875. /**
  876.   * @}
  877.   */
  878.  
  879. /** @defgroup SPI_LL_EF_IT_Management Interrupt Management
  880.   * @{
  881.   */
  882.  
  883. /**
  884.   * @brief  Enable error interrupt
  885.   * @note   This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
  886.   * @rmtoll CR2          ERRIE         LL_SPI_EnableIT_ERR
  887.   * @param  SPIx SPI Instance
  888.   * @retval None
  889.   */
  890. __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
  891. {
  892.   SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
  893. }
  894.  
  895. /**
  896.   * @brief  Enable Rx buffer not empty interrupt
  897.   * @rmtoll CR2          RXNEIE        LL_SPI_EnableIT_RXNE
  898.   * @param  SPIx SPI Instance
  899.   * @retval None
  900.   */
  901. __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
  902. {
  903.   SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
  904. }
  905.  
  906. /**
  907.   * @brief  Enable Tx buffer empty interrupt
  908.   * @rmtoll CR2          TXEIE         LL_SPI_EnableIT_TXE
  909.   * @param  SPIx SPI Instance
  910.   * @retval None
  911.   */
  912. __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
  913. {
  914.   SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
  915. }
  916.  
  917. /**
  918.   * @brief  Disable error interrupt
  919.   * @note   This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
  920.   * @rmtoll CR2          ERRIE         LL_SPI_DisableIT_ERR
  921.   * @param  SPIx SPI Instance
  922.   * @retval None
  923.   */
  924. __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
  925. {
  926.   CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
  927. }
  928.  
  929. /**
  930.   * @brief  Disable Rx buffer not empty interrupt
  931.   * @rmtoll CR2          RXNEIE        LL_SPI_DisableIT_RXNE
  932.   * @param  SPIx SPI Instance
  933.   * @retval None
  934.   */
  935. __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
  936. {
  937.   CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
  938. }
  939.  
  940. /**
  941.   * @brief  Disable Tx buffer empty interrupt
  942.   * @rmtoll CR2          TXEIE         LL_SPI_DisableIT_TXE
  943.   * @param  SPIx SPI Instance
  944.   * @retval None
  945.   */
  946. __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
  947. {
  948.   CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
  949. }
  950.  
  951. /**
  952.   * @brief  Check if error interrupt is enabled
  953.   * @rmtoll CR2          ERRIE         LL_SPI_IsEnabledIT_ERR
  954.   * @param  SPIx SPI Instance
  955.   * @retval State of bit (1 or 0).
  956.   */
  957. __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
  958. {
  959.   return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
  960. }
  961.  
  962. /**
  963.   * @brief  Check if Rx buffer not empty interrupt is enabled
  964.   * @rmtoll CR2          RXNEIE        LL_SPI_IsEnabledIT_RXNE
  965.   * @param  SPIx SPI Instance
  966.   * @retval State of bit (1 or 0).
  967.   */
  968. __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
  969. {
  970.   return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL);
  971. }
  972.  
  973. /**
  974.   * @brief  Check if Tx buffer empty interrupt
  975.   * @rmtoll CR2          TXEIE         LL_SPI_IsEnabledIT_TXE
  976.   * @param  SPIx SPI Instance
  977.   * @retval State of bit (1 or 0).
  978.   */
  979. __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
  980. {
  981.   return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
  982. }
  983.  
  984. /**
  985.   * @}
  986.   */
  987.  
  988. /** @defgroup SPI_LL_EF_DMA_Management DMA Management
  989.   * @{
  990.   */
  991.  
  992. /**
  993.   * @brief  Enable DMA Rx
  994.   * @rmtoll CR2          RXDMAEN       LL_SPI_EnableDMAReq_RX
  995.   * @param  SPIx SPI Instance
  996.   * @retval None
  997.   */
  998. __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
  999. {
  1000.   SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
  1001. }
  1002.  
  1003. /**
  1004.   * @brief  Disable DMA Rx
  1005.   * @rmtoll CR2          RXDMAEN       LL_SPI_DisableDMAReq_RX
  1006.   * @param  SPIx SPI Instance
  1007.   * @retval None
  1008.   */
  1009. __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
  1010. {
  1011.   CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
  1012. }
  1013.  
  1014. /**
  1015.   * @brief  Check if DMA Rx is enabled
  1016.   * @rmtoll CR2          RXDMAEN       LL_SPI_IsEnabledDMAReq_RX
  1017.   * @param  SPIx SPI Instance
  1018.   * @retval State of bit (1 or 0).
  1019.   */
  1020. __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
  1021. {
  1022.   return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL);
  1023. }
  1024.  
  1025. /**
  1026.   * @brief  Enable DMA Tx
  1027.   * @rmtoll CR2          TXDMAEN       LL_SPI_EnableDMAReq_TX
  1028.   * @param  SPIx SPI Instance
  1029.   * @retval None
  1030.   */
  1031. __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
  1032. {
  1033.   SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
  1034. }
  1035.  
  1036. /**
  1037.   * @brief  Disable DMA Tx
  1038.   * @rmtoll CR2          TXDMAEN       LL_SPI_DisableDMAReq_TX
  1039.   * @param  SPIx SPI Instance
  1040.   * @retval None
  1041.   */
  1042. __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
  1043. {
  1044.   CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
  1045. }
  1046.  
  1047. /**
  1048.   * @brief  Check if DMA Tx is enabled
  1049.   * @rmtoll CR2          TXDMAEN       LL_SPI_IsEnabledDMAReq_TX
  1050.   * @param  SPIx SPI Instance
  1051.   * @retval State of bit (1 or 0).
  1052.   */
  1053. __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
  1054. {
  1055.   return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL);
  1056. }
  1057.  
  1058. /**
  1059.   * @brief  Get the data register address used for DMA transfer
  1060.   * @rmtoll DR           DR            LL_SPI_DMA_GetRegAddr
  1061.   * @param  SPIx SPI Instance
  1062.   * @retval Address of data register
  1063.   */
  1064. __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
  1065. {
  1066.   return (uint32_t) &(SPIx->DR);
  1067. }
  1068.  
  1069. /**
  1070.   * @}
  1071.   */
  1072.  
  1073. /** @defgroup SPI_LL_EF_DATA_Management DATA Management
  1074.   * @{
  1075.   */
  1076.  
  1077. /**
  1078.   * @brief  Read 8-Bits in the data register
  1079.   * @rmtoll DR           DR            LL_SPI_ReceiveData8
  1080.   * @param  SPIx SPI Instance
  1081.   * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
  1082.   */
  1083. __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
  1084. {
  1085.   return (uint8_t)(READ_REG(SPIx->DR));
  1086. }
  1087.  
  1088. /**
  1089.   * @brief  Read 16-Bits in the data register
  1090.   * @rmtoll DR           DR            LL_SPI_ReceiveData16
  1091.   * @param  SPIx SPI Instance
  1092.   * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
  1093.   */
  1094. __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
  1095. {
  1096.   return (uint16_t)(READ_REG(SPIx->DR));
  1097. }
  1098.  
  1099. /**
  1100.   * @brief  Write 8-Bits in the data register
  1101.   * @rmtoll DR           DR            LL_SPI_TransmitData8
  1102.   * @param  SPIx SPI Instance
  1103.   * @param  TxData Value between Min_Data=0x00 and Max_Data=0xFF
  1104.   * @retval None
  1105.   */
  1106. __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
  1107. {
  1108. #if defined (__GNUC__)
  1109.   __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
  1110.   *spidr = TxData;
  1111. #else
  1112.   *((__IO uint8_t *)&SPIx->DR) = TxData;
  1113. #endif /* __GNUC__ */
  1114. }
  1115.  
  1116. /**
  1117.   * @brief  Write 16-Bits in the data register
  1118.   * @rmtoll DR           DR            LL_SPI_TransmitData16
  1119.   * @param  SPIx SPI Instance
  1120.   * @param  TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
  1121.   * @retval None
  1122.   */
  1123. __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
  1124. {
  1125. #if defined (__GNUC__)
  1126.   __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
  1127.   *spidr = TxData;
  1128. #else
  1129.   SPIx->DR = TxData;
  1130. #endif /* __GNUC__ */
  1131. }
  1132.  
  1133. /**
  1134.   * @}
  1135.   */
  1136. #if defined(USE_FULL_LL_DRIVER)
  1137. /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
  1138.   * @{
  1139.   */
  1140.  
  1141. ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
  1142. ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
  1143. void        LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
  1144.  
  1145. /**
  1146.   * @}
  1147.   */
  1148. #endif /* USE_FULL_LL_DRIVER */
  1149. /**
  1150.   * @}
  1151.   */
  1152.  
  1153. /**
  1154.   * @}
  1155.   */
  1156.  
  1157. #if defined(SPI_I2S_SUPPORT)
  1158. /** @defgroup I2S_LL I2S
  1159.   * @{
  1160.   */
  1161.  
  1162. /* Private variables ---------------------------------------------------------*/
  1163. /* Private constants ---------------------------------------------------------*/
  1164. /* Private macros ------------------------------------------------------------*/
  1165.  
  1166. /* Exported types ------------------------------------------------------------*/
  1167. #if defined(USE_FULL_LL_DRIVER)
  1168. /** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
  1169.   * @{
  1170.   */
  1171.  
  1172. /**
  1173.   * @brief  I2S Init structure definition
  1174.   */
  1175.  
  1176. typedef struct
  1177. {
  1178.   uint32_t Mode;                    /*!< Specifies the I2S operating mode.
  1179.                                          This parameter can be a value of @ref I2S_LL_EC_MODE
  1180.  
  1181.                                          This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
  1182.  
  1183.   uint32_t Standard;                /*!< Specifies the standard used for the I2S communication.
  1184.                                          This parameter can be a value of @ref I2S_LL_EC_STANDARD
  1185.  
  1186.                                          This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
  1187.  
  1188.  
  1189.   uint32_t DataFormat;              /*!< Specifies the data format for the I2S communication.
  1190.                                          This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
  1191.  
  1192.                                          This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
  1193.  
  1194.  
  1195.   uint32_t MCLKOutput;              /*!< Specifies whether the I2S MCLK output is enabled or not.
  1196.                                          This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
  1197.  
  1198.                                          This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
  1199.  
  1200.  
  1201.   uint32_t AudioFreq;               /*!< Specifies the frequency selected for the I2S communication.
  1202.                                          This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
  1203.  
  1204.                                          Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
  1205.                                          and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
  1206.  
  1207.  
  1208.   uint32_t ClockPolarity;           /*!< Specifies the idle state of the I2S clock.
  1209.                                          This parameter can be a value of @ref I2S_LL_EC_POLARITY
  1210.  
  1211.                                          This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
  1212.  
  1213. } LL_I2S_InitTypeDef;
  1214.  
  1215. /**
  1216.   * @}
  1217.   */
  1218. #endif /*USE_FULL_LL_DRIVER*/
  1219.  
  1220. /* Exported constants --------------------------------------------------------*/
  1221. /** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
  1222.   * @{
  1223.   */
  1224.  
  1225. /** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
  1226.   * @brief    Flags defines which can be used with LL_I2S_ReadReg function
  1227.   * @{
  1228.   */
  1229. #define LL_I2S_SR_RXNE                     LL_SPI_SR_RXNE            /*!< Rx buffer not empty flag         */
  1230. #define LL_I2S_SR_TXE                      LL_SPI_SR_TXE             /*!< Tx buffer empty flag             */
  1231. #define LL_I2S_SR_BSY                      LL_SPI_SR_BSY             /*!< Busy flag                        */
  1232. #define LL_I2S_SR_UDR                      SPI_SR_UDR                /*!< Underrun flag                    */
  1233. #define LL_I2S_SR_OVR                      LL_SPI_SR_OVR             /*!< Overrun flag                     */
  1234. #define LL_I2S_SR_FRE                      LL_SPI_SR_FRE             /*!< TI mode frame format error flag  */
  1235. /**
  1236.   * @}
  1237.   */
  1238.  
  1239. /** @defgroup SPI_LL_EC_IT IT Defines
  1240.   * @brief    IT defines which can be used with LL_SPI_ReadReg and  LL_SPI_WriteReg functions
  1241.   * @{
  1242.   */
  1243. #define LL_I2S_CR2_RXNEIE                  LL_SPI_CR2_RXNEIE         /*!< Rx buffer not empty interrupt enable */
  1244. #define LL_I2S_CR2_TXEIE                   LL_SPI_CR2_TXEIE          /*!< Tx buffer empty interrupt enable     */
  1245. #define LL_I2S_CR2_ERRIE                   LL_SPI_CR2_ERRIE          /*!< Error interrupt enable               */
  1246. /**
  1247.   * @}
  1248.   */
  1249.  
  1250. /** @defgroup I2S_LL_EC_DATA_FORMAT Data format
  1251.   * @{
  1252.   */
  1253. #define LL_I2S_DATAFORMAT_16B              0x00000000U                                   /*!< Data length 16 bits, Channel length 16bit */
  1254. #define LL_I2S_DATAFORMAT_16B_EXTENDED     (SPI_I2SCFGR_CHLEN)                           /*!< Data length 16 bits, Channel length 32bit */
  1255. #define LL_I2S_DATAFORMAT_24B              (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)    /*!< Data length 24 bits, Channel length 32bit */
  1256. #define LL_I2S_DATAFORMAT_32B              (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)    /*!< Data length 16 bits, Channel length 32bit */
  1257. /**
  1258.   * @}
  1259.   */
  1260.  
  1261. /** @defgroup I2S_LL_EC_POLARITY Clock Polarity
  1262.   * @{
  1263.   */
  1264. #define LL_I2S_POLARITY_LOW                0x00000000U               /*!< Clock steady state is low level  */
  1265. #define LL_I2S_POLARITY_HIGH               (SPI_I2SCFGR_CKPOL)       /*!< Clock steady state is high level */
  1266. /**
  1267.   * @}
  1268.   */
  1269.  
  1270. /** @defgroup I2S_LL_EC_STANDARD I2s Standard
  1271.   * @{
  1272.   */
  1273. #define LL_I2S_STANDARD_PHILIPS            0x00000000U                                                         /*!< I2S standard philips                      */
  1274. #define LL_I2S_STANDARD_MSB                (SPI_I2SCFGR_I2SSTD_0)                                              /*!< MSB justified standard (left justified)   */
  1275. #define LL_I2S_STANDARD_LSB                (SPI_I2SCFGR_I2SSTD_1)                                              /*!< LSB justified standard (right justified)  */
  1276. #define LL_I2S_STANDARD_PCM_SHORT          (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)                       /*!< PCM standard, short frame synchronization */
  1277. #define LL_I2S_STANDARD_PCM_LONG           (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization  */
  1278. /**
  1279.   * @}
  1280.   */
  1281.  
  1282. /** @defgroup I2S_LL_EC_MODE Operation Mode
  1283.   * @{
  1284.   */
  1285. #define LL_I2S_MODE_SLAVE_TX               0x00000000U                                   /*!< Slave Tx configuration  */
  1286. #define LL_I2S_MODE_SLAVE_RX               (SPI_I2SCFGR_I2SCFG_0)                        /*!< Slave Rx configuration  */
  1287. #define LL_I2S_MODE_MASTER_TX              (SPI_I2SCFGR_I2SCFG_1)                        /*!< Master Tx configuration */
  1288. #define LL_I2S_MODE_MASTER_RX              (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
  1289. /**
  1290.   * @}
  1291.   */
  1292.  
  1293. /** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
  1294.   * @{
  1295.   */
  1296. #define LL_I2S_PRESCALER_PARITY_EVEN       0x00000000U               /*!< Odd factor: Real divider value is =  I2SDIV * 2    */
  1297. #define LL_I2S_PRESCALER_PARITY_ODD        (SPI_I2SPR_ODD >> 8U)     /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
  1298. /**
  1299.   * @}
  1300.   */
  1301.  
  1302. #if defined(USE_FULL_LL_DRIVER)
  1303.  
  1304. /** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
  1305.   * @{
  1306.   */
  1307. #define LL_I2S_MCLK_OUTPUT_DISABLE         0x00000000U               /*!< Master clock output is disabled */
  1308. #define LL_I2S_MCLK_OUTPUT_ENABLE          (SPI_I2SPR_MCKOE)         /*!< Master clock output is enabled  */
  1309. /**
  1310.   * @}
  1311.   */
  1312.  
  1313. /** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
  1314.   * @{
  1315.   */
  1316.  
  1317. #define LL_I2S_AUDIOFREQ_192K              192000U       /*!< Audio Frequency configuration 192000 Hz       */
  1318. #define LL_I2S_AUDIOFREQ_96K               96000U        /*!< Audio Frequency configuration  96000 Hz       */
  1319. #define LL_I2S_AUDIOFREQ_48K               48000U        /*!< Audio Frequency configuration  48000 Hz       */
  1320. #define LL_I2S_AUDIOFREQ_44K               44100U        /*!< Audio Frequency configuration  44100 Hz       */
  1321. #define LL_I2S_AUDIOFREQ_32K               32000U        /*!< Audio Frequency configuration  32000 Hz       */
  1322. #define LL_I2S_AUDIOFREQ_22K               22050U        /*!< Audio Frequency configuration  22050 Hz       */
  1323. #define LL_I2S_AUDIOFREQ_16K               16000U        /*!< Audio Frequency configuration  16000 Hz       */
  1324. #define LL_I2S_AUDIOFREQ_11K               11025U        /*!< Audio Frequency configuration  11025 Hz       */
  1325. #define LL_I2S_AUDIOFREQ_8K                8000U         /*!< Audio Frequency configuration   8000 Hz       */
  1326. #define LL_I2S_AUDIOFREQ_DEFAULT           2U            /*!< Audio Freq not specified. Register I2SDIV = 2 */
  1327. /**
  1328.   * @}
  1329.   */
  1330. #endif /* USE_FULL_LL_DRIVER */
  1331.  
  1332. /**
  1333.   * @}
  1334.   */
  1335.  
  1336. /* Exported macro ------------------------------------------------------------*/
  1337. /** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
  1338.   * @{
  1339.   */
  1340.  
  1341. /** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
  1342.   * @{
  1343.   */
  1344.  
  1345. /**
  1346.   * @brief  Write a value in I2S register
  1347.   * @param  __INSTANCE__ I2S Instance
  1348.   * @param  __REG__ Register to be written
  1349.   * @param  __VALUE__ Value to be written in the register
  1350.   * @retval None
  1351.   */
  1352. #define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
  1353.  
  1354. /**
  1355.   * @brief  Read a value in I2S register
  1356.   * @param  __INSTANCE__ I2S Instance
  1357.   * @param  __REG__ Register to be read
  1358.   * @retval Register value
  1359.   */
  1360. #define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
  1361. /**
  1362.   * @}
  1363.   */
  1364.  
  1365. /**
  1366.   * @}
  1367.   */
  1368.  
  1369.  
  1370. /* Exported functions --------------------------------------------------------*/
  1371.  
  1372. /** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
  1373.   * @{
  1374.   */
  1375.  
  1376. /** @defgroup I2S_LL_EF_Configuration Configuration
  1377.   * @{
  1378.   */
  1379.  
  1380. /**
  1381.   * @brief  Select I2S mode and Enable I2S peripheral
  1382.   * @rmtoll I2SCFGR      I2SMOD        LL_I2S_Enable\n
  1383.   *         I2SCFGR      I2SE          LL_I2S_Enable
  1384.   * @param  SPIx SPI Instance
  1385.   * @retval None
  1386.   */
  1387. __STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
  1388. {
  1389.   SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
  1390. }
  1391.  
  1392. /**
  1393.   * @brief  Disable I2S peripheral
  1394.   * @rmtoll I2SCFGR      I2SE          LL_I2S_Disable
  1395.   * @param  SPIx SPI Instance
  1396.   * @retval None
  1397.   */
  1398. __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
  1399. {
  1400.   CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
  1401. }
  1402.  
  1403. /**
  1404.   * @brief  Check if I2S peripheral is enabled
  1405.   * @rmtoll I2SCFGR      I2SE          LL_I2S_IsEnabled
  1406.   * @param  SPIx SPI Instance
  1407.   * @retval State of bit (1 or 0).
  1408.   */
  1409. __STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
  1410. {
  1411.   return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL);
  1412. }
  1413.  
  1414. /**
  1415.   * @brief  Set I2S data frame length
  1416.   * @rmtoll I2SCFGR      DATLEN        LL_I2S_SetDataFormat\n
  1417.   *         I2SCFGR      CHLEN         LL_I2S_SetDataFormat
  1418.   * @param  SPIx SPI Instance
  1419.   * @param  DataFormat This parameter can be one of the following values:
  1420.   *         @arg @ref LL_I2S_DATAFORMAT_16B
  1421.   *         @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
  1422.   *         @arg @ref LL_I2S_DATAFORMAT_24B
  1423.   *         @arg @ref LL_I2S_DATAFORMAT_32B
  1424.   * @retval None
  1425.   */
  1426. __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
  1427. {
  1428.   MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
  1429. }
  1430.  
  1431. /**
  1432.   * @brief  Get I2S data frame length
  1433.   * @rmtoll I2SCFGR      DATLEN        LL_I2S_GetDataFormat\n
  1434.   *         I2SCFGR      CHLEN         LL_I2S_GetDataFormat
  1435.   * @param  SPIx SPI Instance
  1436.   * @retval Returned value can be one of the following values:
  1437.   *         @arg @ref LL_I2S_DATAFORMAT_16B
  1438.   *         @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
  1439.   *         @arg @ref LL_I2S_DATAFORMAT_24B
  1440.   *         @arg @ref LL_I2S_DATAFORMAT_32B
  1441.   */
  1442. __STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
  1443. {
  1444.   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
  1445. }
  1446.  
  1447. /**
  1448.   * @brief  Set I2S clock polarity
  1449.   * @rmtoll I2SCFGR      CKPOL         LL_I2S_SetClockPolarity
  1450.   * @param  SPIx SPI Instance
  1451.   * @param  ClockPolarity This parameter can be one of the following values:
  1452.   *         @arg @ref LL_I2S_POLARITY_LOW
  1453.   *         @arg @ref LL_I2S_POLARITY_HIGH
  1454.   * @retval None
  1455.   */
  1456. __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
  1457. {
  1458.   SET_BIT(SPIx->I2SCFGR, ClockPolarity);
  1459. }
  1460.  
  1461. /**
  1462.   * @brief  Get I2S clock polarity
  1463.   * @rmtoll I2SCFGR      CKPOL         LL_I2S_GetClockPolarity
  1464.   * @param  SPIx SPI Instance
  1465.   * @retval Returned value can be one of the following values:
  1466.   *         @arg @ref LL_I2S_POLARITY_LOW
  1467.   *         @arg @ref LL_I2S_POLARITY_HIGH
  1468.   */
  1469. __STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
  1470. {
  1471.   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
  1472. }
  1473.  
  1474. /**
  1475.   * @brief  Set I2S standard protocol
  1476.   * @rmtoll I2SCFGR      I2SSTD        LL_I2S_SetStandard\n
  1477.   *         I2SCFGR      PCMSYNC       LL_I2S_SetStandard
  1478.   * @param  SPIx SPI Instance
  1479.   * @param  Standard This parameter can be one of the following values:
  1480.   *         @arg @ref LL_I2S_STANDARD_PHILIPS
  1481.   *         @arg @ref LL_I2S_STANDARD_MSB
  1482.   *         @arg @ref LL_I2S_STANDARD_LSB
  1483.   *         @arg @ref LL_I2S_STANDARD_PCM_SHORT
  1484.   *         @arg @ref LL_I2S_STANDARD_PCM_LONG
  1485.   * @retval None
  1486.   */
  1487. __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
  1488. {
  1489.   MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
  1490. }
  1491.  
  1492. /**
  1493.   * @brief  Get I2S standard protocol
  1494.   * @rmtoll I2SCFGR      I2SSTD        LL_I2S_GetStandard\n
  1495.   *         I2SCFGR      PCMSYNC       LL_I2S_GetStandard
  1496.   * @param  SPIx SPI Instance
  1497.   * @retval Returned value can be one of the following values:
  1498.   *         @arg @ref LL_I2S_STANDARD_PHILIPS
  1499.   *         @arg @ref LL_I2S_STANDARD_MSB
  1500.   *         @arg @ref LL_I2S_STANDARD_LSB
  1501.   *         @arg @ref LL_I2S_STANDARD_PCM_SHORT
  1502.   *         @arg @ref LL_I2S_STANDARD_PCM_LONG
  1503.   */
  1504. __STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
  1505. {
  1506.   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
  1507. }
  1508.  
  1509. /**
  1510.   * @brief  Set I2S transfer mode
  1511.   * @rmtoll I2SCFGR      I2SCFG        LL_I2S_SetTransferMode
  1512.   * @param  SPIx SPI Instance
  1513.   * @param  Mode This parameter can be one of the following values:
  1514.   *         @arg @ref LL_I2S_MODE_SLAVE_TX
  1515.   *         @arg @ref LL_I2S_MODE_SLAVE_RX
  1516.   *         @arg @ref LL_I2S_MODE_MASTER_TX
  1517.   *         @arg @ref LL_I2S_MODE_MASTER_RX
  1518.   * @retval None
  1519.   */
  1520. __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
  1521. {
  1522.   MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
  1523. }
  1524.  
  1525. /**
  1526.   * @brief  Get I2S transfer mode
  1527.   * @rmtoll I2SCFGR      I2SCFG        LL_I2S_GetTransferMode
  1528.   * @param  SPIx SPI Instance
  1529.   * @retval Returned value can be one of the following values:
  1530.   *         @arg @ref LL_I2S_MODE_SLAVE_TX
  1531.   *         @arg @ref LL_I2S_MODE_SLAVE_RX
  1532.   *         @arg @ref LL_I2S_MODE_MASTER_TX
  1533.   *         @arg @ref LL_I2S_MODE_MASTER_RX
  1534.   */
  1535. __STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
  1536. {
  1537.   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
  1538. }
  1539.  
  1540. /**
  1541.   * @brief  Set I2S linear prescaler
  1542.   * @rmtoll I2SPR        I2SDIV        LL_I2S_SetPrescalerLinear
  1543.   * @param  SPIx SPI Instance
  1544.   * @param  PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
  1545.   * @retval None
  1546.   */
  1547. __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
  1548. {
  1549.   MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
  1550. }
  1551.  
  1552. /**
  1553.   * @brief  Get I2S linear prescaler
  1554.   * @rmtoll I2SPR        I2SDIV        LL_I2S_GetPrescalerLinear
  1555.   * @param  SPIx SPI Instance
  1556.   * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
  1557.   */
  1558. __STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
  1559. {
  1560.   return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
  1561. }
  1562.  
  1563. /**
  1564.   * @brief  Set I2S parity prescaler
  1565.   * @rmtoll I2SPR        ODD           LL_I2S_SetPrescalerParity
  1566.   * @param  SPIx SPI Instance
  1567.   * @param  PrescalerParity This parameter can be one of the following values:
  1568.   *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
  1569.   *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
  1570.   * @retval None
  1571.   */
  1572. __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
  1573. {
  1574.   MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
  1575. }
  1576.  
  1577. /**
  1578.   * @brief  Get I2S parity prescaler
  1579.   * @rmtoll I2SPR        ODD           LL_I2S_GetPrescalerParity
  1580.   * @param  SPIx SPI Instance
  1581.   * @retval Returned value can be one of the following values:
  1582.   *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
  1583.   *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
  1584.   */
  1585. __STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
  1586. {
  1587.   return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
  1588. }
  1589.  
  1590. /**
  1591.   * @brief  Enable the master clock output (Pin MCK)
  1592.   * @rmtoll I2SPR        MCKOE         LL_I2S_EnableMasterClock
  1593.   * @param  SPIx SPI Instance
  1594.   * @retval None
  1595.   */
  1596. __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
  1597. {
  1598.   SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
  1599. }
  1600.  
  1601. /**
  1602.   * @brief  Disable the master clock output (Pin MCK)
  1603.   * @rmtoll I2SPR        MCKOE         LL_I2S_DisableMasterClock
  1604.   * @param  SPIx SPI Instance
  1605.   * @retval None
  1606.   */
  1607. __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
  1608. {
  1609.   CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
  1610. }
  1611.  
  1612. /**
  1613.   * @brief  Check if the master clock output (Pin MCK) is enabled
  1614.   * @rmtoll I2SPR        MCKOE         LL_I2S_IsEnabledMasterClock
  1615.   * @param  SPIx SPI Instance
  1616.   * @retval State of bit (1 or 0).
  1617.   */
  1618. __STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
  1619. {
  1620.   return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL);
  1621. }
  1622.  
  1623. /**
  1624.   * @}
  1625.   */
  1626.  
  1627. /** @defgroup I2S_LL_EF_FLAG FLAG Management
  1628.   * @{
  1629.   */
  1630.  
  1631. /**
  1632.   * @brief  Check if Rx buffer is not empty
  1633.   * @rmtoll SR           RXNE          LL_I2S_IsActiveFlag_RXNE
  1634.   * @param  SPIx SPI Instance
  1635.   * @retval State of bit (1 or 0).
  1636.   */
  1637. __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
  1638. {
  1639.   return LL_SPI_IsActiveFlag_RXNE(SPIx);
  1640. }
  1641.  
  1642. /**
  1643.   * @brief  Check if Tx buffer is empty
  1644.   * @rmtoll SR           TXE           LL_I2S_IsActiveFlag_TXE
  1645.   * @param  SPIx SPI Instance
  1646.   * @retval State of bit (1 or 0).
  1647.   */
  1648. __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
  1649. {
  1650.   return LL_SPI_IsActiveFlag_TXE(SPIx);
  1651. }
  1652.  
  1653. /**
  1654.   * @brief  Get busy flag
  1655.   * @rmtoll SR           BSY           LL_I2S_IsActiveFlag_BSY
  1656.   * @param  SPIx SPI Instance
  1657.   * @retval State of bit (1 or 0).
  1658.   */
  1659. __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
  1660. {
  1661.   return LL_SPI_IsActiveFlag_BSY(SPIx);
  1662. }
  1663.  
  1664. /**
  1665.   * @brief  Get overrun error flag
  1666.   * @rmtoll SR           OVR           LL_I2S_IsActiveFlag_OVR
  1667.   * @param  SPIx SPI Instance
  1668.   * @retval State of bit (1 or 0).
  1669.   */
  1670. __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
  1671. {
  1672.   return LL_SPI_IsActiveFlag_OVR(SPIx);
  1673. }
  1674.  
  1675. /**
  1676.   * @brief  Get underrun error flag
  1677.   * @rmtoll SR           UDR           LL_I2S_IsActiveFlag_UDR
  1678.   * @param  SPIx SPI Instance
  1679.   * @retval State of bit (1 or 0).
  1680.   */
  1681. __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
  1682. {
  1683.   return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
  1684. }
  1685.  
  1686. #if defined(SPI_CR2_FRF)
  1687. /**
  1688.   * @brief  Get frame format error flag
  1689.   * @rmtoll SR           FRE           LL_I2S_IsActiveFlag_FRE
  1690.   * @param  SPIx SPI Instance
  1691.   * @retval State of bit (1 or 0).
  1692.   */
  1693. __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
  1694. {
  1695.   return LL_SPI_IsActiveFlag_FRE(SPIx);
  1696. }
  1697. #endif
  1698.  
  1699. /**
  1700.   * @brief  Get channel side flag.
  1701.   * @note   0: Channel Left has to be transmitted or has been received\n
  1702.   *         1: Channel Right has to be transmitted or has been received\n
  1703.   *         It has no significance in PCM mode.
  1704.   * @rmtoll SR           CHSIDE        LL_I2S_IsActiveFlag_CHSIDE
  1705.   * @param  SPIx SPI Instance
  1706.   * @retval State of bit (1 or 0).
  1707.   */
  1708. __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
  1709. {
  1710.   return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL);
  1711. }
  1712.  
  1713. /**
  1714.   * @brief  Clear overrun error flag
  1715.   * @rmtoll SR           OVR           LL_I2S_ClearFlag_OVR
  1716.   * @param  SPIx SPI Instance
  1717.   * @retval None
  1718.   */
  1719. __STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
  1720. {
  1721.   LL_SPI_ClearFlag_OVR(SPIx);
  1722. }
  1723.  
  1724. /**
  1725.   * @brief  Clear underrun error flag
  1726.   * @rmtoll SR           UDR           LL_I2S_ClearFlag_UDR
  1727.   * @param  SPIx SPI Instance
  1728.   * @retval None
  1729.   */
  1730. __STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
  1731. {
  1732.   __IO uint32_t tmpreg;
  1733.   tmpreg = SPIx->SR;
  1734.   (void)tmpreg;
  1735. }
  1736.  
  1737. /**
  1738.   * @brief  Clear frame format error flag
  1739.   * @rmtoll SR           FRE           LL_I2S_ClearFlag_FRE
  1740.   * @param  SPIx SPI Instance
  1741.   * @retval None
  1742.   */
  1743. __STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
  1744. {
  1745.   LL_SPI_ClearFlag_FRE(SPIx);
  1746. }
  1747.  
  1748. /**
  1749.   * @}
  1750.   */
  1751.  
  1752. /** @defgroup I2S_LL_EF_IT Interrupt Management
  1753.   * @{
  1754.   */
  1755.  
  1756. /**
  1757.   * @brief  Enable error IT
  1758.   * @note   This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
  1759.   * @rmtoll CR2          ERRIE         LL_I2S_EnableIT_ERR
  1760.   * @param  SPIx SPI Instance
  1761.   * @retval None
  1762.   */
  1763. __STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
  1764. {
  1765.   LL_SPI_EnableIT_ERR(SPIx);
  1766. }
  1767.  
  1768. /**
  1769.   * @brief  Enable Rx buffer not empty IT
  1770.   * @rmtoll CR2          RXNEIE        LL_I2S_EnableIT_RXNE
  1771.   * @param  SPIx SPI Instance
  1772.   * @retval None
  1773.   */
  1774. __STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
  1775. {
  1776.   LL_SPI_EnableIT_RXNE(SPIx);
  1777. }
  1778.  
  1779. /**
  1780.   * @brief  Enable Tx buffer empty IT
  1781.   * @rmtoll CR2          TXEIE         LL_I2S_EnableIT_TXE
  1782.   * @param  SPIx SPI Instance
  1783.   * @retval None
  1784.   */
  1785. __STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
  1786. {
  1787.   LL_SPI_EnableIT_TXE(SPIx);
  1788. }
  1789.  
  1790. /**
  1791.   * @brief  Disable error IT
  1792.   * @note   This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
  1793.   * @rmtoll CR2          ERRIE         LL_I2S_DisableIT_ERR
  1794.   * @param  SPIx SPI Instance
  1795.   * @retval None
  1796.   */
  1797. __STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
  1798. {
  1799.   LL_SPI_DisableIT_ERR(SPIx);
  1800. }
  1801.  
  1802. /**
  1803.   * @brief  Disable Rx buffer not empty IT
  1804.   * @rmtoll CR2          RXNEIE        LL_I2S_DisableIT_RXNE
  1805.   * @param  SPIx SPI Instance
  1806.   * @retval None
  1807.   */
  1808. __STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
  1809. {
  1810.   LL_SPI_DisableIT_RXNE(SPIx);
  1811. }
  1812.  
  1813. /**
  1814.   * @brief  Disable Tx buffer empty IT
  1815.   * @rmtoll CR2          TXEIE         LL_I2S_DisableIT_TXE
  1816.   * @param  SPIx SPI Instance
  1817.   * @retval None
  1818.   */
  1819. __STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
  1820. {
  1821.   LL_SPI_DisableIT_TXE(SPIx);
  1822. }
  1823.  
  1824. /**
  1825.   * @brief  Check if ERR IT is enabled
  1826.   * @rmtoll CR2          ERRIE         LL_I2S_IsEnabledIT_ERR
  1827.   * @param  SPIx SPI Instance
  1828.   * @retval State of bit (1 or 0).
  1829.   */
  1830. __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
  1831. {
  1832.   return LL_SPI_IsEnabledIT_ERR(SPIx);
  1833. }
  1834.  
  1835. /**
  1836.   * @brief  Check if RXNE IT is enabled
  1837.   * @rmtoll CR2          RXNEIE        LL_I2S_IsEnabledIT_RXNE
  1838.   * @param  SPIx SPI Instance
  1839.   * @retval State of bit (1 or 0).
  1840.   */
  1841. __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
  1842. {
  1843.   return LL_SPI_IsEnabledIT_RXNE(SPIx);
  1844. }
  1845.  
  1846. /**
  1847.   * @brief  Check if TXE IT is enabled
  1848.   * @rmtoll CR2          TXEIE         LL_I2S_IsEnabledIT_TXE
  1849.   * @param  SPIx SPI Instance
  1850.   * @retval State of bit (1 or 0).
  1851.   */
  1852. __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
  1853. {
  1854.   return LL_SPI_IsEnabledIT_TXE(SPIx);
  1855. }
  1856.  
  1857. /**
  1858.   * @}
  1859.   */
  1860.  
  1861. /** @defgroup I2S_LL_EF_DMA DMA Management
  1862.   * @{
  1863.   */
  1864.  
  1865. /**
  1866.   * @brief  Enable DMA Rx
  1867.   * @rmtoll CR2          RXDMAEN       LL_I2S_EnableDMAReq_RX
  1868.   * @param  SPIx SPI Instance
  1869.   * @retval None
  1870.   */
  1871. __STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
  1872. {
  1873.   LL_SPI_EnableDMAReq_RX(SPIx);
  1874. }
  1875.  
  1876. /**
  1877.   * @brief  Disable DMA Rx
  1878.   * @rmtoll CR2          RXDMAEN       LL_I2S_DisableDMAReq_RX
  1879.   * @param  SPIx SPI Instance
  1880.   * @retval None
  1881.   */
  1882. __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
  1883. {
  1884.   LL_SPI_DisableDMAReq_RX(SPIx);
  1885. }
  1886.  
  1887. /**
  1888.   * @brief  Check if DMA Rx is enabled
  1889.   * @rmtoll CR2          RXDMAEN       LL_I2S_IsEnabledDMAReq_RX
  1890.   * @param  SPIx SPI Instance
  1891.   * @retval State of bit (1 or 0).
  1892.   */
  1893. __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
  1894. {
  1895.   return LL_SPI_IsEnabledDMAReq_RX(SPIx);
  1896. }
  1897.  
  1898. /**
  1899.   * @brief  Enable DMA Tx
  1900.   * @rmtoll CR2          TXDMAEN       LL_I2S_EnableDMAReq_TX
  1901.   * @param  SPIx SPI Instance
  1902.   * @retval None
  1903.   */
  1904. __STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
  1905. {
  1906.   LL_SPI_EnableDMAReq_TX(SPIx);
  1907. }
  1908.  
  1909. /**
  1910.   * @brief  Disable DMA Tx
  1911.   * @rmtoll CR2          TXDMAEN       LL_I2S_DisableDMAReq_TX
  1912.   * @param  SPIx SPI Instance
  1913.   * @retval None
  1914.   */
  1915. __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
  1916. {
  1917.   LL_SPI_DisableDMAReq_TX(SPIx);
  1918. }
  1919.  
  1920. /**
  1921.   * @brief  Check if DMA Tx is enabled
  1922.   * @rmtoll CR2          TXDMAEN       LL_I2S_IsEnabledDMAReq_TX
  1923.   * @param  SPIx SPI Instance
  1924.   * @retval State of bit (1 or 0).
  1925.   */
  1926. __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
  1927. {
  1928.   return LL_SPI_IsEnabledDMAReq_TX(SPIx);
  1929. }
  1930.  
  1931. /**
  1932.   * @}
  1933.   */
  1934.  
  1935. /** @defgroup I2S_LL_EF_DATA DATA Management
  1936.   * @{
  1937.   */
  1938.  
  1939. /**
  1940.   * @brief  Read 16-Bits in data register
  1941.   * @rmtoll DR           DR            LL_I2S_ReceiveData16
  1942.   * @param  SPIx SPI Instance
  1943.   * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
  1944.   */
  1945. __STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
  1946. {
  1947.   return LL_SPI_ReceiveData16(SPIx);
  1948. }
  1949.  
  1950. /**
  1951.   * @brief  Write 16-Bits in data register
  1952.   * @rmtoll DR           DR            LL_I2S_TransmitData16
  1953.   * @param  SPIx SPI Instance
  1954.   * @param  TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
  1955.   * @retval None
  1956.   */
  1957. __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
  1958. {
  1959.   LL_SPI_TransmitData16(SPIx, TxData);
  1960. }
  1961.  
  1962. /**
  1963.   * @}
  1964.   */
  1965.  
  1966. #if defined(USE_FULL_LL_DRIVER)
  1967. /** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
  1968.   * @{
  1969.   */
  1970.  
  1971. ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
  1972. ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
  1973. void        LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
  1974. void        LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
  1975.  
  1976. /**
  1977.   * @}
  1978.   */
  1979. #endif /* USE_FULL_LL_DRIVER */
  1980.  
  1981. /**
  1982.   * @}
  1983.   */
  1984.  
  1985. /**
  1986.   * @}
  1987.   */
  1988. #endif /* SPI_I2S_SUPPORT */
  1989.  
  1990. #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
  1991.  
  1992. /**
  1993.   * @}
  1994.   */
  1995.  
  1996. #ifdef __cplusplus
  1997. }
  1998. #endif
  1999.  
  2000. #endif /* STM32L1xx_LL_SPI_H */
  2001.  
  2002. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  2003.