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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32l1xx_ll_fsmc.h
  4.   * @author  MCD Application Team
  5.   * @brief   Header file of FSMC HAL module.
  6.   ******************************************************************************
  7.   * @attention
  8.   *
  9.   * Copyright (c) 2016 STMicroelectronics.
  10.   * All rights reserved.
  11.   *
  12.   * This software is licensed under terms that can be found in the LICENSE file
  13.   * in the root directory of this software component.
  14.   * If no LICENSE file comes with this software, it is provided AS-IS.
  15.   *
  16.   ******************************************************************************
  17.   */
  18.  
  19. /* Define to prevent recursive inclusion -------------------------------------*/
  20. #ifndef STM32L1xx_LL_FSMC_H
  21. #define STM32L1xx_LL_FSMC_H
  22.  
  23. #ifdef __cplusplus
  24. extern "C" {
  25. #endif
  26.  
  27. /* Includes ------------------------------------------------------------------*/
  28. #include "stm32l1xx_hal_def.h"
  29.  
  30. /** @addtogroup STM32L1xx_HAL_Driver
  31.   * @{
  32.   */
  33.  
  34. /** @addtogroup FSMC_LL
  35.   * @{
  36.   */
  37.  
  38. /** @addtogroup FSMC_LL_Private_Macros
  39.   * @{
  40.   */
  41. #if defined(FSMC_BANK1)
  42.  
  43. #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
  44.                                        ((__BANK__) == FSMC_NORSRAM_BANK2) || \
  45.                                        ((__BANK__) == FSMC_NORSRAM_BANK3) || \
  46.                                        ((__BANK__) == FSMC_NORSRAM_BANK4))
  47. #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
  48.                              ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
  49. #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
  50.                                    ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
  51.                                    ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
  52. #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8)  || \
  53.                                                 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
  54.                                                 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
  55. #define IS_FSMC_PAGESIZE(__SIZE__) (((__SIZE__) == FSMC_PAGE_SIZE_NONE) || \
  56.                                    ((__SIZE__) == FSMC_PAGE_SIZE_128) || \
  57.                                    ((__SIZE__) == FSMC_PAGE_SIZE_256) || \
  58.                                    ((__SIZE__) == FSMC_PAGE_SIZE_512) || \
  59.                                    ((__SIZE__) == FSMC_PAGE_SIZE_1024))
  60. #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
  61.                                       ((__MODE__) == FSMC_ACCESS_MODE_B) || \
  62.                                       ((__MODE__) == FSMC_ACCESS_MODE_C) || \
  63.                                       ((__MODE__) == FSMC_ACCESS_MODE_D))
  64. #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
  65.                                      ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
  66. #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
  67.                                             ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
  68. #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
  69.                                              ((__MODE__) == FSMC_WRAP_MODE_ENABLE))
  70. #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
  71.                                                ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
  72. #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
  73.                                                ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
  74. #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
  75.                                          ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
  76. #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
  77.                                         ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
  78. #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
  79.                                     ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
  80. #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
  81. #define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
  82.                                        ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
  83. #define IS_FSMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
  84.                                             ((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
  85. #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
  86. #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
  87. #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
  88. #define IS_FSMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U)
  89. #define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
  90. #define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U))
  91. #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
  92. #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
  93.  
  94. #endif /* FSMC_BANK1 */
  95.  
  96. /**
  97.   * @}
  98.   */
  99.  
  100. /* Exported typedef ----------------------------------------------------------*/
  101.  
  102. /** @defgroup FSMC_LL_Exported_typedef FSMC Low Layer Exported Types
  103.   * @{
  104.   */
  105.  
  106. #if defined(FSMC_BANK1)
  107. #define FSMC_NORSRAM_TypeDef            FSMC_Bank1_TypeDef
  108. #define FSMC_NORSRAM_EXTENDED_TypeDef   FSMC_Bank1E_TypeDef
  109. #endif /* FSMC_BANK1 */
  110.  
  111. #if defined(FSMC_BANK1)
  112. #define FSMC_NORSRAM_DEVICE             FSMC_Bank1
  113. #define FSMC_NORSRAM_EXTENDED_DEVICE    FSMC_Bank1E
  114. #endif /* FSMC_BANK1 */
  115.  
  116. #if defined(FSMC_BANK1)
  117. /**
  118.   * @brief  FSMC NORSRAM Configuration Structure definition
  119.   */
  120. typedef struct
  121. {
  122.   uint32_t NSBank;                       /*!< Specifies the NORSRAM memory device that will be used.
  123.                                               This parameter can be a value of @ref FSMC_NORSRAM_Bank                  */
  124.  
  125.   uint32_t DataAddressMux;               /*!< Specifies whether the address and data values are
  126.                                               multiplexed on the data bus or not.
  127.                                               This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
  128.  
  129.   uint32_t MemoryType;                   /*!< Specifies the type of external memory attached to
  130.                                               the corresponding memory device.
  131.                                               This parameter can be a value of @ref FSMC_Memory_Type                   */
  132.  
  133.   uint32_t MemoryDataWidth;              /*!< Specifies the external memory device width.
  134.                                               This parameter can be a value of @ref FSMC_NORSRAM_Data_Width            */
  135.  
  136.   uint32_t BurstAccessMode;              /*!< Enables or disables the burst access mode for Flash memory,
  137.                                               valid only with synchronous burst Flash memories.
  138.                                               This parameter can be a value of @ref FSMC_Burst_Access_Mode             */
  139.  
  140.   uint32_t WaitSignalPolarity;           /*!< Specifies the wait signal polarity, valid only when accessing
  141.                                               the Flash memory in burst mode.
  142.                                               This parameter can be a value of @ref FSMC_Wait_Signal_Polarity          */
  143.  
  144.   uint32_t WrapMode;                     /*!< Enables or disables the Wrapped burst access mode for Flash
  145.                                               memory, valid only when accessing Flash memories in burst mode.
  146.                                               This parameter can be a value of @ref FSMC_Wrap_Mode                     */
  147.  
  148.   uint32_t WaitSignalActive;             /*!< Specifies if the wait signal is asserted by the memory one
  149.                                               clock cycle before the wait state or during the wait state,
  150.                                               valid only when accessing memories in burst mode.
  151.                                               This parameter can be a value of @ref FSMC_Wait_Timing                   */
  152.  
  153.   uint32_t WriteOperation;               /*!< Enables or disables the write operation in the selected device by the FSMC.
  154.                                               This parameter can be a value of @ref FSMC_Write_Operation               */
  155.  
  156.   uint32_t WaitSignal;                   /*!< Enables or disables the wait state insertion via wait
  157.                                               signal, valid for Flash memory access in burst mode.
  158.                                               This parameter can be a value of @ref FSMC_Wait_Signal                   */
  159.  
  160.   uint32_t ExtendedMode;                 /*!< Enables or disables the extended mode.
  161.                                               This parameter can be a value of @ref FSMC_Extended_Mode                 */
  162.  
  163.   uint32_t AsynchronousWait;             /*!< Enables or disables wait signal during asynchronous transfers,
  164.                                               valid only with asynchronous Flash memories.
  165.                                               This parameter can be a value of @ref FSMC_AsynchronousWait              */
  166.  
  167.   uint32_t WriteBurst;                   /*!< Enables or disables the write burst operation.
  168.                                               This parameter can be a value of @ref FSMC_Write_Burst                   */
  169.  
  170.  
  171.   uint32_t PageSize;                     /*!< Specifies the memory page size.
  172.                                               This parameter can be a value of @ref FSMC_Page_Size                     */
  173. } FSMC_NORSRAM_InitTypeDef;
  174.  
  175. /**
  176.   * @brief  FSMC NORSRAM Timing parameters structure definition
  177.   */
  178. typedef struct
  179. {
  180.   uint32_t AddressSetupTime;             /*!< Defines the number of HCLK cycles to configure
  181.                                               the duration of the address setup time.
  182.                                               This parameter can be a value between Min_Data = 0 and Max_Data = 15.
  183.                                               @note This parameter is not used with synchronous NOR Flash memories.   */
  184.  
  185.   uint32_t AddressHoldTime;              /*!< Defines the number of HCLK cycles to configure
  186.                                               the duration of the address hold time.
  187.                                               This parameter can be a value between Min_Data = 1 and Max_Data = 15.
  188.                                               @note This parameter is not used with synchronous NOR Flash memories.   */
  189.  
  190.   uint32_t DataSetupTime;                /*!< Defines the number of HCLK cycles to configure
  191.                                               the duration of the data setup time.
  192.                                               This parameter can be a value between Min_Data = 1 and Max_Data = 255.
  193.                                               @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
  194.                                               NOR Flash memories.                                                     */
  195.  
  196.   uint32_t BusTurnAroundDuration;        /*!< Defines the number of HCLK cycles to configure
  197.                                               the duration of the bus turnaround.
  198.                                               This parameter can be a value between Min_Data = 0 and Max_Data = 15.
  199.                                               @note This parameter is only used for multiplexed NOR Flash memories.   */
  200.  
  201.   uint32_t CLKDivision;                  /*!< Defines the period of CLK clock output signal, expressed in number of
  202.                                               HCLK cycles. This parameter can be a value between Min_Data = 2 and
  203.                                               Max_Data = 16.
  204.                                               @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
  205.                                               accesses.                                                               */
  206.  
  207.   uint32_t DataLatency;                  /*!< Defines the number of memory clock cycles to issue
  208.                                               to the memory before getting the first data.
  209.                                               The parameter value depends on the memory type as shown below:
  210.                                               - It must be set to 0 in case of a CRAM
  211.                                               - It is don't care in asynchronous NOR, SRAM or ROM accesses
  212.                                               - It may assume a value between Min_Data = 2 and Max_Data = 17
  213.                                                 in NOR Flash memories with synchronous burst mode enable              */
  214.  
  215.   uint32_t AccessMode;                   /*!< Specifies the asynchronous access mode.
  216.                                               This parameter can be a value of @ref FSMC_Access_Mode                   */
  217. } FSMC_NORSRAM_TimingTypeDef;
  218. #endif /* FSMC_BANK1 */
  219.  
  220.  
  221.  
  222.  
  223. /**
  224.   * @}
  225.   */
  226.  
  227. /* Exported constants --------------------------------------------------------*/
  228. /** @addtogroup FSMC_LL_Exported_Constants FSMC Low Layer Exported Constants
  229.   * @{
  230.   */
  231. #if defined(FSMC_BANK1)
  232.  
  233. /** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller
  234.   * @{
  235.   */
  236.  
  237. /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
  238.   * @{
  239.   */
  240. #define FSMC_NORSRAM_BANK1                       (0x00000000U)
  241. #define FSMC_NORSRAM_BANK2                       (0x00000002U)
  242. #define FSMC_NORSRAM_BANK3                       (0x00000004U)
  243. #define FSMC_NORSRAM_BANK4                       (0x00000006U)
  244. /**
  245.   * @}
  246.   */
  247.  
  248. /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
  249.   * @{
  250.   */
  251. #define FSMC_DATA_ADDRESS_MUX_DISABLE            (0x00000000U)
  252. #define FSMC_DATA_ADDRESS_MUX_ENABLE             (0x00000002U)
  253. /**
  254.   * @}
  255.   */
  256.  
  257. /** @defgroup FSMC_Memory_Type FSMC Memory Type
  258.   * @{
  259.   */
  260. #define FSMC_MEMORY_TYPE_SRAM                    (0x00000000U)
  261. #define FSMC_MEMORY_TYPE_PSRAM                   (0x00000004U)
  262. #define FSMC_MEMORY_TYPE_NOR                     (0x00000008U)
  263. /**
  264.   * @}
  265.   */
  266.  
  267. /** @defgroup FSMC_NORSRAM_Data_Width FSMC NORSRAM Data Width
  268.   * @{
  269.   */
  270. #define FSMC_NORSRAM_MEM_BUS_WIDTH_8             (0x00000000U)
  271. #define FSMC_NORSRAM_MEM_BUS_WIDTH_16            (0x00000010U)
  272. #define FSMC_NORSRAM_MEM_BUS_WIDTH_32            (0x00000020U)
  273. /**
  274.   * @}
  275.   */
  276.  
  277. /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
  278.   * @{
  279.   */
  280. #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE         (0x00000040U)
  281. #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE        (0x00000000U)
  282. /**
  283.   * @}
  284.   */
  285.  
  286. /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
  287.   * @{
  288.   */
  289. #define FSMC_BURST_ACCESS_MODE_DISABLE           (0x00000000U)
  290. #define FSMC_BURST_ACCESS_MODE_ENABLE            (0x00000100U)
  291. /**
  292.   * @}
  293.   */
  294.  
  295. /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
  296.   * @{
  297.   */
  298. #define FSMC_WAIT_SIGNAL_POLARITY_LOW            (0x00000000U)
  299. #define FSMC_WAIT_SIGNAL_POLARITY_HIGH           (0x00000200U)
  300. /**
  301.   * @}
  302.   */
  303.  
  304. /** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
  305.   * @{
  306.   */
  307. #define FSMC_WRAP_MODE_DISABLE                   (0x00000000U)
  308. #define FSMC_WRAP_MODE_ENABLE                    (0x00000400U)
  309. /**
  310.   * @}
  311.   */
  312.  
  313. /** @defgroup FSMC_Wait_Timing FSMC Wait Timing
  314.   * @{
  315.   */
  316. #define FSMC_WAIT_TIMING_BEFORE_WS               (0x00000000U)
  317. #define FSMC_WAIT_TIMING_DURING_WS               (0x00000800U)
  318. /**
  319.   * @}
  320.   */
  321.  
  322. /** @defgroup FSMC_Write_Operation FSMC Write Operation
  323.   * @{
  324.   */
  325. #define FSMC_WRITE_OPERATION_DISABLE             (0x00000000U)
  326. #define FSMC_WRITE_OPERATION_ENABLE              (0x00001000U)
  327. /**
  328.   * @}
  329.   */
  330.  
  331. /** @defgroup FSMC_Wait_Signal FSMC Wait Signal
  332.   * @{
  333.   */
  334. #define FSMC_WAIT_SIGNAL_DISABLE                 (0x00000000U)
  335. #define FSMC_WAIT_SIGNAL_ENABLE                  (0x00002000U)
  336. /**
  337.   * @}
  338.   */
  339.  
  340. /** @defgroup FSMC_Extended_Mode FSMC Extended Mode
  341.   * @{
  342.   */
  343. #define FSMC_EXTENDED_MODE_DISABLE               (0x00000000U)
  344. #define FSMC_EXTENDED_MODE_ENABLE                (0x00004000U)
  345. /**
  346.   * @}
  347.   */
  348.  
  349. /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
  350.   * @{
  351.   */
  352. #define FSMC_ASYNCHRONOUS_WAIT_DISABLE           (0x00000000U)
  353. #define FSMC_ASYNCHRONOUS_WAIT_ENABLE            (0x00008000U)
  354. /**
  355.   * @}
  356.   */
  357.  
  358. /** @defgroup FSMC_Page_Size FSMC Page Size
  359.   * @{
  360.   */
  361. #define FSMC_PAGE_SIZE_NONE                      (0x00000000U)
  362. #define FSMC_PAGE_SIZE_128                       FSMC_BCRx_CPSIZE_0
  363. #define FSMC_PAGE_SIZE_256                       FSMC_BCRx_CPSIZE_1
  364. #define FSMC_PAGE_SIZE_512                       (FSMC_BCRx_CPSIZE_0\
  365.                                                  | FSMC_BCRx_CPSIZE_1)
  366. #define FSMC_PAGE_SIZE_1024                      FSMC_BCRx_CPSIZE_2
  367. /**
  368.   * @}
  369.   */
  370.  
  371. /** @defgroup FSMC_Write_Burst FSMC Write Burst
  372.   * @{
  373.   */
  374. #define FSMC_WRITE_BURST_DISABLE                 (0x00000000U)
  375. #define FSMC_WRITE_BURST_ENABLE                  (0x00080000U)
  376. /**
  377.   * @}
  378.   */
  379.  
  380. /** @defgroup FSMC_Continous_Clock FSMC Continuous Clock
  381.   * @{
  382.   */
  383. #define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY          (0x00000000U)
  384. #define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC         (0x00100000U)
  385. /**
  386.   * @}
  387.   */
  388.  
  389. /** @defgroup FSMC_Access_Mode FSMC Access Mode
  390.   * @{
  391.   */
  392. #define FSMC_ACCESS_MODE_A                       (0x00000000U)
  393. #define FSMC_ACCESS_MODE_B                       (0x10000000U)
  394. #define FSMC_ACCESS_MODE_C                       (0x20000000U)
  395. #define FSMC_ACCESS_MODE_D                       (0x30000000U)
  396. /**
  397.   * @}
  398.   */
  399.  
  400. /**
  401.   * @}
  402.   */
  403. #endif /* FSMC_BANK1 */
  404.  
  405.  
  406.  
  407. /** @defgroup FSMC_LL_Interrupt_definition FSMC Low Layer Interrupt definition
  408.   * @{
  409.   */
  410. /**
  411.   * @}
  412.   */
  413.  
  414. /** @defgroup FSMC_LL_Flag_definition FSMC Low Layer Flag definition
  415.   * @{
  416.   */
  417. /**
  418.   * @}
  419.   */
  420.  
  421. /**
  422.   * @}
  423.   */
  424.  
  425. /**
  426.   * @}
  427.   */
  428.  
  429. /* Private macro -------------------------------------------------------------*/
  430. /** @defgroup FSMC_LL_Private_Macros FSMC_LL  Private Macros
  431.   * @{
  432.   */
  433. #if defined(FSMC_BANK1)
  434. /** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Macros
  435.   * @brief macros to handle NOR device enable/disable and read/write operations
  436.   * @{
  437.   */
  438.  
  439. /**
  440.   * @brief  Enable the NORSRAM device access.
  441.   * @param  __INSTANCE__ FSMC_NORSRAM Instance
  442.   * @param  __BANK__ FSMC_NORSRAM Bank
  443.   * @retval None
  444.   */
  445. #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__)  ((__INSTANCE__)->BTCR[(__BANK__)]\
  446.                                                        |= FSMC_BCRx_MBKEN)
  447.  
  448. /**
  449.   * @brief  Disable the NORSRAM device access.
  450.   * @param  __INSTANCE__ FSMC_NORSRAM Instance
  451.   * @param  __BANK__ FSMC_NORSRAM Bank
  452.   * @retval None
  453.   */
  454. #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
  455.                                                        &= ~FSMC_BCRx_MBKEN)
  456.  
  457. /**
  458.   * @}
  459.   */
  460. #endif /* FSMC_BANK1 */
  461.  
  462.  
  463.  
  464.  
  465. /**
  466.   * @}
  467.   */
  468.  
  469. /**
  470.   * @}
  471.   */
  472.  
  473. /* Private functions ---------------------------------------------------------*/
  474. /** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions
  475.   *  @{
  476.   */
  477.  
  478. #if defined(FSMC_BANK1)
  479. /** @defgroup FSMC_LL_NORSRAM  NOR SRAM
  480.   *  @{
  481.   */
  482. /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
  483.   *  @{
  484.   */
  485. HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device,
  486.                                     FSMC_NORSRAM_InitTypeDef *Init);
  487. HAL_StatusTypeDef  FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device,
  488.                                            FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
  489. HAL_StatusTypeDef  FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device,
  490.                                                     FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
  491.                                                     uint32_t ExtendedMode);
  492. HAL_StatusTypeDef  FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device,
  493.                                       FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
  494. /**
  495.   * @}
  496.   */
  497.  
  498. /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
  499.   *  @{
  500.   */
  501. HAL_StatusTypeDef  FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
  502. HAL_StatusTypeDef  FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
  503. /**
  504.   * @}
  505.   */
  506. /**
  507.   * @}
  508.   */
  509. #endif /* FSMC_BANK1 */
  510.  
  511.  
  512.  
  513.  
  514. /**
  515.   * @}
  516.   */
  517.  
  518. /**
  519.   * @}
  520.   */
  521.  
  522. /**
  523.   * @}
  524.   */
  525.  
  526. #ifdef __cplusplus
  527. }
  528. #endif
  529.  
  530. #endif /* STM32L1xx_LL_FSMC_H */
  531.