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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32l1xx_ll_tim.c
  4.   * @author  MCD Application Team
  5.   * @brief   TIM LL module driver.
  6.   ******************************************************************************
  7.   * @attention
  8.   *
  9.   * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
  10.   * All rights reserved.</center></h2>
  11.   *
  12.   * This software component is licensed by ST under BSD 3-Clause license,
  13.   * the "License"; You may not use this file except in compliance with the
  14.   * License. You may obtain a copy of the License at:
  15.   *                        opensource.org/licenses/BSD-3-Clause
  16.   *
  17.   ******************************************************************************
  18.   */
  19. #if defined(USE_FULL_LL_DRIVER)
  20.  
  21. /* Includes ------------------------------------------------------------------*/
  22. #include "stm32l1xx_ll_tim.h"
  23. #include "stm32l1xx_ll_bus.h"
  24.  
  25. #ifdef  USE_FULL_ASSERT
  26. #include "stm32_assert.h"
  27. #else
  28. #define assert_param(expr) ((void)0U)
  29. #endif /* USE_FULL_ASSERT */
  30.  
  31. /** @addtogroup STM32L1xx_LL_Driver
  32.   * @{
  33.   */
  34.  
  35. #if defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM6) || defined (TIM7)
  36.  
  37. /** @addtogroup TIM_LL
  38.   * @{
  39.   */
  40.  
  41. /* Private types -------------------------------------------------------------*/
  42. /* Private variables ---------------------------------------------------------*/
  43. /* Private constants ---------------------------------------------------------*/
  44. /* Private macros ------------------------------------------------------------*/
  45. /** @addtogroup TIM_LL_Private_Macros
  46.   * @{
  47.   */
  48. #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
  49.                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
  50.                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
  51.                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
  52.                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
  53.  
  54. #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
  55.                                             || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
  56.                                             || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
  57.  
  58. #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
  59.                                      || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
  60.                                      || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
  61.                                      || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
  62.                                      || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
  63.                                      || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
  64.                                      || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
  65.                                      || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
  66.  
  67. #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
  68.                                       || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
  69.  
  70. #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
  71.                                          || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
  72.  
  73. #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
  74.                                           || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
  75.                                           || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
  76.  
  77. #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
  78.                                     || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
  79.                                     || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
  80.                                     || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
  81.  
  82. #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
  83.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
  84.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
  85.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
  86.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
  87.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
  88.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
  89.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
  90.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
  91.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
  92.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
  93.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
  94.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
  95.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
  96.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
  97.                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
  98.  
  99. #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
  100.                                           || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
  101.                                           || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
  102.  
  103. #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
  104.                                           || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
  105.                                           || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
  106.  
  107. #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
  108.                                                   || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
  109. /**
  110.   * @}
  111.   */
  112.  
  113.  
  114. /* Private function prototypes -----------------------------------------------*/
  115. /** @defgroup TIM_LL_Private_Functions TIM Private Functions
  116.   * @{
  117.   */
  118. static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
  119. static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
  120. static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
  121. static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
  122. static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
  123. static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
  124. static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
  125. static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
  126. /**
  127.   * @}
  128.   */
  129.  
  130. /* Exported functions --------------------------------------------------------*/
  131. /** @addtogroup TIM_LL_Exported_Functions
  132.   * @{
  133.   */
  134.  
  135. /** @addtogroup TIM_LL_EF_Init
  136.   * @{
  137.   */
  138.  
  139. /**
  140.   * @brief  Set TIMx registers to their reset values.
  141.   * @param  TIMx Timer instance
  142.   * @retval An ErrorStatus enumeration value:
  143.   *          - SUCCESS: TIMx registers are de-initialized
  144.   *          - ERROR: invalid TIMx instance
  145.   */
  146. ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
  147. {
  148.   ErrorStatus result = SUCCESS;
  149.  
  150.   /* Check the parameters */
  151.   assert_param(IS_TIM_INSTANCE(TIMx));
  152.  
  153.   if (TIMx == TIM2)
  154.   {
  155.     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
  156.     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
  157.   }
  158. #if defined(TIM3)
  159.   else if (TIMx == TIM3)
  160.   {
  161.     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
  162.     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
  163.   }
  164. #endif /* TIM3 */
  165. #if defined(TIM4)
  166.   else if (TIMx == TIM4)
  167.   {
  168.     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
  169.     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
  170.   }
  171. #endif /* TIM4 */
  172. #if defined(TIM5)
  173.   else if (TIMx == TIM5)
  174.   {
  175.     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
  176.     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
  177.   }
  178. #endif /* TIM5 */
  179. #if defined(TIM6)
  180.   else if (TIMx == TIM6)
  181.   {
  182.     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
  183.     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
  184.   }
  185. #endif /* TIM6 */
  186. #if defined(TIM7)
  187.   else if (TIMx == TIM7)
  188.   {
  189.     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
  190.     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
  191.   }
  192. #endif /* TIM7 */
  193. #if defined(TIM9)
  194.   else if (TIMx == TIM9)
  195.   {
  196.     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9);
  197.     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9);
  198.   }
  199. #endif /* TIM9 */
  200. #if defined(TIM10)
  201.   else if (TIMx == TIM10)
  202.   {
  203.     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10);
  204.     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10);
  205.   }
  206. #endif /* TIM10 */
  207. #if defined(TIM11)
  208.   else if (TIMx == TIM11)
  209.   {
  210.     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11);
  211.     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11);
  212.   }
  213. #endif /* TIM11 */
  214.   else
  215.   {
  216.     result = ERROR;
  217.   }
  218.  
  219.   return result;
  220. }
  221.  
  222. /**
  223.   * @brief  Set the fields of the time base unit configuration data structure
  224.   *         to their default values.
  225.   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
  226.   * @retval None
  227.   */
  228. void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
  229. {
  230.   /* Set the default configuration */
  231.   TIM_InitStruct->Prescaler         = (uint16_t)0x0000;
  232.   TIM_InitStruct->CounterMode       = LL_TIM_COUNTERMODE_UP;
  233.   TIM_InitStruct->Autoreload        = 0xFFFFFFFFU;
  234.   TIM_InitStruct->ClockDivision     = LL_TIM_CLOCKDIVISION_DIV1;
  235. }
  236.  
  237. /**
  238.   * @brief  Configure the TIMx time base unit.
  239.   * @param  TIMx Timer Instance
  240.   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
  241.   *         (TIMx time base unit configuration data structure)
  242.   * @retval An ErrorStatus enumeration value:
  243.   *          - SUCCESS: TIMx registers are de-initialized
  244.   *          - ERROR: not applicable
  245.   */
  246. ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
  247. {
  248.   uint32_t tmpcr1;
  249.  
  250.   /* Check the parameters */
  251.   assert_param(IS_TIM_INSTANCE(TIMx));
  252.   assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
  253.   assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
  254.  
  255.   tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
  256.  
  257.   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
  258.   {
  259.     /* Select the Counter Mode */
  260.     MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
  261.   }
  262.  
  263.   if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
  264.   {
  265.     /* Set the clock division */
  266.     MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
  267.   }
  268.  
  269.   /* Write to TIMx CR1 */
  270.   LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
  271.  
  272.   /* Set the Autoreload value */
  273.   LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
  274.  
  275.   /* Set the Prescaler value */
  276.   LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
  277.   /* Generate an update event to reload the Prescaler
  278.      and the repetition counter value (if applicable) immediately */
  279.   LL_TIM_GenerateEvent_UPDATE(TIMx);
  280.  
  281.   return SUCCESS;
  282. }
  283.  
  284. /**
  285.   * @brief  Set the fields of the TIMx output channel configuration data
  286.   *         structure to their default values.
  287.   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
  288.   *         (the output channel configuration data structure)
  289.   * @retval None
  290.   */
  291. void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
  292. {
  293.   /* Set the default configuration */
  294.   TIM_OC_InitStruct->OCMode       = LL_TIM_OCMODE_FROZEN;
  295.   TIM_OC_InitStruct->OCState      = LL_TIM_OCSTATE_DISABLE;
  296.   TIM_OC_InitStruct->CompareValue = 0x00000000U;
  297.   TIM_OC_InitStruct->OCPolarity   = LL_TIM_OCPOLARITY_HIGH;
  298. }
  299.  
  300. /**
  301.   * @brief  Configure the TIMx output channel.
  302.   * @param  TIMx Timer Instance
  303.   * @param  Channel This parameter can be one of the following values:
  304.   *         @arg @ref LL_TIM_CHANNEL_CH1
  305.   *         @arg @ref LL_TIM_CHANNEL_CH2
  306.   *         @arg @ref LL_TIM_CHANNEL_CH3
  307.   *         @arg @ref LL_TIM_CHANNEL_CH4
  308.   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
  309.   *         data structure)
  310.   * @retval An ErrorStatus enumeration value:
  311.   *          - SUCCESS: TIMx output channel is initialized
  312.   *          - ERROR: TIMx output channel is not initialized
  313.   */
  314. ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
  315. {
  316.   ErrorStatus result = ERROR;
  317.  
  318.   switch (Channel)
  319.   {
  320.     case LL_TIM_CHANNEL_CH1:
  321.       result = OC1Config(TIMx, TIM_OC_InitStruct);
  322.       break;
  323.     case LL_TIM_CHANNEL_CH2:
  324.       result = OC2Config(TIMx, TIM_OC_InitStruct);
  325.       break;
  326.     case LL_TIM_CHANNEL_CH3:
  327.       result = OC3Config(TIMx, TIM_OC_InitStruct);
  328.       break;
  329.     case LL_TIM_CHANNEL_CH4:
  330.       result = OC4Config(TIMx, TIM_OC_InitStruct);
  331.       break;
  332.     default:
  333.       break;
  334.   }
  335.  
  336.   return result;
  337. }
  338.  
  339. /**
  340.   * @brief  Set the fields of the TIMx input channel configuration data
  341.   *         structure to their default values.
  342.   * @param  TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
  343.   *         data structure)
  344.   * @retval None
  345.   */
  346. void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
  347. {
  348.   /* Set the default configuration */
  349.   TIM_ICInitStruct->ICPolarity    = LL_TIM_IC_POLARITY_RISING;
  350.   TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
  351.   TIM_ICInitStruct->ICPrescaler   = LL_TIM_ICPSC_DIV1;
  352.   TIM_ICInitStruct->ICFilter      = LL_TIM_IC_FILTER_FDIV1;
  353. }
  354.  
  355. /**
  356.   * @brief  Configure the TIMx input channel.
  357.   * @param  TIMx Timer Instance
  358.   * @param  Channel This parameter can be one of the following values:
  359.   *         @arg @ref LL_TIM_CHANNEL_CH1
  360.   *         @arg @ref LL_TIM_CHANNEL_CH2
  361.   *         @arg @ref LL_TIM_CHANNEL_CH3
  362.   *         @arg @ref LL_TIM_CHANNEL_CH4
  363.   * @param  TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
  364.   *         structure)
  365.   * @retval An ErrorStatus enumeration value:
  366.   *          - SUCCESS: TIMx output channel is initialized
  367.   *          - ERROR: TIMx output channel is not initialized
  368.   */
  369. ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
  370. {
  371.   ErrorStatus result = ERROR;
  372.  
  373.   switch (Channel)
  374.   {
  375.     case LL_TIM_CHANNEL_CH1:
  376.       result = IC1Config(TIMx, TIM_IC_InitStruct);
  377.       break;
  378.     case LL_TIM_CHANNEL_CH2:
  379.       result = IC2Config(TIMx, TIM_IC_InitStruct);
  380.       break;
  381.     case LL_TIM_CHANNEL_CH3:
  382.       result = IC3Config(TIMx, TIM_IC_InitStruct);
  383.       break;
  384.     case LL_TIM_CHANNEL_CH4:
  385.       result = IC4Config(TIMx, TIM_IC_InitStruct);
  386.       break;
  387.     default:
  388.       break;
  389.   }
  390.  
  391.   return result;
  392. }
  393.  
  394. /**
  395.   * @brief  Fills each TIM_EncoderInitStruct field with its default value
  396.   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
  397.   *         configuration data structure)
  398.   * @retval None
  399.   */
  400. void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
  401. {
  402.   /* Set the default configuration */
  403.   TIM_EncoderInitStruct->EncoderMode    = LL_TIM_ENCODERMODE_X2_TI1;
  404.   TIM_EncoderInitStruct->IC1Polarity    = LL_TIM_IC_POLARITY_RISING;
  405.   TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
  406.   TIM_EncoderInitStruct->IC1Prescaler   = LL_TIM_ICPSC_DIV1;
  407.   TIM_EncoderInitStruct->IC1Filter      = LL_TIM_IC_FILTER_FDIV1;
  408.   TIM_EncoderInitStruct->IC2Polarity    = LL_TIM_IC_POLARITY_RISING;
  409.   TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
  410.   TIM_EncoderInitStruct->IC2Prescaler   = LL_TIM_ICPSC_DIV1;
  411.   TIM_EncoderInitStruct->IC2Filter      = LL_TIM_IC_FILTER_FDIV1;
  412. }
  413.  
  414. /**
  415.   * @brief  Configure the encoder interface of the timer instance.
  416.   * @param  TIMx Timer Instance
  417.   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
  418.   *         configuration data structure)
  419.   * @retval An ErrorStatus enumeration value:
  420.   *          - SUCCESS: TIMx registers are de-initialized
  421.   *          - ERROR: not applicable
  422.   */
  423. ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
  424. {
  425.   uint32_t tmpccmr1;
  426.   uint32_t tmpccer;
  427.  
  428.   /* Check the parameters */
  429.   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
  430.   assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
  431.   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
  432.   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
  433.   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
  434.   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
  435.   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
  436.   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
  437.   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
  438.   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
  439.  
  440.   /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
  441.   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
  442.  
  443.   /* Get the TIMx CCMR1 register value */
  444.   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
  445.  
  446.   /* Get the TIMx CCER register value */
  447.   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
  448.  
  449.   /* Configure TI1 */
  450.   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
  451.   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
  452.   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
  453.   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
  454.  
  455.   /* Configure TI2 */
  456.   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F  | TIM_CCMR1_IC2PSC);
  457.   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
  458.   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
  459.   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
  460.  
  461.   /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
  462.   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
  463.   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
  464.   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
  465.   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
  466.  
  467.   /* Set encoder mode */
  468.   LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
  469.  
  470.   /* Write to TIMx CCMR1 */
  471.   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
  472.  
  473.   /* Write to TIMx CCER */
  474.   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
  475.  
  476.   return SUCCESS;
  477. }
  478.  
  479. /**
  480.   * @}
  481.   */
  482.  
  483. /**
  484.   * @}
  485.   */
  486.  
  487. /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
  488.   *  @brief   Private functions
  489.   * @{
  490.   */
  491. /**
  492.   * @brief  Configure the TIMx output channel 1.
  493.   * @param  TIMx Timer Instance
  494.   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
  495.   * @retval An ErrorStatus enumeration value:
  496.   *          - SUCCESS: TIMx registers are de-initialized
  497.   *          - ERROR: not applicable
  498.   */
  499. static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
  500. {
  501.   uint32_t tmpccmr1;
  502.   uint32_t tmpccer;
  503.   uint32_t tmpcr2;
  504.  
  505.   /* Check the parameters */
  506.   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
  507.   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
  508.   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
  509.   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
  510.  
  511.   /* Disable the Channel 1: Reset the CC1E Bit */
  512.   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
  513.  
  514.   /* Get the TIMx CCER register value */
  515.   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
  516.  
  517.   /* Get the TIMx CR2 register value */
  518.   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
  519.  
  520.   /* Get the TIMx CCMR1 register value */
  521.   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
  522.  
  523.   /* Reset Capture/Compare selection Bits */
  524.   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
  525.  
  526.   /* Set the Output Compare Mode */
  527.   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
  528.  
  529.   /* Set the Output Compare Polarity */
  530.   MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
  531.  
  532.   /* Set the Output State */
  533.   MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
  534.  
  535.   /* Write to TIMx CR2 */
  536.   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
  537.  
  538.   /* Write to TIMx CCMR1 */
  539.   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
  540.  
  541.   /* Set the Capture Compare Register value */
  542.   LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
  543.  
  544.   /* Write to TIMx CCER */
  545.   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
  546.  
  547.   return SUCCESS;
  548. }
  549.  
  550. /**
  551.   * @brief  Configure the TIMx output channel 2.
  552.   * @param  TIMx Timer Instance
  553.   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
  554.   * @retval An ErrorStatus enumeration value:
  555.   *          - SUCCESS: TIMx registers are de-initialized
  556.   *          - ERROR: not applicable
  557.   */
  558. static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
  559. {
  560.   uint32_t tmpccmr1;
  561.   uint32_t tmpccer;
  562.   uint32_t tmpcr2;
  563.  
  564.   /* Check the parameters */
  565.   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
  566.   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
  567.   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
  568.   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
  569.  
  570.   /* Disable the Channel 2: Reset the CC2E Bit */
  571.   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
  572.  
  573.   /* Get the TIMx CCER register value */
  574.   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
  575.  
  576.   /* Get the TIMx CR2 register value */
  577.   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
  578.  
  579.   /* Get the TIMx CCMR1 register value */
  580.   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
  581.  
  582.   /* Reset Capture/Compare selection Bits */
  583.   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
  584.  
  585.   /* Select the Output Compare Mode */
  586.   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
  587.  
  588.   /* Set the Output Compare Polarity */
  589.   MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
  590.  
  591.   /* Set the Output State */
  592.   MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
  593.  
  594.   /* Write to TIMx CR2 */
  595.   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
  596.  
  597.   /* Write to TIMx CCMR1 */
  598.   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
  599.  
  600.   /* Set the Capture Compare Register value */
  601.   LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
  602.  
  603.   /* Write to TIMx CCER */
  604.   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
  605.  
  606.   return SUCCESS;
  607. }
  608.  
  609. /**
  610.   * @brief  Configure the TIMx output channel 3.
  611.   * @param  TIMx Timer Instance
  612.   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
  613.   * @retval An ErrorStatus enumeration value:
  614.   *          - SUCCESS: TIMx registers are de-initialized
  615.   *          - ERROR: not applicable
  616.   */
  617. static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
  618. {
  619.   uint32_t tmpccmr2;
  620.   uint32_t tmpccer;
  621.   uint32_t tmpcr2;
  622.  
  623.   /* Check the parameters */
  624.   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
  625.   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
  626.   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
  627.   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
  628.  
  629.   /* Disable the Channel 3: Reset the CC3E Bit */
  630.   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
  631.  
  632.   /* Get the TIMx CCER register value */
  633.   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
  634.  
  635.   /* Get the TIMx CR2 register value */
  636.   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
  637.  
  638.   /* Get the TIMx CCMR2 register value */
  639.   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
  640.  
  641.   /* Reset Capture/Compare selection Bits */
  642.   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
  643.  
  644.   /* Select the Output Compare Mode */
  645.   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
  646.  
  647.   /* Set the Output Compare Polarity */
  648.   MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
  649.  
  650.   /* Set the Output State */
  651.   MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
  652.  
  653.   /* Write to TIMx CR2 */
  654.   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
  655.  
  656.   /* Write to TIMx CCMR2 */
  657.   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
  658.  
  659.   /* Set the Capture Compare Register value */
  660.   LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
  661.  
  662.   /* Write to TIMx CCER */
  663.   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
  664.  
  665.   return SUCCESS;
  666. }
  667.  
  668. /**
  669.   * @brief  Configure the TIMx output channel 4.
  670.   * @param  TIMx Timer Instance
  671.   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
  672.   * @retval An ErrorStatus enumeration value:
  673.   *          - SUCCESS: TIMx registers are de-initialized
  674.   *          - ERROR: not applicable
  675.   */
  676. static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
  677. {
  678.   uint32_t tmpccmr2;
  679.   uint32_t tmpccer;
  680.   uint32_t tmpcr2;
  681.  
  682.   /* Check the parameters */
  683.   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
  684.   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
  685.   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
  686.   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
  687.  
  688.   /* Disable the Channel 4: Reset the CC4E Bit */
  689.   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
  690.  
  691.   /* Get the TIMx CCER register value */
  692.   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
  693.  
  694.   /* Get the TIMx CR2 register value */
  695.   tmpcr2 =  LL_TIM_ReadReg(TIMx, CR2);
  696.  
  697.   /* Get the TIMx CCMR2 register value */
  698.   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
  699.  
  700.   /* Reset Capture/Compare selection Bits */
  701.   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
  702.  
  703.   /* Select the Output Compare Mode */
  704.   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
  705.  
  706.   /* Set the Output Compare Polarity */
  707.   MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
  708.  
  709.   /* Set the Output State */
  710.   MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
  711.  
  712.   /* Write to TIMx CR2 */
  713.   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
  714.  
  715.   /* Write to TIMx CCMR2 */
  716.   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
  717.  
  718.   /* Set the Capture Compare Register value */
  719.   LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
  720.  
  721.   /* Write to TIMx CCER */
  722.   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
  723.  
  724.   return SUCCESS;
  725. }
  726.  
  727.  
  728. /**
  729.   * @brief  Configure the TIMx input channel 1.
  730.   * @param  TIMx Timer Instance
  731.   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
  732.   * @retval An ErrorStatus enumeration value:
  733.   *          - SUCCESS: TIMx registers are de-initialized
  734.   *          - ERROR: not applicable
  735.   */
  736. static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
  737. {
  738.   /* Check the parameters */
  739.   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
  740.   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
  741.   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
  742.   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
  743.   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
  744.  
  745.   /* Disable the Channel 1: Reset the CC1E Bit */
  746.   TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
  747.  
  748.   /* Select the Input and set the filter and the prescaler value */
  749.   MODIFY_REG(TIMx->CCMR1,
  750.              (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
  751.              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
  752.  
  753.   /* Select the Polarity and set the CC1E Bit */
  754.   MODIFY_REG(TIMx->CCER,
  755.              (TIM_CCER_CC1P | TIM_CCER_CC1NP),
  756.              (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
  757.  
  758.   return SUCCESS;
  759. }
  760.  
  761. /**
  762.   * @brief  Configure the TIMx input channel 2.
  763.   * @param  TIMx Timer Instance
  764.   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
  765.   * @retval An ErrorStatus enumeration value:
  766.   *          - SUCCESS: TIMx registers are de-initialized
  767.   *          - ERROR: not applicable
  768.   */
  769. static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
  770. {
  771.   /* Check the parameters */
  772.   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
  773.   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
  774.   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
  775.   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
  776.   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
  777.  
  778.   /* Disable the Channel 2: Reset the CC2E Bit */
  779.   TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
  780.  
  781.   /* Select the Input and set the filter and the prescaler value */
  782.   MODIFY_REG(TIMx->CCMR1,
  783.              (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
  784.              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
  785.  
  786.   /* Select the Polarity and set the CC2E Bit */
  787.   MODIFY_REG(TIMx->CCER,
  788.              (TIM_CCER_CC2P | TIM_CCER_CC2NP),
  789.              ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
  790.  
  791.   return SUCCESS;
  792. }
  793.  
  794. /**
  795.   * @brief  Configure the TIMx input channel 3.
  796.   * @param  TIMx Timer Instance
  797.   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
  798.   * @retval An ErrorStatus enumeration value:
  799.   *          - SUCCESS: TIMx registers are de-initialized
  800.   *          - ERROR: not applicable
  801.   */
  802. static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
  803. {
  804.   /* Check the parameters */
  805.   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
  806.   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
  807.   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
  808.   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
  809.   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
  810.  
  811.   /* Disable the Channel 3: Reset the CC3E Bit */
  812.   TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
  813.  
  814.   /* Select the Input and set the filter and the prescaler value */
  815.   MODIFY_REG(TIMx->CCMR2,
  816.              (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
  817.              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
  818.  
  819.   /* Select the Polarity and set the CC3E Bit */
  820.   MODIFY_REG(TIMx->CCER,
  821.              (TIM_CCER_CC3P | TIM_CCER_CC3NP),
  822.              ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
  823.  
  824.   return SUCCESS;
  825. }
  826.  
  827. /**
  828.   * @brief  Configure the TIMx input channel 4.
  829.   * @param  TIMx Timer Instance
  830.   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
  831.   * @retval An ErrorStatus enumeration value:
  832.   *          - SUCCESS: TIMx registers are de-initialized
  833.   *          - ERROR: not applicable
  834.   */
  835. static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
  836. {
  837.   /* Check the parameters */
  838.   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
  839.   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
  840.   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
  841.   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
  842.   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
  843.  
  844.   /* Disable the Channel 4: Reset the CC4E Bit */
  845.   TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
  846.  
  847.   /* Select the Input and set the filter and the prescaler value */
  848.   MODIFY_REG(TIMx->CCMR2,
  849.              (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
  850.              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
  851.  
  852.   /* Select the Polarity and set the CC2E Bit */
  853.   MODIFY_REG(TIMx->CCER,
  854.              (TIM_CCER_CC4P | TIM_CCER_CC4NP),
  855.              ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
  856.  
  857.   return SUCCESS;
  858. }
  859.  
  860.  
  861. /**
  862.   * @}
  863.   */
  864.  
  865. /**
  866.   * @}
  867.   */
  868.  
  869. #endif /* TIM2 || TIM3 || TIM4 || TIM5 || TIM9 || TIM10 || TIM11 TIM6 || TIM7 */
  870.  
  871. /**
  872.   * @}
  873.   */
  874.  
  875. #endif /* USE_FULL_LL_DRIVER */
  876.  
  877. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  878.