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  1. /**
  2.   ******************************************************************************
  3.   * @file    stm32l1xx_ll_fsmc.c
  4.   * @author  MCD Application Team
  5.   * @brief   FSMC Low Layer HAL module driver.
  6.   *
  7.   *          This file provides firmware functions to manage the following
  8.   *          functionalities of the Flexible Static Memory Controller (FSMC) peripheral memories:
  9.   *           + Initialization/de-initialization functions
  10.   *           + Peripheral Control functions
  11.   *           + Peripheral State functions
  12.   *
  13.   @verbatim
  14.   =============================================================================
  15.                         ##### FSMC peripheral features #####
  16.   =============================================================================
  17.     [..] The Flexible static memory controller (FSMC) includes following memory controllers:
  18.          (+) The NOR/PSRAM memory controller
  19.  
  20.     [..] The FSMC functional block makes the interface with synchronous and asynchronous static
  21.          memories. Its main purposes are:
  22.          (+) to translate AHB transactions into the appropriate external device protocol.
  23.          (+) to meet the access time requirements of the external memory devices.
  24.  
  25.     [..] All external memories share the addresses, data and control signals with the controller.
  26.          Each external device is accessed by means of a unique Chip Select. The FSMC performs
  27.          only one access at a time to an external device.
  28.          The main features of the FSMC controller are the following:
  29.           (+) Interface with static-memory mapped devices including:
  30.              (++) Static random access memory (SRAM).
  31.              (++) NOR Flash memory.
  32.              (++) PSRAM (4 memory banks).
  33.           (+) Independent Chip Select control for each memory bank
  34.           (+) Independent configuration for each memory bank
  35.  
  36.   @endverbatim
  37.   ******************************************************************************
  38.   * @attention
  39.   *
  40.   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  41.   * All rights reserved.</center></h2>
  42.   *
  43.   * This software component is licensed by ST under BSD 3-Clause license,
  44.   * the "License"; You may not use this file except in compliance with the
  45.   * License. You may obtain a copy of the License at:
  46.   *                        opensource.org/licenses/BSD-3-Clause
  47.   *
  48.   ******************************************************************************
  49.   */
  50.  
  51. /* Includes ------------------------------------------------------------------*/
  52. #include "stm32l1xx_hal.h"
  53.  
  54. /** @addtogroup STM32L1xx_HAL_Driver
  55.   * @{
  56.   */
  57.  
  58. #if defined(FSMC_BANK1)
  59.  
  60. #if defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED)
  61.  
  62. /** @defgroup FSMC_LL FSMC Low Layer
  63.   * @brief FSMC driver modules
  64.   * @{
  65.   */
  66.  
  67. /* Private typedef -----------------------------------------------------------*/
  68. /* Private define ------------------------------------------------------------*/
  69. /** @defgroup FSMC_LL_Private_Constants FSMC Low Layer Private Constants
  70.   * @{
  71.   */
  72.  
  73. /* ----------------------- FSMC registers bit mask --------------------------- */
  74. /* --- BCR Register ---*/
  75. /* BCR register clear mask */
  76. #define BCR_CLEAR_MASK                 ((uint32_t)(FSMC_BCRx_FACCEN  | FSMC_BCRx_MUXEN     | \
  77.                                                    FSMC_BCRx_MTYP    | FSMC_BCRx_MWID      | \
  78.                                                    FSMC_BCRx_BURSTEN | FSMC_BCRx_WAITPOL   | \
  79.                                                    FSMC_BCRx_WRAPMOD | FSMC_BCRx_WAITCFG   | \
  80.                                                    FSMC_BCRx_WREN    | FSMC_BCRx_WAITEN    | \
  81.                                                    FSMC_BCRx_EXTMOD  | FSMC_BCRx_ASYNCWAIT | \
  82.                                                    FSMC_BCRx_CBURSTRW))
  83. /* --- BTR Register ---*/
  84. /* BTR register clear mask */
  85. #define BTR_CLEAR_MASK                 ((uint32_t)(FSMC_BTRx_ADDSET | FSMC_BTRx_ADDHLD  |\
  86.                                                    FSMC_BTRx_DATAST | FSMC_BTRx_BUSTURN |\
  87.                                                    FSMC_BTRx_CLKDIV | FSMC_BTRx_DATLAT  |\
  88.                                                    FSMC_BTRx_ACCMOD))
  89.  
  90. /* --- BWTR Register ---*/
  91. /* BWTR register clear mask */
  92. #define BWTR_CLEAR_MASK                ((uint32_t)(FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD | \
  93.                                                    FSMC_BWTRx_DATAST | FSMC_BWTRx_ACCMOD | \
  94.                                                    FSMC_BWTRx_BUSTURN))
  95.  
  96. /**
  97.   * @}
  98.   */
  99.  
  100. /* Private macro -------------------------------------------------------------*/
  101. /** @defgroup FSMC_LL_Private_Macros FSMC Low Layer Private Macros
  102.   * @{
  103.   */
  104.  
  105. /**
  106.   * @}
  107.   */
  108.  
  109. /* Private variables ---------------------------------------------------------*/
  110. /* Private function prototypes -----------------------------------------------*/
  111. /* Exported functions --------------------------------------------------------*/
  112.  
  113. /** @defgroup FSMC_LL_Exported_Functions FSMC Low Layer Exported Functions
  114.   * @{
  115.   */
  116.  
  117. /** @defgroup FSMC_NORSRAM FSMC NORSRAM Controller functions
  118.   * @brief    NORSRAM Controller functions
  119.   *
  120.   @verbatim
  121.   ==============================================================================
  122.                    ##### How to use NORSRAM device driver #####
  123.   ==============================================================================
  124.  
  125.   [..]
  126.     This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order
  127.     to run the NORSRAM external devices.
  128.  
  129.     (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit()
  130.     (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init()
  131.     (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init()
  132.     (+) FSMC NORSRAM bank extended timing configuration using the function
  133.         FSMC_NORSRAM_Extended_Timing_Init()
  134.     (+) FSMC NORSRAM bank enable/disable write operation using the functions
  135.         FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable()
  136.  
  137.  
  138. @endverbatim
  139.   * @{
  140.   */
  141.  
  142. /** @defgroup FSMC_NORSRAM_Group1 Initialization/de-initialization functions
  143.   * @brief    Initialization and Configuration functions
  144.   *
  145.   @verbatim
  146.   ==============================================================================
  147.               ##### Initialization and de_initialization functions #####
  148.   ==============================================================================
  149.   [..]
  150.     This section provides functions allowing to:
  151.     (+) Initialize and configure the FSMC NORSRAM interface
  152.     (+) De-initialize the FSMC NORSRAM interface
  153.     (+) Configure the FSMC clock and associated GPIOs
  154.  
  155. @endverbatim
  156.   * @{
  157.   */
  158.  
  159. /**
  160.   * @brief  Initialize the FSMC_NORSRAM device according to the specified
  161.   *         control parameters in the FSMC_NORSRAM_InitTypeDef
  162.   * @param  Device Pointer to NORSRAM device instance
  163.   * @param  Init Pointer to NORSRAM Initialization structure
  164.   * @retval HAL status
  165.   */
  166. HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init)
  167. {
  168.   /* Check the parameters */
  169.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  170.   assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
  171.   assert_param(IS_FSMC_MUX(Init->DataAddressMux));
  172.   assert_param(IS_FSMC_MEMORY(Init->MemoryType));
  173.   assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
  174.   assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
  175.   assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
  176.   assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
  177.   assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
  178.   assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
  179.   assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
  180.   assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
  181.   assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
  182.   assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
  183.  
  184.   /* Disable NORSRAM Device */
  185.   __FSMC_NORSRAM_DISABLE(Device, Init->NSBank);
  186.  
  187.   /* Set NORSRAM device control parameters */
  188.   if (Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
  189.   {
  190.     MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (uint32_t)(FSMC_NORSRAM_FLASH_ACCESS_ENABLE
  191.                | Init->DataAddressMux
  192.                | Init->MemoryType
  193.                | Init->MemoryDataWidth
  194.                | Init->BurstAccessMode
  195.                | Init->WaitSignalPolarity
  196.                | Init->WrapMode
  197.                | Init->WaitSignalActive
  198.                | Init->WriteOperation
  199.                | Init->WaitSignal
  200.                | Init->ExtendedMode
  201.                | Init->AsynchronousWait
  202.                | Init->WriteBurst
  203.                                                                      )
  204.               );
  205.   }
  206.   else
  207.   {
  208.     MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (uint32_t)(FSMC_NORSRAM_FLASH_ACCESS_DISABLE
  209.                | Init->DataAddressMux
  210.                | Init->MemoryType
  211.                | Init->MemoryDataWidth
  212.                | Init->BurstAccessMode
  213.                | Init->WaitSignalPolarity
  214.                | Init->WrapMode
  215.                | Init->WaitSignalActive
  216.                | Init->WriteOperation
  217.                | Init->WaitSignal
  218.                | Init->ExtendedMode
  219.                | Init->AsynchronousWait
  220.                | Init->WriteBurst
  221.                                                                      )
  222.               );
  223.   }
  224.  
  225.   return HAL_OK;
  226. }
  227.  
  228.  
  229. /**
  230.   * @brief  DeInitialize the FSMC_NORSRAM peripheral
  231.   * @param  Device Pointer to NORSRAM device instance
  232.   * @param  ExDevice Pointer to NORSRAM extended mode device instance
  233.   * @param  Bank NORSRAM bank number
  234.   * @retval HAL status
  235.   */
  236. HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
  237. {
  238.   /* Check the parameters */
  239.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  240.   assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
  241.   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
  242.  
  243.   /* Disable the FSMC_NORSRAM device */
  244.   __FSMC_NORSRAM_DISABLE(Device, Bank);
  245.  
  246.   /* De-initialize the FSMC_NORSRAM device */
  247.   /* FSMC_NORSRAM_BANK1 */
  248.   if (Bank == FSMC_NORSRAM_BANK1)
  249.   {
  250.     Device->BTCR[Bank] = 0x000030DB;
  251.   }
  252.   /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */
  253.   else
  254.   {
  255.     Device->BTCR[Bank] = 0x000030D2;
  256.   }
  257.  
  258.   Device->BTCR[Bank + 1] = 0x0FFFFFFF;
  259.   ExDevice->BWTR[Bank]   = 0x0FFFFFFF;
  260.  
  261.   return HAL_OK;
  262. }
  263.  
  264.  
  265. /**
  266.   * @brief  Initialize the FSMC_NORSRAM Timing according to the specified
  267.   *         parameters in the FSMC_NORSRAM_TimingTypeDef
  268.   * @param  Device Pointer to NORSRAM device instance
  269.   * @param  Timing Pointer to NORSRAM Timing structure
  270.   * @param  Bank NORSRAM bank number
  271.   * @retval HAL status
  272.   */
  273. HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
  274. {
  275.   /* Check the parameters */
  276.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  277.   assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
  278.   assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
  279.   assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
  280.   assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
  281.   assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
  282.   assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
  283.   assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
  284.   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
  285.  
  286.   /* Set FSMC_NORSRAM device timing parameters */
  287.   MODIFY_REG(Device->BTCR[Bank + 1],                                                    \
  288.              BTR_CLEAR_MASK,                                                                     \
  289.              (uint32_t)(Timing->AddressSetupTime                                               | \
  290.                         ((Timing->AddressHoldTime)        << POSITION_VAL(FSMC_BTRx_ADDHLD))        | \
  291.                         ((Timing->DataSetupTime)          << POSITION_VAL(FSMC_BTRx_DATAST))        | \
  292.                         ((Timing->BusTurnAroundDuration)  << POSITION_VAL(FSMC_BTRx_BUSTURN))       | \
  293.                         (((Timing->CLKDivision) - 1)        << POSITION_VAL(FSMC_BTRx_CLKDIV))        | \
  294.                         (((Timing->DataLatency) - 2)        << POSITION_VAL(FSMC_BTRx_DATLAT))        | \
  295.                         (Timing->AccessMode)));
  296.  
  297.   return HAL_OK;
  298. }
  299.  
  300. /**
  301.   * @brief  Initialize the FSMC_NORSRAM Extended mode Timing according to the specified
  302.   *         parameters in the FSMC_NORSRAM_TimingTypeDef
  303.   * @param  Device Pointer to NORSRAM device instance
  304.   * @param  Timing Pointer to NORSRAM Timing structure
  305.   * @param  Bank NORSRAM bank number
  306.   * @param  ExtendedMode FSMC Extended Mode
  307.   *          This parameter can be one of the following values:
  308.   *            @arg FSMC_EXTENDED_MODE_DISABLE
  309.   *            @arg FSMC_EXTENDED_MODE_ENABLE
  310.   * @retval HAL status
  311.   */
  312. HAL_StatusTypeDef  FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
  313. {
  314.   /* Check the parameters */
  315.   assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode));
  316.  
  317.   /* Set NORSRAM device timing register for write configuration, if extended mode is used */
  318.   if (ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
  319.   {
  320.     /* Check the parameters */
  321.     assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device));
  322.     assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
  323.     assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
  324.     assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
  325.     assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
  326.     assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
  327.     assert_param(IS_FSMC_NORSRAM_BANK(Bank));
  328.  
  329.     /* Set NORSRAM device timing register for write configuration, if extended mode is used */
  330.     MODIFY_REG(Device->BWTR[Bank],                                                  \
  331.                BWTR_CLEAR_MASK,                                                              \
  332.                (uint32_t)(Timing->AddressSetupTime                                         | \
  333.                           ((Timing->AddressHoldTime)        << POSITION_VAL(FSMC_BWTRx_ADDHLD)) | \
  334.                           ((Timing->DataSetupTime)          << POSITION_VAL(FSMC_BWTRx_DATAST)) | \
  335.                           Timing->AccessMode                                                          | \
  336.                           ((Timing->BusTurnAroundDuration)  << POSITION_VAL(FSMC_BWTRx_BUSTURN))));
  337.   }
  338.   else
  339.   {
  340.     Device->BWTR[Bank] = 0x0FFFFFFF;
  341.   }
  342.  
  343.   return HAL_OK;
  344. }
  345.  
  346.  
  347. /**
  348.   * @}
  349.   */
  350.  
  351.  
  352. /** @defgroup FSMC_NORSRAM_Group2 Control functions
  353.  *  @brief   management functions
  354.  *
  355. @verbatim
  356.   ==============================================================================
  357.                       ##### FSMC_NORSRAM Control functions #####
  358.   ==============================================================================
  359.   [..]
  360.     This subsection provides a set of functions allowing to control dynamically
  361.     the FSMC NORSRAM interface.
  362.  
  363. @endverbatim
  364.   * @{
  365.   */
  366.  
  367. /**
  368.   * @brief  Enables dynamically FSMC_NORSRAM write operation.
  369.   * @param  Device Pointer to NORSRAM device instance
  370.   * @param  Bank NORSRAM bank number
  371.   * @retval HAL status
  372.   */
  373. HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
  374. {
  375.   /* Check the parameters */
  376.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  377.   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
  378.  
  379.   /* Enable write operation */
  380.   SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
  381.  
  382.   return HAL_OK;
  383. }
  384.  
  385. /**
  386.   * @brief  Disables dynamically FSMC_NORSRAM write operation.
  387.   * @param  Device Pointer to NORSRAM device instance
  388.   * @param  Bank NORSRAM bank number
  389.   * @retval HAL status
  390.   */
  391. HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
  392. {
  393.   /* Check the parameters */
  394.   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
  395.   assert_param(IS_FSMC_NORSRAM_BANK(Bank));
  396.  
  397.   /* Disable write operation */
  398.   CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
  399.  
  400.   return HAL_OK;
  401. }
  402.  
  403. /**
  404.   * @}
  405.   */
  406.  
  407. /**
  408.   * @}
  409.   */
  410. /**
  411.   * @}
  412.   */
  413.  
  414. /**
  415.   * @}
  416.   */
  417.  
  418. #endif /* defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) */
  419.  
  420. #endif /* FSMC_BANK1 */
  421.  
  422. /**
  423.   * @}
  424.   */
  425.  
  426. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
  427.