--       Altera EPLD / PCB / VHDL tools        --
-- (c) Philips Semiconductors Southampton 1996-2001 --

-- by: Mike James (Mike.D.James@philips.com)

-- package version:12.02 Verilog  compiled: May 21 2001--

-- Produced by WRITE VHDL (PC-CygWin)
-- at 16:10:14	on 21/05/2001 

LIBRARY IEEE,WORK;
USE IEEE.std_logic_1164.ALL;

ENTITY top IS
  PORT (

     );
END top;

LIBRARY IEEE,WORK;
USE IEEE.std_logic_1164.ALL;



ARCHITECTURE top_arch OF  top IS



COMPONENT  rpl_sub_n5_3
--  DEV_IDENT "rpl_sub_n5_3"

  PORT ( 
);
END COMPONENT;



BEGIN

rpl_sub_n5_3 : rpl_sub_n5_3 
  PORT MAP ( 

   );

-- Buffered signals

-- 

END top_arch;