/*
 * hardware.c
 *
 *  Created on: 19 Aug 2017
 *      Author: Mike
 */
#include "ch.h"
#include "hal.h"
#include "hardware.h"

void TIM1_UP_IRQHandler(void) {
// we have an interrupt here .



}

void initTimer(void) {
	rccEnableTIM1(FALSE);
	rccResetTIM1();
	nvicEnableVector(TIM1_UP_IRQn,
			CORTEX_PRIORITY_MASK(STM32_GPT_TIM1_IRQ_PRIORITY));
	//gptp->clock = STM32_TIMCLK2;

	TIM1->CR1 = 0; /* Initially stopped.           */
	TIM1->CR2 = TIM_CR2_CCDS; /* DMA on UE (if any).          */
	TIM1->PSC = 72; /* Prescaler value.             */
	TIM1->DIER = 0;

}

void stopTimer(void) {
	nvicDisableVector(TIM1_UP_IRQn);
	rccDisableTIM1(FALSE);
}

void startTimer(void) {
	  TIM1->ARR  = 12405;           /* Time constant.               */
	  TIM1->EGR  = TIM_EGR_UG;             /* Update event.                */
	  TIM1->CNT  = 0;                      /* Reset counter.               */
	  /* NOTE: After generating the UG event it takes several clock cycles before
	     SR bit 0 goes to 1. This is because the clearing of CNT has been inserted
	     before the clearing of SR, to give it some time.*/
	  TIM1->SR   = 0;                      /* Clear pending IRQs (if any). */
	  TIM1->DIER = TIM_DIER_UIE;           /* Update Event IRQ enabled.    */
	  TIM1->CR1  = TIM_CR1_URS | TIM_CR1_CEN;
}