--       Altera EPLD / PCB / VHDL tools        --
-- (c) Philips Semiconductors Southampton 1996-2001 --

-- by: Mike James (Mike.D.James@philips.com)

-- package version:12.02 Verilog  compiled: May 21 2001--

-- Produced by 'VERTICAL 12.02 Verilog': WRITE ACF (PC-CygWin)
-- at 15:40:08	on 21/05/2001 

COMPONENTS
BEGIN
END;

WIRED_NETS
BEGIN
-- Routed & Named nets follow --

NAMED

-- Routed & unused nets follow --

ROUTED

-- Unrouted nets follow --

UNROUTED

--Top Level
 CONNECTION "A" "" FREE_NAME; -- 0 nodes
 -- partition port=0 in=0 need_buff=0
END_CONN;
--Top Level
 CONNECTION "B" "" FREE_NAME; -- 0 nodes
 -- partition port=0 in=0 need_buff=0
END_CONN;
--Top Level
 CONNECTION "SUM" "" FREE_NAME; -- 0 nodes
 -- partition port=0 in=0 need_buff=0
END_CONN;
END;

-- Jumper list here --
JOINED_NETS
BEGIN
END;

GENERIC -- Generic constants 
  VERTICAL_INIT        :  env_string      := "./vertical.ini"
END;

-- Alias list here --
JOINED_NETS
BEGIN
END;

-- pin renames on unrouted list follow --
-- pin renames on routed list follow   --
-- pin renames on named list follow    --