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 */
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 */
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#include "ch.h"
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#include "ch.h"
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#include "hal.h"
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#include "hal.h"
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#include "hardware.h"
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#include "hardware.h"
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uint16_t timerSamples[timerSampleSize];
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uint8_t timerInIndex;
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uint8_t timerOutIndex;
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void TIM1_UP_IRQHandler(void) {
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void TIM1_UP_IRQHandler(void) {
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// we have an interrupt here .
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// we have an interrupt here .
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        if (TIM1->SR & TIM_SR_CC1IF) {
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                TIM1->SR &= ~TIM_SR_CC1IF;
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                timerSamples[timerInIndex++] = TIM1->CCMR1;
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                if (timerInIndex == timerSampleSize) {
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                        timerInIndex = 0;
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                }
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        }
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}
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}
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void initTimer(void) {
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void initTimer(void) {
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        rccEnableTIM1(FALSE);
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        rccEnableTIM1(FALSE);
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                        CORTEX_PRIORITY_MASK(STM32_GPT_TIM1_IRQ_PRIORITY));
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                        CORTEX_PRIORITY_MASK(STM32_GPT_TIM1_IRQ_PRIORITY));
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        //gptp->clock = STM32_TIMCLK2;
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        //gptp->clock = STM32_TIMCLK2;
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        TIM1->CR1 = 0; /* Initially stopped.           */
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        TIM1->CR1 = 0; /* Initially stopped.           */
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        TIM1->CR2 = TIM_CR2_CCDS; /* DMA on UE (if any).          */
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        TIM1->CR2 = TIM_CR2_CCDS; /* DMA on UE (if any).          */
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        TIM1->PSC = 72; /* Prescaler value.             */
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        TIM1->PSC = 72 * 3; /* Prescaler value : 3 uS tick timer .             */
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        TIM1->DIER = 0;
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        TIM1->DIER = 0;
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}
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}
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void stopTimer(void) {
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void stopTimer(void) {
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        nvicDisableVector(TIM1_UP_IRQn);
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        nvicDisableVector(TIM1_UP_IRQn);
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        rccDisableTIM1(FALSE);
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        rccDisableTIM1(FALSE);
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}
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}
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void startTimer(void) {
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void startTimer(void) {
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          TIM1->ARR  = 12405;           /* Time constant.               */
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          TIM1->ARR  = 0xFFFF;                 /* Time constant.               */
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          TIM1->EGR  = TIM_EGR_UG;             /* Update event.                */
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          TIM1->EGR  = TIM_EGR_UG;             /* Update event.                */
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          TIM1->CNT  = 0;                      /* Reset counter.               */
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          TIM1->CNT  = 0;                      /* Reset counter.               */
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          /* NOTE: After generating the UG event it takes several clock cycles before
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          /* NOTE: After generating the UG event it takes several clock cycles before
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             SR bit 0 goes to 1. This is because the clearing of CNT has been inserted
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             SR bit 0 goes to 1. This is because the clearing of CNT has been inserted
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             before the clearing of SR, to give it some time.*/
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             before the clearing of SR, to give it some time.*/
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          TIM1->SR   = 0;                      /* Clear pending IRQs (if any). */
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          TIM1->SR   = 0;                      /* Clear pending IRQs (if any). */
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          TIM1->DIER = TIM_DIER_UIE;           /* Update Event IRQ enabled.    */
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          TIM1->DIER = TIM_DIER_UIE;           /* Update Event IRQ enabled.    */
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          TIM1->CR1  = TIM_CR1_URS | TIM_CR1_CEN;
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          TIM1->CR1  = TIM_CR1_URS | TIM_CR1_CEN;
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          TIM1->CCMR1 = 3344;
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}
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}