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Rev 6 | Rev 7 | ||
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Line 255... | Line 255... | ||
255 | /* USER CODE BEGIN TIM6_MspInit 0 */ |
255 | /* USER CODE BEGIN TIM6_MspInit 0 */ |
256 | 256 | ||
257 | /* USER CODE END TIM6_MspInit 0 */ |
257 | /* USER CODE END TIM6_MspInit 0 */ |
258 | /* Peripheral clock enable */ |
258 | /* Peripheral clock enable */ |
259 | __HAL_RCC_TIM6_CLK_ENABLE(); |
259 | __HAL_RCC_TIM6_CLK_ENABLE(); |
- | 260 | /* Peripheral interrupt init */ |
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- | 261 | HAL_NVIC_SetPriority(TIM6_IRQn, 0, 0); |
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- | 262 | HAL_NVIC_EnableIRQ(TIM6_IRQn); |
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260 | /* USER CODE BEGIN TIM6_MspInit 1 */ |
263 | /* USER CODE BEGIN TIM6_MspInit 1 */ |
261 | 264 | ||
262 | /* USER CODE END TIM6_MspInit 1 */ |
265 | /* USER CODE END TIM6_MspInit 1 */ |
263 | } |
266 | } |
264 | 267 | ||
Line 331... | Line 334... | ||
331 | /* USER CODE BEGIN TIM6_MspDeInit 0 */ |
334 | /* USER CODE BEGIN TIM6_MspDeInit 0 */ |
332 | 335 | ||
333 | /* USER CODE END TIM6_MspDeInit 0 */ |
336 | /* USER CODE END TIM6_MspDeInit 0 */ |
334 | /* Peripheral clock disable */ |
337 | /* Peripheral clock disable */ |
335 | __HAL_RCC_TIM6_CLK_DISABLE(); |
338 | __HAL_RCC_TIM6_CLK_DISABLE(); |
- | 339 | ||
- | 340 | /* Peripheral interrupt DeInit*/ |
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- | 341 | HAL_NVIC_DisableIRQ(TIM6_IRQn); |
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- | 342 | ||
336 | } |
343 | } |
337 | /* USER CODE BEGIN TIM6_MspDeInit 1 */ |
344 | /* USER CODE BEGIN TIM6_MspDeInit 1 */ |
338 | 345 | ||
339 | /* USER CODE END TIM6_MspDeInit 1 */ |
346 | /* USER CODE END TIM6_MspDeInit 1 */ |
340 | 347 |