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/* USER CODE END 0 */
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/* USER CODE END 0 */
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/* External variables --------------------------------------------------------*/
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/* External variables --------------------------------------------------------*/
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extern DMA_HandleTypeDef hdma_adc;
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extern DMA_HandleTypeDef hdma_adc;
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extern DMA_HandleTypeDef hdma_spi1_tx;
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/* USER CODE BEGIN EV */
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/* USER CODE BEGIN EV */
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/* USER CODE END EV */
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/* USER CODE END EV */
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/******************************************************************************/
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/******************************************************************************/
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/*           Cortex-M0 Processor Interruption and Exception Handlers          */
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/*           Cortex-M0 Processor Interruption and Exception Handlers          */
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/******************************************************************************/
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/******************************************************************************/
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/**
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/**
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  * @brief This function handles Non maskable interrupt.
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  * @brief This function handles Non maskable interrupt.
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  */
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  */
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void NMI_Handler(void)
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void NMI_Handler(void)
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  /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */
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  /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */
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  /* USER CODE END DMA1_Channel1_IRQn 1 */
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  /* USER CODE END DMA1_Channel1_IRQn 1 */
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}
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}
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/**
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  * @brief This function handles DMA1 channel 2 and 3 interrupts.
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  */
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void DMA1_Channel2_3_IRQHandler(void)
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{
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  /* USER CODE BEGIN DMA1_Channel2_3_IRQn 0 */
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  /* USER CODE END DMA1_Channel2_3_IRQn 0 */
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  HAL_DMA_IRQHandler(&hdma_spi1_tx);
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  /* USER CODE BEGIN DMA1_Channel2_3_IRQn 1 */
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  /* USER CODE END DMA1_Channel2_3_IRQn 1 */
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}
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/* USER CODE BEGIN 1 */
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/* USER CODE BEGIN 1 */
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/* USER CODE END 1 */
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/* USER CODE END 1 */
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/