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| 1 | /** |
1 | /** |
| 2 | ****************************************************************************** |
2 | ****************************************************************************** |
| 3 | * @file stm32l1xx_hal_tim_ex.c |
3 | * @file stm32l1xx_hal_tim_ex.c |
| 4 | * @author MCD Application Team |
4 | * @author MCD Application Team |
| 5 | * @version V1.2.0 |
- | |
| 6 | * @date 01-July-2016 |
- | |
| 7 | * @brief TIM HAL module driver. |
5 | * @brief TIM HAL module driver. |
| 8 | * This file provides firmware functions to manage the following |
6 | * This file provides firmware functions to manage the following |
| 9 | * functionalities of the Timer extension peripheral: |
7 | * functionalities of the Timer Extended peripheral: |
| 10 | * + Time Master and Slave synchronization configuration |
8 | * + Time Master and Slave synchronization configuration |
| - | 9 | * + Time OCRef clear configuration |
|
| 11 | * + Timer remapping capabilities configuration |
10 | * + Timer remapping capabilities configuration |
| 12 | @verbatim |
11 | @verbatim |
| 13 | ============================================================================== |
12 | ============================================================================== |
| 14 | ##### TIMER Extended features ##### |
13 | ##### TIMER Extended features ##### |
| 15 | ============================================================================== |
14 | ============================================================================== |
| 16 | [..] |
15 | [..] |
| 17 | The Timer Extension features include: |
16 | The Timer Extended features include: |
| 18 | (#) Synchronization circuit to control the timer with external signals and to |
17 | (#) Synchronization circuit to control the timer with external signals and to |
| 19 | interconnect several timers together. |
18 | interconnect several timers together. |
| 20 | (#) Timer remapping capabilities configuration |
- | |
| 21 | 19 | ||
| 22 | @endverbatim |
20 | @endverbatim |
| 23 | ****************************************************************************** |
21 | ****************************************************************************** |
| 24 | * @attention |
22 | * @attention |
| 25 | * |
23 | * |
| 26 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
24 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
| - | 25 | * All rights reserved.</center></h2> |
|
| 27 | * |
26 | * |
| 28 | * Redistribution and use in source and binary forms, with or without modification, |
27 | * This software component is licensed by ST under BSD 3-Clause license, |
| 29 | * are permitted provided that the following conditions are met: |
28 | * the "License"; You may not use this file except in compliance with the |
| 30 | * 1. Redistributions of source code must retain the above copyright notice, |
- | |
| 31 | * this list of conditions and the following disclaimer. |
- | |
| 32 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
- | |
| 33 | * this list of conditions and the following disclaimer in the documentation |
- | |
| 34 | * and/or other materials provided with the distribution. |
29 | * License. You may obtain a copy of the License at: |
| 35 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
- | |
| 36 | * may be used to endorse or promote products derived from this software |
30 | * opensource.org/licenses/BSD-3-Clause |
| 37 | * without specific prior written permission. |
- | |
| 38 | * |
- | |
| 39 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
- | |
| 40 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
- | |
| 41 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
- | |
| 42 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
- | |
| 43 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
- | |
| 44 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
- | |
| 45 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
- | |
| 46 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
- | |
| 47 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
- | |
| 48 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
- | |
| 49 | * |
31 | * |
| 50 | ****************************************************************************** |
32 | ****************************************************************************** |
| 51 | */ |
33 | */ |
| 52 | 34 | ||
| 53 | /* Includes ------------------------------------------------------------------*/ |
35 | /* Includes ------------------------------------------------------------------*/ |
| 54 | #include "stm32l1xx_hal.h" |
36 | #include "stm32l1xx_hal.h" |
| 55 | 37 | ||
| 56 | /** @addtogroup STM32L1xx_HAL_Driver |
38 | /** @addtogroup STM32L1xx_HAL_Driver |
| Line 64... | Line 46... | ||
| 64 | 46 | ||
| 65 | #ifdef HAL_TIM_MODULE_ENABLED |
47 | #ifdef HAL_TIM_MODULE_ENABLED |
| 66 | 48 | ||
| 67 | /* Private typedef -----------------------------------------------------------*/ |
49 | /* Private typedef -----------------------------------------------------------*/ |
| 68 | /* Private define ------------------------------------------------------------*/ |
50 | /* Private define ------------------------------------------------------------*/ |
| 69 | /* Private macro -------------------------------------------------------------*/ |
51 | /* Private macros ------------------------------------------------------------*/ |
| 70 | /* Private variables ---------------------------------------------------------*/ |
52 | /* Private variables ---------------------------------------------------------*/ |
| 71 | /* Private function prototypes -----------------------------------------------*/ |
53 | /* Private function prototypes -----------------------------------------------*/ |
| 72 | /* Private functions ---------------------------------------------------------*/ |
- | |
| 73 | - | ||
| 74 | /* Exported functions ---------------------------------------------------------*/ |
- | |
| 75 | 54 | ||
| - | 55 | /* Exported functions --------------------------------------------------------*/ |
|
| 76 | /** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions |
56 | /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions |
| 77 | * @{ |
57 | * @{ |
| 78 | */ |
58 | */ |
| 79 | - | ||
| 80 | /** @defgroup TIMEx_Exported_Functions_Group1 Peripheral Control functions |
59 | /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions |
| 81 | * @brief Peripheral Control functions |
60 | * @brief Peripheral Control functions |
| 82 | * |
61 | * |
| 83 | @verbatim |
62 | @verbatim |
| 84 | ============================================================================== |
63 | ============================================================================== |
| 85 | ##### Peripheral Control functions ##### |
64 | ##### Peripheral Control functions ##### |
| 86 | ============================================================================== |
65 | ============================================================================== |
| 87 | [..] |
66 | [..] |
| 88 | This section provides functions allowing to: |
67 | This section provides functions allowing to: |
| 89 | (+)Configure Master synchronization. |
68 | (+) Configure Master synchronization. |
| 90 | (+) Configure timer remapping capabilities. |
69 | (+) Configure timer remapping capabilities. |
| 91 | 70 | ||
| 92 | @endverbatim |
71 | @endverbatim |
| 93 | * @{ |
72 | * @{ |
| 94 | */ |
73 | */ |
| 95 | 74 | ||
| 96 | /** |
75 | /** |
| 97 | * @brief Configures the TIM in master mode. |
76 | * @brief Configures the TIM in master mode. |
| 98 | * @param htim: TIM handle. |
77 | * @param htim TIM handle. |
| 99 | * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that |
78 | * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that |
| 100 | * contains the selected trigger output (TRGO) and the Master/Slave |
79 | * contains the selected trigger output (TRGO) and the Master/Slave |
| 101 | * mode. |
80 | * mode. |
| 102 | * @retval HAL status |
81 | * @retval HAL status |
| 103 | */ |
82 | */ |
| 104 | HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig) |
83 | HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, |
| - | 84 | TIM_MasterConfigTypeDef *sMasterConfig) |
|
| 105 | { |
85 | { |
| - | 86 | uint32_t tmpcr2; |
|
| - | 87 | uint32_t tmpsmcr; |
|
| - | 88 | ||
| 106 | /* Check the parameters */ |
89 | /* Check the parameters */ |
| 107 | assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); |
90 | assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); |
| 108 | assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); |
91 | assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); |
| 109 | assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); |
92 | assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); |
| 110 | 93 | ||
| - | 94 | /* Check input state */ |
|
| 111 | __HAL_LOCK(htim); |
95 | __HAL_LOCK(htim); |
| 112 | 96 | ||
| - | 97 | /* Change the handler state */ |
|
| 113 | htim->State = HAL_TIM_STATE_BUSY; |
98 | htim->State = HAL_TIM_STATE_BUSY; |
| 114 | 99 | ||
| - | 100 | /* Get the TIMx CR2 register value */ |
|
| - | 101 | tmpcr2 = htim->Instance->CR2; |
|
| - | 102 | ||
| - | 103 | /* Get the TIMx SMCR register value */ |
|
| - | 104 | tmpsmcr = htim->Instance->SMCR; |
|
| - | 105 | ||
| 115 | /* Reset the MMS Bits */ |
106 | /* Reset the MMS Bits */ |
| 116 | htim->Instance->CR2 &= ~TIM_CR2_MMS; |
107 | tmpcr2 &= ~TIM_CR2_MMS; |
| 117 | /* Select the TRGO source */ |
108 | /* Select the TRGO source */ |
| 118 | htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger; |
109 | tmpcr2 |= sMasterConfig->MasterOutputTrigger; |
| - | 110 | ||
| - | 111 | /* Update TIMx CR2 */ |
|
| - | 112 | htim->Instance->CR2 = tmpcr2; |
|
| 119 | 113 | ||
| - | 114 | if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) |
|
| - | 115 | { |
|
| 120 | /* Reset the MSM Bit */ |
116 | /* Reset the MSM Bit */ |
| 121 | htim->Instance->SMCR &= ~TIM_SMCR_MSM; |
117 | tmpsmcr &= ~TIM_SMCR_MSM; |
| 122 | /* Set or Reset the MSM Bit */ |
118 | /* Set master mode */ |
| 123 | htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode; |
119 | tmpsmcr |= sMasterConfig->MasterSlaveMode; |
| - | 120 | ||
| - | 121 | /* Update TIMx SMCR */ |
|
| - | 122 | htim->Instance->SMCR = tmpsmcr; |
|
| - | 123 | } |
|
| 124 | 124 | ||
| - | 125 | /* Change the htim state */ |
|
| 125 | htim->State = HAL_TIM_STATE_READY; |
126 | htim->State = HAL_TIM_STATE_READY; |
| 126 | 127 | ||
| 127 | __HAL_UNLOCK(htim); |
128 | __HAL_UNLOCK(htim); |
| 128 | 129 | ||
| 129 | return HAL_OK; |
130 | return HAL_OK; |
| 130 | } |
131 | } |
| 131 | 132 | ||
| 132 | /** |
133 | /** |
| 133 | * @brief Configures the TIM2/TIM3/TIM9/TIM10/TIM11 Remapping input capabilities. |
134 | * @brief Configures the TIMx Remapping input capabilities. |
| 134 | * @param htim: TIM handle. |
135 | * @param htim TIM handle. |
| 135 | * @param Remap: specifies the TIM remapping source. |
136 | * @param Remap specifies the TIM remapping source. |
| 136 | * This parameter is a combination of the following values depending on TIM instance. |
- | |
| 137 | * @retval HAL status |
- | |
| 138 | * |
137 | * |
| 139 | * @note For TIM2, the parameter can have the following values: |
138 | * For TIM2, the parameter can have the following values:(see note) |
| 140 | * @arg TIM_TIM2_ITR1_TIM10_OC: TIM2 ITR1 input is connected to TIM10 OC |
139 | * @arg TIM_TIM2_ITR1_TIM10_OC: TIM2 ITR1 input is connected to TIM10 OC |
| 141 | * @arg TIM_TIM2_ITR1_TIM5_TGO: TIM2 ITR1 input is connected to TIM5 TGO |
140 | * @arg TIM_TIM2_ITR1_TIM5_TGO: TIM2 ITR1 input is connected to TIM5 TGO |
| 142 | * |
141 | * |
| 143 | * @note For TIM3, the parameter can have the following values: |
142 | * For TIM3, the parameter can have the following values:(see note) |
| 144 | * @arg TIM_TIM3_ITR2_TIM11_OC: TIM3 ITR2 input is connected to TIM11 OC |
143 | * @arg TIM_TIM3_ITR2_TIM11_OC: TIM3 ITR2 input is connected to TIM11 OC |
| 145 | * @arg TIM_TIM3_ITR2_TIM5_TGO: TIM3 ITR2 input is connected to TIM5 TGO |
144 | * @arg TIM_TIM3_ITR2_TIM5_TGO: TIM3 ITR2 input is connected to TIM5 TGO |
| 146 | * |
145 | * |
| 147 | * @note For TIM9, the parameter is a combination of 2 fields (field1 | field2): |
146 | * For TIM9, the parameter is a combination of 2 fields (field1 | field2): |
| - | 147 | * |
|
| 148 | * @note For TIM9, the field1 can have the following values: |
148 | * field1 can have the following values:(see note) |
| 149 | * @arg TIM_TIM9_ITR1_TIM3_TGO: TIM9 ITR1 input is connected to TIM3 TGO |
149 | * @arg TIM_TIM9_ITR1_TIM3_TGO: TIM9 ITR1 input is connected to TIM3 TGO |
| 150 | * @arg TIM_TIM9_ITR1_TS: TIM9 ITR1 input is connected to touch sensing I/O |
150 | * @arg TIM_TIM9_ITR1_TS: TIM9 ITR1 input is connected to touch sensing I/O |
| - | 151 | * |
|
| 151 | * @note For TIM9, the field2 can have the following values: |
152 | * field2 can have the following values: |
| 152 | * @arg TIM_TIM9_GPIO: TIM9 Channel1 is connected to GPIO |
153 | * @arg TIM_TIM9_GPIO: TIM9 Channel1 is connected to GPIO |
| 153 | * @arg TIM_TIM9_LSE: TIM9 Channel1 is connected to LSE internal clock |
154 | * @arg TIM_TIM9_LSE: TIM9 Channel1 is connected to LSE internal clock |
| 154 | * @arg TIM_TIM9_GPIO1: TIM9 Channel1 is connected to GPIO |
155 | * @arg TIM_TIM9_GPIO1: TIM9 Channel1 is connected to GPIO |
| 155 | * @arg TIM_TIM9_GPIO2: TIM9 Channel1 is connected to GPIO |
156 | * @arg TIM_TIM9_GPIO2: TIM9 Channel1 is connected to GPIO |
| 156 | * |
157 | * |
| 157 | * @note For TIM10, the parameter is a combination of 3 fields (field1 | field2 | field3): |
158 | * For TIM10, the parameter is a combination of 3 fields (field1 | field2 | field3): |
| - | 159 | * |
|
| 158 | * @note For TIM10, the field1 can have the following values: |
160 | * field1 can have the following values:(see note) |
| 159 | * @arg TIM_TIM10_TI1RMP: TIM10 Channel 1 depends on TI1_RMP |
161 | * @arg TIM_TIM10_TI1RMP: TIM10 Channel 1 depends on TI1_RMP |
| 160 | * @arg TIM_TIM10_RI: TIM10 Channel 1 is connected to RI |
162 | * @arg TIM_TIM10_RI: TIM10 Channel 1 is connected to RI |
| - | 163 | * |
|
| 161 | * @note For TIM10, the field2 can have the following values: |
164 | * field2 can have the following values:(see note) |
| 162 | * @arg TIM_TIM10_ETR_LSE: TIM10 ETR input is connected to LSE clock |
165 | * @arg TIM_TIM10_ETR_LSE: TIM10 ETR input is connected to LSE clock |
| 163 | * @arg TIM_TIM10_ETR_TIM9_TGO: TIM10 ETR input is connected to TIM9 TGO |
166 | * @arg TIM_TIM10_ETR_TIM9_TGO: TIM10 ETR input is connected to TIM9 TGO |
| - | 167 | * |
|
| 164 | * @note For TIM10, the field3 can have the following values: |
168 | * field3 can have the following values: |
| 165 | * @arg TIM_TIM10_GPIO: TIM10 Channel1 is connected to GPIO |
169 | * @arg TIM_TIM10_GPIO: TIM10 Channel1 is connected to GPIO |
| 166 | * @arg TIM_TIM10_LSI: TIM10 Channel1 is connected to LSI internal clock |
170 | * @arg TIM_TIM10_LSI: TIM10 Channel1 is connected to LSI internal clock |
| 167 | * @arg TIM_TIM10_LSE: TIM10 Channel1 is connected to LSE internal clock |
171 | * @arg TIM_TIM10_LSE: TIM10 Channel1 is connected to LSE internal clock |
| 168 | * @arg TIM_TIM10_RTC: TIM10 Channel1 is connected to RTC wakeup interrupt |
172 | * @arg TIM_TIM10_RTC: TIM10 Channel1 is connected to RTC wakeup interrupt |
| 169 | * |
173 | * |
| 170 | * @note For TIM11, the parameter is a combination of 3 fields (field1 | field2 | field3): |
174 | * For TIM11, the parameter is a combination of 3 fields (field1 | field2 | field3): |
| - | 175 | * |
|
| 171 | * @note For TIM11, the field1 can have the following values: |
176 | * field1 can have the following values:(see note) |
| 172 | * @arg TIM_TIM11_TI1RMP: TIM11 Channel 1 depends on TI1_RMP |
177 | * @arg TIM_TIM11_TI1RMP: TIM11 Channel 1 depends on TI1_RMP |
| 173 | * @arg TIM_TIM11_RI: TIM11 Channel 1 is connected to RI |
178 | * @arg TIM_TIM11_RI: TIM11 Channel 1 is connected to RI |
| - | 179 | * |
|
| 174 | * @note For TIM11, the field2 can have the following values: |
180 | * field2 can have the following values:(see note) |
| 175 | * @arg TIM_TIM11_ETR_LSE: TIM11 ETR input is connected to LSE clock |
181 | * @arg TIM_TIM11_ETR_LSE: TIM11 ETR input is connected to LSE clock |
| 176 | * @arg TIM_TIM11_ETR_TIM9_TGO: TIM11 ETR input is connected to TIM9 TGO |
182 | * @arg TIM_TIM11_ETR_TIM9_TGO: TIM11 ETR input is connected to TIM9 TGO |
| - | 183 | * |
|
| 177 | * @note For TIM11, the field3 can have the following values: |
184 | * field3 can have the following values: |
| 178 | * @arg TIM_TIM11_GPIO: TIM11 Channel1 is connected to GPIO |
185 | * @arg TIM_TIM11_GPIO: TIM11 Channel1 is connected to GPIO |
| 179 | * @arg TIM_TIM11_MSI: TIM11 Channel1 is connected to MSI internal clock |
186 | * @arg TIM_TIM11_MSI: TIM11 Channel1 is connected to MSI internal clock |
| 180 | * @arg TIM_TIM11_HSE_RTC: TIM11 Channel1 is connected to HSE_RTC clock |
187 | * @arg TIM_TIM11_HSE_RTC: TIM11 Channel1 is connected to HSE_RTC clock |
| 181 | * @arg TIM_TIM11_GPIO1: TIM11 Channel1 is connected to GPIO |
188 | * @arg TIM_TIM11_GPIO1: TIM11 Channel1 is connected to GPIO |
| 182 | * |
189 | * |
| - | 190 | * @note Available only in Cat.3, Cat.4,Cat.5 and Cat.6 devices. |
|
| - | 191 | * |
|
| - | 192 | * @retval HAL status |
|
| 183 | */ |
193 | */ |
| 184 | HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) |
194 | HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) |
| 185 | { |
195 | { |
| 186 | __HAL_LOCK(htim); |
196 | __HAL_LOCK(htim); |
| 187 | 197 | ||
| 188 | /* Check parameters */ |
198 | /* Check parameters */ |
| 189 | assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance)); |
- | |
| 190 | assert_param(IS_TIM_REMAP(htim->Instance,Remap)); |
199 | assert_param(IS_TIM_REMAP(htim->Instance, Remap)); |
| 191 | 200 | ||
| 192 | /* Set the Timer remapping configuration */ |
201 | /* Set the Timer remapping configuration */ |
| 193 | htim->Instance->OR = Remap; |
202 | WRITE_REG(htim->Instance->OR, Remap); |
| 194 | - | ||
| 195 | htim->State = HAL_TIM_STATE_READY; |
- | |
| 196 | 203 | ||
| 197 | __HAL_UNLOCK(htim); |
204 | __HAL_UNLOCK(htim); |
| 198 | 205 | ||
| 199 | return HAL_OK; |
206 | return HAL_OK; |
| 200 | } |
207 | } |
| 201 | 208 | ||
| 202 | /** |
209 | /** |
| 203 | * @} |
210 | * @} |
| 204 | */ |
211 | */ |
| 205 | 212 | ||
| 206 | #endif /* HAL_TIM_MODULE_ENABLED */ |
- | |
| 207 | /** |
213 | /** |
| 208 | * @} |
214 | * @} |
| 209 | */ |
215 | */ |
| 210 | 216 | ||
| - | 217 | ||
| - | 218 | #endif /* HAL_TIM_MODULE_ENABLED */ |
|
| 211 | /** |
219 | /** |
| 212 | * @} |
220 | * @} |
| 213 | */ |
221 | */ |
| 214 | 222 | ||
| 215 | /** |
223 | /** |