WebSVN – EngineBay2 – Diff – /trunk/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c

 /**
   ******************************************************************************
   * @file    stm32l1xx_hal_flash_ramfunc.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   FLASH RAMFUNC driver.
   *          This file provides a Flash firmware functions which should be
   *          executed from internal SRAM
+  *
   *  @verbatim
 @endverbatim
   ******************************************************************************
   * @attention
+  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
-  * Redistribution and use in source and binary forms, with or without modification,
+  * This software component is licensed by ST under BSD 3-Clause license,
-  * are permitted provided that the following conditions are met:
+  * the "License"; You may not use this file except in compliance with the
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
+  * License. You may obtain a copy of the License at:
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
+  *                        opensource.org/licenses/BSD-3-Clause
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
   ******************************************************************************
   */
 /* Includes ------------------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
 /** @defgroup FLASH_RAMFUNC_Private_Functions FLASH RAM Private Functions
  * @{
  */
-static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout);
+static __RAM_FUNC HAL_StatusTypeDef FLASHRAM_WaitForLastOperation(uint32_t Timeout);
-static __RAM_FUNC FLASHRAM_SetErrorCode(void);
+static __RAM_FUNC HAL_StatusTypeDef FLASHRAM_SetErrorCode(void);
 /**
   * @}
   */
 /**
   * @brief  Enable  the power down mode during RUN mode.
   * @note  This function can be used only when the user code is running from Internal SRAM.
   * @retval HAL status
   */
-__RAM_FUNC HAL_FLASHEx_EnableRunPowerDown(void)
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void)
+{
   /* Enable the Power Down in Run mode*/
   __HAL_FLASH_POWER_DOWN_ENABLE();
   return HAL_OK;
 /**
   * @brief  Disable the power down mode during RUN mode.
   * @note  This function can be used only when the user code is running from Internal SRAM.
   * @retval HAL status
   */
-__RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void)
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void)
+{
   /* Disable the Power Down in Run mode*/
   __HAL_FLASH_POWER_DOWN_DISABLE();
   return HAL_OK;
   *         and FLASH_BANK2_END.
   * @note   A Page is erased in the Program memory only if the address to load
   *         is the start address of a page (multiple of @ref FLASH_PAGE_SIZE bytes).
   * @retval HAL status
   */
-__RAM_FUNC HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2)
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2)
+{
   HAL_StatusTypeDef status = HAL_OK;
   /* Wait for last operation to be completed */
   status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
     SET_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);
     SET_BIT(FLASH->PECR, FLASH_PECR_ERASE);
     SET_BIT(FLASH->PECR, FLASH_PECR_PROG);
     /* Write 00000000h to the first word of the first program page to erase */
-    *(__IO uint32_t *)Page_Address1 = 0x00000000;
+    *(__IO uint32_t *)Page_Address1 = 0x00000000U;
     /* Write 00000000h to the first word of the second program page to erase */
-    *(__IO uint32_t *)Page_Address2 = 0x00000000;
+    *(__IO uint32_t *)Page_Address2 = 0x00000000U;
     /* Wait for last operation to be completed */
     status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
     /* If the erase operation is completed, disable the ERASE, PROG and PARALLBANK bits */
   *         complete write operation is aborted. Software should then reset the
   *         FPRG and PROG/DATA bits and restart the write operation from the
   *         beginning.
   * @retval HAL status
   */
-__RAM_FUNC HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2)
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2)
+{
+  uint32_t primask_bit;
-  uint32_t count = 0;
+  uint32_t count = 0U;
   HAL_StatusTypeDef status = HAL_OK;
-  /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008)
-     This bit prevents the interruption of multicycle instructions and therefore
-     will increase the interrupt latency. of Cortex-M3. */
-  SET_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk);
   /* Wait for last operation to be completed */
   status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
   if(status == HAL_OK)
+  {
+    /* Disable all IRQs */
+    primask_bit = __get_PRIMASK();
+    __disable_irq();
     /* Proceed to program the new half page */
     SET_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);
     SET_BIT(FLASH->PECR, FLASH_PECR_FPRG);
     SET_BIT(FLASH->PECR, FLASH_PECR_PROG);
-    /* Wait for last operation to be completed */
+    /* Write the first half page directly with 32 different words */
-    status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-    if(status == HAL_OK)
+    while(count < 32U)
+    {
-      /* Disable all IRQs */
-      __disable_irq();
-      /* Write the first half page directly with 32 different words */
-      while(count < 32)
-      {
-        *(__IO uint32_t*) ((uint32_t)(Address1 + (4 * count))) = *pBuffer1;
+      *(__IO uint32_t*) ((uint32_t)(Address1 + (4 * count))) = *pBuffer1;
-        pBuffer1++;
+      pBuffer1++;
-        count ++;
-      }
-      /* Write the second half page directly with 32 different words */
-      count = 0;
-      while(count < 32)
-      {
-        *(__IO uint32_t*) ((uint32_t)(Address2 + (4 * count))) = *pBuffer2;
-        pBuffer2++;
-        count ++;
+      count ++;
-      }
-      /* Enable IRQs */
-      __enable_irq();
-      /* Wait for last operation to be completed */
-      status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
+    }
+    /* Write the second half page directly with 32 different words */
+    count = 0U;
+    while(count < 32U)
+    {
+      *(__IO uint32_t*) ((uint32_t)(Address2 + (4 * count))) = *pBuffer2;
+      pBuffer2++;
+      count ++;
+    }
+    /* Wait for last operation to be completed */
+    status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
     /* if the write operation is completed, disable the PROG, FPRG and PARALLBANK bits */
     CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
     CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG);
     CLEAR_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);
+    /* Enable IRQs */
+    __set_PRIMASK(primask_bit);
+  }
-  CLEAR_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk);
   /* Return the Write Status */
   return status;
+}
 #endif /* FLASH_PECR_PARALLBANK */
 /**
   * @brief  Program a half page in program memory.
-  * @param  Address: specifies the address to be written.
+  * @param  Address specifies the address to be written.
-  * @param  pBuffer: pointer to the buffer  containing the data to be  written to
+  * @param  pBuffer pointer to the buffer  containing the data to be  written to
   *         the half page.
   * @note   To correctly run this function, the @ref HAL_FLASH_Unlock() function
   *         must be called before.
   *         Call the @ref HAL_FLASH_Lock() to disable the flash memory access
   *         (recommended to protect the FLASH memory against possible unwanted operation)
   *         complete write operation is aborted. Software should then reset the
   *         FPRG and PROG/DATA bits and restart the write operation from the
   *         beginning.
   * @retval HAL status
   */
-__RAM_FUNC HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer)
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer)
+{
+  uint32_t primask_bit;
-  uint32_t count = 0;
+  uint32_t count = 0U;
   HAL_StatusTypeDef status = HAL_OK;
-  /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008)
-     This bit prevents the interruption of multicycle instructions and therefore
-     will increase the interrupt latency. of Cortex-M3. */
-  SET_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk);
   /* Wait for last operation to be completed */
   status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
   if(status == HAL_OK)
+  {
+    /* Disable all IRQs */
+    primask_bit = __get_PRIMASK();
+    __disable_irq();
     /* Proceed to program the new half page */
     SET_BIT(FLASH->PECR, FLASH_PECR_FPRG);
     SET_BIT(FLASH->PECR, FLASH_PECR_PROG);
-    /* Disable all IRQs */
-    __disable_irq();
     /* Write one half page directly with 32 different words */
-    while(count < 32)
+    while(count < 32U)
+    {
       *(__IO uint32_t*) ((uint32_t)(Address + (4 * count))) = *pBuffer;
       pBuffer++;
       count ++;
+    }
-    /* Enable IRQs */
-    __enable_irq();
     /* Wait for last operation to be completed */
     status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
     /* If the write operation is completed, disable the PROG and FPRG bits */
     CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
     CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG);
-  }
+    /* Enable IRQs */
-  CLEAR_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk);
+    __set_PRIMASK(primask_bit);
+  }
   /* Return the Write Status */
   return status;
+}
 /**
   *            @arg @ref HAL_FLASH_ERROR_PGA     FLASH Programming Alignment error flag
   *            @arg @ref HAL_FLASH_ERROR_WRP     FLASH Write protected error flag
   *            @arg @ref HAL_FLASH_ERROR_OPTV    FLASH Option valid error flag
   * @retval HAL Status
   */
-__RAM_FUNC HAL_FLASHEx_GetError(uint32_t * Error)
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_GetError(uint32_t * Error)
+{
   *Error = pFlash.ErrorCode;
   return HAL_OK;
+}
   * @{
   */
 /**
   * @brief  Erase a double word in data memory.
-  * @param  Address: specifies the address to be erased.
+  * @param  Address specifies the address to be erased.
   * @note   To correctly run this function, the HAL_FLASH_EEPROM_Unlock() function
   *         must be called before.
   *         Call the HAL_FLASH_EEPROM_Lock() to he data EEPROM access
   *         and Flash program erase control register access(recommended to protect
   *         the DATA_EEPROM against possible unwanted operation).
   *         forbidden (this includes DMA read operations and debugger read
   *         operations such as breakpoints, periodic updates, etc.).
   * @retval HAL status
   */
-__RAM_FUNC HAL_FLASHEx_DATAEEPROM_EraseDoubleWord(uint32_t Address)
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_EraseDoubleWord(uint32_t Address)
+{
+  uint32_t primask_bit;
   HAL_StatusTypeDef status = HAL_OK;
-  /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008)
-     This bit prevents the interruption of multicycle instructions and therefore
-     will increase the interrupt latency. of Cortex-M3. */
-  SET_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk);
   /* Wait for last operation to be completed */
   status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
   if(status == HAL_OK)
+  {
+    /* Disable all IRQs */
+    primask_bit = __get_PRIMASK();
+    __disable_irq();
     /* If the previous operation is completed, proceed to erase the next double word */
     /* Set the ERASE bit */
     SET_BIT(FLASH->PECR, FLASH_PECR_ERASE);
     /* Set DATA bit */
     SET_BIT(FLASH->PECR, FLASH_PECR_DATA);
     /* Write 00000000h to the 2 words to erase */
-    *(__IO uint32_t *)Address = 0x00000000;
+    *(__IO uint32_t *)Address = 0x00000000U;
-    Address += 4;
+    Address += 4U;
-    *(__IO uint32_t *)Address = 0x00000000;
+    *(__IO uint32_t *)Address = 0x00000000U;
     /* Wait for last operation to be completed */
     status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
     /* If the erase operation is completed, disable the ERASE and DATA bits */
     CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE);
     CLEAR_BIT(FLASH->PECR, FLASH_PECR_DATA);
+    /* Enable IRQs */
+    __set_PRIMASK(primask_bit);
+  }
-  CLEAR_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk);
   /* Return the erase status */
   return status;
+}
 /**
   * @brief  Write a double word in data memory without erase.
-  * @param  Address: specifies the address to be written.
+  * @param  Address specifies the address to be written.
-  * @param  Data: specifies the data to be written.
+  * @param  Data specifies the data to be written.
   * @note   To correctly run this function, the HAL_FLASH_EEPROM_Unlock() function
   *         must be called before.
   *         Call the HAL_FLASH_EEPROM_Lock() to he data EEPROM access
   *         and Flash program erase control register access(recommended to protect
   *         the DATA_EEPROM against possible unwanted operation).
   * @note   During the Data memory double word write, all read operations are
   *         forbidden (this includes DMA read operations and debugger read
   *         operations such as breakpoints, periodic updates, etc.).
   * @retval HAL status
   */
-__RAM_FUNC HAL_FLASHEx_DATAEEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data)
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data)
+{
+  uint32_t primask_bit;
   HAL_StatusTypeDef status = HAL_OK;
-  /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008)
-     This bit prevents the interruption of multicycle instructions and therefore
-     will increase the interrupt latency. of Cortex-M3. */
-  SET_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk);
   /* Wait for last operation to be completed */
   status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
   if(status == HAL_OK)
+  {
+    /* Disable all IRQs */
+    primask_bit = __get_PRIMASK();
+    __disable_irq();
     /* If the previous operation is completed, proceed to program the new data*/
     SET_BIT(FLASH->PECR, FLASH_PECR_FPRG);
     SET_BIT(FLASH->PECR, FLASH_PECR_DATA);
     /* Write the 2 words */
      *(__IO uint32_t *)Address = (uint32_t) Data;
-     Address += 4;
+     Address += 4U;
      *(__IO uint32_t *)Address = (uint32_t) (Data >> 32);
     /* Wait for last operation to be completed */
     status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
     /* If the write operation is completed, disable the FPRG and DATA bits */
     CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG);
     CLEAR_BIT(FLASH->PECR, FLASH_PECR_DATA);
+    /* Enable IRQs */
+    __set_PRIMASK(primask_bit);
+  }
-  CLEAR_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk);
   /* Return the Write Status */
   return status;
+}
 /**
 /**
   * @brief  Set the specific FLASH error flag.
   * @retval HAL Status
   */
-static __RAM_FUNC FLASHRAM_SetErrorCode(void)
+static __RAM_FUNC HAL_StatusTypeDef FLASHRAM_SetErrorCode(void)
+{
-  uint32_t flags = 0;
+  uint32_t flags = 0U;
   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
+  {
     pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
     flags |= FLASH_FLAG_WRPERR;
   return HAL_OK;
+}
 /**
   * @brief  Wait for a FLASH operation to complete.
-  * @param  Timeout: maximum flash operationtimeout
+  * @param  Timeout maximum flash operationtimeout
   * @retval HAL status
   */
-static __RAM_FUNC  FLASHRAM_WaitForLastOperation(uint32_t Timeout)
+static __RAM_FUNC HAL_StatusTypeDef FLASHRAM_WaitForLastOperation(uint32_t Timeout)
+{
     /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
        Even if the FLASH operation fails, the BUSY flag will be reset and an error
        flag will be set */
-    while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) && (Timeout != 0x00))
+    while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) && (Timeout != 0x00U))
+    {
       Timeout--;
+    }
-    if(Timeout == 0x00 )
+    if(Timeout == 0x00U)
+    {
       return HAL_TIMEOUT;
+    }
   /* Check FLASH End of Operation flag  */

Subversion Repositories EngineBay2

(root)/trunk/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c – Rev 2 → 28