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| 1 | /** |
1 | /** |
| 2 | ****************************************************************************** |
2 | ****************************************************************************** |
| 3 | * @file stm32l1xx_hal_rcc_ex.h |
3 | * @file stm32l1xx_hal_rcc_ex.h |
| 4 | * @author MCD Application Team |
4 | * @author MCD Application Team |
| 5 | * @version V1.2.0 |
- | |
| 6 | * @date 01-July-2016 |
- | |
| 7 | * @brief Header file of RCC HAL Extension module. |
5 | * @brief Header file of RCC HAL Extension module. |
| 8 | ****************************************************************************** |
6 | ****************************************************************************** |
| 9 | * @attention |
7 | * @attention |
| 10 | * |
8 | * |
| 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
9 | * <h2><center>© Copyright(c) 2017 STMicroelectronics. |
| - | 10 | * All rights reserved.</center></h2> |
|
| 12 | * |
11 | * |
| 13 | * Redistribution and use in source and binary forms, with or without modification, |
12 | * This software component is licensed by ST under BSD 3-Clause license, |
| 14 | * are permitted provided that the following conditions are met: |
13 | * the "License"; You may not use this file except in compliance with the |
| 15 | * 1. Redistributions of source code must retain the above copyright notice, |
- | |
| 16 | * this list of conditions and the following disclaimer. |
- | |
| 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
- | |
| 18 | * this list of conditions and the following disclaimer in the documentation |
- | |
| 19 | * and/or other materials provided with the distribution. |
14 | * License. You may obtain a copy of the License at: |
| 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
- | |
| 21 | * may be used to endorse or promote products derived from this software |
15 | * opensource.org/licenses/BSD-3-Clause |
| 22 | * without specific prior written permission. |
- | |
| 23 | * |
- | |
| 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
- | |
| 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
- | |
| 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
- | |
| 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
- | |
| 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
- | |
| 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
- | |
| 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
- | |
| 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
- | |
| 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
- | |
| 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
- | |
| 34 | * |
16 | * |
| 35 | ****************************************************************************** |
17 | ****************************************************************************** |
| 36 | */ |
18 | */ |
| 37 | 19 | ||
| 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| Line 50... | Line 32... | ||
| 50 | * @{ |
32 | * @{ |
| 51 | */ |
33 | */ |
| 52 | 34 | ||
| 53 | /** @addtogroup RCCEx |
35 | /** @addtogroup RCCEx |
| 54 | * @{ |
36 | * @{ |
| 55 | */ |
37 | */ |
| 56 | 38 | ||
| 57 | /** @addtogroup RCCEx_Private_Constants |
39 | /** @addtogroup RCCEx_Private_Constants |
| 58 | * @{ |
40 | * @{ |
| 59 | */ |
41 | */ |
| 60 | 42 | ||
| 61 | #define LSI_VALUE ((uint32_t)37000) /* ~37kHz */ |
- | |
| 62 | - | ||
| 63 | #if defined(STM32L100xBA) || defined(STM32L151xBA) || defined(STM32L152xBA)\ |
43 | #if defined(STM32L100xBA) || defined(STM32L151xBA) || defined(STM32L152xBA)\ |
| 64 | || defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ |
44 | || defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ |
| 65 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
45 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
| 66 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
46 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
| 67 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX)\ |
47 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX)\ |
| 68 | || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) |
48 | || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) |
| 69 | 49 | ||
| 70 | /* Alias word address of LSECSSON bit */ |
50 | /* Alias word address of LSECSSON bit */ |
| 71 | #define LSECSSON_BITNUMBER POSITION_VAL(RCC_CSR_LSECSSON) |
51 | #define LSECSSON_BITNUMBER RCC_CSR_LSECSSON_Pos |
| 72 | #define CSR_LSECSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSECSSON_BITNUMBER * 4))) |
52 | #define CSR_LSECSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (LSECSSON_BITNUMBER * 4U))) |
| 73 | 53 | ||
| 74 | #endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX*/ |
54 | #endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX*/ |
| 75 | 55 | ||
| 76 | /** |
56 | /** |
| 77 | * @} |
57 | * @} |
| Line 92... | Line 72... | ||
| 92 | 72 | ||
| 93 | /** |
73 | /** |
| 94 | * @} |
74 | * @} |
| 95 | */ |
75 | */ |
| 96 | 76 | ||
| 97 | /* Exported types ------------------------------------------------------------*/ |
77 | /* Exported types ------------------------------------------------------------*/ |
| 98 | 78 | ||
| 99 | /** @defgroup RCCEx_Exported_Types RCCEx Exported Types |
79 | /** @defgroup RCCEx_Exported_Types RCCEx Exported Types |
| 100 | * @{ |
80 | * @{ |
| 101 | */ |
81 | */ |
| 102 | 82 | ||
| 103 | /** |
83 | /** |
| 104 | * @brief RCC extended clocks structure definition |
84 | * @brief RCC extended clocks structure definition |
| 105 | */ |
85 | */ |
| 106 | typedef struct |
86 | typedef struct |
| 107 | { |
87 | { |
| 108 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
88 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
| 109 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
89 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
| Line 130... | Line 110... | ||
| 130 | */ |
110 | */ |
| 131 | 111 | ||
| 132 | /** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection |
112 | /** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection |
| 133 | * @{ |
113 | * @{ |
| 134 | */ |
114 | */ |
| 135 | #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000001) |
115 | #define RCC_PERIPHCLK_RTC (0x00000001U) |
| 136 | 116 | ||
| 137 | #if defined(LCD) |
117 | #if defined(LCD) |
| 138 | 118 | ||
| 139 | #define RCC_PERIPHCLK_LCD ((uint32_t)0x00000002) |
119 | #define RCC_PERIPHCLK_LCD (0x00000002U) |
| 140 | 120 | ||
| 141 | #endif /* LCD */ |
121 | #endif /* LCD */ |
| 142 | 122 | ||
| 143 | /** |
123 | /** |
| 144 | * @} |
124 | * @} |
| Line 164... | Line 144... | ||
| 164 | */ |
144 | */ |
| 165 | 145 | ||
| 166 | /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable |
146 | /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable |
| 167 | * @brief Enables or disables the AHB1 peripheral clock. |
147 | * @brief Enables or disables the AHB1 peripheral clock. |
| 168 | * @note After reset, the peripheral clock (used for registers read/write access) |
148 | * @note After reset, the peripheral clock (used for registers read/write access) |
| 169 | * is disabled and the application software has to enable this clock before |
149 | * is disabled and the application software has to enable this clock before |
| 170 | * using it. |
150 | * using it. |
| 171 | * @{ |
151 | * @{ |
| 172 | */ |
152 | */ |
| 173 | #if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\ |
153 | #if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\ |
| 174 | || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\ |
154 | || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\ |
| 175 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
155 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
| 176 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
156 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
| 177 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
157 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
| 178 | || defined(STM32L162xE) || defined(STM32L162xDX) |
158 | || defined(STM32L162xE) || defined(STM32L162xDX) |
| 179 | 159 | ||
| 180 | #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ |
160 | #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ |
| 181 | __IO uint32_t tmpreg; \ |
161 | __IO uint32_t tmpreg; \ |
| 182 | SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ |
162 | SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ |
| 183 | /* Delay after an RCC peripheral clock enabling */ \ |
163 | /* Delay after an RCC peripheral clock enabling */ \ |
| 184 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ |
164 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ |
| 185 | UNUSED(tmpreg); \ |
165 | UNUSED(tmpreg); \ |
| 186 | } while(0) |
166 | } while(0U) |
| 187 | #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN)) |
167 | #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN)) |
| 188 | 168 | ||
| 189 | #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
169 | #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
| 190 | 170 | ||
| 191 | #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ |
171 | #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ |
| Line 196... | Line 176... | ||
| 196 | __IO uint32_t tmpreg; \ |
176 | __IO uint32_t tmpreg; \ |
| 197 | SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ |
177 | SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ |
| 198 | /* Delay after an RCC peripheral clock enabling */ \ |
178 | /* Delay after an RCC peripheral clock enabling */ \ |
| 199 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ |
179 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ |
| 200 | UNUSED(tmpreg); \ |
180 | UNUSED(tmpreg); \ |
| 201 | } while(0) |
181 | } while(0U) |
| 202 | #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ |
182 | #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ |
| 203 | __IO uint32_t tmpreg; \ |
183 | __IO uint32_t tmpreg; \ |
| 204 | SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\ |
184 | SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\ |
| 205 | /* Delay after an RCC peripheral clock enabling */ \ |
185 | /* Delay after an RCC peripheral clock enabling */ \ |
| 206 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\ |
186 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\ |
| 207 | UNUSED(tmpreg); \ |
187 | UNUSED(tmpreg); \ |
| 208 | } while(0) |
188 | } while(0U) |
| 209 | 189 | ||
| 210 | #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN)) |
190 | #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN)) |
| 211 | #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN)) |
191 | #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN)) |
| 212 | 192 | ||
| 213 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
193 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
| Line 215... | Line 195... | ||
| 215 | #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ |
195 | #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ |
| 216 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
196 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
| 217 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
197 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
| 218 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
198 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
| 219 | || defined(STM32L162xE) || defined(STM32L162xDX) |
199 | || defined(STM32L162xE) || defined(STM32L162xDX) |
| 220 | 200 | ||
| 221 | #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ |
201 | #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ |
| 222 | __IO uint32_t tmpreg; \ |
202 | __IO uint32_t tmpreg; \ |
| 223 | SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ |
203 | SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ |
| 224 | /* Delay after an RCC peripheral clock enabling */ \ |
204 | /* Delay after an RCC peripheral clock enabling */ \ |
| 225 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ |
205 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ |
| 226 | UNUSED(tmpreg); \ |
206 | UNUSED(tmpreg); \ |
| 227 | } while(0) |
207 | } while(0U) |
| 228 | 208 | ||
| 229 | #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) |
209 | #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) |
| 230 | 210 | ||
| 231 | #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
211 | #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
| 232 | 212 | ||
| 233 | #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
213 | #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
| 234 | || defined(STM32L162xE) || defined(STM32L162xDX) |
214 | || defined(STM32L162xE) || defined(STM32L162xDX) |
| 235 | 215 | ||
| 236 | #define __HAL_RCC_CRYP_CLK_ENABLE() do { \ |
216 | #define __HAL_RCC_AES_CLK_ENABLE() do { \ |
| 237 | __IO uint32_t tmpreg; \ |
217 | __IO uint32_t tmpreg; \ |
| 238 | SET_BIT(RCC->AHBENR, RCC_AHBENR_AESEN);\ |
218 | SET_BIT(RCC->AHBENR, RCC_AHBENR_AESEN);\ |
| 239 | /* Delay after an RCC peripheral clock enabling */ \ |
219 | /* Delay after an RCC peripheral clock enabling */ \ |
| 240 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN);\ |
220 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN);\ |
| 241 | UNUSED(tmpreg); \ |
221 | UNUSED(tmpreg); \ |
| 242 | } while(0) |
222 | } while(0U) |
| 243 | #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_AESEN)) |
223 | #define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_AESEN)) |
| 244 | 224 | ||
| 245 | #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ |
225 | #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ |
| 246 | 226 | ||
| 247 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) |
227 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) |
| 248 | 228 | ||
| 249 | #define __HAL_RCC_FSMC_CLK_ENABLE() do { \ |
229 | #define __HAL_RCC_FSMC_CLK_ENABLE() do { \ |
| 250 | __IO uint32_t tmpreg; \ |
230 | __IO uint32_t tmpreg; \ |
| 251 | SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\ |
231 | SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\ |
| 252 | /* Delay after an RCC peripheral clock enabling */ \ |
232 | /* Delay after an RCC peripheral clock enabling */ \ |
| 253 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\ |
233 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\ |
| 254 | UNUSED(tmpreg); \ |
234 | UNUSED(tmpreg); \ |
| 255 | } while(0) |
235 | } while(0U) |
| 256 | #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN)) |
236 | #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN)) |
| 257 | 237 | ||
| 258 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
238 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
| 259 | 239 | ||
| 260 | #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\ |
240 | #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\ |
| 261 | || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\ |
241 | || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\ |
| 262 | || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\ |
242 | || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\ |
| 263 | || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
243 | || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
| 264 | || defined(STM32L162xE) || defined(STM32L162xDX) |
244 | || defined(STM32L162xE) || defined(STM32L162xDX) |
| 265 | 245 | ||
| 266 | #define __HAL_RCC_LCD_CLK_ENABLE() do { \ |
246 | #define __HAL_RCC_LCD_CLK_ENABLE() do { \ |
| 267 | __IO uint32_t tmpreg; \ |
247 | __IO uint32_t tmpreg; \ |
| 268 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN);\ |
248 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN);\ |
| 269 | /* Delay after an RCC peripheral clock enabling */ \ |
249 | /* Delay after an RCC peripheral clock enabling */ \ |
| 270 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN);\ |
250 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN);\ |
| 271 | UNUSED(tmpreg); \ |
251 | UNUSED(tmpreg); \ |
| 272 | } while(0) |
252 | } while(0U) |
| 273 | #define __HAL_RCC_LCD_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LCDEN)) |
253 | #define __HAL_RCC_LCD_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LCDEN)) |
| 274 | 254 | ||
| 275 | #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
255 | #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
| 276 | 256 | ||
| 277 | /** @brief Enables or disables the Low Speed APB (APB1) peripheral clock. |
257 | /** @brief Enables or disables the Low Speed APB (APB1) peripheral clock. |
| 278 | * @note After reset, the peripheral clock (used for registers read/write access) |
258 | * @note After reset, the peripheral clock (used for registers read/write access) |
| 279 | * is disabled and the application software has to enable this clock before |
259 | * is disabled and the application software has to enable this clock before |
| 280 | * using it. |
260 | * using it. |
| 281 | */ |
261 | */ |
| 282 | #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\ |
262 | #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\ |
| 283 | || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ |
263 | || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ |
| 284 | || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
264 | || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
| 285 | || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) |
265 | || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) |
| Line 288... | Line 268... | ||
| 288 | __IO uint32_t tmpreg; \ |
268 | __IO uint32_t tmpreg; \ |
| 289 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ |
269 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ |
| 290 | /* Delay after an RCC peripheral clock enabling */ \ |
270 | /* Delay after an RCC peripheral clock enabling */ \ |
| 291 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ |
271 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ |
| 292 | UNUSED(tmpreg); \ |
272 | UNUSED(tmpreg); \ |
| 293 | } while(0) |
273 | } while(0U) |
| 294 | #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) |
274 | #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) |
| 295 | 275 | ||
| 296 | #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
276 | #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
| 297 | 277 | ||
| 298 | #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ |
278 | #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ |
| Line 305... | Line 285... | ||
| 305 | __IO uint32_t tmpreg; \ |
285 | __IO uint32_t tmpreg; \ |
| 306 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ |
286 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ |
| 307 | /* Delay after an RCC peripheral clock enabling */ \ |
287 | /* Delay after an RCC peripheral clock enabling */ \ |
| 308 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ |
288 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ |
| 309 | UNUSED(tmpreg); \ |
289 | UNUSED(tmpreg); \ |
| 310 | } while(0) |
290 | } while(0U) |
| 311 | #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) |
291 | #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) |
| 312 | 292 | ||
| 313 | #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
293 | #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
| 314 | 294 | ||
| 315 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\ |
295 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\ |
| Line 319... | Line 299... | ||
| 319 | __IO uint32_t tmpreg; \ |
299 | __IO uint32_t tmpreg; \ |
| 320 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ |
300 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ |
| 321 | /* Delay after an RCC peripheral clock enabling */ \ |
301 | /* Delay after an RCC peripheral clock enabling */ \ |
| 322 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ |
302 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ |
| 323 | UNUSED(tmpreg); \ |
303 | UNUSED(tmpreg); \ |
| 324 | } while(0) |
304 | } while(0U) |
| 325 | #define __HAL_RCC_UART5_CLK_ENABLE() do { \ |
305 | #define __HAL_RCC_UART5_CLK_ENABLE() do { \ |
| 326 | __IO uint32_t tmpreg; \ |
306 | __IO uint32_t tmpreg; \ |
| 327 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ |
307 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ |
| 328 | /* Delay after an RCC peripheral clock enabling */ \ |
308 | /* Delay after an RCC peripheral clock enabling */ \ |
| 329 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ |
309 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ |
| 330 | UNUSED(tmpreg); \ |
310 | UNUSED(tmpreg); \ |
| 331 | } while(0) |
311 | } while(0U) |
| 332 | 312 | ||
| 333 | #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) |
313 | #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) |
| 334 | #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) |
314 | #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) |
| 335 | 315 | ||
| 336 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD || (...) || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
316 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD || (...) || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
| Line 341... | Line 321... | ||
| 341 | || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\ |
321 | || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\ |
| 342 | || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC) |
322 | || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC) |
| 343 | 323 | ||
| 344 | #define __HAL_RCC_OPAMP_CLK_ENABLE() __HAL_RCC_COMP_CLK_ENABLE() /* Peripherals COMP and OPAMP share the same clock domain */ |
324 | #define __HAL_RCC_OPAMP_CLK_ENABLE() __HAL_RCC_COMP_CLK_ENABLE() /* Peripherals COMP and OPAMP share the same clock domain */ |
| 345 | #define __HAL_RCC_OPAMP_CLK_DISABLE() __HAL_RCC_COMP_CLK_DISABLE() /* Peripherals COMP and OPAMP share the same clock domain */ |
325 | #define __HAL_RCC_OPAMP_CLK_DISABLE() __HAL_RCC_COMP_CLK_DISABLE() /* Peripherals COMP and OPAMP share the same clock domain */ |
| 346 | 326 | ||
| 347 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || (...) || STM32L162xC || STM32L152xC || STM32L151xC */ |
327 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || (...) || STM32L162xC || STM32L152xC || STM32L151xC */ |
| 348 | 328 | ||
| 349 | /** @brief Enables or disables the High Speed APB (APB2) peripheral clock. |
329 | /** @brief Enables or disables the High Speed APB (APB2) peripheral clock. |
| 350 | * @note After reset, the peripheral clock (used for registers read/write access) |
330 | * @note After reset, the peripheral clock (used for registers read/write access) |
| 351 | * is disabled and the application software has to enable this clock before |
331 | * is disabled and the application software has to enable this clock before |
| 352 | * using it. |
332 | * using it. |
| 353 | */ |
333 | */ |
| 354 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) |
334 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) |
| 355 | 335 | ||
| 356 | #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ |
336 | #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ |
| 357 | __IO uint32_t tmpreg; \ |
337 | __IO uint32_t tmpreg; \ |
| 358 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ |
338 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ |
| 359 | /* Delay after an RCC peripheral clock enabling */ \ |
339 | /* Delay after an RCC peripheral clock enabling */ \ |
| 360 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ |
340 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ |
| 361 | UNUSED(tmpreg); \ |
341 | UNUSED(tmpreg); \ |
| 362 | } while(0) |
342 | } while(0U) |
| 363 | #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) |
343 | #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) |
| 364 | 344 | ||
| 365 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
345 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
| 366 | 346 | ||
| 367 | /** |
347 | /** |
| 368 | * @} |
348 | * @} |
| 369 | */ |
349 | */ |
| 370 | 350 | ||
| 371 | 351 | ||
| 372 | /** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset |
352 | /** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset |
| 373 | * @brief Forces or releases AHB peripheral reset. |
353 | * @brief Forces or releases AHB peripheral reset. |
| 374 | * @{ |
354 | * @{ |
| 375 | */ |
355 | */ |
| 376 | #if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\ |
356 | #if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\ |
| 377 | || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\ |
357 | || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\ |
| 378 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
358 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
| 379 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
359 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
| 380 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
360 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
| 381 | || defined(STM32L162xE) || defined(STM32L162xDX) |
361 | || defined(STM32L162xE) || defined(STM32L162xDX) |
| 382 | 362 | ||
| 383 | #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST)) |
363 | #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST)) |
| 384 | #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST)) |
364 | #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST)) |
| 385 | 365 | ||
| 386 | #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
366 | #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
| 387 | 367 | ||
| Line 400... | Line 380... | ||
| 400 | #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ |
380 | #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ |
| 401 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
381 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
| 402 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
382 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
| 403 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
383 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
| 404 | || defined(STM32L162xE) || defined(STM32L162xDX) |
384 | || defined(STM32L162xE) || defined(STM32L162xDX) |
| 405 | 385 | ||
| 406 | #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA2RST)) |
386 | #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA2RST)) |
| 407 | #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA2RST)) |
387 | #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA2RST)) |
| 408 | 388 | ||
| 409 | #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
389 | #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
| 410 | 390 | ||
| 411 | #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
391 | #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
| 412 | || defined(STM32L162xE) || defined(STM32L162xDX) |
392 | || defined(STM32L162xE) || defined(STM32L162xDX) |
| 413 | 393 | ||
| 414 | #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_AESRST)) |
394 | #define __HAL_RCC_AES_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_AESRST)) |
| 415 | #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_AESRST)) |
395 | #define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_AESRST)) |
| 416 | 396 | ||
| 417 | #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ |
397 | #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ |
| 418 | 398 | ||
| 419 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) |
399 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) |
| 420 | 400 | ||
| 421 | #define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_FSMCRST)) |
401 | #define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_FSMCRST)) |
| 422 | #define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FSMCRST)) |
402 | #define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FSMCRST)) |
| 423 | 403 | ||
| 424 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
404 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
| 425 | 405 | ||
| 426 | #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\ |
406 | #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\ |
| 427 | || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\ |
407 | || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\ |
| 428 | || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\ |
408 | || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\ |
| 429 | || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
409 | || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
| 430 | || defined(STM32L162xE) || defined(STM32L162xDX) |
410 | || defined(STM32L162xE) || defined(STM32L162xDX) |
| 431 | 411 | ||
| 432 | #define __HAL_RCC_LCD_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LCDRST)) |
412 | #define __HAL_RCC_LCD_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LCDRST)) |
| 433 | #define __HAL_RCC_LCD_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LCDRST)) |
413 | #define __HAL_RCC_LCD_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LCDRST)) |
| 434 | 414 | ||
| 435 | #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
415 | #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
| 436 | 416 | ||
| Line 473... | Line 453... | ||
| 473 | || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\ |
453 | || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\ |
| 474 | || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC) |
454 | || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC) |
| 475 | 455 | ||
| 476 | #define __HAL_RCC_OPAMP_FORCE_RESET() __HAL_RCC_COMP_FORCE_RESET() /* Peripherals COMP and OPAMP share the same clock domain */ |
456 | #define __HAL_RCC_OPAMP_FORCE_RESET() __HAL_RCC_COMP_FORCE_RESET() /* Peripherals COMP and OPAMP share the same clock domain */ |
| 477 | #define __HAL_RCC_OPAMP_RELEASE_RESET() __HAL_RCC_COMP_RELEASE_RESET() /* Peripherals COMP and OPAMP share the same clock domain */ |
457 | #define __HAL_RCC_OPAMP_RELEASE_RESET() __HAL_RCC_COMP_RELEASE_RESET() /* Peripherals COMP and OPAMP share the same clock domain */ |
| 478 | 458 | ||
| 479 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ |
459 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ |
| 480 | 460 | ||
| 481 | /** @brief Forces or releases APB2 peripheral reset. |
461 | /** @brief Forces or releases APB2 peripheral reset. |
| 482 | */ |
462 | */ |
| 483 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) |
463 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) |
| 484 | 464 | ||
| 485 | #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) |
465 | #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) |
| Line 503... | Line 483... | ||
| 503 | || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\ |
483 | || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\ |
| 504 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
484 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
| 505 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
485 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
| 506 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
486 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
| 507 | || defined(STM32L162xE) || defined(STM32L162xDX) |
487 | || defined(STM32L162xE) || defined(STM32L162xDX) |
| 508 | 488 | ||
| 509 | #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOELPEN)) |
489 | #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOELPEN)) |
| 510 | #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOELPEN)) |
490 | #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOELPEN)) |
| 511 | 491 | ||
| 512 | #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
492 | #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
| 513 | 493 | ||
| Line 526... | Line 506... | ||
| 526 | #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ |
506 | #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ |
| 527 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
507 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
| 528 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
508 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
| 529 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
509 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
| 530 | || defined(STM32L162xE) || defined(STM32L162xDX) |
510 | || defined(STM32L162xE) || defined(STM32L162xDX) |
| 531 | 511 | ||
| 532 | #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_DMA2LPEN)) |
512 | #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_DMA2LPEN)) |
| 533 | #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA2LPEN)) |
513 | #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA2LPEN)) |
| 534 | 514 | ||
| 535 | #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
515 | #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
| 536 | 516 | ||
| 537 | #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) || defined(STM32L162xDX) |
517 | #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) || defined(STM32L162xDX) |
| 538 | 518 | ||
| 539 | #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_AESLPEN)) |
519 | #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_AESLPEN)) |
| 540 | #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_AESLPEN)) |
520 | #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_AESLPEN)) |
| 541 | 521 | ||
| 542 | #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ |
522 | #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ |
| 543 | 523 | ||
| 544 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) |
524 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) |
| 545 | 525 | ||
| 546 | #define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_FSMCLPEN)) |
526 | #define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_FSMCLPEN)) |
| 547 | #define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FSMCLPEN)) |
527 | #define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FSMCLPEN)) |
| 548 | 528 | ||
| 549 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
529 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
| 550 | 530 | ||
| 551 | #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\ |
531 | #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\ |
| 552 | || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\ |
532 | || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\ |
| 553 | || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\ |
533 | || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\ |
| 554 | || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
534 | || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
| 555 | || defined(STM32L162xE) || defined(STM32L162xDX) |
535 | || defined(STM32L162xE) || defined(STM32L162xDX) |
| 556 | 536 | ||
| 557 | #define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LCDLPEN)) |
537 | #define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LCDLPEN)) |
| 558 | #define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LCDLPEN)) |
538 | #define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LCDLPEN)) |
| 559 | 539 | ||
| 560 | #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
540 | #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
| 561 | 541 | ||
| Line 602... | Line 582... | ||
| 602 | || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\ |
582 | || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\ |
| 603 | || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC) |
583 | || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC) |
| 604 | 584 | ||
| 605 | #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() __HAL_RCC_COMP_CLK_SLEEP_ENABLE() /* Peripherals COMP and OPAMP share the same clock domain */ |
585 | #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() __HAL_RCC_COMP_CLK_SLEEP_ENABLE() /* Peripherals COMP and OPAMP share the same clock domain */ |
| 606 | #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() __HAL_RCC_COMP_CLK_SLEEP_DISABLE() /* Peripherals COMP and OPAMP share the same clock domain */ |
586 | #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() __HAL_RCC_COMP_CLK_SLEEP_DISABLE() /* Peripherals COMP and OPAMP share the same clock domain */ |
| 607 | 587 | ||
| 608 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ |
588 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ |
| 609 | 589 | ||
| 610 | /** @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. |
590 | /** @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. |
| 611 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
591 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| 612 | * power consumption. |
592 | * power consumption. |
| Line 636... | Line 616... | ||
| 636 | || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\ |
616 | || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\ |
| 637 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
617 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
| 638 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
618 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
| 639 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
619 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
| 640 | || defined(STM32L162xE) || defined(STM32L162xDX) |
620 | || defined(STM32L162xE) || defined(STM32L162xDX) |
| 641 | 621 | ||
| 642 | #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET) |
622 | #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != 0U) |
| 643 | #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET) |
623 | #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == 0U) |
| 644 | 624 | ||
| 645 | #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
625 | #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
| 646 | 626 | ||
| 647 | #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ |
627 | #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ |
| 648 | || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
628 | || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
| 649 | || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) |
629 | || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) |
| 650 | 630 | ||
| 651 | #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET) |
631 | #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != 0U) |
| 652 | #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) != RESET) |
632 | #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) != 0U) |
| 653 | #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET) |
633 | #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == 0U) |
| 654 | #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) == RESET) |
634 | #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) == 0U) |
| 655 | 635 | ||
| 656 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
636 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
| 657 | 637 | ||
| 658 | #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ |
638 | #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ |
| 659 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
639 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
| 660 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
640 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
| 661 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
641 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
| 662 | || defined(STM32L162xE) || defined(STM32L162xDX) |
642 | || defined(STM32L162xE) || defined(STM32L162xDX) |
| 663 | 643 | ||
| 664 | #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET) |
644 | #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != 0U) |
| 665 | #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET) |
645 | #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == 0U) |
| 666 | 646 | ||
| 667 | #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
647 | #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
| 668 | 648 | ||
| 669 | #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
649 | #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
| 670 | || defined(STM32L162xE) || defined(STM32L162xDX) |
650 | || defined(STM32L162xE) || defined(STM32L162xDX) |
| 671 | 651 | ||
| 672 | #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_AESEN)) != RESET) |
652 | #define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_AESEN)) != 0U) |
| 673 | #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_AESEN)) == RESET) |
653 | #define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_AESEN)) == 0U) |
| 674 | 654 | ||
| 675 | #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ |
655 | #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ |
| 676 | 656 | ||
| 677 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) |
657 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) |
| 678 | 658 | ||
| 679 | #define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != RESET) |
659 | #define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != 0U) |
| 680 | #define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == RESET) |
660 | #define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == 0U) |
| 681 | 661 | ||
| 682 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
662 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
| 683 | 663 | ||
| 684 | #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\ |
664 | #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\ |
| 685 | || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\ |
665 | || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\ |
| 686 | || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\ |
666 | || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\ |
| 687 | || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
667 | || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
| 688 | || defined(STM32L162xE) || defined(STM32L162xDX) |
668 | || defined(STM32L162xE) || defined(STM32L162xDX) |
| 689 | 669 | ||
| 690 | #define __HAL_RCC_LCD_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LCDEN)) != RESET) |
670 | #define __HAL_RCC_LCD_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LCDEN)) != 0U) |
| 691 | #define __HAL_RCC_LCD_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LCDEN)) == RESET) |
671 | #define __HAL_RCC_LCD_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LCDEN)) == 0U) |
| 692 | 672 | ||
| 693 | #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
673 | #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
| 694 | 674 | ||
| 695 | #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\ |
675 | #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\ |
| 696 | || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ |
676 | || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ |
| 697 | || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
677 | || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
| 698 | || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) |
678 | || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) |
| 699 | 679 | ||
| 700 | #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) |
680 | #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != 0U) |
| 701 | #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) |
681 | #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == 0U) |
| 702 | 682 | ||
| 703 | #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
683 | #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
| 704 | 684 | ||
| 705 | #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ |
685 | #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ |
| 706 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
686 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
| 707 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
687 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
| 708 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
688 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
| 709 | || defined(STM32L162xE) || defined(STM32L162xDX) |
689 | || defined(STM32L162xE) || defined(STM32L162xDX) |
| 710 | 690 | ||
| 711 | #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) |
691 | #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != 0U) |
| 712 | #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) |
692 | #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == 0U) |
| 713 | 693 | ||
| 714 | #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
694 | #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
| 715 | 695 | ||
| 716 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\ |
696 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\ |
| 717 | || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) |
697 | || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) |
| 718 | 698 | ||
| 719 | #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) |
699 | #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != 0U) |
| 720 | #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) |
700 | #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != 0U) |
| 721 | #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) |
701 | #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == 0U) |
| 722 | #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) |
702 | #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == 0U) |
| 723 | 703 | ||
| 724 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
704 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
| 725 | 705 | ||
| 726 | #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ |
706 | #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ |
| 727 | || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
707 | || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
| Line 733... | Line 713... | ||
| 733 | 713 | ||
| 734 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ |
714 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ |
| 735 | 715 | ||
| 736 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) |
716 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) |
| 737 | 717 | ||
| 738 | #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) |
718 | #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != 0U) |
| 739 | #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) |
719 | #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == 0U) |
| 740 | 720 | ||
| 741 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
721 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
| 742 | 722 | ||
| 743 | /** |
723 | /** |
| 744 | * @} |
724 | * @} |
| Line 757... | Line 737... | ||
| 757 | || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\ |
737 | || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\ |
| 758 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
738 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
| 759 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
739 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
| 760 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
740 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
| 761 | || defined(STM32L162xE) || defined(STM32L162xDX) |
741 | || defined(STM32L162xE) || defined(STM32L162xDX) |
| 762 | 742 | ||
| 763 | #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOELPEN)) != RESET) |
743 | #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOELPEN)) != 0U) |
| 764 | #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOELPEN)) == RESET) |
744 | #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOELPEN)) == 0U) |
| 765 | 745 | ||
| 766 | #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
746 | #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
| 767 | 747 | ||
| 768 | #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ |
748 | #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ |
| 769 | || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
749 | || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
| 770 | || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) |
750 | || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) |
| 771 | 751 | ||
| 772 | #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOFLPEN)) != RESET) |
752 | #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOFLPEN)) != 0U) |
| 773 | #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOGLPEN)) != RESET) |
753 | #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOGLPEN)) != 0U) |
| 774 | #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOFLPEN)) == RESET) |
754 | #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOFLPEN)) == 0U) |
| 775 | #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOGLPEN)) == RESET) |
755 | #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOGLPEN)) == 0U) |
| 776 | 756 | ||
| 777 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
757 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
| 778 | 758 | ||
| 779 | #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ |
759 | #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ |
| 780 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
760 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
| 781 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
761 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
| 782 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
762 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
| 783 | || defined(STM32L162xE) || defined(STM32L162xDX) |
763 | || defined(STM32L162xE) || defined(STM32L162xDX) |
| 784 | 764 | ||
| 785 | #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA2LPEN)) != RESET) |
765 | #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA2LPEN)) != 0U) |
| 786 | #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA2LPEN)) == RESET) |
766 | #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA2LPEN)) == 0U) |
| 787 | 767 | ||
| 788 | #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
768 | #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
| 789 | 769 | ||
| 790 | #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
770 | #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
| 791 | || defined(STM32L162xE) || defined(STM32L162xDX) |
771 | || defined(STM32L162xE) || defined(STM32L162xDX) |
| 792 | 772 | ||
| 793 | #define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_AESLPEN)) != RESET) |
773 | #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_AESLPEN)) != 0U) |
| 794 | #define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_AESLPEN)) == RESET) |
774 | #define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_AESLPEN)) == 0U) |
| 795 | 775 | ||
| 796 | #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ |
776 | #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ |
| 797 | 777 | ||
| 798 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) |
778 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) |
| 799 | 779 | ||
| 800 | #define __HAL_RCC_FSMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_FSMCLPEN)) != RESET) |
780 | #define __HAL_RCC_FSMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_FSMCLPEN)) != 0U) |
| 801 | #define __HAL_RCC_FSMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_FSMCLPEN)) == RESET) |
781 | #define __HAL_RCC_FSMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_FSMCLPEN)) == 0U) |
| 802 | 782 | ||
| 803 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
783 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
| 804 | 784 | ||
| 805 | #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\ |
785 | #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\ |
| 806 | || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\ |
786 | || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\ |
| 807 | || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\ |
787 | || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\ |
| 808 | || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
788 | || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
| 809 | || defined(STM32L162xE) || defined(STM32L162xDX) |
789 | || defined(STM32L162xE) || defined(STM32L162xDX) |
| 810 | 790 | ||
| 811 | #define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LCDLPEN)) != RESET) |
791 | #define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LCDLPEN)) != 0U) |
| 812 | #define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LCDLPEN)) == RESET) |
792 | #define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LCDLPEN)) == 0U) |
| 813 | 793 | ||
| 814 | #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
794 | #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
| 815 | 795 | ||
| 816 | #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\ |
796 | #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\ |
| 817 | || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ |
797 | || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ |
| 818 | || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
798 | || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
| 819 | || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) |
799 | || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) |
| 820 | 800 | ||
| 821 | #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET) |
801 | #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != 0U) |
| 822 | #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET) |
802 | #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == 0U) |
| 823 | 803 | ||
| 824 | #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
804 | #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
| 825 | 805 | ||
| 826 | #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ |
806 | #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ |
| 827 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
807 | || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ |
| 828 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
808 | || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ |
| 829 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
809 | || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ |
| 830 | || defined(STM32L162xE) || defined(STM32L162xDX) |
810 | || defined(STM32L162xE) || defined(STM32L162xDX) |
| 831 | 811 | ||
| 832 | #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET) |
812 | #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != 0U) |
| 833 | #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET) |
813 | #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == 0U) |
| 834 | 814 | ||
| 835 | #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
815 | #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
| 836 | 816 | ||
| 837 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\ |
817 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\ |
| 838 | || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) |
818 | || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) |
| 839 | 819 | ||
| 840 | #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET) |
820 | #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != 0U) |
| 841 | #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET) |
821 | #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != 0U) |
| 842 | #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET) |
822 | #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == 0U) |
| 843 | #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET) |
823 | #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == 0U) |
| 844 | 824 | ||
| 845 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
825 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
| 846 | 826 | ||
| 847 | #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ |
827 | #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ |
| 848 | || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
828 | || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ |
| Line 854... | Line 834... | ||
| 854 | 834 | ||
| 855 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ |
835 | #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ |
| 856 | 836 | ||
| 857 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) |
837 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) |
| 858 | 838 | ||
| 859 | #define __HAL_RCC_SDIO_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDIOLPEN)) != RESET) |
839 | #define __HAL_RCC_SDIO_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDIOLPEN)) != 0U) |
| 860 | #define __HAL_RCC_SDIO_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDIOLPEN)) == RESET) |
840 | #define __HAL_RCC_SDIO_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDIOLPEN)) == 0U) |
| 861 | 841 | ||
| 862 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
842 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
| 863 | 843 | ||
| 864 | /** |
844 | /** |
| 865 | * @} |
845 | * @} |
| 866 | */ |
846 | */ |
| 867 | 847 | ||
| 868 | 848 | ||
| 869 | #if defined(RCC_LSECSS_SUPPORT) |
849 | #if defined(RCC_LSECSS_SUPPORT) |
| 870 | 850 | ||
| 871 | /** |
851 | /** |
| 872 | * @brief Enable interrupt on RCC LSE CSS EXTI Line 19. |
852 | * @brief Enable interrupt on RCC LSE CSS EXTI Line 19. |
| 873 | * @retval None |
853 | * @retval None |
| Line 925... | Line 905... | ||
| 925 | */ |
905 | */ |
| 926 | #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \ |
906 | #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \ |
| 927 | do { \ |
907 | do { \ |
| 928 | __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \ |
908 | __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \ |
| 929 | __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \ |
909 | __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \ |
| 930 | } while(0) |
910 | } while(0U) |
| 931 | 911 | ||
| 932 | /** |
912 | /** |
| 933 | * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. |
913 | * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. |
| 934 | * @retval None. |
914 | * @retval None. |
| 935 | */ |
915 | */ |
| 936 | #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \ |
916 | #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \ |
| 937 | do { \ |
917 | do { \ |
| 938 | __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \ |
918 | __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \ |
| 939 | __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \ |
919 | __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \ |
| 940 | } while(0) |
920 | } while(0U) |
| 941 | 921 | ||
| 942 | /** |
922 | /** |
| 943 | * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. |
923 | * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. |
| 944 | * @retval EXTI RCC LSE CSS Line Status. |
924 | * @retval EXTI RCC LSE CSS Line Status. |
| 945 | */ |
925 | */ |
| Line 958... | Line 938... | ||
| 958 | #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, RCC_EXTI_LINE_LSECSS) |
938 | #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, RCC_EXTI_LINE_LSECSS) |
| 959 | 939 | ||
| 960 | #endif /* RCC_LSECSS_SUPPORT */ |
940 | #endif /* RCC_LSECSS_SUPPORT */ |
| 961 | 941 | ||
| 962 | #if defined(LCD) |
942 | #if defined(LCD) |
| 963 | 943 | ||
| 964 | /** @defgroup RCCEx_LCD_Configuration LCD Configuration |
944 | /** @defgroup RCCEx_LCD_Configuration LCD Configuration |
| 965 | * @brief Macros to configure clock source of LCD peripherals. |
945 | * @brief Macros to configure clock source of LCD peripherals. |
| 966 | * @{ |
946 | * @{ |
| 967 | */ |
947 | */ |
| 968 | 948 | ||
| 969 | /** @brief Macro to configures LCD clock (LCDCLK). |
949 | /** @brief Macro to configures LCD clock (LCDCLK). |
| 970 | * @note LCD and RTC use the same configuration |
950 | * @note LCD and RTC use the same configuration |
| 971 | * @note LCD can however be used in the Stop low power mode if the LSE or LSI is used as the |
951 | * @note LCD can however be used in the Stop low power mode if the LSE or LSI is used as the |
| 972 | * LCD clock source. |
952 | * LCD clock source. |
| 973 | * |
953 | * |
| 974 | * @param __LCD_CLKSOURCE__ specifies the LCD clock source. |
954 | * @param __LCD_CLKSOURCE__ specifies the LCD clock source. |
| 975 | * This parameter can be one of the following values: |
955 | * This parameter can be one of the following values: |
| 976 | * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as LCD clock |
956 | * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as LCD clock |
| 977 | * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as LCD clock |
957 | * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as LCD clock |
| 978 | * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as LCD clock |
958 | * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as LCD clock |
| Line 1037... | Line 1017... | ||
| 1037 | */ |
1017 | */ |
| 1038 | 1018 | ||
| 1039 | /** |
1019 | /** |
| 1040 | * @} |
1020 | * @} |
| 1041 | */ |
1021 | */ |
| 1042 | 1022 | ||
| 1043 | #ifdef __cplusplus |
1023 | #ifdef __cplusplus |
| 1044 | } |
1024 | } |
| 1045 | #endif |
1025 | #endif |
| 1046 | 1026 | ||
| 1047 | #endif /* __STM32L1xx_HAL_RCC_EX_H */ |
1027 | #endif /* __STM32L1xx_HAL_RCC_EX_H */ |