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/**
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/**
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  ******************************************************************************
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  ******************************************************************************
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  * @file    stm32l1xx_hal_cortex.h
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  * @file    stm32l1xx_hal_cortex.h
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  * @author  MCD Application Team
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  * @author  MCD Application Team
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  * @version V1.2.0
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  * @date    01-July-2016
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  * @brief   Header file of CORTEX HAL module.
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  * @brief   Header file of CORTEX HAL module.
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  ******************************************************************************
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  ******************************************************************************
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  * @attention
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  * @attention
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  *
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  *
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  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
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  * All rights reserved.</center></h2>
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  *
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  *
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  * Redistribution and use in source and binary forms, with or without modification,
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  * This software component is licensed by ST under BSD 3-Clause license,
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  * are permitted provided that the following conditions are met:
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  * the "License"; You may not use this file except in compliance with the
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  *   1. Redistributions of source code must retain the above copyright notice,
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  *      this list of conditions and the following disclaimer.
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  *   2. Redistributions in binary form must reproduce the above copyright notice,
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  *      this list of conditions and the following disclaimer in the documentation
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  *      and/or other materials provided with the distribution.
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  * License. You may obtain a copy of the License at:
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  *   3. Neither the name of STMicroelectronics nor the names of its contributors
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  *      may be used to endorse or promote products derived from this software
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  *                        opensource.org/licenses/BSD-3-Clause
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  *      without specific prior written permission.
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  *
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  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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  *
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  *
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  ******************************************************************************
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  ******************************************************************************
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  */
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  */
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/* Define to prevent recursive inclusion -------------------------------------*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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/** @defgroup CORTEX_Preemption_Priority_Group  CORTEX Preemption Priority Group
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/** @defgroup CORTEX_Preemption_Priority_Group  CORTEX Preemption Priority Group
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  * @{
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  * @{
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  */
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  */
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#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
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#define NVIC_PRIORITYGROUP_0         (0x00000007U) /*!< 0 bits for pre-emption priority
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                                                                 4 bits for subpriority */
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                                                        4 bits for subpriority */
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#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
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#define NVIC_PRIORITYGROUP_1         (0x00000006U) /*!< 1 bits for pre-emption priority
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                                                                 3 bits for subpriority */
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                                                        3 bits for subpriority */
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#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority
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#define NVIC_PRIORITYGROUP_2         (0x00000005U) /*!< 2 bits for pre-emption priority
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                                                                 2 bits for subpriority */
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                                                        2 bits for subpriority */
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#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority
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#define NVIC_PRIORITYGROUP_3         (0x00000004U) /*!< 3 bits for pre-emption priority
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                                                                 1 bits for subpriority */
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                                                        1 bits for subpriority */
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#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
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#define NVIC_PRIORITYGROUP_4         (0x00000003U) /*!< 4 bits for pre-emption priority
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                                                                 0 bits for subpriority */
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                                                        0 bits for subpriority */
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/**
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/**
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  * @}
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  * @}
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  */
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  */
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/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
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/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
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  * @{
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  * @{
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  */
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  */
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#define SYSTICK_CLKSOURCE_HCLK_DIV8    ((uint32_t)0x00000000)
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#define SYSTICK_CLKSOURCE_HCLK_DIV8    (0x00000000U)
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#define SYSTICK_CLKSOURCE_HCLK         ((uint32_t)0x00000004)
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#define SYSTICK_CLKSOURCE_HCLK         (0x00000004U)
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/**
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/**
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  * @}
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  * @}
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  */
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  */
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#if (__MPU_PRESENT == 1)
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#if (__MPU_PRESENT == 1)
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/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
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/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
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  * @{
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  * @{
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  */
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  */
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#define  MPU_HFNMI_PRIVDEF_NONE      ((uint32_t)0x00000000)  
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#define  MPU_HFNMI_PRIVDEF_NONE      (0x00000000U)  
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#define  MPU_HARDFAULT_NMI           ((uint32_t)0x00000002)
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#define  MPU_HARDFAULT_NMI           (MPU_CTRL_HFNMIENA_Msk)
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#define  MPU_PRIVILEGED_DEFAULT      ((uint32_t)0x00000004)
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#define  MPU_PRIVILEGED_DEFAULT      (MPU_CTRL_PRIVDEFENA_Msk)
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#define  MPU_HFNMI_PRIVDEF           ((uint32_t)0x00000006)
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#define  MPU_HFNMI_PRIVDEF           (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
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/**
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/**
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  * @}
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  * @}
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  */
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  */
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/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
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/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
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/** @defgroup CORTEX_Private_Functions CORTEX Private Functions
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/** @defgroup CORTEX_Private_Functions CORTEX Private Functions
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  * @brief    CORTEX private  functions
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  * @brief    CORTEX private  functions
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  * @{
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  * @{
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  */
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  */
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#if (__MPU_PRESENT == 1)
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/**
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  * @brief  Disables the MPU
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  * @retval None
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  */
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__STATIC_INLINE void HAL_MPU_Disable(void)
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{
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  /* Disable fault exceptions */
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  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
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  /* Disable the MPU */
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  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
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}
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/**
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  * @brief  Enables the MPU
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  * @param  MPU_Control: Specifies the control mode of the MPU during hard fault,
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  *          NMI, FAULTMASK and privileged accessto the default memory
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  *          This parameter can be one of the following values:
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  *            @arg MPU_HFNMI_PRIVDEF_NONE
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  *            @arg MPU_HARDFAULT_NMI
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  *            @arg MPU_PRIVILEGED_DEFAULT
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  *            @arg MPU_HFNMI_PRIVDEF
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  * @retval None
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  */
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__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
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{
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  /* Enable the MPU */
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  MPU->CTRL   = MPU_Control | MPU_CTRL_ENABLE_Msk;
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  /* Enable fault exceptions */
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  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
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}
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#endif /* __MPU_PRESENT */
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/**
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/**
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  * @}
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  * @}
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  */
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  */
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/** @addtogroup CORTEX_Exported_Functions_Group2
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/** @addtogroup CORTEX_Exported_Functions_Group2
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  * @{
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  * @{
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  */
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  */
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/* Peripheral Control functions ***********************************************/
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/* Peripheral Control functions ***********************************************/
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#if (__MPU_PRESENT == 1)
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#if (__MPU_PRESENT == 1)
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void HAL_MPU_Enable(uint32_t MPU_Control);
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void HAL_MPU_Disable(void);
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void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
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void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
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#endif /* __MPU_PRESENT */
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#endif /* __MPU_PRESENT */
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uint32_t HAL_NVIC_GetPriorityGrouping(void);
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uint32_t HAL_NVIC_GetPriorityGrouping(void);
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void     HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
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void     HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
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uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
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uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);