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1 | /** |
1 | /** |
2 | ****************************************************************************** |
2 | ****************************************************************************** |
3 | * @file stm32f1xx_ll_usb.c |
3 | * @file stm32f1xx_ll_usb.c |
4 | * @author MCD Application Team |
4 | * @author MCD Application Team |
5 | * @brief USB Low Layer HAL module driver. |
5 | * @brief USB Low Layer HAL module driver. |
6 | * |
6 | * |
7 | * This file provides firmware functions to manage the following |
7 | * This file provides firmware functions to manage the following |
8 | * functionalities of the USB Peripheral Controller: |
8 | * functionalities of the USB Peripheral Controller: |
9 | * + Initialization/de-initialization functions |
9 | * + Initialization/de-initialization functions |
10 | * + I/O operation functions |
10 | * + I/O operation functions |
11 | * + Peripheral Control functions |
11 | * + Peripheral Control functions |
12 | * + Peripheral State functions |
12 | * + Peripheral State functions |
13 | * |
13 | * |
14 | @verbatim |
14 | ****************************************************************************** |
15 | ============================================================================== |
15 | * @attention |
16 | ##### How to use this driver ##### |
16 | * |
17 | ============================================================================== |
17 | * Copyright (c) 2016 STMicroelectronics. |
18 | [..] |
18 | * All rights reserved. |
19 | (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure. |
19 | * |
20 | 20 | * This software is licensed under terms that can be found in the LICENSE file |
|
21 | (#) Call USB_CoreInit() API to initialize the USB Core peripheral. |
21 | * in the root directory of this software component. |
22 | 22 | * If no LICENSE file comes with this software, it is provided AS-IS. |
|
23 | (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes. |
23 | * |
24 | 24 | ****************************************************************************** |
|
25 | @endverbatim |
25 | @verbatim |
26 | ****************************************************************************** |
26 | ============================================================================== |
27 | * @attention |
27 | ##### How to use this driver ##### |
28 | * |
28 | ============================================================================== |
29 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
29 | [..] |
30 | * All rights reserved.</center></h2> |
30 | (#) Fill parameters of Init structure in USB_CfgTypeDef structure. |
31 | * |
31 | |
32 | * This software component is licensed by ST under BSD 3-Clause license, |
32 | (#) Call USB_CoreInit() API to initialize the USB Core peripheral. |
33 | * the "License"; You may not use this file except in compliance with the |
33 | |
34 | * License. You may obtain a copy of the License at: |
34 | (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes. |
35 | * opensource.org/licenses/BSD-3-Clause |
35 | |
36 | * |
36 | @endverbatim |
37 | ****************************************************************************** |
37 | |
38 | */ |
38 | ****************************************************************************** |
39 | 39 | */ |
|
40 | /* Includes ------------------------------------------------------------------*/ |
40 | |
41 | #include "stm32f1xx_hal.h" |
41 | /* Includes ------------------------------------------------------------------*/ |
42 | 42 | #include "stm32f1xx_hal.h" |
|
43 | /** @addtogroup STM32F1xx_LL_USB_DRIVER |
43 | |
44 | * @{ |
44 | /** @addtogroup STM32F1xx_LL_USB_DRIVER |
45 | */ |
45 | * @{ |
46 | 46 | */ |
|
47 | #if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) |
47 | |
48 | #if defined (USB) || defined (USB_OTG_FS) |
48 | #if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) |
49 | /* Private typedef -----------------------------------------------------------*/ |
49 | #if defined (USB) || defined (USB_OTG_FS) |
50 | /* Private define ------------------------------------------------------------*/ |
50 | /* Private typedef -----------------------------------------------------------*/ |
51 | /* Private macro -------------------------------------------------------------*/ |
51 | /* Private define ------------------------------------------------------------*/ |
52 | /* Private variables ---------------------------------------------------------*/ |
52 | /* Private macro -------------------------------------------------------------*/ |
53 | /* Private function prototypes -----------------------------------------------*/ |
53 | /* Private variables ---------------------------------------------------------*/ |
54 | /* Private functions ---------------------------------------------------------*/ |
54 | /* Private function prototypes -----------------------------------------------*/ |
55 | #if defined (USB_OTG_FS) |
55 | /* Private functions ---------------------------------------------------------*/ |
56 | static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx); |
56 | #if defined (USB_OTG_FS) |
57 | 57 | static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx); |
|
58 | /* Exported functions --------------------------------------------------------*/ |
58 | |
59 | /** @defgroup USB_LL_Exported_Functions USB Low Layer Exported Functions |
59 | /* Exported functions --------------------------------------------------------*/ |
60 | * @{ |
60 | /** @defgroup USB_LL_Exported_Functions USB Low Layer Exported Functions |
61 | */ |
61 | * @{ |
62 | 62 | */ |
|
63 | /** @defgroup USB_LL_Exported_Functions_Group1 Initialization/de-initialization functions |
63 | |
64 | * @brief Initialization and Configuration functions |
64 | /** @defgroup USB_LL_Exported_Functions_Group1 Initialization/de-initialization functions |
65 | * |
65 | * @brief Initialization and Configuration functions |
66 | @verbatim |
66 | * |
67 | =============================================================================== |
67 | @verbatim |
68 | ##### Initialization/de-initialization functions ##### |
68 | =============================================================================== |
69 | =============================================================================== |
69 | ##### Initialization/de-initialization functions ##### |
70 | 70 | =============================================================================== |
|
71 | @endverbatim |
71 | |
72 | * @{ |
72 | @endverbatim |
73 | */ |
73 | * @{ |
74 | 74 | */ |
|
75 | /** |
75 | |
76 | * @brief Initializes the USB Core |
76 | /** |
77 | * @param USBx USB Instance |
77 | * @brief Initializes the USB Core |
78 | * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains |
78 | * @param USBx USB Instance |
79 | * the configuration information for the specified USBx peripheral. |
79 | * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains |
80 | * @retval HAL status |
80 | * the configuration information for the specified USBx peripheral. |
81 | */ |
81 | * @retval HAL status |
82 | HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) |
82 | */ |
83 | { |
83 | HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) |
84 | HAL_StatusTypeDef ret; |
84 | { |
85 | 85 | HAL_StatusTypeDef ret; |
|
86 | 86 | ||
87 | /* Select FS Embedded PHY */ |
87 | /* Select FS Embedded PHY */ |
88 | USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; |
88 | USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; |
89 | 89 | ||
90 | /* Reset after a PHY select */ |
90 | /* Reset after a PHY select */ |
91 | ret = USB_CoreReset(USBx); |
91 | ret = USB_CoreReset(USBx); |
92 | 92 | ||
93 | /* Activate the USB Transceiver */ |
93 | /* Activate the USB Transceiver */ |
94 | USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; |
94 | USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; |
95 | 95 | ||
96 | return ret; |
96 | return ret; |
97 | } |
97 | } |
98 | 98 | ||
99 | 99 | ||
100 | /** |
100 | /** |
101 | * @brief Set the USB turnaround time |
101 | * @brief Set the USB turnaround time |
102 | * @param USBx USB Instance |
102 | * @param USBx USB Instance |
103 | * @param hclk: AHB clock frequency |
103 | * @param hclk: AHB clock frequency |
104 | * @retval USB turnaround time In PHY Clocks number |
104 | * @retval USB turnaround time In PHY Clocks number |
105 | */ |
105 | */ |
106 | HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, |
106 | HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, |
107 | uint32_t hclk, uint8_t speed) |
107 | uint32_t hclk, uint8_t speed) |
108 | { |
108 | { |
109 | uint32_t UsbTrd; |
109 | uint32_t UsbTrd; |
110 | 110 | ||
111 | /* The USBTRD is configured according to the tables below, depending on AHB frequency |
111 | /* The USBTRD is configured according to the tables below, depending on AHB frequency |
112 | used by application. In the low AHB frequency range it is used to stretch enough the USB response |
112 | used by application. In the low AHB frequency range it is used to stretch enough the USB response |
113 | time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access |
113 | time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access |
114 | latency to the Data FIFO */ |
114 | latency to the Data FIFO */ |
115 | if (speed == USBD_FS_SPEED) |
115 | if (speed == USBD_FS_SPEED) |
116 | { |
116 | { |
117 | if ((hclk >= 14200000U) && (hclk < 15000000U)) |
117 | if ((hclk >= 14200000U) && (hclk < 15000000U)) |
118 | { |
118 | { |
119 | /* hclk Clock Range between 14.2-15 MHz */ |
119 | /* hclk Clock Range between 14.2-15 MHz */ |
120 | UsbTrd = 0xFU; |
120 | UsbTrd = 0xFU; |
121 | } |
121 | } |
122 | else if ((hclk >= 15000000U) && (hclk < 16000000U)) |
122 | else if ((hclk >= 15000000U) && (hclk < 16000000U)) |
123 | { |
123 | { |
124 | /* hclk Clock Range between 15-16 MHz */ |
124 | /* hclk Clock Range between 15-16 MHz */ |
125 | UsbTrd = 0xEU; |
125 | UsbTrd = 0xEU; |
126 | } |
126 | } |
127 | else if ((hclk >= 16000000U) && (hclk < 17200000U)) |
127 | else if ((hclk >= 16000000U) && (hclk < 17200000U)) |
128 | { |
128 | { |
129 | /* hclk Clock Range between 16-17.2 MHz */ |
129 | /* hclk Clock Range between 16-17.2 MHz */ |
130 | UsbTrd = 0xDU; |
130 | UsbTrd = 0xDU; |
131 | } |
131 | } |
132 | else if ((hclk >= 17200000U) && (hclk < 18500000U)) |
132 | else if ((hclk >= 17200000U) && (hclk < 18500000U)) |
133 | { |
133 | { |
134 | /* hclk Clock Range between 17.2-18.5 MHz */ |
134 | /* hclk Clock Range between 17.2-18.5 MHz */ |
135 | UsbTrd = 0xCU; |
135 | UsbTrd = 0xCU; |
136 | } |
136 | } |
137 | else if ((hclk >= 18500000U) && (hclk < 20000000U)) |
137 | else if ((hclk >= 18500000U) && (hclk < 20000000U)) |
138 | { |
138 | { |
139 | /* hclk Clock Range between 18.5-20 MHz */ |
139 | /* hclk Clock Range between 18.5-20 MHz */ |
140 | UsbTrd = 0xBU; |
140 | UsbTrd = 0xBU; |
141 | } |
141 | } |
142 | else if ((hclk >= 20000000U) && (hclk < 21800000U)) |
142 | else if ((hclk >= 20000000U) && (hclk < 21800000U)) |
143 | { |
143 | { |
144 | /* hclk Clock Range between 20-21.8 MHz */ |
144 | /* hclk Clock Range between 20-21.8 MHz */ |
145 | UsbTrd = 0xAU; |
145 | UsbTrd = 0xAU; |
146 | } |
146 | } |
147 | else if ((hclk >= 21800000U) && (hclk < 24000000U)) |
147 | else if ((hclk >= 21800000U) && (hclk < 24000000U)) |
148 | { |
148 | { |
149 | /* hclk Clock Range between 21.8-24 MHz */ |
149 | /* hclk Clock Range between 21.8-24 MHz */ |
150 | UsbTrd = 0x9U; |
150 | UsbTrd = 0x9U; |
151 | } |
151 | } |
152 | else if ((hclk >= 24000000U) && (hclk < 27700000U)) |
152 | else if ((hclk >= 24000000U) && (hclk < 27700000U)) |
153 | { |
153 | { |
154 | /* hclk Clock Range between 24-27.7 MHz */ |
154 | /* hclk Clock Range between 24-27.7 MHz */ |
155 | UsbTrd = 0x8U; |
155 | UsbTrd = 0x8U; |
156 | } |
156 | } |
157 | else if ((hclk >= 27700000U) && (hclk < 32000000U)) |
157 | else if ((hclk >= 27700000U) && (hclk < 32000000U)) |
158 | { |
158 | { |
159 | /* hclk Clock Range between 27.7-32 MHz */ |
159 | /* hclk Clock Range between 27.7-32 MHz */ |
160 | UsbTrd = 0x7U; |
160 | UsbTrd = 0x7U; |
161 | } |
161 | } |
162 | else /* if(hclk >= 32000000) */ |
162 | else /* if(hclk >= 32000000) */ |
163 | { |
163 | { |
164 | /* hclk Clock Range between 32-200 MHz */ |
164 | /* hclk Clock Range between 32-200 MHz */ |
165 | UsbTrd = 0x6U; |
165 | UsbTrd = 0x6U; |
166 | } |
166 | } |
167 | } |
167 | } |
168 | else |
168 | else |
169 | { |
169 | { |
170 | UsbTrd = USBD_DEFAULT_TRDT_VALUE; |
170 | UsbTrd = USBD_DEFAULT_TRDT_VALUE; |
171 | } |
171 | } |
172 | 172 | ||
173 | USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; |
173 | USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; |
174 | USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT); |
174 | USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT); |
175 | 175 | ||
176 | return HAL_OK; |
176 | return HAL_OK; |
177 | } |
177 | } |
178 | 178 | ||
179 | /** |
179 | /** |
180 | * @brief USB_EnableGlobalInt |
180 | * @brief USB_EnableGlobalInt |
181 | * Enables the controller's Global Int in the AHB Config reg |
181 | * Enables the controller's Global Int in the AHB Config reg |
182 | * @param USBx Selected device |
182 | * @param USBx Selected device |
183 | * @retval HAL status |
183 | * @retval HAL status |
184 | */ |
184 | */ |
185 | HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) |
185 | HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) |
186 | { |
186 | { |
187 | USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT; |
187 | USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT; |
188 | return HAL_OK; |
188 | return HAL_OK; |
189 | } |
189 | } |
190 | 190 | ||
191 | /** |
191 | /** |
192 | * @brief USB_DisableGlobalInt |
192 | * @brief USB_DisableGlobalInt |
193 | * Disable the controller's Global Int in the AHB Config reg |
193 | * Disable the controller's Global Int in the AHB Config reg |
194 | * @param USBx Selected device |
194 | * @param USBx Selected device |
195 | * @retval HAL status |
195 | * @retval HAL status |
196 | */ |
196 | */ |
197 | HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) |
197 | HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) |
198 | { |
198 | { |
199 | USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; |
199 | USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; |
200 | return HAL_OK; |
200 | return HAL_OK; |
201 | } |
201 | } |
202 | 202 | ||
203 | /** |
203 | /** |
204 | * @brief USB_SetCurrentMode Set functional mode |
204 | * @brief USB_SetCurrentMode Set functional mode |
205 | * @param USBx Selected device |
205 | * @param USBx Selected device |
206 | * @param mode current core mode |
206 | * @param mode current core mode |
207 | * This parameter can be one of these values: |
207 | * This parameter can be one of these values: |
208 | * @arg USB_DEVICE_MODE Peripheral mode |
208 | * @arg USB_DEVICE_MODE Peripheral mode |
209 | * @arg USB_HOST_MODE Host mode |
209 | * @arg USB_HOST_MODE Host mode |
210 | * @retval HAL status |
210 | * @retval HAL status |
211 | */ |
211 | */ |
212 | HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_ModeTypeDef mode) |
212 | HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_ModeTypeDef mode) |
213 | { |
213 | { |
214 | uint32_t ms = 0U; |
214 | uint32_t ms = 0U; |
215 | 215 | ||
216 | USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); |
216 | USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); |
217 | 217 | ||
218 | if (mode == USB_HOST_MODE) |
218 | if (mode == USB_HOST_MODE) |
219 | { |
219 | { |
220 | USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; |
220 | USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; |
221 | 221 | ||
222 | do |
222 | do |
223 | { |
223 | { |
224 | HAL_Delay(1U); |
224 | HAL_Delay(1U); |
225 | ms++; |
225 | ms++; |
226 | } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < 50U)); |
226 | } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < 50U)); |
227 | } |
227 | } |
228 | else if (mode == USB_DEVICE_MODE) |
228 | else if (mode == USB_DEVICE_MODE) |
229 | { |
229 | { |
230 | USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; |
230 | USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; |
231 | 231 | ||
232 | do |
232 | do |
233 | { |
233 | { |
234 | HAL_Delay(1U); |
234 | HAL_Delay(1U); |
235 | ms++; |
235 | ms++; |
236 | } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < 50U)); |
236 | } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < 50U)); |
237 | } |
237 | } |
238 | else |
238 | else |
239 | { |
239 | { |
240 | return HAL_ERROR; |
240 | return HAL_ERROR; |
241 | } |
241 | } |
242 | 242 | ||
243 | if (ms == 50U) |
243 | if (ms == 50U) |
244 | { |
244 | { |
245 | return HAL_ERROR; |
245 | return HAL_ERROR; |
246 | } |
246 | } |
247 | 247 | ||
248 | return HAL_OK; |
248 | return HAL_OK; |
249 | } |
249 | } |
250 | 250 | ||
251 | /** |
251 | /** |
252 | * @brief USB_DevInit Initializes the USB_OTG controller registers |
252 | * @brief USB_DevInit Initializes the USB_OTG controller registers |
253 | * for device mode |
253 | * for device mode |
254 | * @param USBx Selected device |
254 | * @param USBx Selected device |
255 | * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains |
255 | * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains |
256 | * the configuration information for the specified USBx peripheral. |
256 | * the configuration information for the specified USBx peripheral. |
257 | * @retval HAL status |
257 | * @retval HAL status |
258 | */ |
258 | */ |
259 | HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) |
259 | HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) |
260 | { |
260 | { |
261 | HAL_StatusTypeDef ret = HAL_OK; |
261 | HAL_StatusTypeDef ret = HAL_OK; |
262 | uint32_t USBx_BASE = (uint32_t)USBx; |
262 | uint32_t USBx_BASE = (uint32_t)USBx; |
263 | uint32_t i; |
263 | uint32_t i; |
264 | 264 | ||
265 | for (i = 0U; i < 15U; i++) |
265 | for (i = 0U; i < 15U; i++) |
266 | { |
266 | { |
267 | USBx->DIEPTXF[i] = 0U; |
267 | USBx->DIEPTXF[i] = 0U; |
268 | } |
268 | } |
269 | 269 | ||
270 | /* Enable HW VBUS sensing */ |
270 | /* Enable HW VBUS sensing */ |
271 | USBx->GCCFG |= USB_OTG_GCCFG_VBUSBSEN; |
271 | USBx->GCCFG |= USB_OTG_GCCFG_VBUSBSEN; |
272 | 272 | ||
273 | /* Restart the Phy Clock */ |
273 | /* Restart the Phy Clock */ |
274 | USBx_PCGCCTL = 0U; |
274 | USBx_PCGCCTL = 0U; |
275 | 275 | ||
276 | /* Device mode configuration */ |
276 | /* Set Core speed to Full speed mode */ |
277 | USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80; |
277 | (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL); |
278 | 278 | ||
279 | /* Set Core speed to Full speed mode */ |
279 | /* Flush the FIFOs */ |
280 | (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL); |
280 | if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ |
281 | 281 | { |
|
282 | /* Flush the FIFOs */ |
282 | ret = HAL_ERROR; |
283 | if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ |
283 | } |
284 | { |
284 | |
285 | ret = HAL_ERROR; |
285 | if (USB_FlushRxFifo(USBx) != HAL_OK) |
286 | } |
286 | { |
287 | 287 | ret = HAL_ERROR; |
|
288 | if (USB_FlushRxFifo(USBx) != HAL_OK) |
288 | } |
289 | { |
289 | |
290 | ret = HAL_ERROR; |
290 | /* Clear all pending Device Interrupts */ |
291 | } |
291 | USBx_DEVICE->DIEPMSK = 0U; |
292 | 292 | USBx_DEVICE->DOEPMSK = 0U; |
|
293 | /* Clear all pending Device Interrupts */ |
293 | USBx_DEVICE->DAINTMSK = 0U; |
294 | USBx_DEVICE->DIEPMSK = 0U; |
294 | |
295 | USBx_DEVICE->DOEPMSK = 0U; |
295 | for (i = 0U; i < cfg.dev_endpoints; i++) |
296 | USBx_DEVICE->DAINTMSK = 0U; |
296 | { |
297 | 297 | if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) |
|
298 | for (i = 0U; i < cfg.dev_endpoints; i++) |
298 | { |
299 | { |
299 | if (i == 0U) |
300 | if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) |
300 | { |
301 | { |
301 | USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK; |
302 | if (i == 0U) |
302 | } |
303 | { |
303 | else |
304 | USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK; |
304 | { |
305 | } |
305 | USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK; |
306 | else |
306 | } |
307 | { |
307 | } |
308 | USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK; |
308 | else |
309 | } |
309 | { |
310 | } |
310 | USBx_INEP(i)->DIEPCTL = 0U; |
311 | else |
311 | } |
312 | { |
312 | |
313 | USBx_INEP(i)->DIEPCTL = 0U; |
313 | USBx_INEP(i)->DIEPTSIZ = 0U; |
314 | } |
314 | USBx_INEP(i)->DIEPINT = 0xFB7FU; |
315 | 315 | } |
|
316 | USBx_INEP(i)->DIEPTSIZ = 0U; |
316 | |
317 | USBx_INEP(i)->DIEPINT = 0xFB7FU; |
317 | for (i = 0U; i < cfg.dev_endpoints; i++) |
318 | } |
318 | { |
319 | 319 | if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) |
|
320 | for (i = 0U; i < cfg.dev_endpoints; i++) |
320 | { |
321 | { |
321 | if (i == 0U) |
322 | if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) |
322 | { |
323 | { |
323 | USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK; |
324 | if (i == 0U) |
324 | } |
325 | { |
325 | else |
326 | USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK; |
326 | { |
327 | } |
327 | USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK; |
328 | else |
328 | } |
329 | { |
329 | } |
330 | USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK; |
330 | else |
331 | } |
331 | { |
332 | } |
332 | USBx_OUTEP(i)->DOEPCTL = 0U; |
333 | else |
333 | } |
334 | { |
334 | |
335 | USBx_OUTEP(i)->DOEPCTL = 0U; |
335 | USBx_OUTEP(i)->DOEPTSIZ = 0U; |
336 | } |
336 | USBx_OUTEP(i)->DOEPINT = 0xFB7FU; |
337 | 337 | } |
|
338 | USBx_OUTEP(i)->DOEPTSIZ = 0U; |
338 | |
339 | USBx_OUTEP(i)->DOEPINT = 0xFB7FU; |
339 | USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); |
340 | } |
340 | |
341 | 341 | /* Disable all interrupts. */ |
|
342 | USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); |
342 | USBx->GINTMSK = 0U; |
343 | 343 | ||
344 | /* Disable all interrupts. */ |
344 | /* Clear any pending interrupts */ |
345 | USBx->GINTMSK = 0U; |
345 | USBx->GINTSTS = 0xBFFFFFFFU; |
346 | 346 | ||
347 | /* Clear any pending interrupts */ |
347 | /* Enable the common interrupts */ |
348 | USBx->GINTSTS = 0xBFFFFFFFU; |
348 | USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; |
349 | 349 | ||
350 | /* Enable the common interrupts */ |
350 | /* Enable interrupts matching to the Device mode ONLY */ |
351 | USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; |
351 | USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST | |
352 | 352 | USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT | |
|
353 | /* Enable interrupts matching to the Device mode ONLY */ |
353 | USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM | |
354 | USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST | |
354 | USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM; |
355 | USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT | |
355 | |
356 | USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM | |
356 | if (cfg.Sof_enable != 0U) |
357 | USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM; |
357 | { |
358 | 358 | USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM; |
|
359 | if (cfg.Sof_enable != 0U) |
359 | } |
360 | { |
360 | |
361 | USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM; |
361 | if (cfg.vbus_sensing_enable == 1U) |
362 | } |
362 | { |
363 | 363 | USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); |
|
364 | if (cfg.vbus_sensing_enable == 1U) |
364 | } |
365 | { |
365 | |
366 | USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); |
366 | return ret; |
367 | } |
367 | } |
368 | 368 | ||
369 | return ret; |
369 | /** |
370 | } |
370 | * @brief USB_FlushTxFifo Flush a Tx FIFO |
371 | 371 | * @param USBx Selected device |
|
372 | /** |
372 | * @param num FIFO number |
373 | * @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO |
373 | * This parameter can be a value from 1 to 15 |
374 | * @param USBx Selected device |
374 | 15 means Flush all Tx FIFOs |
375 | * @param num FIFO number |
375 | * @retval HAL status |
376 | * This parameter can be a value from 1 to 15 |
376 | */ |
377 | 15 means Flush all Tx FIFOs |
377 | HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) |
378 | * @retval HAL status |
378 | { |
379 | */ |
379 | __IO uint32_t count = 0U; |
380 | HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) |
380 | |
381 | { |
381 | /* Wait for AHB master IDLE state. */ |
382 | uint32_t count = 0U; |
382 | do |
383 | 383 | { |
|
384 | USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); |
384 | count++; |
385 | 385 | ||
386 | do |
386 | if (count > 200000U) |
387 | { |
387 | { |
388 | if (++count > 200000U) |
388 | return HAL_TIMEOUT; |
389 | { |
389 | } |
390 | return HAL_TIMEOUT; |
390 | } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); |
391 | } |
391 | |
392 | } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); |
392 | /* Flush TX Fifo */ |
393 | 393 | count = 0U; |
|
394 | return HAL_OK; |
394 | USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); |
395 | } |
395 | |
396 | 396 | do |
|
397 | /** |
397 | { |
398 | * @brief USB_FlushRxFifo : Flush Rx FIFO |
398 | count++; |
399 | * @param USBx Selected device |
399 | |
400 | * @retval HAL status |
400 | if (count > 200000U) |
401 | */ |
401 | { |
402 | HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) |
402 | return HAL_TIMEOUT; |
403 | { |
403 | } |
404 | uint32_t count = 0; |
404 | } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); |
405 | 405 | ||
406 | USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; |
406 | return HAL_OK; |
407 | 407 | } |
|
408 | do |
408 | |
409 | { |
409 | /** |
410 | if (++count > 200000U) |
410 | * @brief USB_FlushRxFifo Flush Rx FIFO |
411 | { |
411 | * @param USBx Selected device |
412 | return HAL_TIMEOUT; |
412 | * @retval HAL status |
413 | } |
413 | */ |
414 | } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); |
414 | HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) |
415 | 415 | { |
|
416 | return HAL_OK; |
416 | __IO uint32_t count = 0U; |
417 | } |
417 | |
418 | 418 | /* Wait for AHB master IDLE state. */ |
|
419 | /** |
419 | do |
420 | * @brief USB_SetDevSpeed Initializes the DevSpd field of DCFG register |
420 | { |
421 | * depending the PHY type and the enumeration speed of the device. |
421 | count++; |
422 | * @param USBx Selected device |
422 | |
423 | * @param speed device speed |
423 | if (count > 200000U) |
424 | * This parameter can be one of these values: |
424 | { |
425 | * @arg USB_OTG_SPEED_FULL: Full speed mode |
425 | return HAL_TIMEOUT; |
426 | * @retval Hal status |
426 | } |
427 | */ |
427 | } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); |
428 | HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed) |
428 | |
429 | { |
429 | /* Flush RX Fifo */ |
430 | uint32_t USBx_BASE = (uint32_t)USBx; |
430 | count = 0U; |
431 | 431 | USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; |
|
432 | USBx_DEVICE->DCFG |= speed; |
432 | |
433 | return HAL_OK; |
433 | do |
434 | } |
434 | { |
435 | 435 | count++; |
|
436 | /** |
436 | |
437 | * @brief USB_GetDevSpeed Return the Dev Speed |
437 | if (count > 200000U) |
438 | * @param USBx Selected device |
438 | { |
439 | * @retval speed device speed |
439 | return HAL_TIMEOUT; |
440 | * This parameter can be one of these values: |
440 | } |
441 | * @arg USBD_FS_SPEED: Full speed mode |
441 | } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); |
442 | */ |
442 | |
443 | uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) |
443 | return HAL_OK; |
444 | { |
444 | } |
445 | uint32_t USBx_BASE = (uint32_t)USBx; |
445 | |
446 | uint8_t speed; |
446 | /** |
447 | uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD; |
447 | * @brief USB_SetDevSpeed Initializes the DevSpd field of DCFG register |
448 | 448 | * depending the PHY type and the enumeration speed of the device. |
|
449 | if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) || |
449 | * @param USBx Selected device |
450 | (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ)) |
450 | * @param speed device speed |
451 | { |
451 | * This parameter can be one of these values: |
452 | speed = USBD_FS_SPEED; |
452 | * @arg USB_OTG_SPEED_FULL: Full speed mode |
453 | } |
453 | * @retval Hal status |
454 | else |
454 | */ |
455 | { |
455 | HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed) |
456 | speed = 0xFU; |
456 | { |
457 | } |
457 | uint32_t USBx_BASE = (uint32_t)USBx; |
458 | 458 | ||
459 | return speed; |
459 | USBx_DEVICE->DCFG |= speed; |
460 | } |
460 | return HAL_OK; |
461 | 461 | } |
|
462 | /** |
462 | |
463 | * @brief Activate and configure an endpoint |
463 | /** |
464 | * @param USBx Selected device |
464 | * @brief USB_GetDevSpeed Return the Dev Speed |
465 | * @param ep pointer to endpoint structure |
465 | * @param USBx Selected device |
466 | * @retval HAL status |
466 | * @retval speed device speed |
467 | */ |
467 | * This parameter can be one of these values: |
468 | HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) |
468 | * @arg USBD_FS_SPEED: Full speed mode |
469 | { |
469 | */ |
470 | uint32_t USBx_BASE = (uint32_t)USBx; |
470 | uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) |
471 | uint32_t epnum = (uint32_t)ep->num; |
471 | { |
472 | 472 | uint32_t USBx_BASE = (uint32_t)USBx; |
|
473 | if (ep->is_in == 1U) |
473 | uint8_t speed; |
474 | { |
474 | uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD; |
475 | USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); |
475 | |
476 | 476 | if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) || |
|
477 | if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U) |
477 | (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ)) |
478 | { |
478 | { |
479 | USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | |
479 | speed = USBD_FS_SPEED; |
480 | ((uint32_t)ep->type << 18) | (epnum << 22) | |
480 | } |
481 | USB_OTG_DIEPCTL_SD0PID_SEVNFRM | |
481 | else |
482 | USB_OTG_DIEPCTL_USBAEP; |
482 | { |
483 | } |
483 | speed = 0xFU; |
484 | } |
484 | } |
485 | else |
485 | |
486 | { |
486 | return speed; |
487 | USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); |
487 | } |
488 | 488 | ||
489 | if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) |
489 | /** |
490 | { |
490 | * @brief Activate and configure an endpoint |
491 | USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | |
491 | * @param USBx Selected device |
492 | ((uint32_t)ep->type << 18) | |
492 | * @param ep pointer to endpoint structure |
493 | USB_OTG_DIEPCTL_SD0PID_SEVNFRM | |
493 | * @retval HAL status |
494 | USB_OTG_DOEPCTL_USBAEP; |
494 | */ |
495 | } |
495 | HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) |
496 | } |
496 | { |
497 | return HAL_OK; |
497 | uint32_t USBx_BASE = (uint32_t)USBx; |
498 | } |
498 | uint32_t epnum = (uint32_t)ep->num; |
499 | 499 | ||
500 | /** |
500 | if (ep->is_in == 1U) |
501 | * @brief Activate and configure a dedicated endpoint |
501 | { |
502 | * @param USBx Selected device |
502 | USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); |
503 | * @param ep pointer to endpoint structure |
503 | |
504 | * @retval HAL status |
504 | if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U) |
505 | */ |
505 | { |
506 | HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) |
506 | USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | |
507 | { |
507 | ((uint32_t)ep->type << 18) | (epnum << 22) | |
508 | uint32_t USBx_BASE = (uint32_t)USBx; |
508 | USB_OTG_DIEPCTL_SD0PID_SEVNFRM | |
509 | uint32_t epnum = (uint32_t)ep->num; |
509 | USB_OTG_DIEPCTL_USBAEP; |
510 | 510 | } |
|
511 | /* Read DEPCTLn register */ |
511 | } |
512 | if (ep->is_in == 1U) |
512 | else |
513 | { |
513 | { |
514 | if (((USBx_INEP(epnum)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U) |
514 | USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); |
515 | { |
515 | |
516 | USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | |
516 | if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) |
517 | ((uint32_t)ep->type << 18) | (epnum << 22) | |
517 | { |
518 | USB_OTG_DIEPCTL_SD0PID_SEVNFRM | |
518 | USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | |
519 | USB_OTG_DIEPCTL_USBAEP; |
519 | ((uint32_t)ep->type << 18) | |
520 | } |
520 | USB_OTG_DIEPCTL_SD0PID_SEVNFRM | |
521 | 521 | USB_OTG_DOEPCTL_USBAEP; |
|
522 | USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); |
522 | } |
523 | } |
523 | } |
524 | else |
524 | return HAL_OK; |
525 | { |
525 | } |
526 | if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) |
526 | |
527 | { |
527 | /** |
528 | USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | |
528 | * @brief Activate and configure a dedicated endpoint |
529 | ((uint32_t)ep->type << 18) | (epnum << 22) | |
529 | * @param USBx Selected device |
530 | USB_OTG_DOEPCTL_USBAEP; |
530 | * @param ep pointer to endpoint structure |
531 | } |
531 | * @retval HAL status |
532 | 532 | */ |
|
533 | USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); |
533 | HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) |
534 | } |
534 | { |
535 | 535 | uint32_t USBx_BASE = (uint32_t)USBx; |
|
536 | return HAL_OK; |
536 | uint32_t epnum = (uint32_t)ep->num; |
537 | } |
537 | |
538 | 538 | /* Read DEPCTLn register */ |
|
539 | /** |
539 | if (ep->is_in == 1U) |
540 | * @brief De-activate and de-initialize an endpoint |
540 | { |
541 | * @param USBx Selected device |
541 | if (((USBx_INEP(epnum)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U) |
542 | * @param ep pointer to endpoint structure |
542 | { |
543 | * @retval HAL status |
543 | USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | |
544 | */ |
544 | ((uint32_t)ep->type << 18) | (epnum << 22) | |
545 | HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) |
545 | USB_OTG_DIEPCTL_SD0PID_SEVNFRM | |
546 | { |
546 | USB_OTG_DIEPCTL_USBAEP; |
547 | uint32_t USBx_BASE = (uint32_t)USBx; |
547 | } |
548 | uint32_t epnum = (uint32_t)ep->num; |
548 | |
549 | 549 | USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); |
|
550 | /* Read DEPCTLn register */ |
550 | } |
551 | if (ep->is_in == 1U) |
551 | else |
552 | { |
552 | { |
553 | if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) |
553 | if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) |
554 | { |
554 | { |
555 | USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; |
555 | USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | |
556 | USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; |
556 | ((uint32_t)ep->type << 18) | (epnum << 22) | |
557 | } |
557 | USB_OTG_DOEPCTL_USBAEP; |
558 | 558 | } |
|
559 | USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); |
559 | |
560 | USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); |
560 | USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); |
561 | USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | |
561 | } |
562 | USB_OTG_DIEPCTL_MPSIZ | |
562 | |
563 | USB_OTG_DIEPCTL_TXFNUM | |
563 | return HAL_OK; |
564 | USB_OTG_DIEPCTL_SD0PID_SEVNFRM | |
564 | } |
565 | USB_OTG_DIEPCTL_EPTYP); |
565 | |
566 | } |
566 | /** |
567 | else |
567 | * @brief De-activate and de-initialize an endpoint |
568 | { |
568 | * @param USBx Selected device |
569 | if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) |
569 | * @param ep pointer to endpoint structure |
570 | { |
570 | * @retval HAL status |
571 | USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; |
571 | */ |
572 | USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; |
572 | HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) |
573 | } |
573 | { |
574 | 574 | uint32_t USBx_BASE = (uint32_t)USBx; |
|
575 | USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); |
575 | uint32_t epnum = (uint32_t)ep->num; |
576 | USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); |
576 | |
577 | USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP | |
577 | /* Read DEPCTLn register */ |
578 | USB_OTG_DOEPCTL_MPSIZ | |
578 | if (ep->is_in == 1U) |
579 | USB_OTG_DOEPCTL_SD0PID_SEVNFRM | |
579 | { |
580 | USB_OTG_DOEPCTL_EPTYP); |
580 | if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) |
581 | } |
581 | { |
582 | 582 | USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; |
|
583 | return HAL_OK; |
583 | USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; |
584 | } |
584 | } |
585 | 585 | ||
586 | /** |
586 | USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); |
587 | * @brief De-activate and de-initialize a dedicated endpoint |
587 | USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); |
588 | * @param USBx Selected device |
588 | USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | |
589 | * @param ep pointer to endpoint structure |
589 | USB_OTG_DIEPCTL_MPSIZ | |
590 | * @retval HAL status |
590 | USB_OTG_DIEPCTL_TXFNUM | |
591 | */ |
591 | USB_OTG_DIEPCTL_SD0PID_SEVNFRM | |
592 | HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) |
592 | USB_OTG_DIEPCTL_EPTYP); |
593 | { |
593 | } |
594 | uint32_t USBx_BASE = (uint32_t)USBx; |
594 | else |
595 | uint32_t epnum = (uint32_t)ep->num; |
595 | { |
596 | 596 | if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) |
|
597 | /* Read DEPCTLn register */ |
597 | { |
598 | if (ep->is_in == 1U) |
598 | USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; |
599 | { |
599 | USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; |
600 | if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) |
600 | } |
601 | { |
601 | |
602 | USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; |
602 | USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); |
603 | USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; |
603 | USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); |
604 | } |
604 | USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP | |
605 | 605 | USB_OTG_DOEPCTL_MPSIZ | |
|
606 | USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; |
606 | USB_OTG_DOEPCTL_SD0PID_SEVNFRM | |
607 | USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); |
607 | USB_OTG_DOEPCTL_EPTYP); |
608 | } |
608 | } |
609 | else |
609 | |
610 | { |
610 | return HAL_OK; |
611 | if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) |
611 | } |
612 | { |
612 | |
613 | USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; |
613 | /** |
614 | USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; |
614 | * @brief De-activate and de-initialize a dedicated endpoint |
615 | } |
615 | * @param USBx Selected device |
616 | 616 | * @param ep pointer to endpoint structure |
|
617 | USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; |
617 | * @retval HAL status |
618 | USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); |
618 | */ |
619 | } |
619 | HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) |
620 | 620 | { |
|
621 | return HAL_OK; |
621 | uint32_t USBx_BASE = (uint32_t)USBx; |
622 | } |
622 | uint32_t epnum = (uint32_t)ep->num; |
623 | 623 | ||
624 | /** |
624 | /* Read DEPCTLn register */ |
625 | * @brief USB_EPStartXfer : setup and starts a transfer over an EP |
625 | if (ep->is_in == 1U) |
626 | * @param USBx Selected device |
626 | { |
627 | * @param ep pointer to endpoint structure |
627 | if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) |
628 | * @retval HAL status |
628 | { |
629 | */ |
629 | USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; |
630 | HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) |
630 | USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; |
631 | { |
631 | } |
632 | uint32_t USBx_BASE = (uint32_t)USBx; |
632 | |
633 | uint32_t epnum = (uint32_t)ep->num; |
633 | USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; |
634 | uint16_t pktcnt; |
634 | USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); |
635 | 635 | } |
|
636 | /* IN endpoint */ |
636 | else |
637 | if (ep->is_in == 1U) |
637 | { |
638 | { |
638 | if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) |
639 | /* Zero Length Packet? */ |
639 | { |
640 | if (ep->xfer_len == 0U) |
640 | USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; |
641 | { |
641 | USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; |
642 | USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); |
642 | } |
643 | USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); |
643 | |
644 | USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); |
644 | USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; |
645 | } |
645 | USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); |
646 | else |
646 | } |
647 | { |
647 | |
648 | /* Program the transfer size and packet count |
648 | return HAL_OK; |
649 | * as follows: xfersize = N * maxpacket + |
649 | } |
650 | * short_packet pktcnt = N + (short_packet |
650 | |
651 | * exist ? 1 : 0) |
651 | /** |
652 | */ |
652 | * @brief USB_EPStartXfer : setup and starts a transfer over an EP |
653 | USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); |
653 | * @param USBx Selected device |
654 | USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); |
654 | * @param ep pointer to endpoint structure |
655 | USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & |
655 | * @retval HAL status |
656 | (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); |
656 | */ |
657 | 657 | HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) |
|
658 | USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); |
658 | { |
659 | 659 | uint32_t USBx_BASE = (uint32_t)USBx; |
|
660 | if (ep->type == EP_TYPE_ISOC) |
660 | uint32_t epnum = (uint32_t)ep->num; |
661 | { |
661 | uint16_t pktcnt; |
662 | USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); |
662 | |
663 | USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29)); |
663 | /* IN endpoint */ |
664 | } |
664 | if (ep->is_in == 1U) |
665 | } |
665 | { |
666 | /* EP enable, IN data in FIFO */ |
666 | /* Zero Length Packet? */ |
667 | USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); |
667 | if (ep->xfer_len == 0U) |
668 | 668 | { |
|
669 | if (ep->type != EP_TYPE_ISOC) |
669 | USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); |
670 | { |
670 | USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); |
671 | /* Enable the Tx FIFO Empty Interrupt for this EP */ |
671 | USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); |
672 | if (ep->xfer_len > 0U) |
672 | } |
673 | { |
673 | else |
674 | USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); |
674 | { |
675 | } |
675 | /* Program the transfer size and packet count |
676 | } |
676 | * as follows: xfersize = N * maxpacket + |
677 | else |
677 | * short_packet pktcnt = N + (short_packet |
678 | { |
678 | * exist ? 1 : 0) |
679 | if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) |
679 | */ |
680 | { |
680 | USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); |
681 | USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; |
681 | USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); |
682 | } |
682 | |
683 | else |
683 | if (epnum == 0U) |
684 | { |
684 | { |
685 | USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; |
685 | if (ep->xfer_len > ep->maxpacket) |
686 | } |
686 | { |
687 | 687 | ep->xfer_len = ep->maxpacket; |
|
688 | (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len); |
688 | } |
689 | } |
689 | |
690 | } |
690 | USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); |
691 | else /* OUT endpoint */ |
691 | } |
692 | { |
692 | else |
693 | /* Program the transfer size and packet count as follows: |
693 | { |
694 | * pktcnt = N |
694 | USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & |
695 | * xfersize = N * maxpacket |
695 | (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); |
696 | */ |
696 | } |
697 | USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); |
697 | |
698 | USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); |
698 | USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); |
699 | 699 | ||
700 | if (ep->xfer_len == 0U) |
700 | if (ep->type == EP_TYPE_ISOC) |
701 | { |
701 | { |
702 | USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); |
702 | USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); |
703 | USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); |
703 | USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29)); |
704 | } |
704 | } |
705 | else |
705 | } |
706 | { |
706 | /* EP enable, IN data in FIFO */ |
707 | pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); |
707 | USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); |
708 | USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); |
708 | |
709 | USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt); |
709 | if (ep->type != EP_TYPE_ISOC) |
710 | } |
710 | { |
711 | 711 | /* Enable the Tx FIFO Empty Interrupt for this EP */ |
|
712 | if (ep->type == EP_TYPE_ISOC) |
712 | if (ep->xfer_len > 0U) |
713 | { |
713 | { |
714 | if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) |
714 | USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); |
715 | { |
715 | } |
716 | USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; |
716 | } |
717 | } |
717 | else |
718 | else |
718 | { |
719 | { |
719 | if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) |
720 | USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; |
720 | { |
721 | } |
721 | USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; |
722 | } |
722 | } |
723 | /* EP enable */ |
723 | else |
724 | USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); |
724 | { |
725 | } |
725 | USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; |
726 | 726 | } |
|
727 | return HAL_OK; |
727 | |
728 | } |
728 | (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len); |
729 | 729 | } |
|
730 | /** |
730 | } |
731 | * @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0 |
731 | else /* OUT endpoint */ |
732 | * @param USBx Selected device |
732 | { |
733 | * @param ep pointer to endpoint structure |
733 | /* Program the transfer size and packet count as follows: |
734 | * @retval HAL status |
734 | * pktcnt = N |
735 | */ |
735 | * xfersize = N * maxpacket |
736 | HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) |
736 | */ |
737 | { |
737 | USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); |
738 | uint32_t USBx_BASE = (uint32_t)USBx; |
738 | USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); |
739 | uint32_t epnum = (uint32_t)ep->num; |
739 | |
740 | 740 | if (epnum == 0U) |
|
741 | /* IN endpoint */ |
741 | { |
742 | if (ep->is_in == 1U) |
742 | if (ep->xfer_len > 0U) |
743 | { |
743 | { |
744 | /* Zero Length Packet? */ |
744 | ep->xfer_len = ep->maxpacket; |
745 | if (ep->xfer_len == 0U) |
745 | } |
746 | { |
746 | |
747 | USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); |
747 | /* Store transfer size, for EP0 this is equal to endpoint max packet size */ |
748 | USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); |
748 | ep->xfer_size = ep->maxpacket; |
749 | USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); |
749 | |
750 | } |
750 | USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size); |
751 | else |
751 | USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); |
752 | { |
752 | } |
753 | /* Program the transfer size and packet count |
753 | else |
754 | * as follows: xfersize = N * maxpacket + |
754 | { |
755 | * short_packet pktcnt = N + (short_packet |
755 | if (ep->xfer_len == 0U) |
756 | * exist ? 1 : 0) |
756 | { |
757 | */ |
757 | USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); |
758 | USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); |
758 | USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); |
759 | USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); |
759 | } |
760 | 760 | else |
|
761 | if (ep->xfer_len > ep->maxpacket) |
761 | { |
762 | { |
762 | pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); |
763 | ep->xfer_len = ep->maxpacket; |
763 | ep->xfer_size = ep->maxpacket * pktcnt; |
764 | } |
764 | |
765 | USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); |
765 | USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); |
766 | USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); |
766 | USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size; |
767 | } |
767 | } |
768 | 768 | } |
|
769 | /* EP enable, IN data in FIFO */ |
769 | |
770 | USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); |
770 | if (ep->type == EP_TYPE_ISOC) |
771 | 771 | { |
|
772 | /* Enable the Tx FIFO Empty Interrupt for this EP */ |
772 | if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) |
773 | if (ep->xfer_len > 0U) |
773 | { |
774 | { |
774 | USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; |
775 | USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); |
775 | } |
776 | } |
776 | else |
777 | } |
777 | { |
778 | else /* OUT endpoint */ |
778 | USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; |
779 | { |
779 | } |
780 | /* Program the transfer size and packet count as follows: |
780 | } |
781 | * pktcnt = N |
781 | /* EP enable */ |
782 | * xfersize = N * maxpacket |
782 | USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); |
783 | */ |
783 | } |
784 | USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); |
784 | |
785 | USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); |
785 | return HAL_OK; |
786 | 786 | } |
|
787 | if (ep->xfer_len > 0U) |
787 | |
788 | { |
788 | |
789 | ep->xfer_len = ep->maxpacket; |
789 | /** |
790 | } |
790 | * @brief USB_EPStoptXfer Stop transfer on an EP |
791 | 791 | * @param USBx usb device instance |
|
792 | USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); |
792 | * @param ep pointer to endpoint structure |
793 | USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket)); |
793 | * @retval HAL status |
794 | 794 | */ |
|
795 | /* EP enable */ |
795 | HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) |
796 | USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); |
796 | { |
797 | } |
797 | __IO uint32_t count = 0U; |
798 | 798 | HAL_StatusTypeDef ret = HAL_OK; |
|
799 | return HAL_OK; |
799 | uint32_t USBx_BASE = (uint32_t)USBx; |
800 | } |
800 | |
801 | 801 | /* IN endpoint */ |
|
802 | /** |
802 | if (ep->is_in == 1U) |
803 | * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated |
803 | { |
804 | * with the EP/channel |
804 | /* EP enable, IN data in FIFO */ |
805 | * @param USBx Selected device |
805 | if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) |
806 | * @param src pointer to source buffer |
806 | { |
807 | * @param ch_ep_num endpoint or host channel number |
807 | USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_SNAK); |
808 | * @param len Number of bytes to write |
808 | USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_EPDIS); |
809 | * @retval HAL status |
809 | |
810 | */ |
810 | do |
811 | HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, |
811 | { |
812 | uint8_t ch_ep_num, uint16_t len) |
812 | count++; |
813 | { |
813 | |
814 | uint32_t USBx_BASE = (uint32_t)USBx; |
814 | if (count > 10000U) |
815 | uint8_t *pSrc = src; |
815 | { |
816 | uint32_t count32b; |
816 | ret = HAL_ERROR; |
817 | uint32_t i; |
817 | break; |
818 | 818 | } |
|
819 | count32b = ((uint32_t)len + 3U) / 4U; |
819 | } while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA); |
820 | for (i = 0U; i < count32b; i++) |
820 | } |
821 | { |
821 | } |
822 | USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc); |
822 | else /* OUT endpoint */ |
823 | pSrc++; |
823 | { |
824 | pSrc++; |
824 | if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) |
825 | pSrc++; |
825 | { |
826 | pSrc++; |
826 | USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK); |
827 | } |
827 | USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS); |
828 | 828 | ||
829 | return HAL_OK; |
829 | do |
830 | } |
830 | { |
831 | 831 | count++; |
|
832 | /** |
832 | |
833 | * @brief USB_ReadPacket : read a packet from the RX FIFO |
833 | if (count > 10000U) |
834 | * @param USBx Selected device |
834 | { |
835 | * @param dest source pointer |
835 | ret = HAL_ERROR; |
836 | * @param len Number of bytes to read |
836 | break; |
837 | * @retval pointer to destination buffer |
837 | } |
838 | */ |
838 | } while (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA); |
839 | void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) |
839 | } |
840 | { |
840 | } |
841 | uint32_t USBx_BASE = (uint32_t)USBx; |
841 | |
842 | uint8_t *pDest = dest; |
842 | return ret; |
843 | uint32_t pData; |
843 | } |
844 | uint32_t i; |
844 | |
845 | uint32_t count32b = (uint32_t)len >> 2U; |
845 | |
846 | uint16_t remaining_bytes = len % 4U; |
846 | /** |
847 | 847 | * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated |
|
848 | for (i = 0U; i < count32b; i++) |
848 | * with the EP/channel |
849 | { |
849 | * @param USBx Selected device |
850 | __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U)); |
850 | * @param src pointer to source buffer |
851 | pDest++; |
851 | * @param ch_ep_num endpoint or host channel number |
852 | pDest++; |
852 | * @param len Number of bytes to write |
853 | pDest++; |
853 | * @retval HAL status |
854 | pDest++; |
854 | */ |
855 | } |
855 | HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, |
856 | 856 | uint8_t ch_ep_num, uint16_t len) |
|
857 | /* When Number of data is not word aligned, read the remaining byte */ |
857 | { |
858 | if (remaining_bytes != 0U) |
858 | uint32_t USBx_BASE = (uint32_t)USBx; |
859 | { |
859 | uint8_t *pSrc = src; |
860 | i = 0U; |
860 | uint32_t count32b; |
861 | __UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U)); |
861 | uint32_t i; |
862 | 862 | ||
863 | do |
863 | count32b = ((uint32_t)len + 3U) / 4U; |
864 | { |
864 | for (i = 0U; i < count32b; i++) |
865 | *(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i))); |
865 | { |
866 | i++; |
866 | USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc); |
867 | pDest++; |
867 | pSrc++; |
868 | remaining_bytes--; |
868 | pSrc++; |
869 | } while (remaining_bytes != 0U); |
869 | pSrc++; |
870 | } |
870 | pSrc++; |
871 | 871 | } |
|
872 | return ((void *)pDest); |
872 | |
873 | } |
873 | return HAL_OK; |
874 | 874 | } |
|
875 | /** |
875 | |
876 | * @brief USB_EPSetStall : set a stall condition over an EP |
876 | /** |
877 | * @param USBx Selected device |
877 | * @brief USB_ReadPacket : read a packet from the RX FIFO |
878 | * @param ep pointer to endpoint structure |
878 | * @param USBx Selected device |
879 | * @retval HAL status |
879 | * @param dest source pointer |
880 | */ |
880 | * @param len Number of bytes to read |
881 | HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) |
881 | * @retval pointer to destination buffer |
882 | { |
882 | */ |
883 | uint32_t USBx_BASE = (uint32_t)USBx; |
883 | void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) |
884 | uint32_t epnum = (uint32_t)ep->num; |
884 | { |
885 | 885 | uint32_t USBx_BASE = (uint32_t)USBx; |
|
886 | if (ep->is_in == 1U) |
886 | uint8_t *pDest = dest; |
887 | { |
887 | uint32_t pData; |
888 | if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U)) |
888 | uint32_t i; |
889 | { |
889 | uint32_t count32b = (uint32_t)len >> 2U; |
890 | USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); |
890 | uint16_t remaining_bytes = len % 4U; |
891 | } |
891 | |
892 | USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; |
892 | for (i = 0U; i < count32b; i++) |
893 | } |
893 | { |
894 | else |
894 | __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U)); |
895 | { |
895 | pDest++; |
896 | if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U)) |
896 | pDest++; |
897 | { |
897 | pDest++; |
898 | USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); |
898 | pDest++; |
899 | } |
899 | } |
900 | USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; |
900 | |
901 | } |
901 | /* When Number of data is not word aligned, read the remaining byte */ |
902 | 902 | if (remaining_bytes != 0U) |
|
903 | return HAL_OK; |
903 | { |
904 | } |
904 | i = 0U; |
905 | 905 | __UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U)); |
|
906 | /** |
906 | |
907 | * @brief USB_EPClearStall : Clear a stall condition over an EP |
907 | do |
908 | * @param USBx Selected device |
908 | { |
909 | * @param ep pointer to endpoint structure |
909 | *(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i))); |
910 | * @retval HAL status |
910 | i++; |
911 | */ |
911 | pDest++; |
912 | HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) |
912 | remaining_bytes--; |
913 | { |
913 | } while (remaining_bytes != 0U); |
914 | uint32_t USBx_BASE = (uint32_t)USBx; |
914 | } |
915 | uint32_t epnum = (uint32_t)ep->num; |
915 | |
916 | 916 | return ((void *)pDest); |
|
917 | if (ep->is_in == 1U) |
917 | } |
918 | { |
918 | |
919 | USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; |
919 | /** |
920 | if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) |
920 | * @brief USB_EPSetStall : set a stall condition over an EP |
921 | { |
921 | * @param USBx Selected device |
922 | USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ |
922 | * @param ep pointer to endpoint structure |
923 | } |
923 | * @retval HAL status |
924 | } |
924 | */ |
925 | else |
925 | HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) |
926 | { |
926 | { |
927 | USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; |
927 | uint32_t USBx_BASE = (uint32_t)USBx; |
928 | if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) |
928 | uint32_t epnum = (uint32_t)ep->num; |
929 | { |
929 | |
930 | USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ |
930 | if (ep->is_in == 1U) |
931 | } |
931 | { |
932 | } |
932 | if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U)) |
933 | return HAL_OK; |
933 | { |
934 | } |
934 | USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); |
935 | 935 | } |
|
936 | /** |
936 | USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; |
937 | * @brief USB_StopDevice : Stop the usb device mode |
937 | } |
938 | * @param USBx Selected device |
938 | else |
939 | * @retval HAL status |
939 | { |
940 | */ |
940 | if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U)) |
941 | HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) |
941 | { |
942 | { |
942 | USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); |
943 | HAL_StatusTypeDef ret; |
943 | } |
944 | uint32_t USBx_BASE = (uint32_t)USBx; |
944 | USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; |
945 | uint32_t i; |
945 | } |
946 | 946 | ||
947 | /* Clear Pending interrupt */ |
947 | return HAL_OK; |
948 | for (i = 0U; i < 15U; i++) |
948 | } |
949 | { |
949 | |
950 | USBx_INEP(i)->DIEPINT = 0xFB7FU; |
950 | /** |
951 | USBx_OUTEP(i)->DOEPINT = 0xFB7FU; |
951 | * @brief USB_EPClearStall : Clear a stall condition over an EP |
952 | } |
952 | * @param USBx Selected device |
953 | 953 | * @param ep pointer to endpoint structure |
|
954 | /* Clear interrupt masks */ |
954 | * @retval HAL status |
955 | USBx_DEVICE->DIEPMSK = 0U; |
955 | */ |
956 | USBx_DEVICE->DOEPMSK = 0U; |
956 | HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) |
957 | USBx_DEVICE->DAINTMSK = 0U; |
957 | { |
958 | 958 | uint32_t USBx_BASE = (uint32_t)USBx; |
|
959 | /* Flush the FIFO */ |
959 | uint32_t epnum = (uint32_t)ep->num; |
960 | ret = USB_FlushRxFifo(USBx); |
960 | |
961 | if (ret != HAL_OK) |
961 | if (ep->is_in == 1U) |
962 | { |
962 | { |
963 | return ret; |
963 | USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; |
964 | } |
964 | if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) |
965 | 965 | { |
|
966 | ret = USB_FlushTxFifo(USBx, 0x10U); |
966 | USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ |
967 | if (ret != HAL_OK) |
967 | } |
968 | { |
968 | } |
969 | return ret; |
969 | else |
970 | } |
970 | { |
971 | 971 | USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; |
|
972 | return ret; |
972 | if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) |
973 | } |
973 | { |
974 | 974 | USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ |
|
975 | /** |
975 | } |
976 | * @brief USB_SetDevAddress : Stop the usb device mode |
976 | } |
977 | * @param USBx Selected device |
977 | return HAL_OK; |
978 | * @param address new device address to be assigned |
978 | } |
979 | * This parameter can be a value from 0 to 255 |
979 | |
980 | * @retval HAL status |
980 | /** |
981 | */ |
981 | * @brief USB_StopDevice : Stop the usb device mode |
982 | HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address) |
982 | * @param USBx Selected device |
983 | { |
983 | * @retval HAL status |
984 | uint32_t USBx_BASE = (uint32_t)USBx; |
984 | */ |
985 | 985 | HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) |
|
986 | USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD); |
986 | { |
987 | USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD; |
987 | HAL_StatusTypeDef ret; |
988 | 988 | uint32_t USBx_BASE = (uint32_t)USBx; |
|
989 | return HAL_OK; |
989 | uint32_t i; |
990 | } |
990 | |
991 | 991 | /* Clear Pending interrupt */ |
|
992 | /** |
992 | for (i = 0U; i < 15U; i++) |
993 | * @brief USB_DevConnect : Connect the USB device by enabling Rpu |
993 | { |
994 | * @param USBx Selected device |
994 | USBx_INEP(i)->DIEPINT = 0xFB7FU; |
995 | * @retval HAL status |
995 | USBx_OUTEP(i)->DOEPINT = 0xFB7FU; |
996 | */ |
996 | } |
997 | HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx) |
997 | |
998 | { |
998 | /* Clear interrupt masks */ |
999 | uint32_t USBx_BASE = (uint32_t)USBx; |
999 | USBx_DEVICE->DIEPMSK = 0U; |
1000 | 1000 | USBx_DEVICE->DOEPMSK = 0U; |
|
1001 | /* In case phy is stopped, ensure to ungate and restore the phy CLK */ |
1001 | USBx_DEVICE->DAINTMSK = 0U; |
1002 | USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); |
1002 | |
1003 | 1003 | /* Flush the FIFO */ |
|
1004 | USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS; |
1004 | ret = USB_FlushRxFifo(USBx); |
1005 | 1005 | if (ret != HAL_OK) |
|
1006 | return HAL_OK; |
1006 | { |
1007 | } |
1007 | return ret; |
1008 | 1008 | } |
|
1009 | /** |
1009 | |
1010 | * @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu |
1010 | ret = USB_FlushTxFifo(USBx, 0x10U); |
1011 | * @param USBx Selected device |
1011 | if (ret != HAL_OK) |
1012 | * @retval HAL status |
1012 | { |
1013 | */ |
1013 | return ret; |
1014 | HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx) |
1014 | } |
1015 | { |
1015 | |
1016 | uint32_t USBx_BASE = (uint32_t)USBx; |
1016 | return ret; |
1017 | 1017 | } |
|
1018 | /* In case phy is stopped, ensure to ungate and restore the phy CLK */ |
1018 | |
1019 | USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); |
1019 | /** |
1020 | 1020 | * @brief USB_SetDevAddress : Stop the usb device mode |
|
1021 | USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; |
1021 | * @param USBx Selected device |
1022 | 1022 | * @param address new device address to be assigned |
|
1023 | return HAL_OK; |
1023 | * This parameter can be a value from 0 to 255 |
1024 | } |
1024 | * @retval HAL status |
1025 | 1025 | */ |
|
1026 | /** |
1026 | HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address) |
1027 | * @brief USB_ReadInterrupts: return the global USB interrupt status |
1027 | { |
1028 | * @param USBx Selected device |
1028 | uint32_t USBx_BASE = (uint32_t)USBx; |
1029 | * @retval HAL status |
1029 | |
1030 | */ |
1030 | USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD); |
1031 | uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx) |
1031 | USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD; |
1032 | { |
1032 | |
1033 | uint32_t tmpreg; |
1033 | return HAL_OK; |
1034 | 1034 | } |
|
1035 | tmpreg = USBx->GINTSTS; |
1035 | |
1036 | tmpreg &= USBx->GINTMSK; |
1036 | /** |
1037 | 1037 | * @brief USB_DevConnect : Connect the USB device by enabling Rpu |
|
1038 | return tmpreg; |
1038 | * @param USBx Selected device |
1039 | } |
1039 | * @retval HAL status |
1040 | 1040 | */ |
|
1041 | /** |
1041 | HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx) |
1042 | * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status |
1042 | { |
1043 | * @param USBx Selected device |
1043 | uint32_t USBx_BASE = (uint32_t)USBx; |
1044 | * @retval HAL status |
1044 | |
1045 | */ |
1045 | /* In case phy is stopped, ensure to ungate and restore the phy CLK */ |
1046 | uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx) |
1046 | USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); |
1047 | { |
1047 | |
1048 | uint32_t USBx_BASE = (uint32_t)USBx; |
1048 | USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS; |
1049 | uint32_t tmpreg; |
1049 | |
1050 | 1050 | return HAL_OK; |
|
1051 | tmpreg = USBx_DEVICE->DAINT; |
1051 | } |
1052 | tmpreg &= USBx_DEVICE->DAINTMSK; |
1052 | |
1053 | 1053 | /** |
|
1054 | return ((tmpreg & 0xffff0000U) >> 16); |
1054 | * @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu |
1055 | } |
1055 | * @param USBx Selected device |
1056 | 1056 | * @retval HAL status |
|
1057 | /** |
1057 | */ |
1058 | * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status |
1058 | HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx) |
1059 | * @param USBx Selected device |
1059 | { |
1060 | * @retval HAL status |
1060 | uint32_t USBx_BASE = (uint32_t)USBx; |
1061 | */ |
1061 | |
1062 | uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx) |
1062 | /* In case phy is stopped, ensure to ungate and restore the phy CLK */ |
1063 | { |
1063 | USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); |
1064 | uint32_t USBx_BASE = (uint32_t)USBx; |
1064 | |
1065 | uint32_t tmpreg; |
1065 | USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; |
1066 | 1066 | ||
1067 | tmpreg = USBx_DEVICE->DAINT; |
1067 | return HAL_OK; |
1068 | tmpreg &= USBx_DEVICE->DAINTMSK; |
1068 | } |
1069 | 1069 | ||
1070 | return ((tmpreg & 0xFFFFU)); |
1070 | /** |
1071 | } |
1071 | * @brief USB_ReadInterrupts: return the global USB interrupt status |
1072 | 1072 | * @param USBx Selected device |
|
1073 | /** |
1073 | * @retval USB Global Interrupt status |
1074 | * @brief Returns Device OUT EP Interrupt register |
1074 | */ |
1075 | * @param USBx Selected device |
1075 | uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx) |
1076 | * @param epnum endpoint number |
1076 | { |
1077 | * This parameter can be a value from 0 to 15 |
1077 | uint32_t tmpreg; |
1078 | * @retval Device OUT EP Interrupt register |
1078 | |
1079 | */ |
1079 | tmpreg = USBx->GINTSTS; |
1080 | uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) |
1080 | tmpreg &= USBx->GINTMSK; |
1081 | { |
1081 | |
1082 | uint32_t USBx_BASE = (uint32_t)USBx; |
1082 | return tmpreg; |
1083 | uint32_t tmpreg; |
1083 | } |
1084 | 1084 | ||
1085 | tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT; |
1085 | /** |
1086 | tmpreg &= USBx_DEVICE->DOEPMSK; |
1086 | * @brief USB_ReadChInterrupts: return USB channel interrupt status |
1087 | 1087 | * @param USBx Selected device |
|
1088 | return tmpreg; |
1088 | * @param chnum Channel number |
1089 | } |
1089 | * @retval USB Channel Interrupt status |
1090 | 1090 | */ |
|
1091 | /** |
1091 | uint32_t USB_ReadChInterrupts(USB_OTG_GlobalTypeDef *USBx, uint8_t chnum) |
1092 | * @brief Returns Device IN EP Interrupt register |
1092 | { |
1093 | * @param USBx Selected device |
1093 | uint32_t USBx_BASE = (uint32_t)USBx; |
1094 | * @param epnum endpoint number |
1094 | uint32_t tmpreg; |
1095 | * This parameter can be a value from 0 to 15 |
1095 | |
1096 | * @retval Device IN EP Interrupt register |
1096 | tmpreg = USBx_HC(chnum)->HCINT; |
1097 | */ |
1097 | tmpreg &= USBx_HC(chnum)->HCINTMSK; |
1098 | uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) |
1098 | |
1099 | { |
1099 | return tmpreg; |
1100 | uint32_t USBx_BASE = (uint32_t)USBx; |
1100 | } |
1101 | uint32_t tmpreg; |
1101 | |
1102 | uint32_t msk; |
1102 | /** |
1103 | uint32_t emp; |
1103 | * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status |
1104 | 1104 | * @param USBx Selected device |
|
1105 | msk = USBx_DEVICE->DIEPMSK; |
1105 | * @retval USB Device OUT EP interrupt status |
1106 | emp = USBx_DEVICE->DIEPEMPMSK; |
1106 | */ |
1107 | msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7; |
1107 | uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx) |
1108 | tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk; |
1108 | { |
1109 | 1109 | uint32_t USBx_BASE = (uint32_t)USBx; |
|
1110 | return tmpreg; |
1110 | uint32_t tmpreg; |
1111 | } |
1111 | |
1112 | 1112 | tmpreg = USBx_DEVICE->DAINT; |
|
1113 | /** |
1113 | tmpreg &= USBx_DEVICE->DAINTMSK; |
1114 | * @brief USB_ClearInterrupts: clear a USB interrupt |
1114 | |
1115 | * @param USBx Selected device |
1115 | return ((tmpreg & 0xffff0000U) >> 16); |
1116 | * @param interrupt flag |
1116 | } |
1117 | * @retval None |
1117 | |
1118 | */ |
1118 | /** |
1119 | void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) |
1119 | * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status |
1120 | { |
1120 | * @param USBx Selected device |
1121 | USBx->GINTSTS |= interrupt; |
1121 | * @retval USB Device IN EP interrupt status |
1122 | } |
1122 | */ |
1123 | 1123 | uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx) |
|
1124 | /** |
1124 | { |
1125 | * @brief Returns USB core mode |
1125 | uint32_t USBx_BASE = (uint32_t)USBx; |
1126 | * @param USBx Selected device |
1126 | uint32_t tmpreg; |
1127 | * @retval return core mode : Host or Device |
1127 | |
1128 | * This parameter can be one of these values: |
1128 | tmpreg = USBx_DEVICE->DAINT; |
1129 | * 0 : Host |
1129 | tmpreg &= USBx_DEVICE->DAINTMSK; |
1130 | * 1 : Device |
1130 | |
1131 | */ |
1131 | return ((tmpreg & 0xFFFFU)); |
1132 | uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) |
1132 | } |
1133 | { |
1133 | |
1134 | return ((USBx->GINTSTS) & 0x1U); |
1134 | /** |
1135 | } |
1135 | * @brief Returns Device OUT EP Interrupt register |
1136 | 1136 | * @param USBx Selected device |
|
1137 | /** |
1137 | * @param epnum endpoint number |
1138 | * @brief Activate EP0 for Setup transactions |
1138 | * This parameter can be a value from 0 to 15 |
1139 | * @param USBx Selected device |
1139 | * @retval Device OUT EP Interrupt register |
1140 | * @retval HAL status |
1140 | */ |
1141 | */ |
1141 | uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) |
1142 | HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx) |
1142 | { |
1143 | { |
1143 | uint32_t USBx_BASE = (uint32_t)USBx; |
1144 | uint32_t USBx_BASE = (uint32_t)USBx; |
1144 | uint32_t tmpreg; |
1145 | 1145 | ||
1146 | /* Set the MPS of the IN EP0 to 64 bytes */ |
1146 | tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT; |
1147 | USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; |
1147 | tmpreg &= USBx_DEVICE->DOEPMSK; |
1148 | 1148 | ||
1149 | USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; |
1149 | return tmpreg; |
1150 | 1150 | } |
|
1151 | return HAL_OK; |
1151 | |
1152 | } |
1152 | /** |
1153 | 1153 | * @brief Returns Device IN EP Interrupt register |
|
1154 | /** |
1154 | * @param USBx Selected device |
1155 | * @brief Prepare the EP0 to start the first control setup |
1155 | * @param epnum endpoint number |
1156 | * @param USBx Selected device |
1156 | * This parameter can be a value from 0 to 15 |
1157 | * @param psetup pointer to setup packet |
1157 | * @retval Device IN EP Interrupt register |
1158 | * @retval HAL status |
1158 | */ |
1159 | */ |
1159 | uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) |
1160 | HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t *psetup) |
1160 | { |
1161 | { |
1161 | uint32_t USBx_BASE = (uint32_t)USBx; |
1162 | uint32_t USBx_BASE = (uint32_t)USBx; |
1162 | uint32_t tmpreg; |
1163 | uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); |
1163 | uint32_t msk; |
1164 | UNUSED(psetup); |
1164 | uint32_t emp; |
1165 | 1165 | ||
1166 | if (gSNPSiD > USB_OTG_CORE_ID_300A) |
1166 | msk = USBx_DEVICE->DIEPMSK; |
1167 | { |
1167 | emp = USBx_DEVICE->DIEPEMPMSK; |
1168 | if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) |
1168 | msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7; |
1169 | { |
1169 | tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk; |
1170 | return HAL_OK; |
1170 | |
1171 | } |
1171 | return tmpreg; |
1172 | } |
1172 | } |
1173 | 1173 | ||
1174 | USBx_OUTEP(0U)->DOEPTSIZ = 0U; |
1174 | /** |
1175 | USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); |
1175 | * @brief USB_ClearInterrupts: clear a USB interrupt |
1176 | USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U); |
1176 | * @param USBx Selected device |
1177 | USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; |
1177 | * @param interrupt flag |
1178 | 1178 | * @retval None |
|
1179 | return HAL_OK; |
1179 | */ |
1180 | } |
1180 | void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) |
1181 | 1181 | { |
|
1182 | /** |
1182 | USBx->GINTSTS &= interrupt; |
1183 | * @brief Reset the USB Core (needed after USB clock settings change) |
1183 | } |
1184 | * @param USBx Selected device |
1184 | |
1185 | * @retval HAL status |
1185 | /** |
1186 | */ |
1186 | * @brief Returns USB core mode |
1187 | static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) |
1187 | * @param USBx Selected device |
1188 | { |
1188 | * @retval return core mode : Host or Device |
1189 | uint32_t count = 0U; |
1189 | * This parameter can be one of these values: |
1190 | 1190 | * 0 : Host |
|
1191 | /* Wait for AHB master IDLE state. */ |
1191 | * 1 : Device |
1192 | do |
1192 | */ |
1193 | { |
1193 | uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) |
1194 | if (++count > 200000U) |
1194 | { |
1195 | { |
1195 | return ((USBx->GINTSTS) & 0x1U); |
1196 | return HAL_TIMEOUT; |
1196 | } |
1197 | } |
1197 | |
1198 | } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); |
1198 | /** |
1199 | 1199 | * @brief Activate EP0 for Setup transactions |
|
1200 | /* Core Soft Reset */ |
1200 | * @param USBx Selected device |
1201 | count = 0U; |
1201 | * @retval HAL status |
1202 | USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; |
1202 | */ |
1203 | 1203 | HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx) |
|
1204 | do |
1204 | { |
1205 | { |
1205 | uint32_t USBx_BASE = (uint32_t)USBx; |
1206 | if (++count > 200000U) |
1206 | |
1207 | { |
1207 | /* Set the MPS of the IN EP0 to 64 bytes */ |
1208 | return HAL_TIMEOUT; |
1208 | USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; |
1209 | } |
1209 | |
1210 | } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); |
1210 | USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; |
1211 | 1211 | ||
1212 | return HAL_OK; |
1212 | return HAL_OK; |
1213 | } |
1213 | } |
1214 | 1214 | ||
1215 | /** |
1215 | /** |
1216 | * @brief USB_HostInit : Initializes the USB OTG controller registers |
1216 | * @brief Prepare the EP0 to start the first control setup |
1217 | * for Host mode |
1217 | * @param USBx Selected device |
1218 | * @param USBx Selected device |
1218 | * @param psetup pointer to setup packet |
1219 | * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains |
1219 | * @retval HAL status |
1220 | * the configuration information for the specified USBx peripheral. |
1220 | */ |
1221 | * @retval HAL status |
1221 | HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t *psetup) |
1222 | */ |
1222 | { |
1223 | HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) |
1223 | uint32_t USBx_BASE = (uint32_t)USBx; |
1224 | { |
1224 | uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); |
1225 | uint32_t USBx_BASE = (uint32_t)USBx; |
1225 | UNUSED(psetup); |
1226 | uint32_t i; |
1226 | |
1227 | 1227 | if (gSNPSiD > USB_OTG_CORE_ID_300A) |
|
1228 | /* Restart the Phy Clock */ |
1228 | { |
1229 | USBx_PCGCCTL = 0U; |
1229 | if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) |
1230 | 1230 | { |
|
1231 | /* Disable VBUS sensing */ |
1231 | return HAL_OK; |
1232 | USBx->GCCFG &= ~(USB_OTG_GCCFG_VBUSASEN); |
1232 | } |
1233 | USBx->GCCFG &= ~(USB_OTG_GCCFG_VBUSBSEN); |
1233 | } |
1234 | /* Set default Max speed support */ |
1234 | |
1235 | USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); |
1235 | USBx_OUTEP(0U)->DOEPTSIZ = 0U; |
1236 | 1236 | USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); |
|
1237 | /* Make sure the FIFOs are flushed. */ |
1237 | USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U); |
1238 | (void)USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */ |
1238 | USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; |
1239 | (void)USB_FlushRxFifo(USBx); |
1239 | |
1240 | 1240 | return HAL_OK; |
|
1241 | /* Clear all pending HC Interrupts */ |
1241 | } |
1242 | for (i = 0U; i < cfg.Host_channels; i++) |
1242 | |
1243 | { |
1243 | /** |
1244 | USBx_HC(i)->HCINT = 0xFFFFFFFFU; |
1244 | * @brief Reset the USB Core (needed after USB clock settings change) |
1245 | USBx_HC(i)->HCINTMSK = 0U; |
1245 | * @param USBx Selected device |
1246 | } |
1246 | * @retval HAL status |
1247 | 1247 | */ |
|
1248 | /* Disable all interrupts. */ |
1248 | static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) |
1249 | USBx->GINTMSK = 0U; |
1249 | { |
1250 | 1250 | __IO uint32_t count = 0U; |
|
1251 | /* Clear any pending interrupts */ |
1251 | |
1252 | USBx->GINTSTS = 0xFFFFFFFFU; |
1252 | /* Wait for AHB master IDLE state. */ |
1253 | 1253 | do |
|
1254 | /* set Rx FIFO size */ |
1254 | { |
1255 | USBx->GRXFSIZ = 0x80U; |
1255 | count++; |
1256 | USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U); |
1256 | |
1257 | USBx->HPTXFSIZ = (uint32_t)(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U); |
1257 | if (count > 200000U) |
1258 | /* Enable the common interrupts */ |
1258 | { |
1259 | USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; |
1259 | return HAL_TIMEOUT; |
1260 | 1260 | } |
|
1261 | /* Enable interrupts matching to the Host mode ONLY */ |
1261 | } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); |
1262 | USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM | \ |
1262 | |
1263 | USB_OTG_GINTMSK_SOFM | USB_OTG_GINTSTS_DISCINT | \ |
1263 | /* Core Soft Reset */ |
1264 | USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); |
1264 | count = 0U; |
1265 | 1265 | USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; |
|
1266 | return HAL_OK; |
1266 | |
1267 | } |
1267 | do |
1268 | 1268 | { |
|
1269 | /** |
1269 | count++; |
1270 | * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the |
1270 | |
1271 | * HCFG register on the PHY type and set the right frame interval |
1271 | if (count > 200000U) |
1272 | * @param USBx Selected device |
1272 | { |
1273 | * @param freq clock frequency |
1273 | return HAL_TIMEOUT; |
1274 | * This parameter can be one of these values: |
1274 | } |
1275 | * HCFG_48_MHZ : Full Speed 48 MHz Clock |
1275 | } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); |
1276 | * HCFG_6_MHZ : Low Speed 6 MHz Clock |
1276 | |
1277 | * @retval HAL status |
1277 | return HAL_OK; |
1278 | */ |
1278 | } |
1279 | HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq) |
1279 | |
1280 | { |
1280 | /** |
1281 | uint32_t USBx_BASE = (uint32_t)USBx; |
1281 | * @brief USB_HostInit : Initializes the USB OTG controller registers |
1282 | 1282 | * for Host mode |
|
1283 | USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS); |
1283 | * @param USBx Selected device |
1284 | USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS; |
1284 | * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains |
1285 | 1285 | * the configuration information for the specified USBx peripheral. |
|
1286 | if (freq == HCFG_48_MHZ) |
1286 | * @retval HAL status |
1287 | { |
1287 | */ |
1288 | USBx_HOST->HFIR = 48000U; |
1288 | HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) |
1289 | } |
1289 | { |
1290 | else if (freq == HCFG_6_MHZ) |
1290 | HAL_StatusTypeDef ret = HAL_OK; |
1291 | { |
1291 | uint32_t USBx_BASE = (uint32_t)USBx; |
1292 | USBx_HOST->HFIR = 6000U; |
1292 | uint32_t i; |
1293 | } |
1293 | |
1294 | else |
1294 | /* Restart the Phy Clock */ |
1295 | { |
1295 | USBx_PCGCCTL = 0U; |
1296 | /* ... */ |
1296 | |
1297 | } |
1297 | /* Disable VBUS sensing */ |
1298 | 1298 | USBx->GCCFG &= ~(USB_OTG_GCCFG_VBUSASEN); |
|
1299 | return HAL_OK; |
1299 | USBx->GCCFG &= ~(USB_OTG_GCCFG_VBUSBSEN); |
1300 | } |
1300 | /* Set default Max speed support */ |
1301 | 1301 | USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); |
|
1302 | /** |
1302 | |
1303 | * @brief USB_OTG_ResetPort : Reset Host Port |
1303 | /* Make sure the FIFOs are flushed. */ |
1304 | * @param USBx Selected device |
1304 | if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ |
1305 | * @retval HAL status |
1305 | { |
1306 | * @note (1)The application must wait at least 10 ms |
1306 | ret = HAL_ERROR; |
1307 | * before clearing the reset bit. |
1307 | } |
1308 | */ |
1308 | |
1309 | HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) |
1309 | if (USB_FlushRxFifo(USBx) != HAL_OK) |
1310 | { |
1310 | { |
1311 | uint32_t USBx_BASE = (uint32_t)USBx; |
1311 | ret = HAL_ERROR; |
1312 | 1312 | } |
|
1313 | __IO uint32_t hprt0 = 0U; |
1313 | |
1314 | 1314 | /* Clear all pending HC Interrupts */ |
|
1315 | hprt0 = USBx_HPRT0; |
1315 | for (i = 0U; i < cfg.Host_channels; i++) |
1316 | 1316 | { |
|
1317 | hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | |
1317 | USBx_HC(i)->HCINT = CLEAR_INTERRUPT_MASK; |
1318 | USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); |
1318 | USBx_HC(i)->HCINTMSK = 0U; |
1319 | 1319 | } |
|
1320 | USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0); |
1320 | |
1321 | HAL_Delay(100U); /* See Note #1 */ |
1321 | /* Disable all interrupts. */ |
1322 | USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0); |
1322 | USBx->GINTMSK = 0U; |
1323 | HAL_Delay(10U); |
1323 | |
1324 | 1324 | /* Clear any pending interrupts */ |
|
1325 | return HAL_OK; |
1325 | USBx->GINTSTS = CLEAR_INTERRUPT_MASK; |
1326 | } |
1326 | |
1327 | 1327 | /* set Rx FIFO size */ |
|
1328 | /** |
1328 | USBx->GRXFSIZ = 0x80U; |
1329 | * @brief USB_DriveVbus : activate or de-activate vbus |
1329 | USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U); |
1330 | * @param state VBUS state |
1330 | USBx->HPTXFSIZ = (uint32_t)(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U); |
1331 | * This parameter can be one of these values: |
1331 | /* Enable the common interrupts */ |
1332 | * 0 : Deactivate VBUS |
1332 | USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; |
1333 | * 1 : Activate VBUS |
1333 | |
1334 | * @retval HAL status |
1334 | /* Enable interrupts matching to the Host mode ONLY */ |
1335 | */ |
1335 | USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM | \ |
1336 | HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state) |
1336 | USB_OTG_GINTMSK_SOFM | USB_OTG_GINTSTS_DISCINT | \ |
1337 | { |
1337 | USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); |
1338 | uint32_t USBx_BASE = (uint32_t)USBx; |
1338 | |
1339 | __IO uint32_t hprt0 = 0U; |
1339 | return ret; |
1340 | 1340 | } |
|
1341 | hprt0 = USBx_HPRT0; |
1341 | |
1342 | 1342 | /** |
|
1343 | hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | |
1343 | * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the |
1344 | USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); |
1344 | * HCFG register on the PHY type and set the right frame interval |
1345 | 1345 | * @param USBx Selected device |
|
1346 | if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U)) |
1346 | * @param freq clock frequency |
1347 | { |
1347 | * This parameter can be one of these values: |
1348 | USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0); |
1348 | * HCFG_48_MHZ : Full Speed 48 MHz Clock |
1349 | } |
1349 | * HCFG_6_MHZ : Low Speed 6 MHz Clock |
1350 | if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U)) |
1350 | * @retval HAL status |
1351 | { |
1351 | */ |
1352 | USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0); |
1352 | HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq) |
1353 | } |
1353 | { |
1354 | return HAL_OK; |
1354 | uint32_t USBx_BASE = (uint32_t)USBx; |
1355 | } |
1355 | |
1356 | 1356 | USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS); |
|
1357 | /** |
1357 | USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS; |
1358 | * @brief Return Host Core speed |
1358 | |
1359 | * @param USBx Selected device |
1359 | if (freq == HCFG_48_MHZ) |
1360 | * @retval speed : Host speed |
1360 | { |
1361 | * This parameter can be one of these values: |
1361 | USBx_HOST->HFIR = HFIR_48_MHZ; |
1362 | * @arg HCD_SPEED_FULL: Full speed mode |
1362 | } |
1363 | * @arg HCD_SPEED_LOW: Low speed mode |
1363 | else if (freq == HCFG_6_MHZ) |
1364 | */ |
1364 | { |
1365 | uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx) |
1365 | USBx_HOST->HFIR = HFIR_6_MHZ; |
1366 | { |
1366 | } |
1367 | uint32_t USBx_BASE = (uint32_t)USBx; |
1367 | else |
1368 | __IO uint32_t hprt0 = 0U; |
1368 | { |
1369 | 1369 | return HAL_ERROR; |
|
1370 | hprt0 = USBx_HPRT0; |
1370 | } |
1371 | return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17); |
1371 | |
1372 | } |
1372 | return HAL_OK; |
1373 | 1373 | } |
|
1374 | /** |
1374 | |
1375 | * @brief Return Host Current Frame number |
1375 | /** |
1376 | * @param USBx Selected device |
1376 | * @brief USB_OTG_ResetPort : Reset Host Port |
1377 | * @retval current frame number |
1377 | * @param USBx Selected device |
1378 | */ |
1378 | * @retval HAL status |
1379 | uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx) |
1379 | * @note (1)The application must wait at least 10 ms |
1380 | { |
1380 | * before clearing the reset bit. |
1381 | uint32_t USBx_BASE = (uint32_t)USBx; |
1381 | */ |
1382 | 1382 | HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) |
|
1383 | return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM); |
1383 | { |
1384 | } |
1384 | uint32_t USBx_BASE = (uint32_t)USBx; |
1385 | 1385 | ||
1386 | /** |
1386 | __IO uint32_t hprt0 = 0U; |
1387 | * @brief Initialize a host channel |
1387 | |
1388 | * @param USBx Selected device |
1388 | hprt0 = USBx_HPRT0; |
1389 | * @param ch_num Channel number |
1389 | |
1390 | * This parameter can be a value from 1 to 15 |
1390 | hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | |
1391 | * @param epnum Endpoint number |
1391 | USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); |
1392 | * This parameter can be a value from 1 to 15 |
1392 | |
1393 | * @param dev_address Current device address |
1393 | USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0); |
1394 | * This parameter can be a value from 0 to 255 |
1394 | HAL_Delay(100U); /* See Note #1 */ |
1395 | * @param speed Current device speed |
1395 | USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0); |
1396 | * This parameter can be one of these values: |
1396 | HAL_Delay(10U); |
1397 | * @arg USB_OTG_SPEED_FULL: Full speed mode |
1397 | |
1398 | * @arg USB_OTG_SPEED_LOW: Low speed mode |
1398 | return HAL_OK; |
1399 | * @param ep_type Endpoint Type |
1399 | } |
1400 | * This parameter can be one of these values: |
1400 | |
1401 | * @arg EP_TYPE_CTRL: Control type |
1401 | /** |
1402 | * @arg EP_TYPE_ISOC: Isochronous type |
1402 | * @brief USB_DriveVbus : activate or de-activate vbus |
1403 | * @arg EP_TYPE_BULK: Bulk type |
1403 | * @param state VBUS state |
1404 | * @arg EP_TYPE_INTR: Interrupt type |
1404 | * This parameter can be one of these values: |
1405 | * @param mps Max Packet Size |
1405 | * 0 : Deactivate VBUS |
1406 | * This parameter can be a value from 0 to 32K |
1406 | * 1 : Activate VBUS |
1407 | * @retval HAL state |
1407 | * @retval HAL status |
1408 | */ |
1408 | */ |
1409 | HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, |
1409 | HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state) |
1410 | uint8_t epnum, uint8_t dev_address, uint8_t speed, |
1410 | { |
1411 | uint8_t ep_type, uint16_t mps) |
1411 | uint32_t USBx_BASE = (uint32_t)USBx; |
1412 | { |
1412 | __IO uint32_t hprt0 = 0U; |
1413 | HAL_StatusTypeDef ret = HAL_OK; |
1413 | |
1414 | uint32_t USBx_BASE = (uint32_t)USBx; |
1414 | hprt0 = USBx_HPRT0; |
1415 | uint32_t HCcharEpDir; |
1415 | |
1416 | uint32_t HCcharLowSpeed; |
1416 | hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | |
1417 | uint32_t HostCoreSpeed; |
1417 | USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); |
1418 | 1418 | ||
1419 | /* Clear old interrupt conditions for this host channel. */ |
1419 | if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U)) |
1420 | USBx_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU; |
1420 | { |
1421 | 1421 | USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0); |
|
1422 | /* Enable channel interrupts required for this transfer. */ |
1422 | } |
1423 | switch (ep_type) |
1423 | if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U)) |
1424 | { |
1424 | { |
1425 | case EP_TYPE_CTRL: |
1425 | USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0); |
1426 | case EP_TYPE_BULK: |
1426 | } |
1427 | USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | |
1427 | return HAL_OK; |
1428 | USB_OTG_HCINTMSK_STALLM | |
1428 | } |
1429 | USB_OTG_HCINTMSK_TXERRM | |
1429 | |
1430 | USB_OTG_HCINTMSK_DTERRM | |
1430 | /** |
1431 | USB_OTG_HCINTMSK_AHBERR | |
1431 | * @brief Return Host Core speed |
1432 | USB_OTG_HCINTMSK_NAKM; |
1432 | * @param USBx Selected device |
1433 | 1433 | * @retval speed : Host speed |
|
1434 | if ((epnum & 0x80U) == 0x80U) |
1434 | * This parameter can be one of these values: |
1435 | { |
1435 | * @arg HCD_SPEED_FULL: Full speed mode |
1436 | USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; |
1436 | * @arg HCD_SPEED_LOW: Low speed mode |
1437 | } |
1437 | */ |
1438 | break; |
1438 | uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx) |
1439 | 1439 | { |
|
1440 | case EP_TYPE_INTR: |
1440 | uint32_t USBx_BASE = (uint32_t)USBx; |
1441 | USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | |
1441 | __IO uint32_t hprt0 = 0U; |
1442 | USB_OTG_HCINTMSK_STALLM | |
1442 | |
1443 | USB_OTG_HCINTMSK_TXERRM | |
1443 | hprt0 = USBx_HPRT0; |
1444 | USB_OTG_HCINTMSK_DTERRM | |
1444 | return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17); |
1445 | USB_OTG_HCINTMSK_NAKM | |
1445 | } |
1446 | USB_OTG_HCINTMSK_AHBERR | |
1446 | |
1447 | USB_OTG_HCINTMSK_FRMORM; |
1447 | /** |
1448 | 1448 | * @brief Return Host Current Frame number |
|
1449 | if ((epnum & 0x80U) == 0x80U) |
1449 | * @param USBx Selected device |
1450 | { |
1450 | * @retval current frame number |
1451 | USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; |
1451 | */ |
1452 | } |
1452 | uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx) |
1453 | 1453 | { |
|
1454 | break; |
1454 | uint32_t USBx_BASE = (uint32_t)USBx; |
1455 | 1455 | ||
1456 | case EP_TYPE_ISOC: |
1456 | return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM); |
1457 | USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | |
1457 | } |
1458 | USB_OTG_HCINTMSK_ACKM | |
1458 | |
1459 | USB_OTG_HCINTMSK_AHBERR | |
1459 | /** |
1460 | USB_OTG_HCINTMSK_FRMORM; |
1460 | * @brief Initialize a host channel |
1461 | 1461 | * @param USBx Selected device |
|
1462 | if ((epnum & 0x80U) == 0x80U) |
1462 | * @param ch_num Channel number |
1463 | { |
1463 | * This parameter can be a value from 1 to 15 |
1464 | USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM); |
1464 | * @param epnum Endpoint number |
1465 | } |
1465 | * This parameter can be a value from 1 to 15 |
1466 | break; |
1466 | * @param dev_address Current device address |
1467 | 1467 | * This parameter can be a value from 0 to 255 |
|
1468 | default: |
1468 | * @param speed Current device speed |
1469 | ret = HAL_ERROR; |
1469 | * This parameter can be one of these values: |
1470 | break; |
1470 | * @arg USB_OTG_SPEED_FULL: Full speed mode |
1471 | } |
1471 | * @arg USB_OTG_SPEED_LOW: Low speed mode |
1472 | 1472 | * @param ep_type Endpoint Type |
|
1473 | /* Enable the top level host channel interrupt. */ |
1473 | * This parameter can be one of these values: |
1474 | USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU); |
1474 | * @arg EP_TYPE_CTRL: Control type |
1475 | 1475 | * @arg EP_TYPE_ISOC: Isochronous type |
|
1476 | /* Make sure host channel interrupts are enabled. */ |
1476 | * @arg EP_TYPE_BULK: Bulk type |
1477 | USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM; |
1477 | * @arg EP_TYPE_INTR: Interrupt type |
1478 | 1478 | * @param mps Max Packet Size |
|
1479 | /* Program the HCCHAR register */ |
1479 | * This parameter can be a value from 0 to 32K |
1480 | if ((epnum & 0x80U) == 0x80U) |
1480 | * @retval HAL state |
1481 | { |
1481 | */ |
1482 | HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR; |
1482 | HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, |
1483 | } |
1483 | uint8_t epnum, uint8_t dev_address, uint8_t speed, |
1484 | else |
1484 | uint8_t ep_type, uint16_t mps) |
1485 | { |
1485 | { |
1486 | HCcharEpDir = 0U; |
1486 | HAL_StatusTypeDef ret = HAL_OK; |
1487 | } |
1487 | uint32_t USBx_BASE = (uint32_t)USBx; |
1488 | 1488 | uint32_t HCcharEpDir; |
|
1489 | HostCoreSpeed = USB_GetHostSpeed(USBx); |
1489 | uint32_t HCcharLowSpeed; |
1490 | 1490 | uint32_t HostCoreSpeed; |
|
1491 | /* LS device plugged to HUB */ |
1491 | |
1492 | if ((speed == HPRT0_PRTSPD_LOW_SPEED) && (HostCoreSpeed != HPRT0_PRTSPD_LOW_SPEED)) |
1492 | /* Clear old interrupt conditions for this host channel. */ |
1493 | { |
1493 | USBx_HC((uint32_t)ch_num)->HCINT = CLEAR_INTERRUPT_MASK; |
1494 | HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV; |
1494 | |
1495 | } |
1495 | /* Enable channel interrupts required for this transfer. */ |
1496 | else |
1496 | switch (ep_type) |
1497 | { |
1497 | { |
1498 | HCcharLowSpeed = 0U; |
1498 | case EP_TYPE_CTRL: |
1499 | } |
1499 | case EP_TYPE_BULK: |
1500 | 1500 | USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | |
|
1501 | USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) | |
1501 | USB_OTG_HCINTMSK_STALLM | |
1502 | ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) | |
1502 | USB_OTG_HCINTMSK_TXERRM | |
1503 | (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) | |
1503 | USB_OTG_HCINTMSK_DTERRM | |
1504 | ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | HCcharEpDir | HCcharLowSpeed; |
1504 | USB_OTG_HCINTMSK_AHBERR | |
1505 | 1505 | USB_OTG_HCINTMSK_NAKM; |
|
1506 | if (ep_type == EP_TYPE_INTR) |
1506 | |
1507 | { |
1507 | if ((epnum & 0x80U) == 0x80U) |
1508 | USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ; |
1508 | { |
1509 | } |
1509 | USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; |
1510 | 1510 | } |
|
1511 | return ret; |
1511 | break; |
1512 | } |
1512 | |
1513 | 1513 | case EP_TYPE_INTR: |
|
1514 | /** |
1514 | USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | |
1515 | * @brief Start a transfer over a host channel |
1515 | USB_OTG_HCINTMSK_STALLM | |
1516 | * @param USBx Selected device |
1516 | USB_OTG_HCINTMSK_TXERRM | |
1517 | * @param hc pointer to host channel structure |
1517 | USB_OTG_HCINTMSK_DTERRM | |
1518 | * @retval HAL state |
1518 | USB_OTG_HCINTMSK_NAKM | |
1519 | */ |
1519 | USB_OTG_HCINTMSK_AHBERR | |
1520 | HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc) |
1520 | USB_OTG_HCINTMSK_FRMORM; |
1521 | { |
1521 | |
1522 | uint32_t USBx_BASE = (uint32_t)USBx; |
1522 | if ((epnum & 0x80U) == 0x80U) |
1523 | uint32_t ch_num = (uint32_t)hc->ch_num; |
1523 | { |
1524 | __IO uint32_t tmpreg; |
1524 | USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; |
1525 | uint8_t is_oddframe; |
1525 | } |
1526 | uint16_t len_words; |
1526 | |
1527 | uint16_t num_packets; |
1527 | break; |
1528 | uint16_t max_hc_pkt_count = 256U; |
1528 | |
1529 | 1529 | case EP_TYPE_ISOC: |
|
1530 | /* Compute the expected number of packets associated to the transfer */ |
1530 | USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | |
1531 | if (hc->xfer_len > 0U) |
1531 | USB_OTG_HCINTMSK_ACKM | |
1532 | { |
1532 | USB_OTG_HCINTMSK_AHBERR | |
1533 | num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet); |
1533 | USB_OTG_HCINTMSK_FRMORM; |
1534 | 1534 | ||
1535 | if (num_packets > max_hc_pkt_count) |
1535 | if ((epnum & 0x80U) == 0x80U) |
1536 | { |
1536 | { |
1537 | num_packets = max_hc_pkt_count; |
1537 | USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM); |
1538 | hc->XferSize = (uint32_t)num_packets * hc->max_packet; |
1538 | } |
1539 | } |
1539 | break; |
1540 | } |
1540 | |
1541 | else |
1541 | default: |
1542 | { |
1542 | ret = HAL_ERROR; |
1543 | num_packets = 1U; |
1543 | break; |
1544 | } |
1544 | } |
1545 | 1545 | ||
1546 | /* |
1546 | /* Enable host channel Halt interrupt */ |
1547 | * For IN channel HCTSIZ.XferSize is expected to be an integer multiple of |
1547 | USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM; |
1548 | * max_packet size. |
1548 | |
1549 | */ |
1549 | /* Enable the top level host channel interrupt. */ |
1550 | if (hc->ep_is_in != 0U) |
1550 | USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU); |
1551 | { |
1551 | |
1552 | hc->XferSize = (uint32_t)num_packets * hc->max_packet; |
1552 | /* Make sure host channel interrupts are enabled. */ |
1553 | } |
1553 | USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM; |
1554 | else |
1554 | |
1555 | { |
1555 | /* Program the HCCHAR register */ |
1556 | hc->XferSize = hc->xfer_len; |
1556 | if ((epnum & 0x80U) == 0x80U) |
1557 | } |
1557 | { |
1558 | 1558 | HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR; |
|
1559 | /* Initialize the HCTSIZn register */ |
1559 | } |
1560 | USBx_HC(ch_num)->HCTSIZ = (hc->XferSize & USB_OTG_HCTSIZ_XFRSIZ) | |
1560 | else |
1561 | (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | |
1561 | { |
1562 | (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID); |
1562 | HCcharEpDir = 0U; |
1563 | 1563 | } |
|
1564 | is_oddframe = (((uint32_t)USBx_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U; |
1564 | |
1565 | USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; |
1565 | HostCoreSpeed = USB_GetHostSpeed(USBx); |
1566 | USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29; |
1566 | |
1567 | 1567 | /* LS device plugged to HUB */ |
|
1568 | /* Set host channel enable */ |
1568 | if ((speed == HPRT0_PRTSPD_LOW_SPEED) && (HostCoreSpeed != HPRT0_PRTSPD_LOW_SPEED)) |
1569 | tmpreg = USBx_HC(ch_num)->HCCHAR; |
1569 | { |
1570 | tmpreg &= ~USB_OTG_HCCHAR_CHDIS; |
1570 | HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV; |
1571 | 1571 | } |
|
1572 | /* make sure to set the correct ep direction */ |
1572 | else |
1573 | if (hc->ep_is_in != 0U) |
1573 | { |
1574 | { |
1574 | HCcharLowSpeed = 0U; |
1575 | tmpreg |= USB_OTG_HCCHAR_EPDIR; |
1575 | } |
1576 | } |
1576 | |
1577 | else |
1577 | USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) | |
1578 | { |
1578 | ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) | |
1579 | tmpreg &= ~USB_OTG_HCCHAR_EPDIR; |
1579 | (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) | |
1580 | } |
1580 | ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | |
1581 | tmpreg |= USB_OTG_HCCHAR_CHENA; |
1581 | USB_OTG_HCCHAR_MC_0 | HCcharEpDir | HCcharLowSpeed; |
1582 | USBx_HC(ch_num)->HCCHAR = tmpreg; |
1582 | |
1583 | 1583 | if ((ep_type == EP_TYPE_INTR) || (ep_type == EP_TYPE_ISOC)) |
|
1584 | if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U)) |
1584 | { |
1585 | { |
1585 | USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; |
1586 | switch (hc->ep_type) |
1586 | } |
1587 | { |
1587 | |
1588 | /* Non periodic transfer */ |
1588 | return ret; |
1589 | case EP_TYPE_CTRL: |
1589 | } |
1590 | case EP_TYPE_BULK: |
1590 | |
1591 | 1591 | /** |
|
1592 | len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); |
1592 | * @brief Start a transfer over a host channel |
1593 | 1593 | * @param USBx Selected device |
|
1594 | /* check if there is enough space in FIFO space */ |
1594 | * @param hc pointer to host channel structure |
1595 | if (len_words > (USBx->HNPTXSTS & 0xFFFFU)) |
1595 | * @retval HAL state |
1596 | { |
1596 | */ |
1597 | /* need to process data in nptxfempty interrupt */ |
1597 | HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc) |
1598 | USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM; |
1598 | { |
1599 | } |
1599 | uint32_t USBx_BASE = (uint32_t)USBx; |
1600 | break; |
1600 | uint32_t ch_num = (uint32_t)hc->ch_num; |
1601 | 1601 | __IO uint32_t tmpreg; |
|
1602 | /* Periodic transfer */ |
1602 | uint8_t is_oddframe; |
1603 | case EP_TYPE_INTR: |
1603 | uint16_t len_words; |
1604 | case EP_TYPE_ISOC: |
1604 | uint16_t num_packets; |
1605 | len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); |
1605 | uint16_t max_hc_pkt_count = HC_MAX_PKT_CNT; |
1606 | /* check if there is enough space in FIFO space */ |
1606 | |
1607 | if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */ |
1607 | /* Compute the expected number of packets associated to the transfer */ |
1608 | { |
1608 | if (hc->xfer_len > 0U) |
1609 | /* need to process data in ptxfempty interrupt */ |
1609 | { |
1610 | USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM; |
1610 | num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet); |
1611 | } |
1611 | |
1612 | break; |
1612 | if (num_packets > max_hc_pkt_count) |
1613 | 1613 | { |
|
1614 | default: |
1614 | num_packets = max_hc_pkt_count; |
1615 | break; |
1615 | hc->XferSize = (uint32_t)num_packets * hc->max_packet; |
1616 | } |
1616 | } |
1617 | 1617 | } |
|
1618 | /* Write packet into the Tx FIFO. */ |
1618 | else |
1619 | (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len); |
1619 | { |
1620 | } |
1620 | num_packets = 1U; |
1621 | 1621 | } |
|
1622 | return HAL_OK; |
1622 | |
1623 | } |
1623 | /* |
1624 | 1624 | * For IN channel HCTSIZ.XferSize is expected to be an integer multiple of |
|
1625 | /** |
1625 | * max_packet size. |
1626 | * @brief Read all host channel interrupts status |
1626 | */ |
1627 | * @param USBx Selected device |
1627 | if (hc->ep_is_in != 0U) |
1628 | * @retval HAL state |
1628 | { |
1629 | */ |
1629 | hc->XferSize = (uint32_t)num_packets * hc->max_packet; |
1630 | uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx) |
1630 | } |
1631 | { |
1631 | else |
1632 | uint32_t USBx_BASE = (uint32_t)USBx; |
1632 | { |
1633 | 1633 | hc->XferSize = hc->xfer_len; |
|
1634 | return ((USBx_HOST->HAINT) & 0xFFFFU); |
1634 | } |
1635 | } |
1635 | |
1636 | 1636 | /* Initialize the HCTSIZn register */ |
|
1637 | /** |
1637 | USBx_HC(ch_num)->HCTSIZ = (hc->XferSize & USB_OTG_HCTSIZ_XFRSIZ) | |
1638 | * @brief Halt a host channel |
1638 | (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | |
1639 | * @param USBx Selected device |
1639 | (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID); |
1640 | * @param hc_num Host Channel number |
1640 | |
1641 | * This parameter can be a value from 1 to 15 |
1641 | is_oddframe = (((uint32_t)USBx_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U; |
1642 | * @retval HAL state |
1642 | USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; |
1643 | */ |
1643 | USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29; |
1644 | HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) |
1644 | |
1645 | { |
1645 | /* Set host channel enable */ |
1646 | uint32_t USBx_BASE = (uint32_t)USBx; |
1646 | tmpreg = USBx_HC(ch_num)->HCCHAR; |
1647 | uint32_t hcnum = (uint32_t)hc_num; |
1647 | tmpreg &= ~USB_OTG_HCCHAR_CHDIS; |
1648 | uint32_t count = 0U; |
1648 | |
1649 | uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18; |
1649 | /* make sure to set the correct ep direction */ |
1650 | uint32_t ChannelEna = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31; |
1650 | if (hc->ep_is_in != 0U) |
1651 | 1651 | { |
|
1652 | if (((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == USB_OTG_GAHBCFG_DMAEN) && |
1652 | tmpreg |= USB_OTG_HCCHAR_EPDIR; |
1653 | (ChannelEna == 0U)) |
1653 | } |
1654 | { |
1654 | else |
1655 | return HAL_OK; |
1655 | { |
1656 | } |
1656 | tmpreg &= ~USB_OTG_HCCHAR_EPDIR; |
1657 | 1657 | } |
|
1658 | /* Check for space in the request queue to issue the halt. */ |
1658 | tmpreg |= USB_OTG_HCCHAR_CHENA; |
1659 | if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK)) |
1659 | USBx_HC(ch_num)->HCCHAR = tmpreg; |
1660 | { |
1660 | |
1661 | USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; |
1661 | if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U)) |
1662 | 1662 | { |
|
1663 | if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U) |
1663 | switch (hc->ep_type) |
1664 | { |
1664 | { |
1665 | if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U) |
1665 | /* Non periodic transfer */ |
1666 | { |
1666 | case EP_TYPE_CTRL: |
1667 | USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; |
1667 | case EP_TYPE_BULK: |
1668 | USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; |
1668 | |
1669 | USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; |
1669 | len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); |
1670 | do |
1670 | |
1671 | { |
1671 | /* check if there is enough space in FIFO space */ |
1672 | if (++count > 1000U) |
1672 | if (len_words > (USBx->HNPTXSTS & 0xFFFFU)) |
1673 | { |
1673 | { |
1674 | break; |
1674 | /* need to process data in nptxfempty interrupt */ |
1675 | } |
1675 | USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM; |
1676 | } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); |
1676 | } |
1677 | } |
1677 | break; |
1678 | else |
1678 | |
1679 | { |
1679 | /* Periodic transfer */ |
1680 | USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; |
1680 | case EP_TYPE_INTR: |
1681 | } |
1681 | case EP_TYPE_ISOC: |
1682 | } |
1682 | len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); |
1683 | } |
1683 | /* check if there is enough space in FIFO space */ |
1684 | else |
1684 | if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */ |
1685 | { |
1685 | { |
1686 | USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; |
1686 | /* need to process data in ptxfempty interrupt */ |
1687 | 1687 | USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM; |
|
1688 | if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U) |
1688 | } |
1689 | { |
1689 | break; |
1690 | USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; |
1690 | |
1691 | USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; |
1691 | default: |
1692 | USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; |
1692 | break; |
1693 | do |
1693 | } |
1694 | { |
1694 | |
1695 | if (++count > 1000U) |
1695 | /* Write packet into the Tx FIFO. */ |
1696 | { |
1696 | (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len); |
1697 | break; |
1697 | } |
1698 | } |
1698 | |
1699 | } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); |
1699 | return HAL_OK; |
1700 | } |
1700 | } |
1701 | else |
1701 | |
1702 | { |
1702 | /** |
1703 | USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; |
1703 | * @brief Read all host channel interrupts status |
1704 | } |
1704 | * @param USBx Selected device |
1705 | } |
1705 | * @retval HAL state |
1706 | 1706 | */ |
|
1707 | return HAL_OK; |
1707 | uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx) |
1708 | } |
1708 | { |
1709 | 1709 | uint32_t USBx_BASE = (uint32_t)USBx; |
|
1710 | /** |
1710 | |
1711 | * @brief Initiate Do Ping protocol |
1711 | return ((USBx_HOST->HAINT) & 0xFFFFU); |
1712 | * @param USBx Selected device |
1712 | } |
1713 | * @param hc_num Host Channel number |
1713 | |
1714 | * This parameter can be a value from 1 to 15 |
1714 | /** |
1715 | * @retval HAL state |
1715 | * @brief Halt a host channel |
1716 | */ |
1716 | * @param USBx Selected device |
1717 | HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num) |
1717 | * @param hc_num Host Channel number |
1718 | { |
1718 | * This parameter can be a value from 1 to 15 |
1719 | uint32_t USBx_BASE = (uint32_t)USBx; |
1719 | * @retval HAL state |
1720 | uint32_t chnum = (uint32_t)ch_num; |
1720 | */ |
1721 | uint32_t num_packets = 1U; |
1721 | HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) |
1722 | uint32_t tmpreg; |
1722 | { |
1723 | 1723 | uint32_t USBx_BASE = (uint32_t)USBx; |
|
1724 | USBx_HC(chnum)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | |
1724 | uint32_t hcnum = (uint32_t)hc_num; |
1725 | USB_OTG_HCTSIZ_DOPING; |
1725 | __IO uint32_t count = 0U; |
1726 | 1726 | uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18; |
|
1727 | /* Set host channel enable */ |
1727 | uint32_t ChannelEna = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31; |
1728 | tmpreg = USBx_HC(chnum)->HCCHAR; |
1728 | uint32_t SplitEna = (USBx_HC(hcnum)->HCSPLT & USB_OTG_HCSPLT_SPLITEN) >> 31; |
1729 | tmpreg &= ~USB_OTG_HCCHAR_CHDIS; |
1729 | |
1730 | tmpreg |= USB_OTG_HCCHAR_CHENA; |
1730 | /* In buffer DMA, Channel disable must not be programmed for non-split periodic channels. |
1731 | USBx_HC(chnum)->HCCHAR = tmpreg; |
1731 | At the end of the next uframe/frame (in the worst case), the core generates a channel halted |
1732 | 1732 | and disables the channel automatically. */ |
|
1733 | return HAL_OK; |
1733 | |
1734 | } |
1734 | if ((((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == USB_OTG_GAHBCFG_DMAEN) && (SplitEna == 0U)) && |
1735 | 1735 | ((ChannelEna == 0U) || (((HcEpType == HCCHAR_ISOC) || (HcEpType == HCCHAR_INTR))))) |
|
1736 | /** |
1736 | { |
1737 | * @brief Stop Host Core |
1737 | return HAL_OK; |
1738 | * @param USBx Selected device |
1738 | } |
1739 | * @retval HAL state |
1739 | |
1740 | */ |
1740 | /* Check for space in the request queue to issue the halt. */ |
1741 | HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) |
1741 | if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK)) |
1742 | { |
1742 | { |
1743 | uint32_t USBx_BASE = (uint32_t)USBx; |
1743 | USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; |
1744 | uint32_t count = 0U; |
1744 | |
1745 | uint32_t value; |
1745 | if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U) |
1746 | uint32_t i; |
1746 | { |
1747 | 1747 | if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U) |
|
1748 | (void)USB_DisableGlobalInt(USBx); |
1748 | { |
1749 | 1749 | USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; |
|
1750 | /* Flush FIFO */ |
1750 | USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; |
1751 | (void)USB_FlushTxFifo(USBx, 0x10U); |
1751 | do |
1752 | (void)USB_FlushRxFifo(USBx); |
1752 | { |
1753 | 1753 | count++; |
|
1754 | /* Flush out any leftover queued requests. */ |
1754 | |
1755 | for (i = 0U; i <= 15U; i++) |
1755 | if (count > 1000U) |
1756 | { |
1756 | { |
1757 | value = USBx_HC(i)->HCCHAR; |
1757 | break; |
1758 | value |= USB_OTG_HCCHAR_CHDIS; |
1758 | } |
1759 | value &= ~USB_OTG_HCCHAR_CHENA; |
1759 | } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); |
1760 | value &= ~USB_OTG_HCCHAR_EPDIR; |
1760 | } |
1761 | USBx_HC(i)->HCCHAR = value; |
1761 | else |
1762 | } |
1762 | { |
1763 | 1763 | USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; |
|
1764 | /* Halt all channels to put them into a known state. */ |
1764 | } |
1765 | for (i = 0U; i <= 15U; i++) |
1765 | } |
1766 | { |
1766 | else |
1767 | value = USBx_HC(i)->HCCHAR; |
1767 | { |
1768 | value |= USB_OTG_HCCHAR_CHDIS; |
1768 | USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; |
1769 | value |= USB_OTG_HCCHAR_CHENA; |
1769 | } |
1770 | value &= ~USB_OTG_HCCHAR_EPDIR; |
1770 | } |
1771 | USBx_HC(i)->HCCHAR = value; |
1771 | else |
1772 | 1772 | { |
|
1773 | do |
1773 | USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; |
1774 | { |
1774 | |
1775 | if (++count > 1000U) |
1775 | if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U) |
1776 | { |
1776 | { |
1777 | break; |
1777 | USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; |
1778 | } |
1778 | USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; |
1779 | } while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); |
1779 | do |
1780 | } |
1780 | { |
1781 | 1781 | count++; |
|
1782 | /* Clear any pending Host interrupts */ |
1782 | |
1783 | USBx_HOST->HAINT = 0xFFFFFFFFU; |
1783 | if (count > 1000U) |
1784 | USBx->GINTSTS = 0xFFFFFFFFU; |
1784 | { |
1785 | 1785 | break; |
|
1786 | return HAL_OK; |
1786 | } |
1787 | } |
1787 | } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); |
1788 | 1788 | } |
|
1789 | /** |
1789 | else |
1790 | * @brief USB_ActivateRemoteWakeup active remote wakeup signalling |
1790 | { |
1791 | * @param USBx Selected device |
1791 | USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; |
1792 | * @retval HAL status |
1792 | } |
1793 | */ |
1793 | } |
1794 | HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) |
1794 | |
1795 | { |
1795 | return HAL_OK; |
1796 | uint32_t USBx_BASE = (uint32_t)USBx; |
1796 | } |
1797 | 1797 | ||
1798 | if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) |
1798 | /** |
1799 | { |
1799 | * @brief Initiate Do Ping protocol |
1800 | /* active Remote wakeup signalling */ |
1800 | * @param USBx Selected device |
1801 | USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG; |
1801 | * @param hc_num Host Channel number |
1802 | } |
1802 | * This parameter can be a value from 1 to 15 |
1803 | 1803 | * @retval HAL state |
|
1804 | return HAL_OK; |
1804 | */ |
1805 | } |
1805 | HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num) |
1806 | 1806 | { |
|
1807 | /** |
1807 | uint32_t USBx_BASE = (uint32_t)USBx; |
1808 | * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling |
1808 | uint32_t chnum = (uint32_t)ch_num; |
1809 | * @param USBx Selected device |
1809 | uint32_t num_packets = 1U; |
1810 | * @retval HAL status |
1810 | uint32_t tmpreg; |
1811 | */ |
1811 | |
1812 | HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) |
1812 | USBx_HC(chnum)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | |
1813 | { |
1813 | USB_OTG_HCTSIZ_DOPING; |
1814 | uint32_t USBx_BASE = (uint32_t)USBx; |
1814 | |
1815 | 1815 | /* Set host channel enable */ |
|
1816 | /* active Remote wakeup signalling */ |
1816 | tmpreg = USBx_HC(chnum)->HCCHAR; |
1817 | USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG); |
1817 | tmpreg &= ~USB_OTG_HCCHAR_CHDIS; |
1818 | 1818 | tmpreg |= USB_OTG_HCCHAR_CHENA; |
|
1819 | return HAL_OK; |
1819 | USBx_HC(chnum)->HCCHAR = tmpreg; |
1820 | } |
1820 | |
1821 | #endif /* defined (USB_OTG_FS) */ |
1821 | return HAL_OK; |
1822 | 1822 | } |
|
1823 | #if defined (USB) |
1823 | |
1824 | /** |
1824 | /** |
1825 | * @brief Initializes the USB Core |
1825 | * @brief Stop Host Core |
1826 | * @param USBx USB Instance |
1826 | * @param USBx Selected device |
1827 | * @param cfg pointer to a USB_CfgTypeDef structure that contains |
1827 | * @retval HAL state |
1828 | * the configuration information for the specified USBx peripheral. |
1828 | */ |
1829 | * @retval HAL status |
1829 | HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) |
1830 | */ |
1830 | { |
1831 | HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) |
1831 | HAL_StatusTypeDef ret = HAL_OK; |
1832 | { |
1832 | uint32_t USBx_BASE = (uint32_t)USBx; |
1833 | /* Prevent unused argument(s) compilation warning */ |
1833 | __IO uint32_t count = 0U; |
1834 | UNUSED(USBx); |
1834 | uint32_t value; |
1835 | UNUSED(cfg); |
1835 | uint32_t i; |
1836 | 1836 | ||
1837 | /* NOTE : - This function is not required by USB Device FS peripheral, it is used |
1837 | (void)USB_DisableGlobalInt(USBx); |
1838 | only by USB OTG FS peripheral. |
1838 | |
1839 | - This function is added to ensure compatibility across platforms. |
1839 | /* Flush USB FIFO */ |
1840 | */ |
1840 | if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ |
1841 | 1841 | { |
|
1842 | return HAL_OK; |
1842 | ret = HAL_ERROR; |
1843 | } |
1843 | } |
1844 | 1844 | ||
1845 | /** |
1845 | if (USB_FlushRxFifo(USBx) != HAL_OK) |
1846 | * @brief USB_EnableGlobalInt |
1846 | { |
1847 | * Enables the controller's Global Int in the AHB Config reg |
1847 | ret = HAL_ERROR; |
1848 | * @param USBx Selected device |
1848 | } |
1849 | * @retval HAL status |
1849 | |
1850 | */ |
1850 | /* Flush out any leftover queued requests. */ |
1851 | HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx) |
1851 | for (i = 0U; i <= 15U; i++) |
1852 | { |
1852 | { |
1853 | uint32_t winterruptmask; |
1853 | value = USBx_HC(i)->HCCHAR; |
1854 | 1854 | value |= USB_OTG_HCCHAR_CHDIS; |
|
1855 | /* Clear pending interrupts */ |
1855 | value &= ~USB_OTG_HCCHAR_CHENA; |
1856 | USBx->ISTR = 0U; |
1856 | value &= ~USB_OTG_HCCHAR_EPDIR; |
1857 | 1857 | USBx_HC(i)->HCCHAR = value; |
|
1858 | /* Set winterruptmask variable */ |
1858 | } |
1859 | winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | |
1859 | |
1860 | USB_CNTR_SUSPM | USB_CNTR_ERRM | |
1860 | /* Halt all channels to put them into a known state. */ |
1861 | USB_CNTR_SOFM | USB_CNTR_ESOFM | |
1861 | for (i = 0U; i <= 15U; i++) |
1862 | USB_CNTR_RESETM; |
1862 | { |
1863 | 1863 | value = USBx_HC(i)->HCCHAR; |
|
1864 | /* Set interrupt mask */ |
1864 | value |= USB_OTG_HCCHAR_CHDIS; |
1865 | USBx->CNTR = (uint16_t)winterruptmask; |
1865 | value |= USB_OTG_HCCHAR_CHENA; |
1866 | 1866 | value &= ~USB_OTG_HCCHAR_EPDIR; |
|
1867 | return HAL_OK; |
1867 | USBx_HC(i)->HCCHAR = value; |
1868 | } |
1868 | |
1869 | 1869 | do |
|
1870 | /** |
1870 | { |
1871 | * @brief USB_DisableGlobalInt |
1871 | count++; |
1872 | * Disable the controller's Global Int in the AHB Config reg |
1872 | |
1873 | * @param USBx Selected device |
1873 | if (count > 1000U) |
1874 | * @retval HAL status |
1874 | { |
1875 | */ |
1875 | break; |
1876 | HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx) |
1876 | } |
1877 | { |
1877 | } while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); |
1878 | uint32_t winterruptmask; |
1878 | } |
1879 | 1879 | ||
1880 | /* Set winterruptmask variable */ |
1880 | /* Clear any pending Host interrupts */ |
1881 | winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | |
1881 | USBx_HOST->HAINT = CLEAR_INTERRUPT_MASK; |
1882 | USB_CNTR_SUSPM | USB_CNTR_ERRM | |
1882 | USBx->GINTSTS = CLEAR_INTERRUPT_MASK; |
1883 | USB_CNTR_SOFM | USB_CNTR_ESOFM | |
1883 | |
1884 | USB_CNTR_RESETM; |
1884 | (void)USB_EnableGlobalInt(USBx); |
1885 | 1885 | ||
1886 | /* Clear interrupt mask */ |
1886 | return ret; |
1887 | USBx->CNTR &= (uint16_t)(~winterruptmask); |
1887 | } |
1888 | 1888 | ||
1889 | return HAL_OK; |
1889 | /** |
1890 | } |
1890 | * @brief USB_ActivateRemoteWakeup active remote wakeup signalling |
1891 | 1891 | * @param USBx Selected device |
|
1892 | /** |
1892 | * @retval HAL status |
1893 | * @brief USB_SetCurrentMode Set functional mode |
1893 | */ |
1894 | * @param USBx Selected device |
1894 | HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) |
1895 | * @param mode current core mode |
1895 | { |
1896 | * This parameter can be one of the these values: |
1896 | uint32_t USBx_BASE = (uint32_t)USBx; |
1897 | * @arg USB_DEVICE_MODE Peripheral mode |
1897 | |
1898 | * @retval HAL status |
1898 | if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) |
1899 | */ |
1899 | { |
1900 | HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode) |
1900 | /* active Remote wakeup signalling */ |
1901 | { |
1901 | USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG; |
1902 | /* Prevent unused argument(s) compilation warning */ |
1902 | } |
1903 | UNUSED(USBx); |
1903 | |
1904 | UNUSED(mode); |
1904 | return HAL_OK; |
1905 | 1905 | } |
|
1906 | /* NOTE : - This function is not required by USB Device FS peripheral, it is used |
1906 | |
1907 | only by USB OTG FS peripheral. |
1907 | /** |
1908 | - This function is added to ensure compatibility across platforms. |
1908 | * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling |
1909 | */ |
1909 | * @param USBx Selected device |
1910 | return HAL_OK; |
1910 | * @retval HAL status |
1911 | } |
1911 | */ |
1912 | 1912 | HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) |
|
1913 | /** |
1913 | { |
1914 | * @brief USB_DevInit Initializes the USB controller registers |
1914 | uint32_t USBx_BASE = (uint32_t)USBx; |
1915 | * for device mode |
1915 | |
1916 | * @param USBx Selected device |
1916 | /* active Remote wakeup signalling */ |
1917 | * @param cfg pointer to a USB_CfgTypeDef structure that contains |
1917 | USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG); |
1918 | * the configuration information for the specified USBx peripheral. |
1918 | |
1919 | * @retval HAL status |
1919 | return HAL_OK; |
1920 | */ |
1920 | } |
1921 | HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) |
1921 | #endif /* defined (USB_OTG_FS) */ |
1922 | { |
1922 | |
1923 | /* Prevent unused argument(s) compilation warning */ |
1923 | #if defined (USB) |
1924 | UNUSED(cfg); |
1924 | /** |
1925 | 1925 | * @brief Initializes the USB Core |
|
1926 | /* Init Device */ |
1926 | * @param USBx USB Instance |
1927 | /* CNTR_FRES = 1 */ |
1927 | * @param cfg pointer to a USB_CfgTypeDef structure that contains |
1928 | USBx->CNTR = (uint16_t)USB_CNTR_FRES; |
1928 | * the configuration information for the specified USBx peripheral. |
1929 | 1929 | * @retval HAL status |
|
1930 | /* CNTR_FRES = 0 */ |
1930 | */ |
1931 | USBx->CNTR = 0U; |
1931 | HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) |
1932 | 1932 | { |
|
1933 | /* Clear pending interrupts */ |
1933 | /* Prevent unused argument(s) compilation warning */ |
1934 | USBx->ISTR = 0U; |
1934 | UNUSED(USBx); |
1935 | 1935 | UNUSED(cfg); |
|
1936 | /*Set Btable Address*/ |
1936 | |
1937 | USBx->BTABLE = BTABLE_ADDRESS; |
1937 | /* NOTE : - This function is not required by USB Device FS peripheral, it is used |
1938 | 1938 | only by USB OTG FS peripheral. |
|
1939 | return HAL_OK; |
1939 | - This function is added to ensure compatibility across platforms. |
1940 | } |
1940 | */ |
1941 | 1941 | ||
1942 | /** |
1942 | return HAL_OK; |
1943 | * @brief USB_FlushTxFifo : Flush a Tx FIFO |
1943 | } |
1944 | * @param USBx : Selected device |
1944 | |
1945 | * @param num : FIFO number |
1945 | /** |
1946 | * This parameter can be a value from 1 to 15 |
1946 | * @brief USB_EnableGlobalInt |
1947 | 15 means Flush all Tx FIFOs |
1947 | * Enables the controller's Global Int in the AHB Config reg |
1948 | * @retval HAL status |
1948 | * @param USBx Selected device |
1949 | */ |
1949 | * @retval HAL status |
1950 | HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num) |
1950 | */ |
1951 | { |
1951 | HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx) |
1952 | /* Prevent unused argument(s) compilation warning */ |
1952 | { |
1953 | UNUSED(USBx); |
1953 | uint32_t winterruptmask; |
1954 | UNUSED(num); |
1954 | |
1955 | 1955 | /* Clear pending interrupts */ |
|
1956 | /* NOTE : - This function is not required by USB Device FS peripheral, it is used |
1956 | USBx->ISTR = 0U; |
1957 | only by USB OTG FS peripheral. |
1957 | |
1958 | - This function is added to ensure compatibility across platforms. |
1958 | /* Set winterruptmask variable */ |
1959 | */ |
1959 | winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | |
1960 | 1960 | USB_CNTR_SUSPM | USB_CNTR_ERRM | |
|
1961 | return HAL_OK; |
1961 | USB_CNTR_SOFM | USB_CNTR_ESOFM | |
1962 | } |
1962 | USB_CNTR_RESETM; |
1963 | 1963 | ||
1964 | /** |
1964 | /* Set interrupt mask */ |
1965 | * @brief USB_FlushRxFifo : Flush Rx FIFO |
1965 | USBx->CNTR = (uint16_t)winterruptmask; |
1966 | * @param USBx : Selected device |
1966 | |
1967 | * @retval HAL status |
1967 | return HAL_OK; |
1968 | */ |
1968 | } |
1969 | HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx) |
1969 | |
1970 | { |
1970 | /** |
1971 | /* Prevent unused argument(s) compilation warning */ |
1971 | * @brief USB_DisableGlobalInt |
1972 | UNUSED(USBx); |
1972 | * Disable the controller's Global Int in the AHB Config reg |
1973 | 1973 | * @param USBx Selected device |
|
1974 | /* NOTE : - This function is not required by USB Device FS peripheral, it is used |
1974 | * @retval HAL status |
1975 | only by USB OTG FS peripheral. |
1975 | */ |
1976 | - This function is added to ensure compatibility across platforms. |
1976 | HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx) |
1977 | */ |
1977 | { |
1978 | 1978 | uint32_t winterruptmask; |
|
1979 | return HAL_OK; |
1979 | |
1980 | } |
1980 | /* Set winterruptmask variable */ |
1981 | 1981 | winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | |
|
1982 | #if defined (HAL_PCD_MODULE_ENABLED) |
1982 | USB_CNTR_SUSPM | USB_CNTR_ERRM | |
1983 | /** |
1983 | USB_CNTR_SOFM | USB_CNTR_ESOFM | |
1984 | * @brief Activate and configure an endpoint |
1984 | USB_CNTR_RESETM; |
1985 | * @param USBx Selected device |
1985 | |
1986 | * @param ep pointer to endpoint structure |
1986 | /* Clear interrupt mask */ |
1987 | * @retval HAL status |
1987 | USBx->CNTR &= (uint16_t)(~winterruptmask); |
1988 | */ |
1988 | |
1989 | HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) |
1989 | return HAL_OK; |
1990 | { |
1990 | } |
1991 | HAL_StatusTypeDef ret = HAL_OK; |
1991 | |
1992 | uint16_t wEpRegVal; |
1992 | /** |
1993 | 1993 | * @brief USB_SetCurrentMode Set functional mode |
|
1994 | wEpRegVal = PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_T_MASK; |
1994 | * @param USBx Selected device |
1995 | 1995 | * @param mode current core mode |
|
1996 | /* initialize Endpoint */ |
1996 | * This parameter can be one of the these values: |
1997 | switch (ep->type) |
1997 | * @arg USB_DEVICE_MODE Peripheral mode |
1998 | { |
1998 | * @retval HAL status |
1999 | case EP_TYPE_CTRL: |
1999 | */ |
2000 | wEpRegVal |= USB_EP_CONTROL; |
2000 | HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode) |
2001 | break; |
2001 | { |
2002 | 2002 | /* Prevent unused argument(s) compilation warning */ |
|
2003 | case EP_TYPE_BULK: |
2003 | UNUSED(USBx); |
2004 | wEpRegVal |= USB_EP_BULK; |
2004 | UNUSED(mode); |
2005 | break; |
2005 | |
2006 | 2006 | /* NOTE : - This function is not required by USB Device FS peripheral, it is used |
|
2007 | case EP_TYPE_INTR: |
2007 | only by USB OTG FS peripheral. |
2008 | wEpRegVal |= USB_EP_INTERRUPT; |
2008 | - This function is added to ensure compatibility across platforms. |
2009 | break; |
2009 | */ |
2010 | 2010 | return HAL_OK; |
|
2011 | case EP_TYPE_ISOC: |
2011 | } |
2012 | wEpRegVal |= USB_EP_ISOCHRONOUS; |
2012 | |
2013 | break; |
2013 | /** |
2014 | 2014 | * @brief USB_DevInit Initializes the USB controller registers |
|
2015 | default: |
2015 | * for device mode |
2016 | ret = HAL_ERROR; |
2016 | * @param USBx Selected device |
2017 | break; |
2017 | * @param cfg pointer to a USB_CfgTypeDef structure that contains |
2018 | } |
2018 | * the configuration information for the specified USBx peripheral. |
2019 | 2019 | * @retval HAL status |
|
2020 | PCD_SET_ENDPOINT(USBx, ep->num, (wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); |
2020 | */ |
2021 | 2021 | HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) |
|
2022 | PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num); |
2022 | { |
2023 | 2023 | /* Prevent unused argument(s) compilation warning */ |
|
2024 | if (ep->doublebuffer == 0U) |
2024 | UNUSED(cfg); |
2025 | { |
2025 | |
2026 | if (ep->is_in != 0U) |
2026 | /* Init Device */ |
2027 | { |
2027 | /* CNTR_FRES = 1 */ |
2028 | /*Set the endpoint Transmit buffer address */ |
2028 | USBx->CNTR = (uint16_t)USB_CNTR_FRES; |
2029 | PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress); |
2029 | |
2030 | PCD_CLEAR_TX_DTOG(USBx, ep->num); |
2030 | /* CNTR_FRES = 0 */ |
2031 | 2031 | USBx->CNTR = 0U; |
|
2032 | if (ep->type != EP_TYPE_ISOC) |
2032 | |
2033 | { |
2033 | /* Clear pending interrupts */ |
2034 | /* Configure NAK status for the Endpoint */ |
2034 | USBx->ISTR = 0U; |
2035 | PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); |
2035 | |
2036 | } |
2036 | /*Set Btable Address*/ |
2037 | else |
2037 | USBx->BTABLE = BTABLE_ADDRESS; |
2038 | { |
2038 | |
2039 | /* Configure TX Endpoint to disabled state */ |
2039 | return HAL_OK; |
2040 | PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); |
2040 | } |
2041 | } |
2041 | |
2042 | } |
2042 | /** |
2043 | else |
2043 | * @brief USB_FlushTxFifo : Flush a Tx FIFO |
2044 | { |
2044 | * @param USBx : Selected device |
2045 | /*Set the endpoint Receive buffer address */ |
2045 | * @param num : FIFO number |
2046 | PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress); |
2046 | * This parameter can be a value from 1 to 15 |
2047 | 2047 | 15 means Flush all Tx FIFOs |
|
2048 | /*Set the endpoint Receive buffer counter*/ |
2048 | * @retval HAL status |
2049 | PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket); |
2049 | */ |
2050 | PCD_CLEAR_RX_DTOG(USBx, ep->num); |
2050 | HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef const *USBx, uint32_t num) |
2051 | 2051 | { |
|
2052 | /* Configure VALID status for the Endpoint*/ |
2052 | /* Prevent unused argument(s) compilation warning */ |
2053 | PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); |
2053 | UNUSED(USBx); |
2054 | } |
2054 | UNUSED(num); |
2055 | } |
2055 | |
2056 | /*Double Buffer*/ |
2056 | /* NOTE : - This function is not required by USB Device FS peripheral, it is used |
2057 | else |
2057 | only by USB OTG FS peripheral. |
2058 | { |
2058 | - This function is added to ensure compatibility across platforms. |
2059 | /* Set the endpoint as double buffered */ |
2059 | */ |
2060 | PCD_SET_EP_DBUF(USBx, ep->num); |
2060 | |
2061 | 2061 | return HAL_OK; |
|
2062 | /* Set buffer address for double buffered mode */ |
2062 | } |
2063 | PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1); |
2063 | |
2064 | 2064 | /** |
|
2065 | if (ep->is_in == 0U) |
2065 | * @brief USB_FlushRxFifo : Flush Rx FIFO |
2066 | { |
2066 | * @param USBx : Selected device |
2067 | /* Clear the data toggle bits for the endpoint IN/OUT */ |
2067 | * @retval HAL status |
2068 | PCD_CLEAR_RX_DTOG(USBx, ep->num); |
2068 | */ |
2069 | PCD_CLEAR_TX_DTOG(USBx, ep->num); |
2069 | HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef const *USBx) |
2070 | 2070 | { |
|
2071 | PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); |
2071 | /* Prevent unused argument(s) compilation warning */ |
2072 | PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); |
2072 | UNUSED(USBx); |
2073 | } |
2073 | |
2074 | else |
2074 | /* NOTE : - This function is not required by USB Device FS peripheral, it is used |
2075 | { |
2075 | only by USB OTG FS peripheral. |
2076 | /* Clear the data toggle bits for the endpoint IN/OUT */ |
2076 | - This function is added to ensure compatibility across platforms. |
2077 | PCD_CLEAR_RX_DTOG(USBx, ep->num); |
2077 | */ |
2078 | PCD_CLEAR_TX_DTOG(USBx, ep->num); |
2078 | |
2079 | 2079 | return HAL_OK; |
|
2080 | if (ep->type != EP_TYPE_ISOC) |
2080 | } |
2081 | { |
2081 | |
2082 | /* Configure NAK status for the Endpoint */ |
2082 | |
2083 | PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); |
2083 | #if defined (HAL_PCD_MODULE_ENABLED) |
2084 | } |
2084 | /** |
2085 | else |
2085 | * @brief Activate and configure an endpoint |
2086 | { |
2086 | * @param USBx Selected device |
2087 | /* Configure TX Endpoint to disabled state */ |
2087 | * @param ep pointer to endpoint structure |
2088 | PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); |
2088 | * @retval HAL status |
2089 | } |
2089 | */ |
2090 | 2090 | HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) |
|
2091 | PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); |
2091 | { |
2092 | } |
2092 | HAL_StatusTypeDef ret = HAL_OK; |
2093 | } |
2093 | uint16_t wEpRegVal; |
2094 | 2094 | ||
2095 | return ret; |
2095 | wEpRegVal = PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_T_MASK; |
2096 | } |
2096 | |
2097 | 2097 | /* initialize Endpoint */ |
|
2098 | /** |
2098 | switch (ep->type) |
2099 | * @brief De-activate and de-initialize an endpoint |
2099 | { |
2100 | * @param USBx Selected device |
2100 | case EP_TYPE_CTRL: |
2101 | * @param ep pointer to endpoint structure |
2101 | wEpRegVal |= USB_EP_CONTROL; |
2102 | * @retval HAL status |
2102 | break; |
2103 | */ |
2103 | |
2104 | HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) |
2104 | case EP_TYPE_BULK: |
2105 | { |
2105 | wEpRegVal |= USB_EP_BULK; |
2106 | if (ep->doublebuffer == 0U) |
2106 | break; |
2107 | { |
2107 | |
2108 | if (ep->is_in != 0U) |
2108 | case EP_TYPE_INTR: |
2109 | { |
2109 | wEpRegVal |= USB_EP_INTERRUPT; |
2110 | PCD_CLEAR_TX_DTOG(USBx, ep->num); |
2110 | break; |
2111 | 2111 | ||
2112 | /* Configure DISABLE status for the Endpoint*/ |
2112 | case EP_TYPE_ISOC: |
2113 | PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); |
2113 | wEpRegVal |= USB_EP_ISOCHRONOUS; |
2114 | } |
2114 | break; |
2115 | else |
2115 | |
2116 | { |
2116 | default: |
2117 | PCD_CLEAR_RX_DTOG(USBx, ep->num); |
2117 | ret = HAL_ERROR; |
2118 | 2118 | break; |
|
2119 | /* Configure DISABLE status for the Endpoint*/ |
2119 | } |
2120 | PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); |
2120 | |
2121 | } |
2121 | PCD_SET_ENDPOINT(USBx, ep->num, (wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); |
2122 | } |
2122 | |
2123 | /*Double Buffer*/ |
2123 | PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num); |
2124 | else |
2124 | |
2125 | { |
2125 | if (ep->doublebuffer == 0U) |
2126 | if (ep->is_in == 0U) |
2126 | { |
2127 | { |
2127 | if (ep->is_in != 0U) |
2128 | /* Clear the data toggle bits for the endpoint IN/OUT*/ |
2128 | { |
2129 | PCD_CLEAR_RX_DTOG(USBx, ep->num); |
2129 | /*Set the endpoint Transmit buffer address */ |
2130 | PCD_CLEAR_TX_DTOG(USBx, ep->num); |
2130 | PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress); |
2131 | 2131 | PCD_CLEAR_TX_DTOG(USBx, ep->num); |
|
2132 | /* Reset value of the data toggle bits for the endpoint out*/ |
2132 | |
2133 | PCD_TX_DTOG(USBx, ep->num); |
2133 | if (ep->type != EP_TYPE_ISOC) |
2134 | 2134 | { |
|
2135 | PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); |
2135 | /* Configure NAK status for the Endpoint */ |
2136 | PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); |
2136 | PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); |
2137 | } |
2137 | } |
2138 | else |
2138 | else |
2139 | { |
2139 | { |
2140 | /* Clear the data toggle bits for the endpoint IN/OUT*/ |
2140 | /* Configure TX Endpoint to disabled state */ |
2141 | PCD_CLEAR_RX_DTOG(USBx, ep->num); |
2141 | PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); |
2142 | PCD_CLEAR_TX_DTOG(USBx, ep->num); |
2142 | } |
2143 | PCD_RX_DTOG(USBx, ep->num); |
2143 | } |
2144 | 2144 | else |
|
2145 | /* Configure DISABLE status for the Endpoint*/ |
2145 | { |
2146 | PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); |
2146 | /* Set the endpoint Receive buffer address */ |
2147 | PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); |
2147 | PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress); |
2148 | } |
2148 | |
2149 | } |
2149 | /* Set the endpoint Receive buffer counter */ |
2150 | 2150 | PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket); |
|
2151 | return HAL_OK; |
2151 | PCD_CLEAR_RX_DTOG(USBx, ep->num); |
2152 | } |
2152 | |
2153 | 2153 | if (ep->num == 0U) |
|
2154 | /** |
2154 | { |
2155 | * @brief USB_EPStartXfer setup and starts a transfer over an EP |
2155 | /* Configure VALID status for EP0 */ |
2156 | * @param USBx Selected device |
2156 | PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); |
2157 | * @param ep pointer to endpoint structure |
2157 | } |
2158 | * @retval HAL status |
2158 | else |
2159 | */ |
2159 | { |
2160 | HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) |
2160 | /* Configure NAK status for OUT Endpoint */ |
2161 | { |
2161 | PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_NAK); |
2162 | uint32_t len; |
2162 | } |
2163 | uint16_t pmabuffer; |
2163 | } |
2164 | uint16_t wEPVal; |
2164 | } |
2165 | 2165 | #if (USE_USB_DOUBLE_BUFFER == 1U) |
|
2166 | /* IN endpoint */ |
2166 | /* Double Buffer */ |
2167 | if (ep->is_in == 1U) |
2167 | else |
2168 | { |
2168 | { |
2169 | /*Multi packet transfer*/ |
2169 | if (ep->type == EP_TYPE_BULK) |
2170 | if (ep->xfer_len > ep->maxpacket) |
2170 | { |
2171 | { |
2171 | /* Set bulk endpoint as double buffered */ |
2172 | len = ep->maxpacket; |
2172 | PCD_SET_BULK_EP_DBUF(USBx, ep->num); |
2173 | } |
2173 | } |
2174 | else |
2174 | else |
2175 | { |
2175 | { |
2176 | len = ep->xfer_len; |
2176 | /* Set the ISOC endpoint in double buffer mode */ |
2177 | } |
2177 | PCD_CLEAR_EP_KIND(USBx, ep->num); |
2178 | 2178 | } |
|
2179 | /* configure and validate Tx endpoint */ |
2179 | |
2180 | if (ep->doublebuffer == 0U) |
2180 | /* Set buffer address for double buffered mode */ |
2181 | { |
2181 | PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1); |
2182 | USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len); |
2182 | |
2183 | PCD_SET_EP_TX_CNT(USBx, ep->num, len); |
2183 | if (ep->is_in == 0U) |
2184 | } |
2184 | { |
2185 | else |
2185 | /* Clear the data toggle bits for the endpoint IN/OUT */ |
2186 | { |
2186 | PCD_CLEAR_RX_DTOG(USBx, ep->num); |
2187 | /* double buffer bulk management */ |
2187 | PCD_CLEAR_TX_DTOG(USBx, ep->num); |
2188 | if (ep->type == EP_TYPE_BULK) |
2188 | |
2189 | { |
2189 | PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); |
2190 | if (ep->xfer_len_db > ep->maxpacket) |
2190 | PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); |
2191 | { |
2191 | } |
2192 | /* enable double buffer */ |
2192 | else |
2193 | PCD_SET_EP_DBUF(USBx, ep->num); |
2193 | { |
2194 | 2194 | /* Clear the data toggle bits for the endpoint IN/OUT */ |
|
2195 | /* each Time to write in PMA xfer_len_db will */ |
2195 | PCD_CLEAR_RX_DTOG(USBx, ep->num); |
2196 | ep->xfer_len_db -= len; |
2196 | PCD_CLEAR_TX_DTOG(USBx, ep->num); |
2197 | 2197 | ||
2198 | /* Fill the two first buffer in the Buffer0 & Buffer1 */ |
2198 | if (ep->type != EP_TYPE_ISOC) |
2199 | if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U) |
2199 | { |
2200 | { |
2200 | /* Configure NAK status for the Endpoint */ |
2201 | /* Set the Double buffer counter for pmabuffer1 */ |
2201 | PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); |
2202 | PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); |
2202 | } |
2203 | pmabuffer = ep->pmaaddr1; |
2203 | else |
2204 | 2204 | { |
|
2205 | /* Write the user buffer to USB PMA */ |
2205 | /* Configure TX Endpoint to disabled state */ |
2206 | USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); |
2206 | PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); |
2207 | ep->xfer_buff += len; |
2207 | } |
2208 | 2208 | ||
2209 | if (ep->xfer_len_db > ep->maxpacket) |
2209 | PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); |
2210 | { |
2210 | } |
2211 | ep->xfer_len_db -= len; |
2211 | } |
2212 | } |
2212 | #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ |
2213 | else |
2213 | |
2214 | { |
2214 | return ret; |
2215 | len = ep->xfer_len_db; |
2215 | } |
2216 | ep->xfer_len_db = 0U; |
2216 | |
2217 | } |
2217 | /** |
2218 | 2218 | * @brief De-activate and de-initialize an endpoint |
|
2219 | /* Set the Double buffer counter for pmabuffer0 */ |
2219 | * @param USBx Selected device |
2220 | PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); |
2220 | * @param ep pointer to endpoint structure |
2221 | pmabuffer = ep->pmaaddr0; |
2221 | * @retval HAL status |
2222 | 2222 | */ |
|
2223 | /* Write the user buffer to USB PMA */ |
2223 | HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) |
2224 | USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); |
2224 | { |
2225 | } |
2225 | if (ep->doublebuffer == 0U) |
2226 | else |
2226 | { |
2227 | { |
2227 | if (ep->is_in != 0U) |
2228 | /* Set the Double buffer counter for pmabuffer0 */ |
2228 | { |
2229 | PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); |
2229 | PCD_CLEAR_TX_DTOG(USBx, ep->num); |
2230 | pmabuffer = ep->pmaaddr0; |
2230 | |
2231 | 2231 | /* Configure DISABLE status for the Endpoint */ |
|
2232 | /* Write the user buffer to USB PMA */ |
2232 | PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); |
2233 | USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); |
2233 | } |
2234 | ep->xfer_buff += len; |
2234 | |
2235 | 2235 | else |
|
2236 | if (ep->xfer_len_db > ep->maxpacket) |
2236 | { |
2237 | { |
2237 | PCD_CLEAR_RX_DTOG(USBx, ep->num); |
2238 | ep->xfer_len_db -= len; |
2238 | |
2239 | } |
2239 | /* Configure DISABLE status for the Endpoint */ |
2240 | else |
2240 | PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); |
2241 | { |
2241 | } |
2242 | len = ep->xfer_len_db; |
2242 | } |
2243 | ep->xfer_len_db = 0U; |
2243 | #if (USE_USB_DOUBLE_BUFFER == 1U) |
2244 | } |
2244 | /* Double Buffer */ |
2245 | 2245 | else |
|
2246 | /* Set the Double buffer counter for pmabuffer1 */ |
2246 | { |
2247 | PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); |
2247 | if (ep->is_in == 0U) |
2248 | pmabuffer = ep->pmaaddr1; |
2248 | { |
2249 | 2249 | /* Clear the data toggle bits for the endpoint IN/OUT*/ |
|
2250 | /* Write the user buffer to USB PMA */ |
2250 | PCD_CLEAR_RX_DTOG(USBx, ep->num); |
2251 | USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); |
2251 | PCD_CLEAR_TX_DTOG(USBx, ep->num); |
2252 | } |
2252 | |
2253 | } |
2253 | /* Reset value of the data toggle bits for the endpoint out*/ |
2254 | /* auto Switch to single buffer mode when transfer <Mps no need to manage in double buffer */ |
2254 | PCD_TX_DTOG(USBx, ep->num); |
2255 | else |
2255 | |
2256 | { |
2256 | PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); |
2257 | len = ep->xfer_len_db; |
2257 | PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); |
2258 | 2258 | } |
|
2259 | /* disable double buffer mode */ |
2259 | else |
2260 | PCD_CLEAR_EP_DBUF(USBx, ep->num); |
2260 | { |
2261 | 2261 | /* Clear the data toggle bits for the endpoint IN/OUT*/ |
|
2262 | /* Set Tx count with nbre of byte to be transmitted */ |
2262 | PCD_CLEAR_RX_DTOG(USBx, ep->num); |
2263 | PCD_SET_EP_TX_CNT(USBx, ep->num, len); |
2263 | PCD_CLEAR_TX_DTOG(USBx, ep->num); |
2264 | pmabuffer = ep->pmaaddr0; |
2264 | PCD_RX_DTOG(USBx, ep->num); |
2265 | 2265 | ||
2266 | /* Write the user buffer to USB PMA */ |
2266 | /* Configure DISABLE status for the Endpoint*/ |
2267 | USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); |
2267 | PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); |
2268 | } |
2268 | PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); |
2269 | }/* end if bulk double buffer */ |
2269 | } |
2270 | 2270 | } |
|
2271 | /* manage isochronous double buffer IN mode */ |
2271 | #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ |
2272 | else |
2272 | |
2273 | { |
2273 | return HAL_OK; |
2274 | /* enable double buffer */ |
2274 | } |
2275 | PCD_SET_EP_DBUF(USBx, ep->num); |
2275 | |
2276 | 2276 | /** |
|
2277 | /* each Time to write in PMA xfer_len_db will */ |
2277 | * @brief USB_EPStartXfer setup and starts a transfer over an EP |
2278 | ep->xfer_len_db -= len; |
2278 | * @param USBx Selected device |
2279 | 2279 | * @param ep pointer to endpoint structure |
|
2280 | /* Fill the data buffer */ |
2280 | * @retval HAL status |
2281 | if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U) |
2281 | */ |
2282 | { |
2282 | HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) |
2283 | /* Set the Double buffer counter for pmabuffer1 */ |
2283 | { |
2284 | PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); |
2284 | uint32_t len; |
2285 | pmabuffer = ep->pmaaddr1; |
2285 | #if (USE_USB_DOUBLE_BUFFER == 1U) |
2286 | 2286 | uint16_t pmabuffer; |
|
2287 | /* Write the user buffer to USB PMA */ |
2287 | uint16_t wEPVal; |
2288 | USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); |
2288 | #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ |
2289 | ep->xfer_buff += len; |
2289 | |
2290 | 2290 | /* IN endpoint */ |
|
2291 | if (ep->xfer_len_db > ep->maxpacket) |
2291 | if (ep->is_in == 1U) |
2292 | { |
2292 | { |
2293 | ep->xfer_len_db -= len; |
2293 | /*Multi packet transfer*/ |
2294 | } |
2294 | if (ep->xfer_len > ep->maxpacket) |
2295 | else |
2295 | { |
2296 | { |
2296 | len = ep->maxpacket; |
2297 | len = ep->xfer_len_db; |
2297 | } |
2298 | ep->xfer_len_db = 0U; |
2298 | else |
2299 | } |
2299 | { |
2300 | 2300 | len = ep->xfer_len; |
|
2301 | if (len > 0U) |
2301 | } |
2302 | { |
2302 | |
2303 | /* Set the Double buffer counter for pmabuffer0 */ |
2303 | /* configure and validate Tx endpoint */ |
2304 | PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); |
2304 | if (ep->doublebuffer == 0U) |
2305 | pmabuffer = ep->pmaaddr0; |
2305 | { |
2306 | 2306 | USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len); |
|
2307 | /* Write the user buffer to USB PMA */ |
2307 | PCD_SET_EP_TX_CNT(USBx, ep->num, len); |
2308 | USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); |
2308 | } |
2309 | } |
2309 | #if (USE_USB_DOUBLE_BUFFER == 1U) |
2310 | } |
2310 | else |
2311 | else |
2311 | { |
2312 | { |
2312 | /* double buffer bulk management */ |
2313 | /* Set the Double buffer counter for pmabuffer0 */ |
2313 | if (ep->type == EP_TYPE_BULK) |
2314 | PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); |
2314 | { |
2315 | pmabuffer = ep->pmaaddr0; |
2315 | if (ep->xfer_len_db > ep->maxpacket) |
2316 | 2316 | { |
|
2317 | /* Write the user buffer to USB PMA */ |
2317 | /* enable double buffer */ |
2318 | USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); |
2318 | PCD_SET_BULK_EP_DBUF(USBx, ep->num); |
2319 | ep->xfer_buff += len; |
2319 | |
2320 | 2320 | /* each Time to write in PMA xfer_len_db will */ |
|
2321 | if (ep->xfer_len_db > ep->maxpacket) |
2321 | ep->xfer_len_db -= len; |
2322 | { |
2322 | |
2323 | ep->xfer_len_db -= len; |
2323 | /* Fill the two first buffer in the Buffer0 & Buffer1 */ |
2324 | } |
2324 | if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U) |
2325 | else |
2325 | { |
2326 | { |
2326 | /* Set the Double buffer counter for pmabuffer1 */ |
2327 | len = ep->xfer_len_db; |
2327 | PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); |
2328 | ep->xfer_len_db = 0U; |
2328 | pmabuffer = ep->pmaaddr1; |
2329 | } |
2329 | |
2330 | 2330 | /* Write the user buffer to USB PMA */ |
|
2331 | if (len > 0U) |
2331 | USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); |
2332 | { |
2332 | ep->xfer_buff += len; |
2333 | /* Set the Double buffer counter for pmabuffer1 */ |
2333 | |
2334 | PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); |
2334 | if (ep->xfer_len_db > ep->maxpacket) |
2335 | pmabuffer = ep->pmaaddr1; |
2335 | { |
2336 | 2336 | ep->xfer_len_db -= len; |
|
2337 | /* Write the user buffer to USB PMA */ |
2337 | } |
2338 | USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); |
2338 | else |
2339 | } |
2339 | { |
2340 | } |
2340 | len = ep->xfer_len_db; |
2341 | } |
2341 | ep->xfer_len_db = 0U; |
2342 | } |
2342 | } |
2343 | 2343 | ||
2344 | PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID); |
2344 | /* Set the Double buffer counter for pmabuffer0 */ |
2345 | } |
2345 | PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); |
2346 | else /* OUT endpoint */ |
2346 | pmabuffer = ep->pmaaddr0; |
2347 | { |
2347 | |
2348 | if (ep->doublebuffer == 0U) |
2348 | /* Write the user buffer to USB PMA */ |
2349 | { |
2349 | USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); |
2350 | /* Multi packet transfer */ |
2350 | } |
2351 | if (ep->xfer_len > ep->maxpacket) |
2351 | else |
2352 | { |
2352 | { |
2353 | len = ep->maxpacket; |
2353 | /* Set the Double buffer counter for pmabuffer0 */ |
2354 | ep->xfer_len -= len; |
2354 | PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); |
2355 | } |
2355 | pmabuffer = ep->pmaaddr0; |
2356 | else |
2356 | |
2357 | { |
2357 | /* Write the user buffer to USB PMA */ |
2358 | len = ep->xfer_len; |
2358 | USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); |
2359 | ep->xfer_len = 0U; |
2359 | ep->xfer_buff += len; |
2360 | } |
2360 | |
2361 | /* configure and validate Rx endpoint */ |
2361 | if (ep->xfer_len_db > ep->maxpacket) |
2362 | PCD_SET_EP_RX_CNT(USBx, ep->num, len); |
2362 | { |
2363 | } |
2363 | ep->xfer_len_db -= len; |
2364 | else |
2364 | } |
2365 | { |
2365 | else |
2366 | /* First Transfer Coming From HAL_PCD_EP_Receive & From ISR */ |
2366 | { |
2367 | /* Set the Double buffer counter */ |
2367 | len = ep->xfer_len_db; |
2368 | if (ep->type == EP_TYPE_BULK) |
2368 | ep->xfer_len_db = 0U; |
2369 | { |
2369 | } |
2370 | PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); |
2370 | |
2371 | 2371 | /* Set the Double buffer counter for pmabuffer1 */ |
|
2372 | /* Coming from ISR */ |
2372 | PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); |
2373 | if (ep->xfer_count != 0U) |
2373 | pmabuffer = ep->pmaaddr1; |
2374 | { |
2374 | |
2375 | /* update last value to check if there is blocking state */ |
2375 | /* Write the user buffer to USB PMA */ |
2376 | wEPVal = PCD_GET_ENDPOINT(USBx, ep->num); |
2376 | USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); |
2377 | 2377 | } |
|
2378 | /*Blocking State */ |
2378 | } |
2379 | if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) || |
2379 | /* auto Switch to single buffer mode when transfer <Mps no need to manage in double buffer */ |
2380 | (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U))) |
2380 | else |
2381 | { |
2381 | { |
2382 | PCD_FreeUserBuffer(USBx, ep->num, 0U); |
2382 | len = ep->xfer_len_db; |
2383 | } |
2383 | |
2384 | } |
2384 | /* disable double buffer mode for Bulk endpoint */ |
2385 | } |
2385 | PCD_CLEAR_BULK_EP_DBUF(USBx, ep->num); |
2386 | /* iso out double */ |
2386 | |
2387 | else if (ep->type == EP_TYPE_ISOC) |
2387 | /* Set Tx count with nbre of byte to be transmitted */ |
2388 | { |
2388 | PCD_SET_EP_TX_CNT(USBx, ep->num, len); |
2389 | /* Multi packet transfer */ |
2389 | pmabuffer = ep->pmaaddr0; |
2390 | if (ep->xfer_len > ep->maxpacket) |
2390 | |
2391 | { |
2391 | /* Write the user buffer to USB PMA */ |
2392 | len = ep->maxpacket; |
2392 | USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); |
2393 | ep->xfer_len -= len; |
2393 | } |
2394 | } |
2394 | } |
2395 | else |
2395 | else /* manage isochronous double buffer IN mode */ |
2396 | { |
2396 | { |
2397 | len = ep->xfer_len; |
2397 | /* each Time to write in PMA xfer_len_db will */ |
2398 | ep->xfer_len = 0U; |
2398 | ep->xfer_len_db -= len; |
2399 | } |
2399 | |
2400 | PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len); |
2400 | /* Fill the data buffer */ |
2401 | } |
2401 | if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U) |
2402 | else |
2402 | { |
2403 | { |
2403 | /* Set the Double buffer counter for pmabuffer1 */ |
2404 | return HAL_ERROR; |
2404 | PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); |
2405 | } |
2405 | pmabuffer = ep->pmaaddr1; |
2406 | } |
2406 | |
2407 | 2407 | /* Write the user buffer to USB PMA */ |
|
2408 | PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); |
2408 | USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); |
2409 | } |
2409 | } |
2410 | 2410 | else |
|
2411 | return HAL_OK; |
2411 | { |
2412 | } |
2412 | /* Set the Double buffer counter for pmabuffer0 */ |
2413 | 2413 | PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); |
|
2414 | 2414 | pmabuffer = ep->pmaaddr0; |
|
2415 | /** |
2415 | |
2416 | * @brief USB_EPSetStall set a stall condition over an EP |
2416 | /* Write the user buffer to USB PMA */ |
2417 | * @param USBx Selected device |
2417 | USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); |
2418 | * @param ep pointer to endpoint structure |
2418 | } |
2419 | * @retval HAL status |
2419 | } |
2420 | */ |
2420 | } |
2421 | HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) |
2421 | #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ |
2422 | { |
2422 | |
2423 | if (ep->is_in != 0U) |
2423 | PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID); |
2424 | { |
2424 | } |
2425 | PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_STALL); |
2425 | else /* OUT endpoint */ |
2426 | } |
2426 | { |
2427 | else |
2427 | if (ep->doublebuffer == 0U) |
2428 | { |
2428 | { |
2429 | PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_STALL); |
2429 | /* Multi packet transfer */ |
2430 | } |
2430 | if (ep->xfer_len > ep->maxpacket) |
2431 | 2431 | { |
|
2432 | return HAL_OK; |
2432 | len = ep->maxpacket; |
2433 | } |
2433 | ep->xfer_len -= len; |
2434 | 2434 | } |
|
2435 | /** |
2435 | else |
2436 | * @brief USB_EPClearStall Clear a stall condition over an EP |
2436 | { |
2437 | * @param USBx Selected device |
2437 | len = ep->xfer_len; |
2438 | * @param ep pointer to endpoint structure |
2438 | ep->xfer_len = 0U; |
2439 | * @retval HAL status |
2439 | } |
2440 | */ |
2440 | /* configure and validate Rx endpoint */ |
2441 | HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) |
2441 | PCD_SET_EP_RX_CNT(USBx, ep->num, len); |
2442 | { |
2442 | } |
2443 | if (ep->doublebuffer == 0U) |
2443 | #if (USE_USB_DOUBLE_BUFFER == 1U) |
2444 | { |
2444 | else |
2445 | if (ep->is_in != 0U) |
2445 | { |
2446 | { |
2446 | /* First Transfer Coming From HAL_PCD_EP_Receive & From ISR */ |
2447 | PCD_CLEAR_TX_DTOG(USBx, ep->num); |
2447 | /* Set the Double buffer counter */ |
2448 | 2448 | if (ep->type == EP_TYPE_BULK) |
|
2449 | if (ep->type != EP_TYPE_ISOC) |
2449 | { |
2450 | { |
2450 | PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); |
2451 | /* Configure NAK status for the Endpoint */ |
2451 | |
2452 | PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); |
2452 | /* Coming from ISR */ |
2453 | } |
2453 | if (ep->xfer_count != 0U) |
2454 | } |
2454 | { |
2455 | else |
2455 | /* update last value to check if there is blocking state */ |
2456 | { |
2456 | wEPVal = PCD_GET_ENDPOINT(USBx, ep->num); |
2457 | PCD_CLEAR_RX_DTOG(USBx, ep->num); |
2457 | |
2458 | 2458 | /*Blocking State */ |
|
2459 | /* Configure VALID status for the Endpoint */ |
2459 | if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) || |
2460 | PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); |
2460 | (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U))) |
2461 | } |
2461 | { |
2462 | } |
2462 | PCD_FREE_USER_BUFFER(USBx, ep->num, 0U); |
2463 | 2463 | } |
|
2464 | return HAL_OK; |
2464 | } |
2465 | } |
2465 | } |
2466 | #endif |
2466 | /* iso out double */ |
2467 | 2467 | else if (ep->type == EP_TYPE_ISOC) |
|
2468 | /** |
2468 | { |
2469 | * @brief USB_StopDevice Stop the usb device mode |
2469 | /* Multi packet transfer */ |
2470 | * @param USBx Selected device |
2470 | if (ep->xfer_len > ep->maxpacket) |
2471 | * @retval HAL status |
2471 | { |
2472 | */ |
2472 | len = ep->maxpacket; |
2473 | HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx) |
2473 | ep->xfer_len -= len; |
2474 | { |
2474 | } |
2475 | /* disable all interrupts and force USB reset */ |
2475 | else |
2476 | USBx->CNTR = (uint16_t)USB_CNTR_FRES; |
2476 | { |
2477 | 2477 | len = ep->xfer_len; |
|
2478 | /* clear interrupt status register */ |
2478 | ep->xfer_len = 0U; |
2479 | USBx->ISTR = 0U; |
2479 | } |
2480 | 2480 | PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len); |
|
2481 | /* switch-off device */ |
2481 | } |
2482 | USBx->CNTR = (uint16_t)(USB_CNTR_FRES | USB_CNTR_PDWN); |
2482 | else |
2483 | 2483 | { |
|
2484 | return HAL_OK; |
2484 | return HAL_ERROR; |
2485 | } |
2485 | } |
2486 | 2486 | } |
|
2487 | /** |
2487 | #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ |
2488 | * @brief USB_SetDevAddress Stop the usb device mode |
2488 | |
2489 | * @param USBx Selected device |
2489 | PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); |
2490 | * @param address new device address to be assigned |
2490 | } |
2491 | * This parameter can be a value from 0 to 255 |
2491 | |
2492 | * @retval HAL status |
2492 | return HAL_OK; |
2493 | */ |
2493 | } |
2494 | HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address) |
2494 | |
2495 | { |
2495 | |
2496 | if (address == 0U) |
2496 | /** |
2497 | { |
2497 | * @brief USB_EPSetStall set a stall condition over an EP |
2498 | /* set device address and enable function */ |
2498 | * @param USBx Selected device |
2499 | USBx->DADDR = (uint16_t)USB_DADDR_EF; |
2499 | * @param ep pointer to endpoint structure |
2500 | } |
2500 | * @retval HAL status |
2501 | 2501 | */ |
|
2502 | return HAL_OK; |
2502 | HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) |
2503 | } |
2503 | { |
2504 | 2504 | if (ep->is_in != 0U) |
|
2505 | /** |
2505 | { |
2506 | * @brief USB_DevConnect Connect the USB device by enabling the pull-up/pull-down |
2506 | PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_STALL); |
2507 | * @param USBx Selected device |
2507 | } |
2508 | * @retval HAL status |
2508 | else |
2509 | */ |
2509 | { |
2510 | HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx) |
2510 | PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_STALL); |
2511 | { |
2511 | } |
2512 | /* Prevent unused argument(s) compilation warning */ |
2512 | |
2513 | UNUSED(USBx); |
2513 | return HAL_OK; |
2514 | 2514 | } |
|
2515 | /* NOTE : - This function is not required by USB Device FS peripheral, it is used |
2515 | |
2516 | only by USB OTG FS peripheral. |
2516 | /** |
2517 | - This function is added to ensure compatibility across platforms. |
2517 | * @brief USB_EPClearStall Clear a stall condition over an EP |
2518 | */ |
2518 | * @param USBx Selected device |
2519 | 2519 | * @param ep pointer to endpoint structure |
|
2520 | return HAL_OK; |
2520 | * @retval HAL status |
2521 | } |
2521 | */ |
2522 | 2522 | HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) |
|
2523 | /** |
2523 | { |
2524 | * @brief USB_DevDisconnect Disconnect the USB device by disabling the pull-up/pull-down |
2524 | if (ep->doublebuffer == 0U) |
2525 | * @param USBx Selected device |
2525 | { |
2526 | * @retval HAL status |
2526 | if (ep->is_in != 0U) |
2527 | */ |
2527 | { |
2528 | HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx) |
2528 | PCD_CLEAR_TX_DTOG(USBx, ep->num); |
2529 | { |
2529 | |
2530 | /* Prevent unused argument(s) compilation warning */ |
2530 | if (ep->type != EP_TYPE_ISOC) |
2531 | UNUSED(USBx); |
2531 | { |
2532 | 2532 | /* Configure NAK status for the Endpoint */ |
|
2533 | /* NOTE : - This function is not required by USB Device FS peripheral, it is used |
2533 | PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); |
2534 | only by USB OTG FS peripheral. |
2534 | } |
2535 | - This function is added to ensure compatibility across platforms. |
2535 | } |
2536 | */ |
2536 | else |
2537 | 2537 | { |
|
2538 | return HAL_OK; |
2538 | PCD_CLEAR_RX_DTOG(USBx, ep->num); |
2539 | } |
2539 | |
2540 | 2540 | /* Configure VALID status for the Endpoint */ |
|
2541 | /** |
2541 | PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); |
2542 | * @brief USB_ReadInterrupts return the global USB interrupt status |
2542 | } |
2543 | * @param USBx Selected device |
2543 | } |
2544 | * @retval HAL status |
2544 | |
2545 | */ |
2545 | return HAL_OK; |
2546 | uint32_t USB_ReadInterrupts(USB_TypeDef *USBx) |
2546 | } |
2547 | { |
2547 | |
2548 | uint32_t tmpreg; |
2548 | /** |
2549 | 2549 | * @brief USB_EPStoptXfer Stop transfer on an EP |
|
2550 | tmpreg = USBx->ISTR; |
2550 | * @param USBx usb device instance |
2551 | return tmpreg; |
2551 | * @param ep pointer to endpoint structure |
2552 | } |
2552 | * @retval HAL status |
2553 | 2553 | */ |
|
2554 | /** |
2554 | HAL_StatusTypeDef USB_EPStopXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) |
2555 | * @brief USB_ReadDevAllOutEpInterrupt return the USB device OUT endpoints interrupt status |
2555 | { |
2556 | * @param USBx Selected device |
2556 | /* IN endpoint */ |
2557 | * @retval HAL status |
2557 | if (ep->is_in == 1U) |
2558 | */ |
2558 | { |
2559 | uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx) |
2559 | if (ep->doublebuffer == 0U) |
2560 | { |
2560 | { |
2561 | /* Prevent unused argument(s) compilation warning */ |
2561 | if (ep->type != EP_TYPE_ISOC) |
2562 | UNUSED(USBx); |
2562 | { |
2563 | /* NOTE : - This function is not required by USB Device FS peripheral, it is used |
2563 | /* Configure NAK status for the Endpoint */ |
2564 | only by USB OTG FS peripheral. |
2564 | PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); |
2565 | - This function is added to ensure compatibility across platforms. |
2565 | } |
2566 | */ |
2566 | else |
2567 | return (0); |
2567 | { |
2568 | } |
2568 | /* Configure TX Endpoint to disabled state */ |
2569 | 2569 | PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); |
|
2570 | /** |
2570 | } |
2571 | * @brief USB_ReadDevAllInEpInterrupt return the USB device IN endpoints interrupt status |
2571 | } |
2572 | * @param USBx Selected device |
2572 | } |
2573 | * @retval HAL status |
2573 | else /* OUT endpoint */ |
2574 | */ |
2574 | { |
2575 | uint32_t USB_ReadDevAllInEpInterrupt(USB_TypeDef *USBx) |
2575 | if (ep->doublebuffer == 0U) |
2576 | { |
2576 | { |
2577 | /* Prevent unused argument(s) compilation warning */ |
2577 | if (ep->type != EP_TYPE_ISOC) |
2578 | UNUSED(USBx); |
2578 | { |
2579 | /* NOTE : - This function is not required by USB Device FS peripheral, it is used |
2579 | /* Configure NAK status for the Endpoint */ |
2580 | only by USB OTG FS peripheral. |
2580 | PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_NAK); |
2581 | - This function is added to ensure compatibility across platforms. |
2581 | } |
2582 | */ |
2582 | else |
2583 | return (0); |
2583 | { |
2584 | } |
2584 | /* Configure RX Endpoint to disabled state */ |
2585 | 2585 | PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); |
|
2586 | /** |
2586 | } |
2587 | * @brief Returns Device OUT EP Interrupt register |
2587 | } |
2588 | * @param USBx Selected device |
2588 | } |
2589 | * @param epnum endpoint number |
2589 | |
2590 | * This parameter can be a value from 0 to 15 |
2590 | return HAL_OK; |
2591 | * @retval Device OUT EP Interrupt register |
2591 | } |
2592 | */ |
2592 | #endif /* defined (HAL_PCD_MODULE_ENABLED) */ |
2593 | uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum) |
2593 | |
2594 | { |
2594 | /** |
2595 | /* Prevent unused argument(s) compilation warning */ |
2595 | * @brief USB_StopDevice Stop the usb device mode |
2596 | UNUSED(USBx); |
2596 | * @param USBx Selected device |
2597 | UNUSED(epnum); |
2597 | * @retval HAL status |
2598 | /* NOTE : - This function is not required by USB Device FS peripheral, it is used |
2598 | */ |
2599 | only by USB OTG FS peripheral. |
2599 | HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx) |
2600 | - This function is added to ensure compatibility across platforms. |
2600 | { |
2601 | */ |
2601 | /* disable all interrupts and force USB reset */ |
2602 | return (0); |
2602 | USBx->CNTR = (uint16_t)USB_CNTR_FRES; |
2603 | } |
2603 | |
2604 | 2604 | /* clear interrupt status register */ |
|
2605 | /** |
2605 | USBx->ISTR = 0U; |
2606 | * @brief Returns Device IN EP Interrupt register |
2606 | |
2607 | * @param USBx Selected device |
2607 | /* switch-off device */ |
2608 | * @param epnum endpoint number |
2608 | USBx->CNTR = (uint16_t)(USB_CNTR_FRES | USB_CNTR_PDWN); |
2609 | * This parameter can be a value from 0 to 15 |
2609 | |
2610 | * @retval Device IN EP Interrupt register |
2610 | return HAL_OK; |
2611 | */ |
2611 | } |
2612 | uint32_t USB_ReadDevInEPInterrupt(USB_TypeDef *USBx, uint8_t epnum) |
2612 | |
2613 | { |
2613 | /** |
2614 | /* Prevent unused argument(s) compilation warning */ |
2614 | * @brief USB_SetDevAddress Stop the usb device mode |
2615 | UNUSED(USBx); |
2615 | * @param USBx Selected device |
2616 | UNUSED(epnum); |
2616 | * @param address new device address to be assigned |
2617 | /* NOTE : - This function is not required by USB Device FS peripheral, it is used |
2617 | * This parameter can be a value from 0 to 255 |
2618 | only by USB OTG FS peripheral. |
2618 | * @retval HAL status |
2619 | - This function is added to ensure compatibility across platforms. |
2619 | */ |
2620 | */ |
2620 | HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address) |
2621 | return (0); |
2621 | { |
2622 | } |
2622 | if (address == 0U) |
2623 | 2623 | { |
|
2624 | /** |
2624 | /* set device address and enable function */ |
2625 | * @brief USB_ClearInterrupts: clear a USB interrupt |
2625 | USBx->DADDR = (uint16_t)USB_DADDR_EF; |
2626 | * @param USBx Selected device |
2626 | } |
2627 | * @param interrupt flag |
2627 | |
2628 | * @retval None |
2628 | return HAL_OK; |
2629 | */ |
2629 | } |
2630 | void USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt) |
2630 | |
2631 | { |
2631 | /** |
2632 | /* Prevent unused argument(s) compilation warning */ |
2632 | * @brief USB_DevConnect Connect the USB device by enabling the pull-up/pull-down |
2633 | UNUSED(USBx); |
2633 | * @param USBx Selected device |
2634 | UNUSED(interrupt); |
2634 | * @retval HAL status |
2635 | /* NOTE : - This function is not required by USB Device FS peripheral, it is used |
2635 | */ |
2636 | only by USB OTG FS peripheral. |
2636 | HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx) |
2637 | - This function is added to ensure compatibility across platforms. |
2637 | { |
2638 | */ |
2638 | /* Prevent unused argument(s) compilation warning */ |
2639 | } |
2639 | UNUSED(USBx); |
2640 | 2640 | ||
2641 | /** |
2641 | /* NOTE : - This function is not required by USB Device FS peripheral, it is used |
2642 | * @brief Prepare the EP0 to start the first control setup |
2642 | only by USB OTG FS peripheral. |
2643 | * @param USBx Selected device |
2643 | - This function is added to ensure compatibility across platforms. |
2644 | * @param psetup pointer to setup packet |
2644 | */ |
2645 | * @retval HAL status |
2645 | |
2646 | */ |
2646 | return HAL_OK; |
2647 | HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup) |
2647 | } |
2648 | { |
2648 | |
2649 | /* Prevent unused argument(s) compilation warning */ |
2649 | /** |
2650 | UNUSED(USBx); |
2650 | * @brief USB_DevDisconnect Disconnect the USB device by disabling the pull-up/pull-down |
2651 | UNUSED(psetup); |
2651 | * @param USBx Selected device |
2652 | /* NOTE : - This function is not required by USB Device FS peripheral, it is used |
2652 | * @retval HAL status |
2653 | only by USB OTG FS peripheral. |
2653 | */ |
2654 | - This function is added to ensure compatibility across platforms. |
2654 | HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx) |
2655 | */ |
2655 | { |
2656 | return HAL_OK; |
2656 | /* Prevent unused argument(s) compilation warning */ |
2657 | } |
2657 | UNUSED(USBx); |
2658 | 2658 | ||
2659 | /** |
2659 | /* NOTE : - This function is not required by USB Device FS peripheral, it is used |
2660 | * @brief USB_ActivateRemoteWakeup : active remote wakeup signalling |
2660 | only by USB OTG FS peripheral. |
2661 | * @param USBx Selected device |
2661 | - This function is added to ensure compatibility across platforms. |
2662 | * @retval HAL status |
2662 | */ |
2663 | */ |
2663 | |
2664 | HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx) |
2664 | return HAL_OK; |
2665 | { |
2665 | } |
2666 | USBx->CNTR |= (uint16_t)USB_CNTR_RESUME; |
2666 | |
2667 | 2667 | /** |
|
2668 | return HAL_OK; |
2668 | * @brief USB_ReadInterrupts return the global USB interrupt status |
2669 | } |
2669 | * @param USBx Selected device |
2670 | 2670 | * @retval USB Global Interrupt status |
|
2671 | /** |
2671 | */ |
2672 | * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling |
2672 | uint32_t USB_ReadInterrupts(USB_TypeDef const *USBx) |
2673 | * @param USBx Selected device |
2673 | { |
2674 | * @retval HAL status |
2674 | uint32_t tmpreg; |
2675 | */ |
2675 | |
2676 | HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx) |
2676 | tmpreg = USBx->ISTR; |
2677 | { |
2677 | return tmpreg; |
2678 | USBx->CNTR &= (uint16_t)(~USB_CNTR_RESUME); |
2678 | } |
2679 | 2679 | ||
2680 | return HAL_OK; |
2680 | /** |
2681 | } |
2681 | * @brief USB_ReadDevAllOutEpInterrupt return the USB device OUT endpoints interrupt status |
2682 | 2682 | * @param USBx Selected device |
|
2683 | /** |
2683 | * @retval HAL status |
2684 | * @brief Copy a buffer from user memory area to packet memory area (PMA) |
2684 | */ |
2685 | * @param USBx USB peripheral instance register address. |
2685 | uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx) |
2686 | * @param pbUsrBuf pointer to user memory area. |
2686 | { |
2687 | * @param wPMABufAddr address into PMA. |
2687 | /* Prevent unused argument(s) compilation warning */ |
2688 | * @param wNBytes no. of bytes to be copied. |
2688 | UNUSED(USBx); |
2689 | * @retval None |
2689 | /* NOTE : - This function is not required by USB Device FS peripheral, it is used |
2690 | */ |
2690 | only by USB OTG FS peripheral. |
2691 | void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) |
2691 | - This function is added to ensure compatibility across platforms. |
2692 | { |
2692 | */ |
2693 | uint32_t n = ((uint32_t)wNBytes + 1U) >> 1; |
2693 | return (0); |
2694 | uint32_t BaseAddr = (uint32_t)USBx; |
2694 | } |
2695 | uint32_t i, temp1, temp2; |
2695 | |
2696 | __IO uint16_t *pdwVal; |
2696 | /** |
2697 | uint8_t *pBuf = pbUsrBuf; |
2697 | * @brief USB_ReadDevAllInEpInterrupt return the USB device IN endpoints interrupt status |
2698 | 2698 | * @param USBx Selected device |
|
2699 | pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS)); |
2699 | * @retval HAL status |
2700 | 2700 | */ |
|
2701 | for (i = n; i != 0U; i--) |
2701 | uint32_t USB_ReadDevAllInEpInterrupt(USB_TypeDef *USBx) |
2702 | { |
2702 | { |
2703 | temp1 = *pBuf; |
2703 | /* Prevent unused argument(s) compilation warning */ |
2704 | pBuf++; |
2704 | UNUSED(USBx); |
2705 | temp2 = temp1 | ((uint16_t)((uint16_t) *pBuf << 8)); |
2705 | /* NOTE : - This function is not required by USB Device FS peripheral, it is used |
2706 | *pdwVal = (uint16_t)temp2; |
2706 | only by USB OTG FS peripheral. |
2707 | pdwVal++; |
2707 | - This function is added to ensure compatibility across platforms. |
2708 | 2708 | */ |
|
2709 | #if PMA_ACCESS > 1U |
2709 | return (0); |
2710 | pdwVal++; |
2710 | } |
2711 | #endif |
2711 | |
2712 | 2712 | /** |
|
2713 | pBuf++; |
2713 | * @brief Returns Device OUT EP Interrupt register |
2714 | } |
2714 | * @param USBx Selected device |
2715 | } |
2715 | * @param epnum endpoint number |
2716 | 2716 | * This parameter can be a value from 0 to 15 |
|
2717 | /** |
2717 | * @retval Device OUT EP Interrupt register |
2718 | * @brief Copy data from packet memory area (PMA) to user memory buffer |
2718 | */ |
2719 | * @param USBx USB peripheral instance register address. |
2719 | uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum) |
2720 | * @param pbUsrBuf pointer to user memory area. |
2720 | { |
2721 | * @param wPMABufAddr address into PMA. |
2721 | /* Prevent unused argument(s) compilation warning */ |
2722 | * @param wNBytes no. of bytes to be copied. |
2722 | UNUSED(USBx); |
2723 | * @retval None |
2723 | UNUSED(epnum); |
2724 | */ |
2724 | /* NOTE : - This function is not required by USB Device FS peripheral, it is used |
2725 | void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) |
2725 | only by USB OTG FS peripheral. |
2726 | { |
2726 | - This function is added to ensure compatibility across platforms. |
2727 | uint32_t n = (uint32_t)wNBytes >> 1; |
2727 | */ |
2728 | uint32_t BaseAddr = (uint32_t)USBx; |
2728 | return (0); |
2729 | uint32_t i, temp; |
2729 | } |
2730 | __IO uint16_t *pdwVal; |
2730 | |
2731 | uint8_t *pBuf = pbUsrBuf; |
2731 | /** |
2732 | 2732 | * @brief Returns Device IN EP Interrupt register |
|
2733 | pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS)); |
2733 | * @param USBx Selected device |
2734 | 2734 | * @param epnum endpoint number |
|
2735 | for (i = n; i != 0U; i--) |
2735 | * This parameter can be a value from 0 to 15 |
2736 | { |
2736 | * @retval Device IN EP Interrupt register |
2737 | temp = *(__IO uint16_t *)pdwVal; |
2737 | */ |
2738 | pdwVal++; |
2738 | uint32_t USB_ReadDevInEPInterrupt(USB_TypeDef *USBx, uint8_t epnum) |
2739 | *pBuf = (uint8_t)((temp >> 0) & 0xFFU); |
2739 | { |
2740 | pBuf++; |
2740 | /* Prevent unused argument(s) compilation warning */ |
2741 | *pBuf = (uint8_t)((temp >> 8) & 0xFFU); |
2741 | UNUSED(USBx); |
2742 | pBuf++; |
2742 | UNUSED(epnum); |
2743 | 2743 | /* NOTE : - This function is not required by USB Device FS peripheral, it is used |
|
2744 | #if PMA_ACCESS > 1U |
2744 | only by USB OTG FS peripheral. |
2745 | pdwVal++; |
2745 | - This function is added to ensure compatibility across platforms. |
2746 | #endif |
2746 | */ |
2747 | } |
2747 | return (0); |
2748 | 2748 | } |
|
2749 | if ((wNBytes % 2U) != 0U) |
2749 | |
2750 | { |
2750 | /** |
2751 | temp = *pdwVal; |
2751 | * @brief USB_ClearInterrupts: clear a USB interrupt |
2752 | *pBuf = (uint8_t)((temp >> 0) & 0xFFU); |
2752 | * @param USBx Selected device |
2753 | } |
2753 | * @param interrupt flag |
2754 | } |
2754 | * @retval None |
2755 | #endif /* defined (USB) */ |
2755 | */ |
2756 | 2756 | void USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt) |
|
2757 | /** |
2757 | { |
2758 | * @} |
2758 | /* Prevent unused argument(s) compilation warning */ |
2759 | */ |
2759 | UNUSED(USBx); |
2760 | 2760 | UNUSED(interrupt); |
|
2761 | /** |
2761 | /* NOTE : - This function is not required by USB Device FS peripheral, it is used |
2762 | * @} |
2762 | only by USB OTG FS peripheral. |
2763 | */ |
2763 | - This function is added to ensure compatibility across platforms. |
2764 | #endif /* defined (USB) || defined (USB_OTG_FS) */ |
2764 | */ |
2765 | #endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */ |
2765 | } |
2766 | 2766 | ||
2767 | /** |
2767 | /** |
2768 | * @} |
2768 | * @brief Prepare the EP0 to start the first control setup |
2769 | */ |
2769 | * @param USBx Selected device |
2770 | 2770 | * @param psetup pointer to setup packet |
|
2771 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
2771 | * @retval HAL status |
- | 2772 | */ |
|
- | 2773 | HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup) |
|
- | 2774 | { |
|
- | 2775 | /* Prevent unused argument(s) compilation warning */ |
|
- | 2776 | UNUSED(USBx); |
|
- | 2777 | UNUSED(psetup); |
|
- | 2778 | /* NOTE : - This function is not required by USB Device FS peripheral, it is used |
|
- | 2779 | only by USB OTG FS peripheral. |
|
- | 2780 | - This function is added to ensure compatibility across platforms. |
|
- | 2781 | */ |
|
- | 2782 | return HAL_OK; |
|
- | 2783 | } |
|
- | 2784 | ||
- | 2785 | /** |
|
- | 2786 | * @brief USB_ActivateRemoteWakeup : active remote wakeup signalling |
|
- | 2787 | * @param USBx Selected device |
|
- | 2788 | * @retval HAL status |
|
- | 2789 | */ |
|
- | 2790 | HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx) |
|
- | 2791 | { |
|
- | 2792 | USBx->CNTR |= (uint16_t)USB_CNTR_RESUME; |
|
- | 2793 | ||
- | 2794 | return HAL_OK; |
|
- | 2795 | } |
|
- | 2796 | ||
- | 2797 | /** |
|
- | 2798 | * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling |
|
- | 2799 | * @param USBx Selected device |
|
- | 2800 | * @retval HAL status |
|
- | 2801 | */ |
|
- | 2802 | HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx) |
|
- | 2803 | { |
|
- | 2804 | USBx->CNTR &= (uint16_t)(~USB_CNTR_RESUME); |
|
- | 2805 | ||
- | 2806 | return HAL_OK; |
|
- | 2807 | } |
|
- | 2808 | ||
- | 2809 | /** |
|
- | 2810 | * @brief Copy a buffer from user memory area to packet memory area (PMA) |
|
- | 2811 | * @param USBx USB peripheral instance register address. |
|
- | 2812 | * @param pbUsrBuf pointer to user memory area. |
|
- | 2813 | * @param wPMABufAddr address into PMA. |
|
- | 2814 | * @param wNBytes no. of bytes to be copied. |
|
- | 2815 | * @retval None |
|
- | 2816 | */ |
|
- | 2817 | void USB_WritePMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) |
|
- | 2818 | { |
|
- | 2819 | uint32_t n = ((uint32_t)wNBytes + 1U) >> 1; |
|
- | 2820 | uint32_t BaseAddr = (uint32_t)USBx; |
|
- | 2821 | uint32_t count; |
|
- | 2822 | uint16_t WrVal; |
|
- | 2823 | __IO uint16_t *pdwVal; |
|
- | 2824 | uint8_t *pBuf = pbUsrBuf; |
|
- | 2825 | ||
- | 2826 | pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS)); |
|
- | 2827 | ||
- | 2828 | for (count = n; count != 0U; count--) |
|
- | 2829 | { |
|
- | 2830 | WrVal = pBuf[0]; |
|
- | 2831 | WrVal |= (uint16_t)pBuf[1] << 8; |
|
- | 2832 | *pdwVal = (WrVal & 0xFFFFU); |
|
- | 2833 | pdwVal++; |
|
- | 2834 | ||
- | 2835 | #if PMA_ACCESS > 1U |
|
- | 2836 | pdwVal++; |
|
- | 2837 | #endif /* PMA_ACCESS */ |
|
- | 2838 | ||
- | 2839 | pBuf++; |
|
- | 2840 | pBuf++; |
|
- | 2841 | } |
|
- | 2842 | } |
|
- | 2843 | ||
- | 2844 | /** |
|
- | 2845 | * @brief Copy data from packet memory area (PMA) to user memory buffer |
|
- | 2846 | * @param USBx USB peripheral instance register address. |
|
- | 2847 | * @param pbUsrBuf pointer to user memory area. |
|
- | 2848 | * @param wPMABufAddr address into PMA. |
|
- | 2849 | * @param wNBytes no. of bytes to be copied. |
|
- | 2850 | * @retval None |
|
- | 2851 | */ |
|
- | 2852 | void USB_ReadPMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) |
|
- | 2853 | { |
|
- | 2854 | uint32_t n = (uint32_t)wNBytes >> 1; |
|
- | 2855 | uint32_t BaseAddr = (uint32_t)USBx; |
|
- | 2856 | uint32_t count; |
|
- | 2857 | uint32_t RdVal; |
|
- | 2858 | __IO uint16_t *pdwVal; |
|
- | 2859 | uint8_t *pBuf = pbUsrBuf; |
|
- | 2860 | ||
- | 2861 | pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS)); |
|
- | 2862 | ||
- | 2863 | for (count = n; count != 0U; count--) |
|
- | 2864 | { |
|
- | 2865 | RdVal = *(__IO uint16_t *)pdwVal; |
|
- | 2866 | pdwVal++; |
|
- | 2867 | *pBuf = (uint8_t)((RdVal >> 0) & 0xFFU); |
|
- | 2868 | pBuf++; |
|
- | 2869 | *pBuf = (uint8_t)((RdVal >> 8) & 0xFFU); |
|
- | 2870 | pBuf++; |
|
- | 2871 | ||
- | 2872 | #if PMA_ACCESS > 1U |
|
- | 2873 | pdwVal++; |
|
- | 2874 | #endif /* PMA_ACCESS */ |
|
- | 2875 | } |
|
- | 2876 | ||
- | 2877 | if ((wNBytes % 2U) != 0U) |
|
- | 2878 | { |
|
- | 2879 | RdVal = *pdwVal; |
|
- | 2880 | *pBuf = (uint8_t)((RdVal >> 0) & 0xFFU); |
|
- | 2881 | } |
|
- | 2882 | } |
|
- | 2883 | ||
- | 2884 | #endif /* defined (USB) */ |
|
- | 2885 | /** |
|
- | 2886 | * @} |
|
- | 2887 | */ |
|
- | 2888 | ||
- | 2889 | /** |
|
- | 2890 | * @} |
|
- | 2891 | */ |
|
- | 2892 | #endif /* defined (USB) || defined (USB_OTG_FS) */ |
|
- | 2893 | #endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */ |
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- | 2894 | ||
- | 2895 | /** |
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- | 2896 | * @} |
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- | 2897 | */ |