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1 | /** |
1 | /** |
2 | ****************************************************************************** |
2 | ****************************************************************************** |
3 | * @file stm32f1xx_ll_sdmmc.c |
3 | * @file stm32f1xx_ll_sdmmc.c |
4 | * @author MCD Application Team |
4 | * @author MCD Application Team |
5 | * @brief SDMMC Low Layer HAL module driver. |
5 | * @brief SDMMC Low Layer HAL module driver. |
6 | * |
6 | * |
7 | * This file provides firmware functions to manage the following |
7 | * This file provides firmware functions to manage the following |
8 | * functionalities of the SDMMC peripheral: |
8 | * functionalities of the SDMMC peripheral: |
9 | * + Initialization/de-initialization functions |
9 | * + Initialization/de-initialization functions |
10 | * + I/O operation functions |
10 | * + I/O operation functions |
11 | * + Peripheral Control functions |
11 | * + Peripheral Control functions |
12 | * + Peripheral State functions |
12 | * + Peripheral State functions |
13 | * |
13 | * |
14 | @verbatim |
14 | ****************************************************************************** |
15 | ============================================================================== |
15 | * @attention |
16 | ##### SDMMC peripheral features ##### |
16 | * |
17 | ============================================================================== |
17 | * Copyright (c) 2016 STMicroelectronics. |
18 | [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the AHB |
18 | * All rights reserved. |
19 | peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA |
19 | * |
20 | devices. |
20 | * This software is licensed under terms that can be found in the LICENSE file |
21 | |
21 | * in the root directory of this software component. |
22 | [..] The SDMMC features include the following: |
22 | * If no LICENSE file comes with this software, it is provided AS-IS. |
23 | (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support |
23 | * |
24 | for three different databus modes: 1-bit (default), 4-bit and 8-bit |
24 | ****************************************************************************** |
25 | (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility) |
25 | @verbatim |
26 | (+) Full compliance with SD Memory Card Specifications Version 2.0 |
26 | ============================================================================== |
27 | (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two |
27 | ##### SDMMC peripheral features ##### |
28 | different data bus modes: 1-bit (default) and 4-bit |
28 | ============================================================================== |
29 | (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol |
29 | [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the AHB |
30 | Rev1.1) |
30 | peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA |
31 | (+) Data transfer up to 48 MHz for the 8 bit mode |
31 | devices. |
32 | (+) Data and command output enable signals to control external bidirectional drivers |
32 | |
33 | |
33 | [..] The SDMMC features include the following: |
34 | ##### How to use this driver ##### |
34 | (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support |
35 | ============================================================================== |
35 | for three different databus modes: 1-bit (default), 4-bit and 8-bit |
36 | [..] |
36 | (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility) |
37 | This driver is a considered as a driver of service for external devices drivers |
37 | (+) Full compliance with SD Memory Card Specifications Version 2.0 |
38 | that interfaces with the SDMMC peripheral. |
38 | (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two |
39 | According to the device used (SD card/ MMC card / SDMMC card ...), a set of APIs |
39 | different data bus modes: 1-bit (default) and 4-bit |
40 | is used in the device's driver to perform SDMMC operations and functionalities. |
40 | (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol |
41 | |
41 | Rev1.1) |
42 | This driver is almost transparent for the final user, it is only used to implement other |
42 | (+) Data transfer up to 48 MHz for the 8 bit mode |
43 | functionalities of the external device. |
43 | (+) Data and command output enable signals to control external bidirectional drivers |
44 | |
44 | |
45 | [..] |
45 | ##### How to use this driver ##### |
46 | (+) The SDMMC clock (SDMMCCLK = 48 MHz) is coming from a specific output (MSI, PLLUSB1CLK, |
46 | ============================================================================== |
47 | PLLUSB2CLK). Before start working with SDMMC peripheral make sure that the |
47 | [..] |
48 | PLL is well configured. |
48 | This driver is a considered as a driver of service for external devices drivers |
49 | The SDMMC peripheral uses two clock signals: |
49 | that interfaces with the SDMMC peripheral. |
50 | (++) SDMMC adapter clock (SDMMCCLK = 48 MHz) |
50 | According to the device used (SD card/ MMC card / SDMMC card ...), a set of APIs |
51 | (++) APB2 bus clock (PCLK2) |
51 | is used in the device's driver to perform SDMMC operations and functionalities. |
52 | |
52 | |
53 | -@@- PCLK2 and SDMMC_CK clock frequencies must respect the following condition: |
53 | This driver is almost transparent for the final user, it is only used to implement other |
54 | Frequency(PCLK2) >= (3 / 8 x Frequency(SDMMC_CK)) |
54 | functionalities of the external device. |
55 | |
55 | |
56 | (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC |
56 | [..] |
57 | peripheral. |
57 | (+) The SDMMC clock (SDMMCCLK = 48 MHz) is coming from a specific output (MSI, PLLUSB1CLK, |
58 | 58 | PLLUSB2CLK). Before start working with SDMMC peripheral make sure that the |
|
59 | (+) Enable the Power ON State using the SDIO_PowerState_ON() |
59 | PLL is well configured. |
60 | function and disable it using the function SDIO_PowerState_OFF(). |
60 | The SDMMC peripheral uses two clock signals: |
61 | |
61 | (++) SDMMC adapter clock (SDMMCCLK = 48 MHz) |
62 | (+) Enable/Disable the clock using the __SDIO_ENABLE()/__SDIO_DISABLE() macros. |
62 | (++) APB2 bus clock (PCLK2) |
63 | |
63 | |
64 | (+) Enable/Disable the peripheral interrupts using the macros __SDIO_ENABLE_IT() |
64 | -@@- PCLK2 and SDMMC_CK clock frequencies must respect the following condition: |
65 | and __SDIO_DISABLE_IT() if you need to use interrupt mode. |
65 | Frequency(PCLK2) >= (3 / 8 x Frequency(SDMMC_CK)) |
66 | |
66 | |
67 | (+) When using the DMA mode |
67 | (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC |
68 | (++) Configure the DMA in the MSP layer of the external device |
68 | peripheral. |
69 | (++) Active the needed channel Request |
69 | |
70 | (++) Enable the DMA using __SDIO_DMA_ENABLE() macro or Disable it using the macro |
70 | (+) Enable the Power ON State using the SDIO_PowerState_ON() |
71 | __SDIO_DMA_DISABLE(). |
71 | function and disable it using the function SDIO_PowerState_OFF(). |
72 | |
72 | |
73 | (+) To control the CPSM (Command Path State Machine) and send |
73 | (+) Enable/Disable the clock using the __SDIO_ENABLE()/__SDIO_DISABLE() macros. |
74 | commands to the card use the SDIO_SendCommand(), |
74 | |
75 | SDIO_GetCommandResponse() and SDIO_GetResponse() functions. First, user has |
75 | (+) Enable/Disable the peripheral interrupts using the macros __SDIO_ENABLE_IT() |
76 | to fill the command structure (pointer to SDIO_CmdInitTypeDef) according |
76 | and __SDIO_DISABLE_IT() if you need to use interrupt mode. |
77 | to the selected command to be sent. |
77 | |
78 | The parameters that should be filled are: |
78 | (+) When using the DMA mode |
79 | (++) Command Argument |
79 | (++) Configure the DMA in the MSP layer of the external device |
80 | (++) Command Index |
80 | (++) Active the needed channel Request |
81 | (++) Command Response type |
81 | (++) Enable the DMA using __SDIO_DMA_ENABLE() macro or Disable it using the macro |
82 | (++) Command Wait |
82 | __SDIO_DMA_DISABLE(). |
83 | (++) CPSM Status (Enable or Disable). |
83 | |
84 | |
84 | (+) To control the CPSM (Command Path State Machine) and send |
85 | -@@- To check if the command is well received, read the SDIO_CMDRESP |
85 | commands to the card use the SDIO_SendCommand(), |
86 | register using the SDIO_GetCommandResponse(). |
86 | SDIO_GetCommandResponse() and SDIO_GetResponse() functions. First, user has |
87 | The SDMMC responses registers (SDIO_RESP1 to SDIO_RESP2), use the |
87 | to fill the command structure (pointer to SDIO_CmdInitTypeDef) according |
88 | SDIO_GetResponse() function. |
88 | to the selected command to be sent. |
89 | |
89 | The parameters that should be filled are: |
90 | (+) To control the DPSM (Data Path State Machine) and send/receive |
90 | (++) Command Argument |
91 | data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(), |
91 | (++) Command Index |
92 | SDIO_ReadFIFO(), SDIO_WriteFIFO() and SDIO_GetFIFOCount() functions. |
92 | (++) Command Response type |
93 | |
93 | (++) Command Wait |
94 | *** Read Operations *** |
94 | (++) CPSM Status (Enable or Disable). |
95 | ======================= |
95 | |
96 | [..] |
96 | -@@- To check if the command is well received, read the SDIO_CMDRESP |
97 | (#) First, user has to fill the data structure (pointer to |
97 | register using the SDIO_GetCommandResponse(). |
98 | SDIO_DataInitTypeDef) according to the selected data type to be received. |
98 | The SDMMC responses registers (SDIO_RESP1 to SDIO_RESP2), use the |
99 | The parameters that should be filled are: |
99 | SDIO_GetResponse() function. |
100 | (++) Data TimeOut |
100 | |
101 | (++) Data Length |
101 | (+) To control the DPSM (Data Path State Machine) and send/receive |
102 | (++) Data Block size |
102 | data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(), |
103 | (++) Data Transfer direction: should be from card (To SDMMC) |
103 | SDIO_ReadFIFO(), SDIO_WriteFIFO() and SDIO_GetFIFOCount() functions. |
104 | (++) Data Transfer mode |
104 | |
105 | (++) DPSM Status (Enable or Disable) |
105 | *** Read Operations *** |
106 | |
106 | ======================= |
107 | (#) Configure the SDMMC resources to receive the data from the card |
107 | [..] |
108 | according to selected transfer mode (Refer to Step 8, 9 and 10). |
108 | (#) First, user has to fill the data structure (pointer to |
109 | |
109 | SDIO_DataInitTypeDef) according to the selected data type to be received. |
110 | (#) Send the selected Read command (refer to step 11). |
110 | The parameters that should be filled are: |
111 | |
111 | (++) Data TimeOut |
112 | (#) Use the SDIO flags/interrupts to check the transfer status. |
112 | (++) Data Length |
113 | |
113 | (++) Data Block size |
114 | *** Write Operations *** |
114 | (++) Data Transfer direction: should be from card (To SDMMC) |
115 | ======================== |
115 | (++) Data Transfer mode |
116 | [..] |
116 | (++) DPSM Status (Enable or Disable) |
117 | (#) First, user has to fill the data structure (pointer to |
117 | |
118 | SDIO_DataInitTypeDef) according to the selected data type to be received. |
118 | (#) Configure the SDMMC resources to receive the data from the card |
119 | The parameters that should be filled are: |
119 | according to selected transfer mode (Refer to Step 8, 9 and 10). |
120 | (++) Data TimeOut |
120 | |
121 | (++) Data Length |
121 | (#) Send the selected Read command (refer to step 11). |
122 | (++) Data Block size |
122 | |
123 | (++) Data Transfer direction: should be to card (To CARD) |
123 | (#) Use the SDIO flags/interrupts to check the transfer status. |
124 | (++) Data Transfer mode |
124 | |
125 | (++) DPSM Status (Enable or Disable) |
125 | *** Write Operations *** |
126 | |
126 | ======================== |
127 | (#) Configure the SDMMC resources to send the data to the card according to |
127 | [..] |
128 | selected transfer mode. |
128 | (#) First, user has to fill the data structure (pointer to |
129 | |
129 | SDIO_DataInitTypeDef) according to the selected data type to be received. |
130 | (#) Send the selected Write command. |
130 | The parameters that should be filled are: |
131 | |
131 | (++) Data TimeOut |
132 | (#) Use the SDIO flags/interrupts to check the transfer status. |
132 | (++) Data Length |
133 | |
133 | (++) Data Block size |
134 | *** Command management operations *** |
134 | (++) Data Transfer direction: should be to card (To CARD) |
135 | ===================================== |
135 | (++) Data Transfer mode |
136 | [..] |
136 | (++) DPSM Status (Enable or Disable) |
137 | (#) The commands used for Read/Write/Erase operations are managed in |
137 | |
138 | separate functions. |
138 | (#) Configure the SDMMC resources to send the data to the card according to |
139 | Each function allows to send the needed command with the related argument, |
139 | selected transfer mode. |
140 | then check the response. |
140 | |
141 | By the same approach, you could implement a command and check the response. |
141 | (#) Send the selected Write command. |
142 | |
142 | |
143 | @endverbatim |
143 | (#) Use the SDIO flags/interrupts to check the transfer status. |
144 | ****************************************************************************** |
144 | |
145 | * @attention |
145 | *** Command management operations *** |
146 | * |
146 | ===================================== |
147 | * <h2><center>© Copyright (c) 2018 STMicroelectronics. |
147 | [..] |
148 | * All rights reserved.</center></h2> |
148 | (#) The commands used for Read/Write/Erase operations are managed in |
149 | * |
149 | separate functions. |
150 | * This software component is licensed by ST under BSD 3-Clause license, |
150 | Each function allows to send the needed command with the related argument, |
151 | * the "License"; You may not use this file except in compliance with the |
151 | then check the response. |
152 | * License. You may obtain a copy of the License at: |
152 | By the same approach, you could implement a command and check the response. |
153 | * opensource.org/licenses/BSD-3-Clause |
153 | |
154 | * |
154 | @endverbatim |
155 | ****************************************************************************** |
155 | ****************************************************************************** |
156 | */ |
156 | */ |
157 | 157 | ||
158 | /* Includes ------------------------------------------------------------------*/ |
158 | /* Includes ------------------------------------------------------------------*/ |
159 | #include "stm32f1xx_hal.h" |
159 | #include "stm32f1xx_hal.h" |
160 | 160 | ||
161 | #if defined(SDIO) |
161 | #if defined(SDIO) |
162 | 162 | ||
163 | /** @addtogroup STM32F1xx_HAL_Driver |
163 | /** @addtogroup STM32F1xx_HAL_Driver |
164 | * @{ |
164 | * @{ |
165 | */ |
165 | */ |
166 | 166 | ||
167 | /** @defgroup SDMMC_LL SDMMC Low Layer |
167 | /** @defgroup SDMMC_LL SDMMC Low Layer |
168 | * @brief Low layer module for SD |
168 | * @brief Low layer module for SD |
169 | * @{ |
169 | * @{ |
170 | */ |
170 | */ |
171 | 171 | ||
172 | #if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED) |
172 | #if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED) |
173 | 173 | ||
174 | /* Private typedef -----------------------------------------------------------*/ |
174 | /* Private typedef -----------------------------------------------------------*/ |
175 | /* Private define ------------------------------------------------------------*/ |
175 | /* Private define ------------------------------------------------------------*/ |
176 | /* Private macro -------------------------------------------------------------*/ |
176 | /* Private macro -------------------------------------------------------------*/ |
177 | /* Private variables ---------------------------------------------------------*/ |
177 | /* Private variables ---------------------------------------------------------*/ |
178 | /* Private function prototypes -----------------------------------------------*/ |
178 | /* Private function prototypes -----------------------------------------------*/ |
179 | static uint32_t SDMMC_GetCmdError(SDIO_TypeDef *SDIOx); |
179 | static uint32_t SDMMC_GetCmdError(SDIO_TypeDef *SDIOx); |
180 | static uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout); |
180 | |
181 | static uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx); |
181 | /* Exported functions --------------------------------------------------------*/ |
182 | static uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx); |
182 | |
183 | static uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx); |
183 | /** @defgroup SDMMC_LL_Exported_Functions SDMMC Low Layer Exported Functions |
184 | static uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA); |
184 | * @{ |
185 | 185 | */ |
|
186 | /* Exported functions --------------------------------------------------------*/ |
186 | |
187 | 187 | /** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions |
|
188 | /** @defgroup SDMMC_LL_Exported_Functions SDMMC Low Layer Exported Functions |
188 | * @brief Initialization and Configuration functions |
189 | * @{ |
189 | * |
190 | */ |
190 | @verbatim |
191 | 191 | =============================================================================== |
|
192 | /** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions |
192 | ##### Initialization/de-initialization functions ##### |
193 | * @brief Initialization and Configuration functions |
193 | =============================================================================== |
194 | * |
194 | [..] This section provides functions allowing to: |
195 | @verbatim |
195 | |
196 | =============================================================================== |
196 | @endverbatim |
197 | ##### Initialization/de-initialization functions ##### |
197 | * @{ |
198 | =============================================================================== |
198 | */ |
199 | [..] This section provides functions allowing to: |
199 | |
200 | |
200 | /** |
201 | @endverbatim |
201 | * @brief Initializes the SDMMC according to the specified |
202 | * @{ |
202 | * parameters in the SDMMC_InitTypeDef and create the associated handle. |
203 | */ |
203 | * @param SDIOx: Pointer to SDMMC register base |
204 | 204 | * @param Init: SDMMC initialization structure |
|
205 | /** |
205 | * @retval HAL status |
206 | * @brief Initializes the SDMMC according to the specified |
206 | */ |
207 | * parameters in the SDMMC_InitTypeDef and create the associated handle. |
207 | HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init) |
208 | * @param SDIOx: Pointer to SDMMC register base |
208 | { |
209 | * @param Init: SDMMC initialization structure |
209 | uint32_t tmpreg = 0; |
210 | * @retval HAL status |
210 | |
211 | */ |
211 | /* Check the parameters */ |
212 | HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init) |
212 | assert_param(IS_SDIO_ALL_INSTANCE(SDIOx)); |
213 | { |
213 | assert_param(IS_SDIO_CLOCK_EDGE(Init.ClockEdge)); |
214 | uint32_t tmpreg = 0; |
214 | assert_param(IS_SDIO_CLOCK_BYPASS(Init.ClockBypass)); |
215 | 215 | assert_param(IS_SDIO_CLOCK_POWER_SAVE(Init.ClockPowerSave)); |
|
216 | /* Check the parameters */ |
216 | assert_param(IS_SDIO_BUS_WIDE(Init.BusWide)); |
217 | assert_param(IS_SDIO_ALL_INSTANCE(SDIOx)); |
217 | assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl)); |
218 | assert_param(IS_SDIO_CLOCK_EDGE(Init.ClockEdge)); |
218 | assert_param(IS_SDIO_CLKDIV(Init.ClockDiv)); |
219 | assert_param(IS_SDIO_CLOCK_BYPASS(Init.ClockBypass)); |
219 | |
220 | assert_param(IS_SDIO_CLOCK_POWER_SAVE(Init.ClockPowerSave)); |
220 | /* Set SDMMC configuration parameters */ |
221 | assert_param(IS_SDIO_BUS_WIDE(Init.BusWide)); |
221 | tmpreg |= (Init.ClockEdge |\ |
222 | assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl)); |
222 | Init.ClockBypass |\ |
223 | assert_param(IS_SDIO_CLKDIV(Init.ClockDiv)); |
223 | Init.ClockPowerSave |\ |
224 | 224 | Init.BusWide |\ |
|
225 | /* Set SDMMC configuration parameters */ |
225 | Init.HardwareFlowControl |\ |
226 | tmpreg |= (Init.ClockEdge |\ |
226 | Init.ClockDiv |
227 | Init.ClockBypass |\ |
227 | ); |
228 | Init.ClockPowerSave |\ |
228 | |
229 | Init.BusWide |\ |
229 | /* Write to SDMMC CLKCR */ |
230 | Init.HardwareFlowControl |\ |
230 | MODIFY_REG(SDIOx->CLKCR, CLKCR_CLEAR_MASK, tmpreg); |
231 | Init.ClockDiv |
231 | |
232 | ); |
232 | return HAL_OK; |
233 | 233 | } |
|
234 | /* Write to SDMMC CLKCR */ |
234 | |
235 | MODIFY_REG(SDIOx->CLKCR, CLKCR_CLEAR_MASK, tmpreg); |
235 | |
236 | 236 | /** |
|
237 | return HAL_OK; |
237 | * @} |
238 | } |
238 | */ |
239 | 239 | ||
240 | 240 | /** @defgroup HAL_SDMMC_LL_Group2 IO operation functions |
|
241 | /** |
241 | * @brief Data transfers functions |
242 | * @} |
242 | * |
243 | */ |
243 | @verbatim |
244 | 244 | =============================================================================== |
|
245 | /** @defgroup HAL_SDMMC_LL_Group2 IO operation functions |
245 | ##### I/O operation functions ##### |
246 | * @brief Data transfers functions |
246 | =============================================================================== |
247 | * |
247 | [..] |
248 | @verbatim |
248 | This subsection provides a set of functions allowing to manage the SDMMC data |
249 | =============================================================================== |
249 | transfers. |
250 | ##### I/O operation functions ##### |
250 | |
251 | =============================================================================== |
251 | @endverbatim |
252 | [..] |
252 | * @{ |
253 | This subsection provides a set of functions allowing to manage the SDMMC data |
253 | */ |
254 | transfers. |
254 | |
255 | 255 | /** |
|
256 | @endverbatim |
256 | * @brief Read data (word) from Rx FIFO in blocking mode (polling) |
257 | * @{ |
257 | * @param SDIOx: Pointer to SDMMC register base |
258 | */ |
258 | * @retval HAL status |
259 | 259 | */ |
|
260 | /** |
260 | uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx) |
261 | * @brief Read data (word) from Rx FIFO in blocking mode (polling) |
261 | { |
262 | * @param SDIOx: Pointer to SDMMC register base |
262 | /* Read data from Rx FIFO */ |
263 | * @retval HAL status |
263 | return (SDIOx->FIFO); |
264 | */ |
264 | } |
265 | uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx) |
265 | |
266 | { |
266 | /** |
267 | /* Read data from Rx FIFO */ |
267 | * @brief Write data (word) to Tx FIFO in blocking mode (polling) |
268 | return (SDIOx->FIFO); |
268 | * @param SDIOx: Pointer to SDMMC register base |
269 | } |
269 | * @param pWriteData: pointer to data to write |
270 | 270 | * @retval HAL status |
|
271 | /** |
271 | */ |
272 | * @brief Write data (word) to Tx FIFO in blocking mode (polling) |
272 | HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData) |
273 | * @param SDIOx: Pointer to SDMMC register base |
273 | { |
274 | * @param pWriteData: pointer to data to write |
274 | /* Write data to FIFO */ |
275 | * @retval HAL status |
275 | SDIOx->FIFO = *pWriteData; |
276 | */ |
276 | |
277 | HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData) |
277 | return HAL_OK; |
278 | { |
278 | } |
279 | /* Write data to FIFO */ |
279 | |
280 | SDIOx->FIFO = *pWriteData; |
280 | /** |
281 | 281 | * @} |
|
282 | return HAL_OK; |
282 | */ |
283 | } |
283 | |
284 | 284 | /** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions |
|
285 | /** |
285 | * @brief management functions |
286 | * @} |
286 | * |
287 | */ |
287 | @verbatim |
288 | 288 | =============================================================================== |
|
289 | /** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions |
289 | ##### Peripheral Control functions ##### |
290 | * @brief management functions |
290 | =============================================================================== |
291 | * |
291 | [..] |
292 | @verbatim |
292 | This subsection provides a set of functions allowing to control the SDMMC data |
293 | =============================================================================== |
293 | transfers. |
294 | ##### Peripheral Control functions ##### |
294 | |
295 | =============================================================================== |
295 | @endverbatim |
296 | [..] |
296 | * @{ |
297 | This subsection provides a set of functions allowing to control the SDMMC data |
297 | */ |
298 | transfers. |
298 | |
299 | 299 | /** |
|
300 | @endverbatim |
300 | * @brief Set SDMMC Power state to ON. |
301 | * @{ |
301 | * @param SDIOx: Pointer to SDMMC register base |
302 | */ |
302 | * @retval HAL status |
303 | 303 | */ |
|
304 | /** |
304 | HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx) |
305 | * @brief Set SDMMC Power state to ON. |
305 | { |
306 | * @param SDIOx: Pointer to SDMMC register base |
306 | /* Set power state to ON */ |
307 | * @retval HAL status |
307 | SDIOx->POWER = SDIO_POWER_PWRCTRL; |
308 | */ |
308 | |
309 | HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx) |
309 | return HAL_OK; |
310 | { |
310 | } |
311 | /* Set power state to ON */ |
311 | |
312 | SDIOx->POWER = SDIO_POWER_PWRCTRL; |
312 | /** |
313 | 313 | * @brief Set SDMMC Power state to OFF. |
|
314 | /* 1ms: required power up waiting time before starting the SD initialization |
314 | * @param SDIOx: Pointer to SDMMC register base |
315 | sequence */ |
315 | * @retval HAL status |
316 | HAL_Delay(2); |
316 | */ |
317 | 317 | HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx) |
|
318 | return HAL_OK; |
318 | { |
319 | } |
319 | /* Set power state to OFF */ |
320 | 320 | SDIOx->POWER = (uint32_t)0x00000000; |
|
321 | /** |
321 | |
322 | * @brief Set SDMMC Power state to OFF. |
322 | return HAL_OK; |
323 | * @param SDIOx: Pointer to SDMMC register base |
323 | } |
324 | * @retval HAL status |
324 | |
325 | */ |
325 | /** |
326 | HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx) |
326 | * @brief Get SDMMC Power state. |
327 | { |
327 | * @param SDIOx: Pointer to SDMMC register base |
328 | /* Set power state to OFF */ |
328 | * @retval Power status of the controller. The returned value can be one of the |
329 | SDIOx->POWER = (uint32_t)0x00000000; |
329 | * following values: |
330 | 330 | * - 0x00: Power OFF |
|
331 | return HAL_OK; |
331 | * - 0x02: Power UP |
332 | } |
332 | * - 0x03: Power ON |
333 | 333 | */ |
|
334 | /** |
334 | uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx) |
335 | * @brief Get SDMMC Power state. |
335 | { |
336 | * @param SDIOx: Pointer to SDMMC register base |
336 | return (SDIOx->POWER & SDIO_POWER_PWRCTRL); |
337 | * @retval Power status of the controller. The returned value can be one of the |
337 | } |
338 | * following values: |
338 | |
339 | * - 0x00: Power OFF |
339 | /** |
340 | * - 0x02: Power UP |
340 | * @brief Configure the SDMMC command path according to the specified parameters in |
341 | * - 0x03: Power ON |
341 | * SDIO_CmdInitTypeDef structure and send the command |
342 | */ |
342 | * @param SDIOx: Pointer to SDMMC register base |
343 | uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx) |
343 | * @param Command: pointer to a SDIO_CmdInitTypeDef structure that contains |
344 | { |
344 | * the configuration information for the SDMMC command |
345 | return (SDIOx->POWER & SDIO_POWER_PWRCTRL); |
345 | * @retval HAL status |
346 | } |
346 | */ |
347 | 347 | HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command) |
|
348 | /** |
348 | { |
349 | * @brief Configure the SDMMC command path according to the specified parameters in |
349 | uint32_t tmpreg = 0; |
350 | * SDIO_CmdInitTypeDef structure and send the command |
350 | |
351 | * @param SDIOx: Pointer to SDMMC register base |
351 | /* Check the parameters */ |
352 | * @param Command: pointer to a SDIO_CmdInitTypeDef structure that contains |
352 | assert_param(IS_SDIO_CMD_INDEX(Command->CmdIndex)); |
353 | * the configuration information for the SDMMC command |
353 | assert_param(IS_SDIO_RESPONSE(Command->Response)); |
354 | * @retval HAL status |
354 | assert_param(IS_SDIO_WAIT(Command->WaitForInterrupt)); |
355 | */ |
355 | assert_param(IS_SDIO_CPSM(Command->CPSM)); |
356 | HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command) |
356 | |
357 | { |
357 | /* Set the SDMMC Argument value */ |
358 | uint32_t tmpreg = 0; |
358 | SDIOx->ARG = Command->Argument; |
359 | 359 | ||
360 | /* Check the parameters */ |
360 | /* Set SDMMC command parameters */ |
361 | assert_param(IS_SDIO_CMD_INDEX(Command->CmdIndex)); |
361 | tmpreg |= (uint32_t)(Command->CmdIndex |\ |
362 | assert_param(IS_SDIO_RESPONSE(Command->Response)); |
362 | Command->Response |\ |
363 | assert_param(IS_SDIO_WAIT(Command->WaitForInterrupt)); |
363 | Command->WaitForInterrupt |\ |
364 | assert_param(IS_SDIO_CPSM(Command->CPSM)); |
364 | Command->CPSM); |
365 | 365 | ||
366 | /* Set the SDMMC Argument value */ |
366 | /* Write to SDMMC CMD register */ |
367 | SDIOx->ARG = Command->Argument; |
367 | MODIFY_REG(SDIOx->CMD, CMD_CLEAR_MASK, tmpreg); |
368 | 368 | ||
369 | /* Set SDMMC command parameters */ |
369 | return HAL_OK; |
370 | tmpreg |= (uint32_t)(Command->CmdIndex |\ |
370 | } |
371 | Command->Response |\ |
371 | |
372 | Command->WaitForInterrupt |\ |
372 | /** |
373 | Command->CPSM); |
373 | * @brief Return the command index of last command for which response received |
374 | 374 | * @param SDIOx: Pointer to SDMMC register base |
|
375 | /* Write to SDMMC CMD register */ |
375 | * @retval Command index of the last command response received |
376 | MODIFY_REG(SDIOx->CMD, CMD_CLEAR_MASK, tmpreg); |
376 | */ |
377 | 377 | uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx) |
|
378 | return HAL_OK; |
378 | { |
379 | } |
379 | return (uint8_t)(SDIOx->RESPCMD); |
380 | 380 | } |
|
381 | /** |
381 | |
382 | * @brief Return the command index of last command for which response received |
382 | |
383 | * @param SDIOx: Pointer to SDMMC register base |
383 | /** |
384 | * @retval Command index of the last command response received |
384 | * @brief Return the response received from the card for the last command |
385 | */ |
385 | * @param SDIOx: Pointer to SDMMC register base |
386 | uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx) |
386 | * @param Response: Specifies the SDMMC response register. |
387 | { |
387 | * This parameter can be one of the following values: |
388 | return (uint8_t)(SDIOx->RESPCMD); |
388 | * @arg SDIO_RESP1: Response Register 1 |
389 | } |
389 | * @arg SDIO_RESP2: Response Register 2 |
390 | 390 | * @arg SDIO_RESP3: Response Register 3 |
|
391 | 391 | * @arg SDIO_RESP4: Response Register 4 |
|
392 | /** |
392 | * @retval The Corresponding response register value |
393 | * @brief Return the response received from the card for the last command |
393 | */ |
394 | * @param SDIOx: Pointer to SDMMC register base |
394 | uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response) |
395 | * @param Response: Specifies the SDMMC response register. |
395 | { |
396 | * This parameter can be one of the following values: |
396 | uint32_t tmp; |
397 | * @arg SDIO_RESP1: Response Register 1 |
397 | |
398 | * @arg SDIO_RESP2: Response Register 2 |
398 | /* Check the parameters */ |
399 | * @arg SDIO_RESP3: Response Register 3 |
399 | assert_param(IS_SDIO_RESP(Response)); |
400 | * @arg SDIO_RESP4: Response Register 4 |
400 | |
401 | * @retval The Corresponding response register value |
401 | /* Get the response */ |
402 | */ |
402 | tmp = (uint32_t)(&(SDIOx->RESP1)) + Response; |
403 | uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response) |
403 | |
404 | { |
404 | return (*(__IO uint32_t *) tmp); |
405 | uint32_t tmp; |
405 | } |
406 | 406 | ||
407 | /* Check the parameters */ |
407 | /** |
408 | assert_param(IS_SDIO_RESP(Response)); |
408 | * @brief Configure the SDMMC data path according to the specified |
409 | 409 | * parameters in the SDIO_DataInitTypeDef. |
|
410 | /* Get the response */ |
410 | * @param SDIOx: Pointer to SDIO register base |
411 | tmp = (uint32_t)(&(SDIOx->RESP1)) + Response; |
411 | * @param Data : pointer to a SDIO_DataInitTypeDef structure |
412 | 412 | * that contains the configuration information for the SDMMC data. |
|
413 | return (*(__IO uint32_t *) tmp); |
413 | * @retval HAL status |
414 | } |
414 | */ |
415 | 415 | HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data) |
|
416 | /** |
416 | { |
417 | * @brief Configure the SDMMC data path according to the specified |
417 | uint32_t tmpreg = 0; |
418 | * parameters in the SDIO_DataInitTypeDef. |
418 | |
419 | * @param SDIOx: Pointer to SDIO register base |
419 | /* Check the parameters */ |
420 | * @param Data : pointer to a SDIO_DataInitTypeDef structure |
420 | assert_param(IS_SDIO_DATA_LENGTH(Data->DataLength)); |
421 | * that contains the configuration information for the SDMMC data. |
421 | assert_param(IS_SDIO_BLOCK_SIZE(Data->DataBlockSize)); |
422 | * @retval HAL status |
422 | assert_param(IS_SDIO_TRANSFER_DIR(Data->TransferDir)); |
423 | */ |
423 | assert_param(IS_SDIO_TRANSFER_MODE(Data->TransferMode)); |
424 | HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data) |
424 | assert_param(IS_SDIO_DPSM(Data->DPSM)); |
425 | { |
425 | |
426 | uint32_t tmpreg = 0; |
426 | /* Set the SDMMC Data TimeOut value */ |
427 | 427 | SDIOx->DTIMER = Data->DataTimeOut; |
|
428 | /* Check the parameters */ |
428 | |
429 | assert_param(IS_SDIO_DATA_LENGTH(Data->DataLength)); |
429 | /* Set the SDMMC DataLength value */ |
430 | assert_param(IS_SDIO_BLOCK_SIZE(Data->DataBlockSize)); |
430 | SDIOx->DLEN = Data->DataLength; |
431 | assert_param(IS_SDIO_TRANSFER_DIR(Data->TransferDir)); |
431 | |
432 | assert_param(IS_SDIO_TRANSFER_MODE(Data->TransferMode)); |
432 | /* Set the SDMMC data configuration parameters */ |
433 | assert_param(IS_SDIO_DPSM(Data->DPSM)); |
433 | tmpreg |= (uint32_t)(Data->DataBlockSize |\ |
434 | 434 | Data->TransferDir |\ |
|
435 | /* Set the SDMMC Data TimeOut value */ |
435 | Data->TransferMode |\ |
436 | SDIOx->DTIMER = Data->DataTimeOut; |
436 | Data->DPSM); |
437 | 437 | ||
438 | /* Set the SDMMC DataLength value */ |
438 | /* Write to SDMMC DCTRL */ |
439 | SDIOx->DLEN = Data->DataLength; |
439 | MODIFY_REG(SDIOx->DCTRL, DCTRL_CLEAR_MASK, tmpreg); |
440 | 440 | ||
441 | /* Set the SDMMC data configuration parameters */ |
441 | return HAL_OK; |
442 | tmpreg |= (uint32_t)(Data->DataBlockSize |\ |
442 | |
443 | Data->TransferDir |\ |
443 | } |
444 | Data->TransferMode |\ |
444 | |
445 | Data->DPSM); |
445 | /** |
446 | 446 | * @brief Returns number of remaining data bytes to be transferred. |
|
447 | /* Write to SDMMC DCTRL */ |
447 | * @param SDIOx: Pointer to SDIO register base |
448 | MODIFY_REG(SDIOx->DCTRL, DCTRL_CLEAR_MASK, tmpreg); |
448 | * @retval Number of remaining data bytes to be transferred |
449 | 449 | */ |
|
450 | return HAL_OK; |
450 | uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx) |
451 | 451 | { |
|
452 | } |
452 | return (SDIOx->DCOUNT); |
453 | 453 | } |
|
454 | /** |
454 | |
455 | * @brief Returns number of remaining data bytes to be transferred. |
455 | /** |
456 | * @param SDIOx: Pointer to SDIO register base |
456 | * @brief Get the FIFO data |
457 | * @retval Number of remaining data bytes to be transferred |
457 | * @param SDIOx: Pointer to SDIO register base |
458 | */ |
458 | * @retval Data received |
459 | uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx) |
459 | */ |
460 | { |
460 | uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx) |
461 | return (SDIOx->DCOUNT); |
461 | { |
462 | } |
462 | return (SDIOx->FIFO); |
463 | 463 | } |
|
464 | /** |
464 | |
465 | * @brief Get the FIFO data |
465 | /** |
466 | * @param SDIOx: Pointer to SDIO register base |
466 | * @brief Sets one of the two options of inserting read wait interval. |
467 | * @retval Data received |
467 | * @param SDIOx: Pointer to SDIO register base |
468 | */ |
468 | * @param SDIO_ReadWaitMode: SDMMC Read Wait operation mode. |
469 | uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx) |
469 | * This parameter can be: |
470 | { |
470 | * @arg SDIO_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK |
471 | return (SDIOx->FIFO); |
471 | * @arg SDIO_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2 |
472 | } |
472 | * @retval None |
473 | 473 | */ |
|
474 | /** |
474 | HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode) |
475 | * @brief Sets one of the two options of inserting read wait interval. |
475 | { |
476 | * @param SDIOx: Pointer to SDIO register base |
476 | /* Check the parameters */ |
477 | * @param SDIO_ReadWaitMode: SDMMC Read Wait operation mode. |
477 | assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode)); |
478 | * This parameter can be: |
478 | |
479 | * @arg SDIO_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK |
479 | /* Set SDMMC read wait mode */ |
480 | * @arg SDIO_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2 |
480 | MODIFY_REG(SDIOx->DCTRL, SDIO_DCTRL_RWMOD, SDIO_ReadWaitMode); |
481 | * @retval None |
481 | |
482 | */ |
482 | return HAL_OK; |
483 | HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode) |
483 | } |
484 | { |
484 | |
485 | /* Check the parameters */ |
485 | /** |
486 | assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode)); |
486 | * @} |
487 | 487 | */ |
|
488 | /* Set SDMMC read wait mode */ |
488 | |
489 | MODIFY_REG(SDIOx->DCTRL, SDIO_DCTRL_RWMOD, SDIO_ReadWaitMode); |
489 | |
490 | 490 | /** @defgroup HAL_SDMMC_LL_Group4 Command management functions |
|
491 | return HAL_OK; |
491 | * @brief Data transfers functions |
492 | } |
492 | * |
493 | 493 | @verbatim |
|
494 | /** |
494 | =============================================================================== |
495 | * @} |
495 | ##### Commands management functions ##### |
496 | */ |
496 | =============================================================================== |
497 | 497 | [..] |
|
498 | 498 | This subsection provides a set of functions allowing to manage the needed commands. |
|
499 | /** @defgroup HAL_SDMMC_LL_Group4 Command management functions |
499 | |
500 | * @brief Data transfers functions |
500 | @endverbatim |
501 | * |
501 | * @{ |
502 | @verbatim |
502 | */ |
503 | =============================================================================== |
503 | |
504 | ##### Commands management functions ##### |
504 | /** |
505 | =============================================================================== |
505 | * @brief Send the Data Block Length command and check the response |
506 | [..] |
506 | * @param SDIOx: Pointer to SDIO register base |
507 | This subsection provides a set of functions allowing to manage the needed commands. |
507 | * @retval HAL status |
508 | 508 | */ |
|
509 | @endverbatim |
509 | uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize) |
510 | * @{ |
510 | { |
511 | */ |
511 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
512 | 512 | uint32_t errorstate; |
|
513 | /** |
513 | |
514 | * @brief Send the Data Block Length command and check the response |
514 | /* Set Block Size for Card */ |
515 | * @param SDIOx: Pointer to SDIO register base |
515 | sdmmc_cmdinit.Argument = (uint32_t)BlockSize; |
516 | * @retval HAL status |
516 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_BLOCKLEN; |
517 | */ |
517 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
518 | uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize) |
518 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
519 | { |
519 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
520 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
520 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
521 | uint32_t errorstate; |
521 | |
522 | 522 | /* Check for error conditions */ |
|
523 | /* Set Block Size for Card */ |
523 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SET_BLOCKLEN, SDIO_CMDTIMEOUT); |
524 | sdmmc_cmdinit.Argument = (uint32_t)BlockSize; |
524 | |
525 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_BLOCKLEN; |
525 | return errorstate; |
526 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
526 | } |
527 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
527 | |
528 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
528 | /** |
529 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
529 | * @brief Send the Read Single Block command and check the response |
530 | 530 | * @param SDIOx: Pointer to SDIO register base |
|
531 | /* Check for error conditions */ |
531 | * @retval HAL status |
532 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SET_BLOCKLEN, SDIO_CMDTIMEOUT); |
532 | */ |
533 | 533 | uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd) |
|
534 | return errorstate; |
534 | { |
535 | } |
535 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
536 | 536 | uint32_t errorstate; |
|
537 | /** |
537 | |
538 | * @brief Send the Read Single Block command and check the response |
538 | /* Set Block Size for Card */ |
539 | * @param SDIOx: Pointer to SDIO register base |
539 | sdmmc_cmdinit.Argument = (uint32_t)ReadAdd; |
540 | * @retval HAL status |
540 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_SINGLE_BLOCK; |
541 | */ |
541 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
542 | uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd) |
542 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
543 | { |
543 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
544 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
544 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
545 | uint32_t errorstate; |
545 | |
546 | 546 | /* Check for error conditions */ |
|
547 | /* Set Block Size for Card */ |
547 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_READ_SINGLE_BLOCK, SDIO_CMDTIMEOUT); |
548 | sdmmc_cmdinit.Argument = (uint32_t)ReadAdd; |
548 | |
549 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_SINGLE_BLOCK; |
549 | return errorstate; |
550 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
550 | } |
551 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
551 | |
552 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
552 | /** |
553 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
553 | * @brief Send the Read Multi Block command and check the response |
554 | 554 | * @param SDIOx: Pointer to SDIO register base |
|
555 | /* Check for error conditions */ |
555 | * @retval HAL status |
556 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_READ_SINGLE_BLOCK, SDIO_CMDTIMEOUT); |
556 | */ |
557 | 557 | uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd) |
|
558 | return errorstate; |
558 | { |
559 | } |
559 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
560 | 560 | uint32_t errorstate; |
|
561 | /** |
561 | |
562 | * @brief Send the Read Multi Block command and check the response |
562 | /* Set Block Size for Card */ |
563 | * @param SDIOx: Pointer to SDIO register base |
563 | sdmmc_cmdinit.Argument = (uint32_t)ReadAdd; |
564 | * @retval HAL status |
564 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_MULT_BLOCK; |
565 | */ |
565 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
566 | uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd) |
566 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
567 | { |
567 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
568 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
568 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
569 | uint32_t errorstate; |
569 | |
570 | 570 | /* Check for error conditions */ |
|
571 | /* Set Block Size for Card */ |
571 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_READ_MULT_BLOCK, SDIO_CMDTIMEOUT); |
572 | sdmmc_cmdinit.Argument = (uint32_t)ReadAdd; |
572 | |
573 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_MULT_BLOCK; |
573 | return errorstate; |
574 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
574 | } |
575 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
575 | |
576 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
576 | /** |
577 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
577 | * @brief Send the Write Single Block command and check the response |
578 | 578 | * @param SDIOx: Pointer to SDIO register base |
|
579 | /* Check for error conditions */ |
579 | * @retval HAL status |
580 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_READ_MULT_BLOCK, SDIO_CMDTIMEOUT); |
580 | */ |
581 | 581 | uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd) |
|
582 | return errorstate; |
582 | { |
583 | } |
583 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
584 | 584 | uint32_t errorstate; |
|
585 | /** |
585 | |
586 | * @brief Send the Write Single Block command and check the response |
586 | /* Set Block Size for Card */ |
587 | * @param SDIOx: Pointer to SDIO register base |
587 | sdmmc_cmdinit.Argument = (uint32_t)WriteAdd; |
588 | * @retval HAL status |
588 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_SINGLE_BLOCK; |
589 | */ |
589 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
590 | uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd) |
590 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
591 | { |
591 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
592 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
592 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
593 | uint32_t errorstate; |
593 | |
594 | 594 | /* Check for error conditions */ |
|
595 | /* Set Block Size for Card */ |
595 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_WRITE_SINGLE_BLOCK, SDIO_CMDTIMEOUT); |
596 | sdmmc_cmdinit.Argument = (uint32_t)WriteAdd; |
596 | |
597 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_SINGLE_BLOCK; |
597 | return errorstate; |
598 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
598 | } |
599 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
599 | |
600 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
600 | /** |
601 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
601 | * @brief Send the Write Multi Block command and check the response |
602 | 602 | * @param SDIOx: Pointer to SDIO register base |
|
603 | /* Check for error conditions */ |
603 | * @retval HAL status |
604 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_WRITE_SINGLE_BLOCK, SDIO_CMDTIMEOUT); |
604 | */ |
605 | 605 | uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd) |
|
606 | return errorstate; |
606 | { |
607 | } |
607 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
608 | 608 | uint32_t errorstate; |
|
609 | /** |
609 | |
610 | * @brief Send the Write Multi Block command and check the response |
610 | /* Set Block Size for Card */ |
611 | * @param SDIOx: Pointer to SDIO register base |
611 | sdmmc_cmdinit.Argument = (uint32_t)WriteAdd; |
612 | * @retval HAL status |
612 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_MULT_BLOCK; |
613 | */ |
613 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
614 | uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd) |
614 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
615 | { |
615 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
616 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
616 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
617 | uint32_t errorstate; |
617 | |
618 | 618 | /* Check for error conditions */ |
|
619 | /* Set Block Size for Card */ |
619 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_WRITE_MULT_BLOCK, SDIO_CMDTIMEOUT); |
620 | sdmmc_cmdinit.Argument = (uint32_t)WriteAdd; |
620 | |
621 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_MULT_BLOCK; |
621 | return errorstate; |
622 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
622 | } |
623 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
623 | |
624 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
624 | /** |
625 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
625 | * @brief Send the Start Address Erase command for SD and check the response |
626 | 626 | * @param SDIOx: Pointer to SDIO register base |
|
627 | /* Check for error conditions */ |
627 | * @retval HAL status |
628 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_WRITE_MULT_BLOCK, SDIO_CMDTIMEOUT); |
628 | */ |
629 | 629 | uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd) |
|
630 | return errorstate; |
630 | { |
631 | } |
631 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
632 | 632 | uint32_t errorstate; |
|
633 | /** |
633 | |
634 | * @brief Send the Start Address Erase command for SD and check the response |
634 | /* Set Block Size for Card */ |
635 | * @param SDIOx: Pointer to SDIO register base |
635 | sdmmc_cmdinit.Argument = (uint32_t)StartAdd; |
636 | * @retval HAL status |
636 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_START; |
637 | */ |
637 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
638 | uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd) |
638 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
639 | { |
639 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
640 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
640 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
641 | uint32_t errorstate; |
641 | |
642 | 642 | /* Check for error conditions */ |
|
643 | /* Set Block Size for Card */ |
643 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_ERASE_GRP_START, SDIO_CMDTIMEOUT); |
644 | sdmmc_cmdinit.Argument = (uint32_t)StartAdd; |
644 | |
645 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_START; |
645 | return errorstate; |
646 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
646 | } |
647 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
647 | |
648 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
648 | /** |
649 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
649 | * @brief Send the End Address Erase command for SD and check the response |
650 | 650 | * @param SDIOx: Pointer to SDIO register base |
|
651 | /* Check for error conditions */ |
651 | * @retval HAL status |
652 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_ERASE_GRP_START, SDIO_CMDTIMEOUT); |
652 | */ |
653 | 653 | uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd) |
|
654 | return errorstate; |
654 | { |
655 | } |
655 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
656 | 656 | uint32_t errorstate; |
|
657 | /** |
657 | |
658 | * @brief Send the End Address Erase command for SD and check the response |
658 | /* Set Block Size for Card */ |
659 | * @param SDIOx: Pointer to SDIO register base |
659 | sdmmc_cmdinit.Argument = (uint32_t)EndAdd; |
660 | * @retval HAL status |
660 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_END; |
661 | */ |
661 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
662 | uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd) |
662 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
663 | { |
663 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
664 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
664 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
665 | uint32_t errorstate; |
665 | |
666 | 666 | /* Check for error conditions */ |
|
667 | /* Set Block Size for Card */ |
667 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_ERASE_GRP_END, SDIO_CMDTIMEOUT); |
668 | sdmmc_cmdinit.Argument = (uint32_t)EndAdd; |
668 | |
669 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_END; |
669 | return errorstate; |
670 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
670 | } |
671 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
671 | |
672 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
672 | /** |
673 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
673 | * @brief Send the Start Address Erase command and check the response |
674 | 674 | * @param SDIOx: Pointer to SDIO register base |
|
675 | /* Check for error conditions */ |
675 | * @retval HAL status |
676 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_ERASE_GRP_END, SDIO_CMDTIMEOUT); |
676 | */ |
677 | 677 | uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd) |
|
678 | return errorstate; |
678 | { |
679 | } |
679 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
680 | 680 | uint32_t errorstate; |
|
681 | /** |
681 | |
682 | * @brief Send the Start Address Erase command and check the response |
682 | /* Set Block Size for Card */ |
683 | * @param SDIOx: Pointer to SDIO register base |
683 | sdmmc_cmdinit.Argument = (uint32_t)StartAdd; |
684 | * @retval HAL status |
684 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_START; |
685 | */ |
685 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
686 | uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd) |
686 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
687 | { |
687 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
688 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
688 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
689 | uint32_t errorstate; |
689 | |
690 | 690 | /* Check for error conditions */ |
|
691 | /* Set Block Size for Card */ |
691 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE_GRP_START, SDIO_CMDTIMEOUT); |
692 | sdmmc_cmdinit.Argument = (uint32_t)StartAdd; |
692 | |
693 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_START; |
693 | return errorstate; |
694 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
694 | } |
695 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
695 | |
696 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
696 | /** |
697 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
697 | * @brief Send the End Address Erase command and check the response |
698 | 698 | * @param SDIOx: Pointer to SDIO register base |
|
699 | /* Check for error conditions */ |
699 | * @retval HAL status |
700 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE_GRP_START, SDIO_CMDTIMEOUT); |
700 | */ |
701 | 701 | uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd) |
|
702 | return errorstate; |
702 | { |
703 | } |
703 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
704 | 704 | uint32_t errorstate; |
|
705 | /** |
705 | |
706 | * @brief Send the End Address Erase command and check the response |
706 | /* Set Block Size for Card */ |
707 | * @param SDIOx: Pointer to SDIO register base |
707 | sdmmc_cmdinit.Argument = (uint32_t)EndAdd; |
708 | * @retval HAL status |
708 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_END; |
709 | */ |
709 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
710 | uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd) |
710 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
711 | { |
711 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
712 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
712 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
713 | uint32_t errorstate; |
713 | |
714 | 714 | /* Check for error conditions */ |
|
715 | /* Set Block Size for Card */ |
715 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE_GRP_END, SDIO_CMDTIMEOUT); |
716 | sdmmc_cmdinit.Argument = (uint32_t)EndAdd; |
716 | |
717 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_END; |
717 | return errorstate; |
718 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
718 | } |
719 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
719 | |
720 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
720 | /** |
721 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
721 | * @brief Send the Erase command and check the response |
722 | 722 | * @param SDIOx: Pointer to SDIO register base |
|
723 | /* Check for error conditions */ |
723 | * @retval HAL status |
724 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE_GRP_END, SDIO_CMDTIMEOUT); |
724 | */ |
725 | 725 | uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx) |
|
726 | return errorstate; |
726 | { |
727 | } |
727 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
728 | 728 | uint32_t errorstate; |
|
729 | /** |
729 | |
730 | * @brief Send the Erase command and check the response |
730 | /* Set Block Size for Card */ |
731 | * @param SDIOx: Pointer to SDIO register base |
731 | sdmmc_cmdinit.Argument = 0U; |
732 | * @retval HAL status |
732 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE; |
733 | */ |
733 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
734 | uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx) |
734 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
735 | { |
735 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
736 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
736 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
737 | uint32_t errorstate; |
737 | |
738 | 738 | /* Check for error conditions */ |
|
739 | /* Set Block Size for Card */ |
739 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE, SDIO_MAXERASETIMEOUT); |
740 | sdmmc_cmdinit.Argument = 0U; |
740 | |
741 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE; |
741 | return errorstate; |
742 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
742 | } |
743 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
743 | |
744 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
744 | /** |
745 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
745 | * @brief Send the Stop Transfer command and check the response. |
746 | 746 | * @param SDIOx: Pointer to SDIO register base |
|
747 | /* Check for error conditions */ |
747 | * @retval HAL status |
748 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE, SDIO_MAXERASETIMEOUT); |
748 | */ |
749 | 749 | uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx) |
|
750 | return errorstate; |
750 | { |
751 | } |
751 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
752 | 752 | uint32_t errorstate; |
|
753 | /** |
753 | |
754 | * @brief Send the Stop Transfer command and check the response. |
754 | /* Send CMD12 STOP_TRANSMISSION */ |
755 | * @param SDIOx: Pointer to SDIO register base |
755 | sdmmc_cmdinit.Argument = 0U; |
756 | * @retval HAL status |
756 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_STOP_TRANSMISSION; |
757 | */ |
757 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
758 | uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx) |
758 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
759 | { |
759 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
760 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
760 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
761 | uint32_t errorstate; |
761 | |
762 | 762 | /* Check for error conditions */ |
|
763 | /* Send CMD12 STOP_TRANSMISSION */ |
763 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_STOP_TRANSMISSION, SDIO_STOPTRANSFERTIMEOUT); |
764 | sdmmc_cmdinit.Argument = 0U; |
764 | |
765 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_STOP_TRANSMISSION; |
765 | return errorstate; |
766 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
766 | } |
767 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
767 | |
768 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
768 | /** |
769 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
769 | * @brief Send the Select Deselect command and check the response. |
770 | 770 | * @param SDIOx: Pointer to SDIO register base |
|
771 | /* Check for error conditions */ |
771 | * @param addr: Address of the card to be selected |
772 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_STOP_TRANSMISSION, SDIO_STOPTRANSFERTIMEOUT); |
772 | * @retval HAL status |
773 | 773 | */ |
|
774 | return errorstate; |
774 | uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr) |
775 | } |
775 | { |
776 | 776 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
|
777 | /** |
777 | uint32_t errorstate; |
778 | * @brief Send the Select Deselect command and check the response. |
778 | |
779 | * @param SDIOx: Pointer to SDIO register base |
779 | /* Send CMD7 SDMMC_SEL_DESEL_CARD */ |
780 | * @param addr: Address of the card to be selected |
780 | sdmmc_cmdinit.Argument = (uint32_t)Addr; |
781 | * @retval HAL status |
781 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEL_DESEL_CARD; |
782 | */ |
782 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
783 | uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr) |
783 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
784 | { |
784 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
785 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
785 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
786 | uint32_t errorstate; |
786 | |
787 | 787 | /* Check for error conditions */ |
|
788 | /* Send CMD7 SDMMC_SEL_DESEL_CARD */ |
788 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SEL_DESEL_CARD, SDIO_CMDTIMEOUT); |
789 | sdmmc_cmdinit.Argument = (uint32_t)Addr; |
789 | |
790 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEL_DESEL_CARD; |
790 | return errorstate; |
791 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
791 | } |
792 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
792 | |
793 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
793 | /** |
794 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
794 | * @brief Send the Go Idle State command and check the response. |
795 | 795 | * @param SDIOx: Pointer to SDIO register base |
|
796 | /* Check for error conditions */ |
796 | * @retval HAL status |
797 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SEL_DESEL_CARD, SDIO_CMDTIMEOUT); |
797 | */ |
798 | 798 | uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx) |
|
799 | return errorstate; |
799 | { |
800 | } |
800 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
801 | 801 | uint32_t errorstate; |
|
802 | /** |
802 | |
803 | * @brief Send the Go Idle State command and check the response. |
803 | sdmmc_cmdinit.Argument = 0U; |
804 | * @param SDIOx: Pointer to SDIO register base |
804 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_GO_IDLE_STATE; |
805 | * @retval HAL status |
805 | sdmmc_cmdinit.Response = SDIO_RESPONSE_NO; |
806 | */ |
806 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
807 | uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx) |
807 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
808 | { |
808 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
809 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
809 | |
810 | uint32_t errorstate; |
810 | /* Check for error conditions */ |
811 | 811 | errorstate = SDMMC_GetCmdError(SDIOx); |
|
812 | sdmmc_cmdinit.Argument = 0U; |
812 | |
813 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_GO_IDLE_STATE; |
813 | return errorstate; |
814 | sdmmc_cmdinit.Response = SDIO_RESPONSE_NO; |
814 | } |
815 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
815 | |
816 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
816 | /** |
817 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
817 | * @brief Send the Operating Condition command and check the response. |
818 | 818 | * @param SDIOx: Pointer to SDIO register base |
|
819 | /* Check for error conditions */ |
819 | * @retval HAL status |
820 | errorstate = SDMMC_GetCmdError(SDIOx); |
820 | */ |
821 | 821 | uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx) |
|
822 | return errorstate; |
822 | { |
823 | } |
823 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
824 | 824 | uint32_t errorstate; |
|
825 | /** |
825 | |
826 | * @brief Send the Operating Condition command and check the response. |
826 | /* Send CMD8 to verify SD card interface operating condition */ |
827 | * @param SDIOx: Pointer to SDIO register base |
827 | /* Argument: - [31:12]: Reserved (shall be set to '0') |
828 | * @retval HAL status |
828 | - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V) |
829 | */ |
829 | - [7:0]: Check Pattern (recommended 0xAA) */ |
830 | uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx) |
830 | /* CMD Response: R7 */ |
831 | { |
831 | sdmmc_cmdinit.Argument = SDMMC_CHECK_PATTERN; |
832 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
832 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD; |
833 | uint32_t errorstate; |
833 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
834 | 834 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
|
835 | /* Send CMD8 to verify SD card interface operating condition */ |
835 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
836 | /* Argument: - [31:12]: Reserved (shall be set to '0') |
836 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
837 | - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V) |
837 | |
838 | - [7:0]: Check Pattern (recommended 0xAA) */ |
838 | /* Check for error conditions */ |
839 | /* CMD Response: R7 */ |
839 | errorstate = SDMMC_GetCmdResp7(SDIOx); |
840 | sdmmc_cmdinit.Argument = SDMMC_CHECK_PATTERN; |
840 | |
841 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD; |
841 | return errorstate; |
842 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
842 | } |
843 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
843 | |
844 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
844 | /** |
845 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
845 | * @brief Send the Application command to verify that that the next command |
846 | 846 | * is an application specific com-mand rather than a standard command |
|
847 | /* Check for error conditions */ |
847 | * and check the response. |
848 | errorstate = SDMMC_GetCmdResp7(SDIOx); |
848 | * @param SDIOx: Pointer to SDIO register base |
849 | 849 | * @param Argument: Command Argument |
|
850 | return errorstate; |
850 | * @retval HAL status |
851 | } |
851 | */ |
852 | 852 | uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument) |
|
853 | /** |
853 | { |
854 | * @brief Send the Application command to verify that that the next command |
854 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
855 | * is an application specific com-mand rather than a standard command |
855 | uint32_t errorstate; |
856 | * and check the response. |
856 | |
857 | * @param SDIOx: Pointer to SDIO register base |
857 | sdmmc_cmdinit.Argument = (uint32_t)Argument; |
858 | * @param Argument: Command Argument |
858 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_CMD; |
859 | * @retval HAL status |
859 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
860 | */ |
860 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
861 | uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument) |
861 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
862 | { |
862 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
863 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
863 | |
864 | uint32_t errorstate; |
864 | /* Check for error conditions */ |
865 | 865 | /* If there is a HAL_ERROR, it is a MMC card, else |
|
866 | sdmmc_cmdinit.Argument = (uint32_t)Argument; |
866 | it is a SD card: SD card 2.0 (voltage range mismatch) |
867 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_CMD; |
867 | or SD card 1.x */ |
868 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
868 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_APP_CMD, SDIO_CMDTIMEOUT); |
869 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
869 | |
870 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
870 | return errorstate; |
871 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
871 | } |
872 | 872 | ||
873 | /* Check for error conditions */ |
873 | /** |
874 | /* If there is a HAL_ERROR, it is a MMC card, else |
874 | * @brief Send the command asking the accessed card to send its operating |
875 | it is a SD card: SD card 2.0 (voltage range mismatch) |
875 | * condition register (OCR) |
876 | or SD card 1.x */ |
876 | * @param SDIOx: Pointer to SDIO register base |
877 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_APP_CMD, SDIO_CMDTIMEOUT); |
877 | * @param Argument: Command Argument |
878 | 878 | * @retval HAL status |
|
879 | return errorstate; |
879 | */ |
880 | } |
880 | uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t Argument) |
881 | 881 | { |
|
882 | /** |
882 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
883 | * @brief Send the command asking the accessed card to send its operating |
883 | uint32_t errorstate; |
884 | * condition register (OCR) |
884 | |
885 | * @param SDIOx: Pointer to SDIO register base |
885 | sdmmc_cmdinit.Argument = SDMMC_VOLTAGE_WINDOW_SD | Argument; |
886 | * @param Argument: Command Argument |
886 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_OP_COND; |
887 | * @retval HAL status |
887 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
888 | */ |
888 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
889 | uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t Argument) |
889 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
890 | { |
890 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
891 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
891 | |
892 | uint32_t errorstate; |
892 | /* Check for error conditions */ |
893 | 893 | errorstate = SDMMC_GetCmdResp3(SDIOx); |
|
894 | sdmmc_cmdinit.Argument = SDMMC_VOLTAGE_WINDOW_SD | Argument; |
894 | |
895 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_OP_COND; |
895 | return errorstate; |
896 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
896 | } |
897 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
897 | |
898 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
898 | /** |
899 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
899 | * @brief Send the Bus Width command and check the response. |
900 | 900 | * @param SDIOx: Pointer to SDIO register base |
|
901 | /* Check for error conditions */ |
901 | * @param BusWidth: BusWidth |
902 | errorstate = SDMMC_GetCmdResp3(SDIOx); |
902 | * @retval HAL status |
903 | 903 | */ |
|
904 | return errorstate; |
904 | uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth) |
905 | } |
905 | { |
906 | 906 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
|
907 | /** |
907 | uint32_t errorstate; |
908 | * @brief Send the Bus Width command and check the response. |
908 | |
909 | * @param SDIOx: Pointer to SDIO register base |
909 | sdmmc_cmdinit.Argument = (uint32_t)BusWidth; |
910 | * @param BusWidth: BusWidth |
910 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_SD_SET_BUSWIDTH; |
911 | * @retval HAL status |
911 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
912 | */ |
912 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
913 | uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth) |
913 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
914 | { |
914 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
915 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
915 | |
916 | uint32_t errorstate; |
916 | /* Check for error conditions */ |
917 | 917 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_APP_SD_SET_BUSWIDTH, SDIO_CMDTIMEOUT); |
|
918 | sdmmc_cmdinit.Argument = (uint32_t)BusWidth; |
918 | |
919 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_SD_SET_BUSWIDTH; |
919 | return errorstate; |
920 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
920 | } |
921 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
921 | |
922 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
922 | /** |
923 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
923 | * @brief Send the Send SCR command and check the response. |
924 | 924 | * @param SDIOx: Pointer to SDIO register base |
|
925 | /* Check for error conditions */ |
925 | * @retval HAL status |
926 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_APP_SD_SET_BUSWIDTH, SDIO_CMDTIMEOUT); |
926 | */ |
927 | 927 | uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx) |
|
928 | return errorstate; |
928 | { |
929 | } |
929 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
930 | 930 | uint32_t errorstate; |
|
931 | /** |
931 | |
932 | * @brief Send the Send SCR command and check the response. |
932 | /* Send CMD51 SD_APP_SEND_SCR */ |
933 | * @param SDIOx: Pointer to SDIO register base |
933 | sdmmc_cmdinit.Argument = 0U; |
934 | * @retval HAL status |
934 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_SEND_SCR; |
935 | */ |
935 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
936 | uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx) |
936 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
937 | { |
937 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
938 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
938 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
939 | uint32_t errorstate; |
939 | |
940 | 940 | /* Check for error conditions */ |
|
941 | /* Send CMD51 SD_APP_SEND_SCR */ |
941 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_APP_SEND_SCR, SDIO_CMDTIMEOUT); |
942 | sdmmc_cmdinit.Argument = 0U; |
942 | |
943 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_SEND_SCR; |
943 | return errorstate; |
944 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
944 | } |
945 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
945 | |
946 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
946 | /** |
947 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
947 | * @brief Send the Send CID command and check the response. |
948 | 948 | * @param SDIOx: Pointer to SDIO register base |
|
949 | /* Check for error conditions */ |
949 | * @retval HAL status |
950 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_APP_SEND_SCR, SDIO_CMDTIMEOUT); |
950 | */ |
951 | 951 | uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx) |
|
952 | return errorstate; |
952 | { |
953 | } |
953 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
954 | 954 | uint32_t errorstate; |
|
955 | /** |
955 | |
956 | * @brief Send the Send CID command and check the response. |
956 | /* Send CMD2 ALL_SEND_CID */ |
957 | * @param SDIOx: Pointer to SDIO register base |
957 | sdmmc_cmdinit.Argument = 0U; |
958 | * @retval HAL status |
958 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ALL_SEND_CID; |
959 | */ |
959 | sdmmc_cmdinit.Response = SDIO_RESPONSE_LONG; |
960 | uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx) |
960 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
961 | { |
961 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
962 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
962 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
963 | uint32_t errorstate; |
963 | |
964 | 964 | /* Check for error conditions */ |
|
965 | /* Send CMD2 ALL_SEND_CID */ |
965 | errorstate = SDMMC_GetCmdResp2(SDIOx); |
966 | sdmmc_cmdinit.Argument = 0U; |
966 | |
967 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ALL_SEND_CID; |
967 | return errorstate; |
968 | sdmmc_cmdinit.Response = SDIO_RESPONSE_LONG; |
968 | } |
969 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
969 | |
970 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
970 | /** |
971 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
971 | * @brief Send the Send CSD command and check the response. |
972 | 972 | * @param SDIOx: Pointer to SDIO register base |
|
973 | /* Check for error conditions */ |
973 | * @param Argument: Command Argument |
974 | errorstate = SDMMC_GetCmdResp2(SDIOx); |
974 | * @retval HAL status |
975 | 975 | */ |
|
976 | return errorstate; |
976 | uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument) |
977 | } |
977 | { |
978 | 978 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
|
979 | /** |
979 | uint32_t errorstate; |
980 | * @brief Send the Send CSD command and check the response. |
980 | |
981 | * @param SDIOx: Pointer to SDIO register base |
981 | /* Send CMD9 SEND_CSD */ |
982 | * @param Argument: Command Argument |
982 | sdmmc_cmdinit.Argument = Argument; |
983 | * @retval HAL status |
983 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_CSD; |
984 | */ |
984 | sdmmc_cmdinit.Response = SDIO_RESPONSE_LONG; |
985 | uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument) |
985 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
986 | { |
986 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
987 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
987 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
988 | uint32_t errorstate; |
988 | |
989 | 989 | /* Check for error conditions */ |
|
990 | /* Send CMD9 SEND_CSD */ |
990 | errorstate = SDMMC_GetCmdResp2(SDIOx); |
991 | sdmmc_cmdinit.Argument = Argument; |
991 | |
992 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_CSD; |
992 | return errorstate; |
993 | sdmmc_cmdinit.Response = SDIO_RESPONSE_LONG; |
993 | } |
994 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
994 | |
995 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
995 | /** |
996 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
996 | * @brief Send the Send CSD command and check the response. |
997 | 997 | * @param SDIOx: Pointer to SDIO register base |
|
998 | /* Check for error conditions */ |
998 | * @param pRCA: Card RCA |
999 | errorstate = SDMMC_GetCmdResp2(SDIOx); |
999 | * @retval HAL status |
1000 | 1000 | */ |
|
1001 | return errorstate; |
1001 | uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA) |
1002 | } |
1002 | { |
1003 | 1003 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
|
1004 | /** |
1004 | uint32_t errorstate; |
1005 | * @brief Send the Send CSD command and check the response. |
1005 | |
1006 | * @param SDIOx: Pointer to SDIO register base |
1006 | /* Send CMD3 SD_CMD_SET_REL_ADDR */ |
1007 | * @param pRCA: Card RCA |
1007 | sdmmc_cmdinit.Argument = 0U; |
1008 | * @retval HAL status |
1008 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR; |
1009 | */ |
1009 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
1010 | uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA) |
1010 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
1011 | { |
1011 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
1012 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
1012 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
1013 | uint32_t errorstate; |
1013 | |
1014 | 1014 | /* Check for error conditions */ |
|
1015 | /* Send CMD3 SD_CMD_SET_REL_ADDR */ |
1015 | errorstate = SDMMC_GetCmdResp6(SDIOx, SDMMC_CMD_SET_REL_ADDR, pRCA); |
1016 | sdmmc_cmdinit.Argument = 0U; |
1016 | |
1017 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR; |
1017 | return errorstate; |
1018 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
1018 | } |
1019 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
1019 | |
1020 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
1020 | /** |
1021 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
1021 | * @brief Send the Set Relative Address command to MMC card (not SD card). |
1022 | 1022 | * @param SDIOx Pointer to SDIO register base |
|
1023 | /* Check for error conditions */ |
1023 | * @param RCA Card RCA |
1024 | errorstate = SDMMC_GetCmdResp6(SDIOx, SDMMC_CMD_SET_REL_ADDR, pRCA); |
1024 | * @retval HAL status |
1025 | 1025 | */ |
|
1026 | return errorstate; |
1026 | uint32_t SDMMC_CmdSetRelAddMmc(SDIO_TypeDef *SDIOx, uint16_t RCA) |
1027 | } |
1027 | { |
1028 | 1028 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
|
1029 | /** |
1029 | uint32_t errorstate; |
1030 | * @brief Send the Status command and check the response. |
1030 | |
1031 | * @param SDIOx: Pointer to SDIO register base |
1031 | /* Send CMD3 SD_CMD_SET_REL_ADDR */ |
1032 | * @param Argument: Command Argument |
1032 | sdmmc_cmdinit.Argument = ((uint32_t)RCA << 16U); |
1033 | * @retval HAL status |
1033 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR; |
1034 | */ |
1034 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
1035 | uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument) |
1035 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
1036 | { |
1036 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
1037 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
1037 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
1038 | uint32_t errorstate; |
1038 | |
1039 | 1039 | /* Check for error conditions */ |
|
1040 | sdmmc_cmdinit.Argument = Argument; |
1040 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SET_REL_ADDR, SDIO_CMDTIMEOUT); |
1041 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_STATUS; |
1041 | |
1042 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
1042 | return errorstate; |
1043 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
1043 | } |
1044 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
1044 | |
1045 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
1045 | /** |
1046 | 1046 | * @brief Send the Status command and check the response. |
|
1047 | /* Check for error conditions */ |
1047 | * @param SDIOx: Pointer to SDIO register base |
1048 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SEND_STATUS, SDIO_CMDTIMEOUT); |
1048 | * @param Argument: Command Argument |
1049 | 1049 | * @retval HAL status |
|
1050 | return errorstate; |
1050 | */ |
1051 | } |
1051 | uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument) |
1052 | 1052 | { |
|
1053 | /** |
1053 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
1054 | * @brief Send the Status register command and check the response. |
1054 | uint32_t errorstate; |
1055 | * @param SDIOx: Pointer to SDIO register base |
1055 | |
1056 | * @retval HAL status |
1056 | sdmmc_cmdinit.Argument = Argument; |
1057 | */ |
1057 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_STATUS; |
1058 | uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx) |
1058 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
1059 | { |
1059 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
1060 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
1060 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
1061 | uint32_t errorstate; |
1061 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
1062 | 1062 | ||
1063 | sdmmc_cmdinit.Argument = 0U; |
1063 | /* Check for error conditions */ |
1064 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_STATUS; |
1064 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SEND_STATUS, SDIO_CMDTIMEOUT); |
1065 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
1065 | |
1066 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
1066 | return errorstate; |
1067 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
1067 | } |
1068 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
1068 | |
1069 | 1069 | /** |
|
1070 | /* Check for error conditions */ |
1070 | * @brief Send the Status register command and check the response. |
1071 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_APP_STATUS, SDIO_CMDTIMEOUT); |
1071 | * @param SDIOx: Pointer to SDIO register base |
1072 | 1072 | * @retval HAL status |
|
1073 | return errorstate; |
1073 | */ |
1074 | } |
1074 | uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx) |
1075 | 1075 | { |
|
1076 | /** |
1076 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
1077 | * @brief Sends host capacity support information and activates the card's |
1077 | uint32_t errorstate; |
1078 | * initialization process. Send SDMMC_CMD_SEND_OP_COND command |
1078 | |
1079 | * @param SDIOx: Pointer to SDIO register base |
1079 | sdmmc_cmdinit.Argument = 0U; |
1080 | * @parame Argument: Argument used for the command |
1080 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_STATUS; |
1081 | * @retval HAL status |
1081 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
1082 | */ |
1082 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
1083 | uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument) |
1083 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
1084 | { |
1084 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
1085 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
1085 | |
1086 | uint32_t errorstate; |
1086 | /* Check for error conditions */ |
1087 | 1087 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_APP_STATUS, SDIO_CMDTIMEOUT); |
|
1088 | sdmmc_cmdinit.Argument = Argument; |
1088 | |
1089 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_OP_COND; |
1089 | return errorstate; |
1090 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
1090 | } |
1091 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
1091 | |
1092 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
1092 | /** |
1093 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
1093 | * @brief Sends host capacity support information and activates the card's |
1094 | 1094 | * initialization process. Send SDMMC_CMD_SEND_OP_COND command |
|
1095 | /* Check for error conditions */ |
1095 | * @param SDIOx: Pointer to SDIO register base |
1096 | errorstate = SDMMC_GetCmdResp3(SDIOx); |
1096 | * @parame Argument: Argument used for the command |
1097 | 1097 | * @retval HAL status |
|
1098 | return errorstate; |
1098 | */ |
1099 | } |
1099 | uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument) |
1100 | 1100 | { |
|
1101 | /** |
1101 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
1102 | * @brief Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH command |
1102 | uint32_t errorstate; |
1103 | * @param SDIOx: Pointer to SDIO register base |
1103 | |
1104 | * @parame Argument: Argument used for the command |
1104 | sdmmc_cmdinit.Argument = Argument; |
1105 | * @retval HAL status |
1105 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_OP_COND; |
1106 | */ |
1106 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
1107 | uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument) |
1107 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
1108 | { |
1108 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
1109 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
1109 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
1110 | uint32_t errorstate; |
1110 | |
1111 | 1111 | /* Check for error conditions */ |
|
1112 | /* Send CMD6 to activate SDR50 Mode and Power Limit 1.44W */ |
1112 | errorstate = SDMMC_GetCmdResp3(SDIOx); |
1113 | /* CMD Response: R1 */ |
1113 | |
1114 | sdmmc_cmdinit.Argument = Argument; /* SDMMC_SDR25_SWITCH_PATTERN */ |
1114 | return errorstate; |
1115 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SWITCH; |
1115 | } |
1116 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
1116 | |
1117 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
1117 | /** |
1118 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
1118 | * @brief Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH command |
1119 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
1119 | * @param SDIOx: Pointer to SDIO register base |
1120 | 1120 | * @parame Argument: Argument used for the command |
|
1121 | /* Check for error conditions */ |
1121 | * @retval HAL status |
1122 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_HS_SWITCH, SDIO_CMDTIMEOUT); |
1122 | */ |
1123 | 1123 | uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument) |
|
1124 | return errorstate; |
1124 | { |
1125 | } |
1125 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
1126 | 1126 | uint32_t errorstate; |
|
1127 | /** |
1127 | |
1128 | * @} |
1128 | /* Send CMD6 to activate SDR50 Mode and Power Limit 1.44W */ |
1129 | */ |
1129 | /* CMD Response: R1 */ |
1130 | 1130 | sdmmc_cmdinit.Argument = Argument; /* SDMMC_SDR25_SWITCH_PATTERN */ |
|
1131 | /* Private function ----------------------------------------------------------*/ |
1131 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SWITCH; |
1132 | /** @addtogroup SD_Private_Functions |
1132 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
1133 | * @{ |
1133 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
1134 | */ |
1134 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
1135 | 1135 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
|
1136 | /** |
1136 | |
1137 | * @brief Checks for error conditions for CMD0. |
1137 | /* Check for error conditions */ |
1138 | * @param hsd: SD handle |
1138 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_HS_SWITCH, SDIO_CMDTIMEOUT); |
1139 | * @retval SD Card error state |
1139 | |
1140 | */ |
1140 | return errorstate; |
1141 | static uint32_t SDMMC_GetCmdError(SDIO_TypeDef *SDIOx) |
1141 | } |
1142 | { |
1142 | |
1143 | /* 8 is the number of required instructions cycles for the below loop statement. |
1143 | /** |
1144 | The SDIO_CMDTIMEOUT is expressed in ms */ |
1144 | * @brief Send the Send EXT_CSD command and check the response. |
1145 | uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); |
1145 | * @param SDIOx Pointer to SDMMC register base |
1146 | 1146 | * @param Argument Command Argument |
|
1147 | do |
1147 | * @retval HAL status |
1148 | { |
1148 | */ |
1149 | if (count-- == 0U) |
1149 | uint32_t SDMMC_CmdSendEXTCSD(SDIO_TypeDef *SDIOx, uint32_t Argument) |
1150 | { |
1150 | { |
1151 | return SDMMC_ERROR_TIMEOUT; |
1151 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
1152 | } |
1152 | uint32_t errorstate; |
1153 | 1153 | ||
1154 | }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CMDSENT)); |
1154 | /* Send CMD9 SEND_CSD */ |
1155 | 1155 | sdmmc_cmdinit.Argument = Argument; |
|
1156 | /* Clear all the static flags */ |
1156 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD; |
1157 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS); |
1157 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
1158 | 1158 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
|
1159 | return SDMMC_ERROR_NONE; |
1159 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
1160 | } |
1160 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
1161 | 1161 | ||
1162 | /** |
1162 | /* Check for error conditions */ |
1163 | * @brief Checks for error conditions for R1 response. |
1163 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_HS_SEND_EXT_CSD,SDIO_CMDTIMEOUT); |
1164 | * @param hsd: SD handle |
1164 | |
1165 | * @param SD_CMD: The sent command index |
1165 | return errorstate; |
1166 | * @retval SD Card error state |
1166 | } |
1167 | */ |
1167 | |
1168 | static uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout) |
1168 | /** |
1169 | { |
1169 | * @} |
1170 | uint32_t response_r1; |
1170 | */ |
1171 | uint32_t sta_reg; |
1171 | |
1172 | 1172 | /** @defgroup HAL_SDMMC_LL_Group5 Responses management functions |
|
1173 | /* 8 is the number of required instructions cycles for the below loop statement. |
1173 | * @brief Responses functions |
1174 | The Timeout is expressed in ms */ |
1174 | * |
1175 | uint32_t count = Timeout * (SystemCoreClock / 8U /1000U); |
1175 | @verbatim |
1176 | 1176 | =============================================================================== |
|
1177 | do |
1177 | ##### Responses management functions ##### |
1178 | { |
1178 | =============================================================================== |
1179 | if (count-- == 0U) |
1179 | [..] |
1180 | { |
1180 | This subsection provides a set of functions allowing to manage the needed responses. |
1181 | return SDMMC_ERROR_TIMEOUT; |
1181 | |
1182 | } |
1182 | @endverbatim |
1183 | sta_reg = SDIOx->STA; |
1183 | * @{ |
1184 | }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) || |
1184 | */ |
1185 | ((sta_reg & SDIO_FLAG_CMDACT) != 0U )); |
1185 | /** |
1186 | 1186 | * @brief Checks for error conditions for R1 response. |
|
1187 | if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT)) |
1187 | * @param SDIOx Pointer to SDMMC register base |
1188 | { |
1188 | * @param SD_CMD: The sent command index |
1189 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT); |
1189 | * @retval SD Card error state |
1190 | 1190 | */ |
|
1191 | return SDMMC_ERROR_CMD_RSP_TIMEOUT; |
1191 | uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout) |
1192 | } |
1192 | { |
1193 | else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL)) |
1193 | uint32_t response_r1; |
1194 | { |
1194 | uint32_t sta_reg; |
1195 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL); |
1195 | |
1196 | 1196 | /* 8 is the number of required instructions cycles for the below loop statement. |
|
1197 | return SDMMC_ERROR_CMD_CRC_FAIL; |
1197 | The Timeout is expressed in ms */ |
1198 | } |
1198 | uint32_t count = Timeout * (SystemCoreClock / 8U /1000U); |
1199 | else |
1199 | |
1200 | { |
1200 | do |
1201 | /* Nothing to do */ |
1201 | { |
1202 | } |
1202 | if (count-- == 0U) |
1203 | 1203 | { |
|
1204 | /* Clear all the static flags */ |
1204 | return SDMMC_ERROR_TIMEOUT; |
1205 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS); |
1205 | } |
1206 | 1206 | sta_reg = SDIOx->STA; |
|
1207 | /* Check response received is of desired command */ |
1207 | }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) || |
1208 | if(SDIO_GetCommandResponse(SDIOx) != SD_CMD) |
1208 | ((sta_reg & SDIO_FLAG_CMDACT) != 0U )); |
1209 | { |
1209 | |
1210 | return SDMMC_ERROR_CMD_CRC_FAIL; |
1210 | if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT)) |
1211 | } |
1211 | { |
1212 | 1212 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT); |
|
1213 | /* We have received response, retrieve it for analysis */ |
1213 | |
1214 | response_r1 = SDIO_GetResponse(SDIOx, SDIO_RESP1); |
1214 | return SDMMC_ERROR_CMD_RSP_TIMEOUT; |
1215 | 1215 | } |
|
1216 | if((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO) |
1216 | else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL)) |
1217 | { |
1217 | { |
1218 | return SDMMC_ERROR_NONE; |
1218 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL); |
1219 | } |
1219 | |
1220 | else if((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE) |
1220 | return SDMMC_ERROR_CMD_CRC_FAIL; |
1221 | { |
1221 | } |
1222 | return SDMMC_ERROR_ADDR_OUT_OF_RANGE; |
1222 | else |
1223 | } |
1223 | { |
1224 | else if((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED) |
1224 | /* Nothing to do */ |
1225 | { |
1225 | } |
1226 | return SDMMC_ERROR_ADDR_MISALIGNED; |
1226 | |
1227 | } |
1227 | /* Clear all the static flags */ |
1228 | else if((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR) |
1228 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS); |
1229 | { |
1229 | |
1230 | return SDMMC_ERROR_BLOCK_LEN_ERR; |
1230 | /* Check response received is of desired command */ |
1231 | } |
1231 | if(SDIO_GetCommandResponse(SDIOx) != SD_CMD) |
1232 | else if((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR) |
1232 | { |
1233 | { |
1233 | return SDMMC_ERROR_CMD_CRC_FAIL; |
1234 | return SDMMC_ERROR_ERASE_SEQ_ERR; |
1234 | } |
1235 | } |
1235 | |
1236 | else if((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM) |
1236 | /* We have received response, retrieve it for analysis */ |
1237 | { |
1237 | response_r1 = SDIO_GetResponse(SDIOx, SDIO_RESP1); |
1238 | return SDMMC_ERROR_BAD_ERASE_PARAM; |
1238 | |
1239 | } |
1239 | if((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO) |
1240 | else if((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION) |
1240 | { |
1241 | { |
1241 | return SDMMC_ERROR_NONE; |
1242 | return SDMMC_ERROR_WRITE_PROT_VIOLATION; |
1242 | } |
1243 | } |
1243 | else if((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE) |
1244 | else if((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED) |
1244 | { |
1245 | { |
1245 | return SDMMC_ERROR_ADDR_OUT_OF_RANGE; |
1246 | return SDMMC_ERROR_LOCK_UNLOCK_FAILED; |
1246 | } |
1247 | } |
1247 | else if((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED) |
1248 | else if((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED) |
1248 | { |
1249 | { |
1249 | return SDMMC_ERROR_ADDR_MISALIGNED; |
1250 | return SDMMC_ERROR_COM_CRC_FAILED; |
1250 | } |
1251 | } |
1251 | else if((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR) |
1252 | else if((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD) |
1252 | { |
1253 | { |
1253 | return SDMMC_ERROR_BLOCK_LEN_ERR; |
1254 | return SDMMC_ERROR_ILLEGAL_CMD; |
1254 | } |
1255 | } |
1255 | else if((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR) |
1256 | else if((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED) |
1256 | { |
1257 | { |
1257 | return SDMMC_ERROR_ERASE_SEQ_ERR; |
1258 | return SDMMC_ERROR_CARD_ECC_FAILED; |
1258 | } |
1259 | } |
1259 | else if((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM) |
1260 | else if((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR) |
1260 | { |
1261 | { |
1261 | return SDMMC_ERROR_BAD_ERASE_PARAM; |
1262 | return SDMMC_ERROR_CC_ERR; |
1262 | } |
1263 | } |
1263 | else if((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION) |
1264 | else if((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN) |
1264 | { |
1265 | { |
1265 | return SDMMC_ERROR_WRITE_PROT_VIOLATION; |
1266 | return SDMMC_ERROR_STREAM_READ_UNDERRUN; |
1266 | } |
1267 | } |
1267 | else if((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED) |
1268 | else if((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN) |
1268 | { |
1269 | { |
1269 | return SDMMC_ERROR_LOCK_UNLOCK_FAILED; |
1270 | return SDMMC_ERROR_STREAM_WRITE_OVERRUN; |
1270 | } |
1271 | } |
1271 | else if((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED) |
1272 | else if((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE) |
1272 | { |
1273 | { |
1273 | return SDMMC_ERROR_COM_CRC_FAILED; |
1274 | return SDMMC_ERROR_CID_CSD_OVERWRITE; |
1274 | } |
1275 | } |
1275 | else if((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD) |
1276 | else if((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP) |
1276 | { |
1277 | { |
1277 | return SDMMC_ERROR_ILLEGAL_CMD; |
1278 | return SDMMC_ERROR_WP_ERASE_SKIP; |
1278 | } |
1279 | } |
1279 | else if((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED) |
1280 | else if((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED) |
1280 | { |
1281 | { |
1281 | return SDMMC_ERROR_CARD_ECC_FAILED; |
1282 | return SDMMC_ERROR_CARD_ECC_DISABLED; |
1282 | } |
1283 | } |
1283 | else if((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR) |
1284 | else if((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET) |
1284 | { |
1285 | { |
1285 | return SDMMC_ERROR_CC_ERR; |
1286 | return SDMMC_ERROR_ERASE_RESET; |
1286 | } |
1287 | } |
1287 | else if((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN) |
1288 | else if((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR) |
1288 | { |
1289 | { |
1289 | return SDMMC_ERROR_STREAM_READ_UNDERRUN; |
1290 | return SDMMC_ERROR_AKE_SEQ_ERR; |
1290 | } |
1291 | } |
1291 | else if((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN) |
1292 | else |
1292 | { |
1293 | { |
1293 | return SDMMC_ERROR_STREAM_WRITE_OVERRUN; |
1294 | return SDMMC_ERROR_GENERAL_UNKNOWN_ERR; |
1294 | } |
1295 | } |
1295 | else if((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE) |
1296 | } |
1296 | { |
1297 | 1297 | return SDMMC_ERROR_CID_CSD_OVERWRITE; |
|
1298 | /** |
1298 | } |
1299 | * @brief Checks for error conditions for R2 (CID or CSD) response. |
1299 | else if((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP) |
1300 | * @param hsd: SD handle |
1300 | { |
1301 | * @retval SD Card error state |
1301 | return SDMMC_ERROR_WP_ERASE_SKIP; |
1302 | */ |
1302 | } |
1303 | static uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx) |
1303 | else if((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED) |
1304 | { |
1304 | { |
1305 | uint32_t sta_reg; |
1305 | return SDMMC_ERROR_CARD_ECC_DISABLED; |
1306 | /* 8 is the number of required instructions cycles for the below loop statement. |
1306 | } |
1307 | The SDIO_CMDTIMEOUT is expressed in ms */ |
1307 | else if((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET) |
1308 | uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); |
1308 | { |
1309 | 1309 | return SDMMC_ERROR_ERASE_RESET; |
|
1310 | do |
1310 | } |
1311 | { |
1311 | else if((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR) |
1312 | if (count-- == 0U) |
1312 | { |
1313 | { |
1313 | return SDMMC_ERROR_AKE_SEQ_ERR; |
1314 | return SDMMC_ERROR_TIMEOUT; |
1314 | } |
1315 | } |
1315 | else |
1316 | sta_reg = SDIOx->STA; |
1316 | { |
1317 | }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) || |
1317 | return SDMMC_ERROR_GENERAL_UNKNOWN_ERR; |
1318 | ((sta_reg & SDIO_FLAG_CMDACT) != 0U )); |
1318 | } |
1319 | 1319 | } |
|
1320 | if (__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT)) |
1320 | |
1321 | { |
1321 | /** |
1322 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT); |
1322 | * @brief Checks for error conditions for R2 (CID or CSD) response. |
1323 | 1323 | * @param SDIOx Pointer to SDMMC register base |
|
1324 | return SDMMC_ERROR_CMD_RSP_TIMEOUT; |
1324 | * @retval SD Card error state |
1325 | } |
1325 | */ |
1326 | else if (__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL)) |
1326 | uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx) |
1327 | { |
1327 | { |
1328 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL); |
1328 | uint32_t sta_reg; |
1329 | 1329 | /* 8 is the number of required instructions cycles for the below loop statement. |
|
1330 | return SDMMC_ERROR_CMD_CRC_FAIL; |
1330 | The SDIO_CMDTIMEOUT is expressed in ms */ |
1331 | } |
1331 | uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); |
1332 | else |
1332 | |
1333 | { |
1333 | do |
1334 | /* No error flag set */ |
1334 | { |
1335 | /* Clear all the static flags */ |
1335 | if (count-- == 0U) |
1336 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS); |
1336 | { |
1337 | } |
1337 | return SDMMC_ERROR_TIMEOUT; |
1338 | 1338 | } |
|
1339 | return SDMMC_ERROR_NONE; |
1339 | sta_reg = SDIOx->STA; |
1340 | } |
1340 | }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) || |
1341 | 1341 | ((sta_reg & SDIO_FLAG_CMDACT) != 0U )); |
|
1342 | /** |
1342 | |
1343 | * @brief Checks for error conditions for R3 (OCR) response. |
1343 | if (__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT)) |
1344 | * @param hsd: SD handle |
1344 | { |
1345 | * @retval SD Card error state |
1345 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT); |
1346 | */ |
1346 | |
1347 | static uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx) |
1347 | return SDMMC_ERROR_CMD_RSP_TIMEOUT; |
1348 | { |
1348 | } |
1349 | uint32_t sta_reg; |
1349 | else if (__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL)) |
1350 | /* 8 is the number of required instructions cycles for the below loop statement. |
1350 | { |
1351 | The SDIO_CMDTIMEOUT is expressed in ms */ |
1351 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL); |
1352 | uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); |
1352 | |
1353 | 1353 | return SDMMC_ERROR_CMD_CRC_FAIL; |
|
1354 | do |
1354 | } |
1355 | { |
1355 | else |
1356 | if (count-- == 0U) |
1356 | { |
1357 | { |
1357 | /* No error flag set */ |
1358 | return SDMMC_ERROR_TIMEOUT; |
1358 | /* Clear all the static flags */ |
1359 | } |
1359 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS); |
1360 | sta_reg = SDIOx->STA; |
1360 | } |
1361 | }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) || |
1361 | |
1362 | ((sta_reg & SDIO_FLAG_CMDACT) != 0U )); |
1362 | return SDMMC_ERROR_NONE; |
1363 | 1363 | } |
|
1364 | if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT)) |
1364 | |
1365 | { |
1365 | /** |
1366 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT); |
1366 | * @brief Checks for error conditions for R3 (OCR) response. |
1367 | 1367 | * @param SDIOx Pointer to SDMMC register base |
|
1368 | return SDMMC_ERROR_CMD_RSP_TIMEOUT; |
1368 | * @retval SD Card error state |
1369 | } |
1369 | */ |
1370 | else |
1370 | uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx) |
1371 | { |
1371 | { |
1372 | /* Clear all the static flags */ |
1372 | uint32_t sta_reg; |
1373 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS); |
1373 | /* 8 is the number of required instructions cycles for the below loop statement. |
1374 | } |
1374 | The SDIO_CMDTIMEOUT is expressed in ms */ |
1375 | 1375 | uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); |
|
1376 | return SDMMC_ERROR_NONE; |
1376 | |
1377 | } |
1377 | do |
1378 | 1378 | { |
|
1379 | /** |
1379 | if (count-- == 0U) |
1380 | * @brief Checks for error conditions for R6 (RCA) response. |
1380 | { |
1381 | * @param hsd: SD handle |
1381 | return SDMMC_ERROR_TIMEOUT; |
1382 | * @param SD_CMD: The sent command index |
1382 | } |
1383 | * @param pRCA: Pointer to the variable that will contain the SD card relative |
1383 | sta_reg = SDIOx->STA; |
1384 | * address RCA |
1384 | }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) || |
1385 | * @retval SD Card error state |
1385 | ((sta_reg & SDIO_FLAG_CMDACT) != 0U )); |
1386 | */ |
1386 | |
1387 | static uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA) |
1387 | if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT)) |
1388 | { |
1388 | { |
1389 | uint32_t response_r1; |
1389 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT); |
1390 | uint32_t sta_reg; |
1390 | |
1391 | 1391 | return SDMMC_ERROR_CMD_RSP_TIMEOUT; |
|
1392 | /* 8 is the number of required instructions cycles for the below loop statement. |
1392 | } |
1393 | The SDIO_CMDTIMEOUT is expressed in ms */ |
1393 | else |
1394 | uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); |
1394 | { |
1395 | 1395 | /* Clear all the static flags */ |
|
1396 | do |
1396 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS); |
1397 | { |
1397 | } |
1398 | if (count-- == 0U) |
1398 | |
1399 | { |
1399 | return SDMMC_ERROR_NONE; |
1400 | return SDMMC_ERROR_TIMEOUT; |
1400 | } |
1401 | } |
1401 | |
1402 | sta_reg = SDIOx->STA; |
1402 | /** |
1403 | }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) || |
1403 | * @brief Checks for error conditions for R6 (RCA) response. |
1404 | ((sta_reg & SDIO_FLAG_CMDACT) != 0U )); |
1404 | * @param SDIOx Pointer to SDMMC register base |
1405 | 1405 | * @param SD_CMD: The sent command index |
|
1406 | if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT)) |
1406 | * @param pRCA: Pointer to the variable that will contain the SD card relative |
1407 | { |
1407 | * address RCA |
1408 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT); |
1408 | * @retval SD Card error state |
1409 | 1409 | */ |
|
1410 | return SDMMC_ERROR_CMD_RSP_TIMEOUT; |
1410 | uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA) |
1411 | } |
1411 | { |
1412 | else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL)) |
1412 | uint32_t response_r1; |
1413 | { |
1413 | uint32_t sta_reg; |
1414 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL); |
1414 | |
1415 | 1415 | /* 8 is the number of required instructions cycles for the below loop statement. |
|
1416 | return SDMMC_ERROR_CMD_CRC_FAIL; |
1416 | The SDIO_CMDTIMEOUT is expressed in ms */ |
1417 | } |
1417 | uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); |
1418 | else |
1418 | |
1419 | { |
1419 | do |
1420 | /* Nothing to do */ |
1420 | { |
1421 | } |
1421 | if (count-- == 0U) |
1422 | 1422 | { |
|
1423 | /* Check response received is of desired command */ |
1423 | return SDMMC_ERROR_TIMEOUT; |
1424 | if(SDIO_GetCommandResponse(SDIOx) != SD_CMD) |
1424 | } |
1425 | { |
1425 | sta_reg = SDIOx->STA; |
1426 | return SDMMC_ERROR_CMD_CRC_FAIL; |
1426 | }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) || |
1427 | } |
1427 | ((sta_reg & SDIO_FLAG_CMDACT) != 0U )); |
1428 | 1428 | ||
1429 | /* Clear all the static flags */ |
1429 | if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT)) |
1430 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS); |
1430 | { |
1431 | 1431 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT); |
|
1432 | /* We have received response, retrieve it. */ |
1432 | |
1433 | response_r1 = SDIO_GetResponse(SDIOx, SDIO_RESP1); |
1433 | return SDMMC_ERROR_CMD_RSP_TIMEOUT; |
1434 | 1434 | } |
|
1435 | if((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO) |
1435 | else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL)) |
1436 | { |
1436 | { |
1437 | *pRCA = (uint16_t) (response_r1 >> 16); |
1437 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL); |
1438 | 1438 | ||
1439 | return SDMMC_ERROR_NONE; |
1439 | return SDMMC_ERROR_CMD_CRC_FAIL; |
1440 | } |
1440 | } |
1441 | else if((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD) |
1441 | else |
1442 | { |
1442 | { |
1443 | return SDMMC_ERROR_ILLEGAL_CMD; |
1443 | /* Nothing to do */ |
1444 | } |
1444 | } |
1445 | else if((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED) |
1445 | |
1446 | { |
1446 | /* Check response received is of desired command */ |
1447 | return SDMMC_ERROR_COM_CRC_FAILED; |
1447 | if(SDIO_GetCommandResponse(SDIOx) != SD_CMD) |
1448 | } |
1448 | { |
1449 | else |
1449 | return SDMMC_ERROR_CMD_CRC_FAIL; |
1450 | { |
1450 | } |
1451 | return SDMMC_ERROR_GENERAL_UNKNOWN_ERR; |
1451 | |
1452 | } |
1452 | /* Clear all the static flags */ |
1453 | } |
1453 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS); |
1454 | 1454 | ||
1455 | /** |
1455 | /* We have received response, retrieve it. */ |
1456 | * @brief Checks for error conditions for R7 response. |
1456 | response_r1 = SDIO_GetResponse(SDIOx, SDIO_RESP1); |
1457 | * @param hsd: SD handle |
1457 | |
1458 | * @retval SD Card error state |
1458 | if((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO) |
1459 | */ |
1459 | { |
1460 | static uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx) |
1460 | *pRCA = (uint16_t) (response_r1 >> 16); |
1461 | { |
1461 | |
1462 | uint32_t sta_reg; |
1462 | return SDMMC_ERROR_NONE; |
1463 | /* 8 is the number of required instructions cycles for the below loop statement. |
1463 | } |
1464 | The SDIO_CMDTIMEOUT is expressed in ms */ |
1464 | else if((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD) |
1465 | uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); |
1465 | { |
1466 | 1466 | return SDMMC_ERROR_ILLEGAL_CMD; |
|
1467 | do |
1467 | } |
1468 | { |
1468 | else if((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED) |
1469 | if (count-- == 0U) |
1469 | { |
1470 | { |
1470 | return SDMMC_ERROR_COM_CRC_FAILED; |
1471 | return SDMMC_ERROR_TIMEOUT; |
1471 | } |
1472 | } |
1472 | else |
1473 | sta_reg = SDIOx->STA; |
1473 | { |
1474 | }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) || |
1474 | return SDMMC_ERROR_GENERAL_UNKNOWN_ERR; |
1475 | ((sta_reg & SDIO_FLAG_CMDACT) != 0U )); |
1475 | } |
1476 | 1476 | } |
|
1477 | if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT)) |
1477 | |
1478 | { |
1478 | /** |
1479 | /* Card is SD V2.0 compliant */ |
1479 | * @brief Checks for error conditions for R7 response. |
1480 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT); |
1480 | * @param SDIOx Pointer to SDMMC register base |
1481 | 1481 | * @retval SD Card error state |
|
1482 | return SDMMC_ERROR_CMD_RSP_TIMEOUT; |
1482 | */ |
1483 | } |
1483 | uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx) |
1484 | else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL)) |
1484 | { |
1485 | { |
1485 | uint32_t sta_reg; |
1486 | /* Card is SD V2.0 compliant */ |
1486 | /* 8 is the number of required instructions cycles for the below loop statement. |
1487 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL); |
1487 | The SDIO_CMDTIMEOUT is expressed in ms */ |
1488 | 1488 | uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); |
|
1489 | return SDMMC_ERROR_CMD_CRC_FAIL; |
1489 | |
1490 | } |
1490 | do |
1491 | else |
1491 | { |
1492 | { |
1492 | if (count-- == 0U) |
1493 | /* Nothing to do */ |
1493 | { |
1494 | } |
1494 | return SDMMC_ERROR_TIMEOUT; |
1495 | 1495 | } |
|
1496 | if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CMDREND)) |
1496 | sta_reg = SDIOx->STA; |
1497 | { |
1497 | }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) || |
1498 | /* Card is SD V2.0 compliant */ |
1498 | ((sta_reg & SDIO_FLAG_CMDACT) != 0U )); |
1499 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CMDREND); |
1499 | |
1500 | } |
1500 | if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT)) |
1501 | 1501 | { |
|
1502 | return SDMMC_ERROR_NONE; |
1502 | /* Card is SD V2.0 compliant */ |
1503 | 1503 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT); |
|
1504 | } |
1504 | |
1505 | 1505 | return SDMMC_ERROR_CMD_RSP_TIMEOUT; |
|
1506 | /** |
1506 | } |
1507 | * @brief Send the Send EXT_CSD command and check the response. |
1507 | else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL)) |
1508 | * @param SDIOx: Pointer to SDMMC register base |
1508 | { |
1509 | * @param Argument: Command Argument |
1509 | /* Card is SD V2.0 compliant */ |
1510 | * @retval HAL status |
1510 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL); |
1511 | */ |
1511 | |
1512 | uint32_t SDMMC_CmdSendEXTCSD(SDIO_TypeDef *SDIOx, uint32_t Argument) |
1512 | return SDMMC_ERROR_CMD_CRC_FAIL; |
1513 | { |
1513 | } |
1514 | SDIO_CmdInitTypeDef sdmmc_cmdinit; |
1514 | else |
1515 | uint32_t errorstate; |
1515 | { |
1516 | 1516 | /* Nothing to do */ |
|
1517 | /* Send CMD9 SEND_CSD */ |
1517 | } |
1518 | sdmmc_cmdinit.Argument = Argument; |
1518 | |
1519 | sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD; |
1519 | if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CMDREND)) |
1520 | sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; |
1520 | { |
1521 | sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; |
1521 | /* Card is SD V2.0 compliant */ |
1522 | sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; |
1522 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CMDREND); |
1523 | (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); |
1523 | } |
1524 | 1524 | ||
1525 | /* Check for error conditions */ |
1525 | return SDMMC_ERROR_NONE; |
1526 | errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_HS_SEND_EXT_CSD,SDIO_CMDTIMEOUT); |
1526 | |
1527 | 1527 | } |
|
1528 | return errorstate; |
1528 | |
1529 | } |
1529 | /** |
1530 | 1530 | * @} |
|
1531 | 1531 | */ |
|
1532 | /** |
1532 | |
1533 | * @} |
1533 | /* Private function ----------------------------------------------------------*/ |
1534 | */ |
1534 | /** @addtogroup SD_Private_Functions |
1535 | 1535 | * @{ |
|
1536 | #endif /* HAL_SD_MODULE_ENABLED || HAL_MMC_MODULE_ENABLED */ |
1536 | */ |
1537 | /** |
1537 | |
1538 | * @} |
1538 | /** |
1539 | */ |
1539 | * @brief Checks for error conditions for CMD0. |
1540 | 1540 | * @param SDIOx Pointer to SDMMC register base |
|
1541 | /** |
1541 | * @retval SD Card error state |
1542 | * @} |
1542 | */ |
1543 | */ |
1543 | static uint32_t SDMMC_GetCmdError(SDIO_TypeDef *SDIOx) |
1544 | 1544 | { |
|
1545 | #endif /* SDIO */ |
1545 | /* 8 is the number of required instructions cycles for the below loop statement. |
1546 | 1546 | The SDIO_CMDTIMEOUT is expressed in ms */ |
|
1547 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
1547 | uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); |
- | 1548 | ||
- | 1549 | do |
|
- | 1550 | { |
|
- | 1551 | if (count-- == 0U) |
|
- | 1552 | { |
|
- | 1553 | return SDMMC_ERROR_TIMEOUT; |
|
- | 1554 | } |
|
- | 1555 | ||
- | 1556 | }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CMDSENT)); |
|
- | 1557 | ||
- | 1558 | /* Clear all the static flags */ |
|
- | 1559 | __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS); |
|
- | 1560 | ||
- | 1561 | return SDMMC_ERROR_NONE; |
|
- | 1562 | } |
|
- | 1563 | ||
- | 1564 | ||
- | 1565 | /** |
|
- | 1566 | * @} |
|
- | 1567 | */ |
|
- | 1568 | ||
- | 1569 | #endif /* HAL_SD_MODULE_ENABLED || HAL_MMC_MODULE_ENABLED */ |
|
- | 1570 | /** |
|
- | 1571 | * @} |
|
- | 1572 | */ |
|
- | 1573 | ||
- | 1574 | /** |
|
- | 1575 | * @} |
|
- | 1576 | */ |
|
- | 1577 | ||
- | 1578 | #endif /* SDIO */ |