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/**
 1 
/**
2 
  ******************************************************************************
 2 
  ******************************************************************************
3 
  * @file    stm32f1xx_ll_fsmc.c
 3 
  * @file    stm32f1xx_ll_fsmc.c
4 
  * @author  MCD Application Team
 4 
  * @author  MCD Application Team
5 
  * @brief   FSMC Low Layer HAL module driver.
 5 
  * @brief   FSMC Low Layer HAL module driver.
6 
  *
 6 
  *
7 
  *          This file provides firmware functions to manage the following
 7 
  *          This file provides firmware functions to manage the following
8 
  *          functionalities of the Flexible Memory Controller (FSMC) peripheral memories:
 8 
  *          functionalities of the Flexible Memory Controller (FSMC) peripheral memories:
9 
  *           + Initialization/de-initialization functions
 9 
  *           + Initialization/de-initialization functions
10 
  *           + Peripheral Control functions
 10 
  *           + Peripheral Control functions
11 
  *           + Peripheral State functions
 11 
  *           + Peripheral State functions
12 
  *
 12 
  *
13 
  @verbatim
 13 
  ******************************************************************************
14 
  ==============================================================================
 14 
  * @attention
15 
                        ##### FSMC peripheral features #####
 15 
  *
16 
  ==============================================================================
 16 
  * Copyright (c) 2016 STMicroelectronics.
17 
  [..] The Flexible memory controller (FSMC) includes following memory controllers:
 17 
  * All rights reserved.
18 
       (+) The NOR/PSRAM memory controller
 18 
  *
19 
       (+) The NAND/PC Card memory controller
 19 
  * This software is licensed under terms that can be found in the LICENSE file
20 
 
 20 
  * in the root directory of this software component.
21 
  [..] The FSMC functional block makes the interface with synchronous and asynchronous static
 21 
  * If no LICENSE file comes with this software, it is provided AS-IS.
22 
       memories and 16-bit PC memory cards. Its main purposes are:
 22 
  *
23 
       (+) to translate AHB transactions into the appropriate external device protocol
 23 
  ******************************************************************************
24 
       (+) to meet the access time requirements of the external memory devices
 24 
  @verbatim
25 
 
 25 
  ==============================================================================
26 
  [..] All external memories share the addresses, data and control signals with the controller.
 26 
                        ##### FSMC peripheral features #####
27 
       Each external device is accessed by means of a unique Chip Select. The FSMC performs
 27 
  ==============================================================================
28 
       only one access at a time to an external device.
 28 
  [..] The Flexible memory controller (FSMC) includes following memory controllers:
29 
       The main features of the FSMC controller are the following:
 29 
       (+) The NOR/PSRAM memory controller
30 
        (+) Interface with static-memory mapped devices including:
 30 
       (+) The NAND/PC Card memory controller
31 
           (++) Static random access memory (SRAM)
 31 
 
32 
           (++) Read-only memory (ROM)
 32 
  [..] The FSMC functional block makes the interface with synchronous and asynchronous static
33 
           (++) NOR Flash memory/OneNAND Flash memory
 33 
       memories and 16-bit PC memory cards. Its main purposes are:
34 
           (++) PSRAM (4 memory banks)
 34 
       (+) to translate AHB transactions into the appropriate external device protocol
35 
           (++) 16-bit PC Card compatible devices
 35 
       (+) to meet the access time requirements of the external memory devices
36 
           (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
 36 
 
37 
                data
 37 
  [..] All external memories share the addresses, data and control signals with the controller.
38 
        (+) Independent Chip Select control for each memory bank
 38 
       Each external device is accessed by means of a unique Chip Select. The FSMC performs
39 
        (+) Independent configuration for each memory bank
 39 
       only one access at a time to an external device.
40 
 
 40 
       The main features of the FSMC controller are the following:
41 
  @endverbatim
 41 
        (+) Interface with static-memory mapped devices including:
42 
  ******************************************************************************
 42 
           (++) Static random access memory (SRAM)
43 
  * @attention
 43 
           (++) Read-only memory (ROM)
44 
  *
 44 
           (++) NOR Flash memory/OneNAND Flash memory
45 
  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
 45 
           (++) PSRAM (4 memory banks)
46 
  * All rights reserved.</center></h2>
 46 
           (++) 16-bit PC Card compatible devices
47 
  *
 47 
           (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
48 
  * This software component is licensed by ST under BSD 3-Clause license,
 48 
                data
49 
  * the "License"; You may not use this file except in compliance with the
 49 
        (+) Independent Chip Select control for each memory bank
50 
  * License. You may obtain a copy of the License at:
 50 
        (+) Independent configuration for each memory bank
51 
  *                       opensource.org/licenses/BSD-3-Clause
 51 
 
52 
  *
 52 
  @endverbatim
53 
  ******************************************************************************
 53 
  ******************************************************************************
54 
  */
 54 
  */
55 
 
 55 
 
56 
/* Includes ------------------------------------------------------------------*/
 56 
/* Includes ------------------------------------------------------------------*/
57 
#include "stm32f1xx_hal.h"
 57 
#include "stm32f1xx_hal.h"
58 
 
 58 
 
59 
/** @addtogroup STM32F1xx_HAL_Driver
 59 
/** @addtogroup STM32F1xx_HAL_Driver
60 
  * @{
 60 
  * @{
61 
  */
 61 
  */
62 
#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED)
 62 
#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) \
63 
 
 63 
 || defined(HAL_SRAM_MODULE_ENABLED)
64 
/** @defgroup FSMC_LL  FSMC Low Layer
 64 
 
65 
  * @brief FSMC driver modules
 65 
/** @defgroup FSMC_LL  FSMC Low Layer
66 
  * @{
 66 
  * @brief FSMC driver modules
67 
  */
 67 
  * @{
68 
 
 68 
  */
69 
/* Private typedef -----------------------------------------------------------*/
 69 
 
70 
/* Private define ------------------------------------------------------------*/
 70 
/* Private typedef -----------------------------------------------------------*/
71 
 
 71 
/* Private define ------------------------------------------------------------*/
72 
/** @defgroup FSMC_LL_Private_Constants FSMC Low Layer Private Constants
 72 
 
73 
  * @{
 73 
/** @defgroup FSMC_LL_Private_Constants FSMC Low Layer Private Constants
74 
  */
 74 
  * @{
75 
 
 75 
  */
76 
/* ----------------------- FSMC registers bit mask --------------------------- */
 76 
 
77 
 
 77 
/* ----------------------- FSMC registers bit mask --------------------------- */
78 
#if defined(FSMC_BANK1)
 78 
 
79 
/* --- BCR Register ---*/
 79 
#if defined(FSMC_BANK1)
80 
/* BCR register clear mask */
 80 
/* --- BCR Register ---*/
81 
 
 81 
/* BCR register clear mask */
82 
/* --- BTR Register ---*/
 82 
 
83 
/* BTR register clear mask */
 83 
/* --- BTR Register ---*/
84 
#define BTR_CLEAR_MASK    ((uint32_t)(FSMC_BTRx_ADDSET | FSMC_BTRx_ADDHLD  |\
 84 
/* BTR register clear mask */
85 
                                      FSMC_BTRx_DATAST | FSMC_BTRx_BUSTURN |\
 85 
#define BTR_CLEAR_MASK    ((uint32_t)(FSMC_BTRx_ADDSET | FSMC_BTRx_ADDHLD  |\
86 
                                      FSMC_BTRx_CLKDIV | FSMC_BTRx_DATLAT  |\
 86 
                                      FSMC_BTRx_DATAST | FSMC_BTRx_BUSTURN |\
87 
                                      FSMC_BTRx_ACCMOD))
 87 
                                      FSMC_BTRx_CLKDIV | FSMC_BTRx_DATLAT  |\
88 
 
 88 
                                      FSMC_BTRx_ACCMOD))
89 
/* --- BWTR Register ---*/
 89 
 
90 
/* BWTR register clear mask */
 90 
/* --- BWTR Register ---*/
91 
#if defined(FSMC_BWTRx_BUSTURN)
 91 
/* BWTR register clear mask */
92 
#define BWTR_CLEAR_MASK   ((uint32_t)(FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD  |\
 92 
#if defined(FSMC_BWTRx_BUSTURN)
93 
                                      FSMC_BWTRx_DATAST | FSMC_BWTRx_BUSTURN |\
 93 
#define BWTR_CLEAR_MASK   ((uint32_t)(FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD  |\
94 
                                      FSMC_BWTRx_ACCMOD))
 94 
                                      FSMC_BWTRx_DATAST | FSMC_BWTRx_BUSTURN |\
95 
#else
 95 
                                      FSMC_BWTRx_ACCMOD))
96 
#define BWTR_CLEAR_MASK   ((uint32_t)(FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD |\
 96 
#else
97 
                                      FSMC_BWTRx_DATAST | FSMC_BWTRx_ACCMOD |\
 97 
#define BWTR_CLEAR_MASK   ((uint32_t)(FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD |\
98 
                                      FSMC_BWTRx_CLKDIV | FSMC_BWTRx_DATLAT))
 98 
                                      FSMC_BWTRx_DATAST | FSMC_BWTRx_ACCMOD |\
99 
#endif /* FSMC_BWTRx_BUSTURN */
 99 
                                      FSMC_BWTRx_CLKDIV | FSMC_BWTRx_DATLAT))
100 
#endif /* FSMC_BANK1 */
 100 
#endif /* FSMC_BWTRx_BUSTURN */
101 
#if defined(FSMC_BANK3)
 101 
#endif /* FSMC_BANK1 */
102 
 
 102 
#if defined(FSMC_BANK3)
103 
/* --- PCR Register ---*/
 103 
 
104 
/* PCR register clear mask */
 104 
/* --- PCR Register ---*/
105 
#define PCR_CLEAR_MASK    ((uint32_t)(FSMC_PCRx_PWAITEN | FSMC_PCRx_PBKEN  | \
 105 
/* PCR register clear mask */
106 
                                      FSMC_PCRx_PTYP    | FSMC_PCRx_PWID   | \
 106 
#define PCR_CLEAR_MASK    ((uint32_t)(FSMC_PCRx_PWAITEN | FSMC_PCRx_PBKEN  | \
107 
                                      FSMC_PCRx_ECCEN   | FSMC_PCRx_TCLR   | \
 107 
                                      FSMC_PCRx_PTYP    | FSMC_PCRx_PWID   | \
108 
                                      FSMC_PCRx_TAR     | FSMC_PCRx_ECCPS))
 108 
                                      FSMC_PCRx_ECCEN   | FSMC_PCRx_TCLR   | \
109 
/* --- PMEM Register ---*/
 109 
                                      FSMC_PCRx_TAR     | FSMC_PCRx_ECCPS))
110 
/* PMEM register clear mask */
 110 
/* --- PMEM Register ---*/
111 
#define PMEM_CLEAR_MASK   ((uint32_t)(FSMC_PMEMx_MEMSETx  | FSMC_PMEMx_MEMWAITx |\
 111 
/* PMEM register clear mask */
112 
                                      FSMC_PMEMx_MEMHOLDx | FSMC_PMEMx_MEMHIZx))
 112 
#define PMEM_CLEAR_MASK   ((uint32_t)(FSMC_PMEMx_MEMSETx  | FSMC_PMEMx_MEMWAITx |\
113 
 
 113 
                                      FSMC_PMEMx_MEMHOLDx | FSMC_PMEMx_MEMHIZx))
114 
/* --- PATT Register ---*/
 114 
 
115 
/* PATT register clear mask */
 115 
/* --- PATT Register ---*/
116 
#define PATT_CLEAR_MASK   ((uint32_t)(FSMC_PATTx_ATTSETx  | FSMC_PATTx_ATTWAITx |\
 116 
/* PATT register clear mask */
117 
                                      FSMC_PATTx_ATTHOLDx | FSMC_PATTx_ATTHIZx))
 117 
#define PATT_CLEAR_MASK   ((uint32_t)(FSMC_PATTx_ATTSETx  | FSMC_PATTx_ATTWAITx |\
118 
 
 118 
                                      FSMC_PATTx_ATTHOLDx | FSMC_PATTx_ATTHIZx))
119 
#endif /* FSMC_BANK3 */
 119 
 
120 
#if defined(FSMC_BANK4)
 120 
#endif /* FSMC_BANK3 */
121 
/* --- PCR Register ---*/
 121 
#if defined(FSMC_BANK4)
122 
/* PCR register clear mask */
 122 
/* --- PCR Register ---*/
123 
#define PCR4_CLEAR_MASK   ((uint32_t)(FSMC_PCR4_PWAITEN | FSMC_PCR4_PBKEN  | \
 123 
/* PCR register clear mask */
124 
                                      FSMC_PCR4_PTYP    | FSMC_PCR4_PWID   | \
 124 
#define PCR4_CLEAR_MASK   ((uint32_t)(FSMC_PCR4_PWAITEN | FSMC_PCR4_PBKEN  | \
125 
                                      FSMC_PCR4_ECCEN   | FSMC_PCR4_TCLR   | \
 125 
                                      FSMC_PCR4_PTYP    | FSMC_PCR4_PWID   | \
126 
                                      FSMC_PCR4_TAR     | FSMC_PCR4_ECCPS))
 126 
                                      FSMC_PCR4_ECCEN   | FSMC_PCR4_TCLR   | \
127 
/* --- PMEM Register ---*/
 127 
                                      FSMC_PCR4_TAR     | FSMC_PCR4_ECCPS))
128 
/* PMEM register clear mask */
 128 
/* --- PMEM Register ---*/
129 
#define PMEM4_CLEAR_MASK  ((uint32_t)(FSMC_PMEM4_MEMSET4  | FSMC_PMEM4_MEMWAIT4 |\
 129 
/* PMEM register clear mask */
130 
                                      FSMC_PMEM4_MEMHOLD4 | FSMC_PMEM4_MEMHIZ4))
 130 
#define PMEM4_CLEAR_MASK  ((uint32_t)(FSMC_PMEM4_MEMSET4  | FSMC_PMEM4_MEMWAIT4 |\
131 
 
 131 
                                      FSMC_PMEM4_MEMHOLD4 | FSMC_PMEM4_MEMHIZ4))
132 
/* --- PATT Register ---*/
 132 
 
133 
/* PATT register clear mask */
 133 
/* --- PATT Register ---*/
134 
#define PATT4_CLEAR_MASK  ((uint32_t)(FSMC_PATT4_ATTSET4  | FSMC_PATT4_ATTWAIT4 |\
 134 
/* PATT register clear mask */
135 
                                      FSMC_PATT4_ATTHOLD4 | FSMC_PATT4_ATTHIZ4))
 135 
#define PATT4_CLEAR_MASK  ((uint32_t)(FSMC_PATT4_ATTSET4  | FSMC_PATT4_ATTWAIT4 |\
136 
 
 136 
                                      FSMC_PATT4_ATTHOLD4 | FSMC_PATT4_ATTHIZ4))
137 
/* --- PIO4 Register ---*/
 137 
 
138 
/* PIO4 register clear mask */
 138 
/* --- PIO4 Register ---*/
139 
#define PIO4_CLEAR_MASK   ((uint32_t)(FSMC_PIO4_IOSET4  | FSMC_PIO4_IOWAIT4 | \
 139 
/* PIO4 register clear mask */
140 
                                      FSMC_PIO4_IOHOLD4 | FSMC_PIO4_IOHIZ4))
 140 
#define PIO4_CLEAR_MASK   ((uint32_t)(FSMC_PIO4_IOSET4  | FSMC_PIO4_IOWAIT4 | \
141 
 
 141 
                                      FSMC_PIO4_IOHOLD4 | FSMC_PIO4_IOHIZ4))
142 
#endif /* FSMC_BANK4 */
 142 
 
143 
 
 143 
#endif /* FSMC_BANK4 */
144 
/**
 144 
 
145 
  * @}
 145 
/**
146 
  */
 146 
  * @}
147 
 
 147 
  */
148 
/* Private macro -------------------------------------------------------------*/
 148 
 
149 
/* Private variables ---------------------------------------------------------*/
 149 
/* Private macro -------------------------------------------------------------*/
150 
/* Private function prototypes -----------------------------------------------*/
 150 
/* Private variables ---------------------------------------------------------*/
151 
/* Exported functions --------------------------------------------------------*/
 151 
/* Private function prototypes -----------------------------------------------*/
152 
 
 152 
/* Exported functions --------------------------------------------------------*/
153 
/** @defgroup FSMC_LL_Exported_Functions FSMC Low Layer Exported Functions
 153 
 
154 
  * @{
 154 
/** @defgroup FSMC_LL_Exported_Functions FSMC Low Layer Exported Functions
155 
  */
 155 
  * @{
156 
 
 156 
  */
157 
#if defined(FSMC_BANK1)
 157 
 
158 
 
 158 
#if defined(FSMC_BANK1)
159 
/** @defgroup FSMC_LL_Exported_Functions_NORSRAM FSMC Low Layer NOR SRAM Exported Functions
 159 
 
160 
  * @brief  NORSRAM Controller functions
 160 
/** @defgroup FSMC_LL_Exported_Functions_NORSRAM FSMC Low Layer NOR SRAM Exported Functions
161 
  *
 161 
  * @brief  NORSRAM Controller functions
162 
  @verbatim
 162 
  *
163 
  ==============================================================================
 163 
  @verbatim
164 
                   ##### How to use NORSRAM device driver #####
 164 
  ==============================================================================
165 
  ==============================================================================
 165 
                   ##### How to use NORSRAM device driver #####
166 
 
 166 
  ==============================================================================
167 
  [..]
 167 
 
168 
    This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order
 168 
  [..]
169 
    to run the NORSRAM external devices.
 169 
    This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order
170 
 
 170 
    to run the NORSRAM external devices.
171 
    (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit()
 171 
 
172 
    (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init()
 172 
    (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit()
173 
    (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init()
 173 
    (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init()
174 
    (+) FSMC NORSRAM bank extended timing configuration using the function
 174 
    (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init()
175 
        FSMC_NORSRAM_Extended_Timing_Init()
 175 
    (+) FSMC NORSRAM bank extended timing configuration using the function
176 
    (+) FSMC NORSRAM bank enable/disable write operation using the functions
 176 
        FSMC_NORSRAM_Extended_Timing_Init()
177 
        FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable()
 177 
    (+) FSMC NORSRAM bank enable/disable write operation using the functions
178 
 
 178 
        FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable()
179 
@endverbatim
 179 
 
180 
  * @{
 180 
@endverbatim
181 
  */
 181 
  * @{
182 
 
 182 
  */
183 
/** @defgroup FSMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
 183 
 
184 
  * @brief    Initialization and Configuration functions
 184 
/** @defgroup FSMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
185 
  *
 185 
  * @brief    Initialization and Configuration functions
186 
  @verbatim
 186 
  *
187 
  ==============================================================================
 187 
  @verbatim
188 
              ##### Initialization and de_initialization functions #####
 188 
  ==============================================================================
189 
  ==============================================================================
 189 
              ##### Initialization and de_initialization functions #####
190 
  [..]
 190 
  ==============================================================================
191 
    This section provides functions allowing to:
 191 
  [..]
192 
    (+) Initialize and configure the FSMC NORSRAM interface
 192 
    This section provides functions allowing to:
193 
    (+) De-initialize the FSMC NORSRAM interface
 193 
    (+) Initialize and configure the FSMC NORSRAM interface
194 
    (+) Configure the FSMC clock and associated GPIOs
 194 
    (+) De-initialize the FSMC NORSRAM interface
195 
 
 195 
    (+) Configure the FSMC clock and associated GPIOs
196 
@endverbatim
 196 
 
197 
  * @{
 197 
@endverbatim
198 
  */
 198 
  * @{
199 
 
 199 
  */
200 
/**
 200 
 
201 
  * @brief  Initialize the FSMC_NORSRAM device according to the specified
 201 
/**
202 
  *         control parameters in the FSMC_NORSRAM_InitTypeDef
 202 
  * @brief  Initialize the FSMC_NORSRAM device according to the specified
203 
  * @param  Device Pointer to NORSRAM device instance
 203 
  *         control parameters in the FSMC_NORSRAM_InitTypeDef
204 
  * @param  Init Pointer to NORSRAM Initialization structure
 204 
  * @param  Device Pointer to NORSRAM device instance
205 
  * @retval HAL status
 205 
  * @param  Init Pointer to NORSRAM Initialization structure
206 
  */
 206 
  * @retval HAL status
207 
HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device,
 207 
  */
208 
                                    FSMC_NORSRAM_InitTypeDef *Init)
 208 
HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device,
209 
{
 209 
                                    FSMC_NORSRAM_InitTypeDef *Init)
210 
  uint32_t flashaccess;
 210 
{
211 
  uint32_t btcr_reg;
 211 
  uint32_t flashaccess;
212 
  uint32_t mask;
 212 
  uint32_t btcr_reg;
213 
 
 213 
  uint32_t mask;
214 
  /* Check the parameters */
 214 
 
215 
  assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
 215 
  /* Check the parameters */
216 
  assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
 216 
  assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
217 
  assert_param(IS_FSMC_MUX(Init->DataAddressMux));
 217 
  assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
218 
  assert_param(IS_FSMC_MEMORY(Init->MemoryType));
 218 
  assert_param(IS_FSMC_MUX(Init->DataAddressMux));
219 
  assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
 219 
  assert_param(IS_FSMC_MEMORY(Init->MemoryType));
220 
  assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
 220 
  assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
221 
  assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
 221 
  assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
222 
  assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
 222 
  assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
223 
  assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
 223 
  assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
224 
  assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
 224 
  assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
225 
  assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
 225 
  assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
226 
  assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
 226 
  assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
227 
  assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
 227 
  assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
228 
  assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
 228 
  assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
229 
  assert_param(IS_FSMC_PAGESIZE(Init->PageSize));
 229 
  assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
230 
 
 230 
  assert_param(IS_FSMC_PAGESIZE(Init->PageSize));
231 
  /* Disable NORSRAM Device */
 231 
 
232 
  __FSMC_NORSRAM_DISABLE(Device, Init->NSBank);
 232 
  /* Disable NORSRAM Device */
233 
 
 233 
  __FSMC_NORSRAM_DISABLE(Device, Init->NSBank);
234 
  /* Set NORSRAM device control parameters */
 234 
 
235 
  if (Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
 235 
  /* Set NORSRAM device control parameters */
236 
  {
 236 
  if (Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
237 
    flashaccess = FSMC_NORSRAM_FLASH_ACCESS_ENABLE;
 237 
  {
238 
  }
 238 
    flashaccess = FSMC_NORSRAM_FLASH_ACCESS_ENABLE;
239 
  else
 239 
  }
240 
  {
 240 
  else
241 
    flashaccess = FSMC_NORSRAM_FLASH_ACCESS_DISABLE;
 241 
  {
242 
  }
 242 
    flashaccess = FSMC_NORSRAM_FLASH_ACCESS_DISABLE;
243 
 
 243 
  }
244 
  btcr_reg = (flashaccess                   | \
 244 
 
245 
              Init->DataAddressMux          | \
 245 
  btcr_reg = (flashaccess                   | \
246 
              Init->MemoryType              | \
 246 
              Init->DataAddressMux          | \
247 
              Init->MemoryDataWidth         | \
 247 
              Init->MemoryType              | \
248 
              Init->BurstAccessMode         | \
 248 
              Init->MemoryDataWidth         | \
249 
              Init->WaitSignalPolarity      | \
 249 
              Init->BurstAccessMode         | \
250 
              Init->WaitSignalActive        | \
 250 
              Init->WaitSignalPolarity      | \
251 
              Init->WriteOperation          | \
 251 
              Init->WaitSignalActive        | \
252 
              Init->WaitSignal              | \
 252 
              Init->WriteOperation          | \
253 
              Init->ExtendedMode            | \
 253 
              Init->WaitSignal              | \
254 
              Init->AsynchronousWait        | \
 254 
              Init->ExtendedMode            | \
255 
              Init->WriteBurst);
 255 
              Init->AsynchronousWait        | \
256 
 
 256 
              Init->WriteBurst);
257 
  btcr_reg |= Init->WrapMode;
 257 
 
258 
  btcr_reg |= Init->PageSize;
 258 
  btcr_reg |= Init->WrapMode;
259 
 
 259 
  btcr_reg |= Init->PageSize;
260 
  mask = (FSMC_BCRx_MBKEN                |
 260 
 
261 
          FSMC_BCRx_MUXEN                |
 261 
  mask = (FSMC_BCRx_MBKEN                |
262 
          FSMC_BCRx_MTYP                 |
 262 
          FSMC_BCRx_MUXEN                |
263 
          FSMC_BCRx_MWID                 |
 263 
          FSMC_BCRx_MTYP                 |
264 
          FSMC_BCRx_FACCEN               |
 264 
          FSMC_BCRx_MWID                 |
265 
          FSMC_BCRx_BURSTEN              |
 265 
          FSMC_BCRx_FACCEN               |
266 
          FSMC_BCRx_WAITPOL              |
 266 
          FSMC_BCRx_BURSTEN              |
267 
          FSMC_BCRx_WAITCFG              |
 267 
          FSMC_BCRx_WAITPOL              |
268 
          FSMC_BCRx_WREN                 |
 268 
          FSMC_BCRx_WAITCFG              |
269 
          FSMC_BCRx_WAITEN               |
 269 
          FSMC_BCRx_WREN                 |
270 
          FSMC_BCRx_EXTMOD               |
 270 
          FSMC_BCRx_WAITEN               |
271 
          FSMC_BCRx_ASYNCWAIT            |
 271 
          FSMC_BCRx_EXTMOD               |
272 
          FSMC_BCRx_CBURSTRW);
 272 
          FSMC_BCRx_ASYNCWAIT            |
273 
 
 273 
          FSMC_BCRx_CBURSTRW);
274 
  mask |= FSMC_BCRx_WRAPMOD;
 274 
 
275 
  mask |= 0x00070000U; /* CPSIZE to be defined in CMSIS file */
 275 
  mask |= FSMC_BCRx_WRAPMOD;
276 
 
 276 
  mask |= 0x00070000U; /* CPSIZE to be defined in CMSIS file */
277 
  MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);
 277 
 
278 
 
 278 
  MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);
279 
 
 279 
 
280 
  return HAL_OK;
 280 
 
281 
}
 281 
  return HAL_OK;
282 
 
 282 
}
283 
/**
 283 
 
284 
  * @brief  DeInitialize the FSMC_NORSRAM peripheral
 284 
/**
285 
  * @param  Device Pointer to NORSRAM device instance
 285 
  * @brief  DeInitialize the FSMC_NORSRAM peripheral
286 
  * @param  ExDevice Pointer to NORSRAM extended mode device instance
 286 
  * @param  Device Pointer to NORSRAM device instance
287 
  * @param  Bank NORSRAM bank number
 287 
  * @param  ExDevice Pointer to NORSRAM extended mode device instance
288 
  * @retval HAL status
 288 
  * @param  Bank NORSRAM bank number
289 
  */
 289 
  * @retval HAL status
290 
HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device,
 290 
  */
291 
                                     FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
 291 
HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device,
292 
{
 292 
                                     FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
293 
  /* Check the parameters */
 293 
{
294 
  assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
 294 
  /* Check the parameters */
295 
  assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
 295 
  assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
296 
  assert_param(IS_FSMC_NORSRAM_BANK(Bank));
 296 
  assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
297 
 
 297 
  assert_param(IS_FSMC_NORSRAM_BANK(Bank));
298 
  /* Disable the FSMC_NORSRAM device */
 298 
 
299 
  __FSMC_NORSRAM_DISABLE(Device, Bank);
 299 
  /* Disable the FSMC_NORSRAM device */
300 
 
 300 
  __FSMC_NORSRAM_DISABLE(Device, Bank);
301 
  /* De-initialize the FSMC_NORSRAM device */
 301 
 
302 
  /* FSMC_NORSRAM_BANK1 */
 302 
  /* De-initialize the FSMC_NORSRAM device */
303 
  if (Bank == FSMC_NORSRAM_BANK1)
 303 
  /* FSMC_NORSRAM_BANK1 */
304 
  {
 304 
  if (Bank == FSMC_NORSRAM_BANK1)
305 
    Device->BTCR[Bank] = 0x000030DBU;
 305 
  {
306 
  }
 306 
    Device->BTCR[Bank] = 0x000030DBU;
307 
  /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */
 307 
  }
308 
  else
 308 
  /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */
309 
  {
 309 
  else
310 
    Device->BTCR[Bank] = 0x000030D2U;
 310 
  {
311 
  }
 311 
    Device->BTCR[Bank] = 0x000030D2U;
312 
 
 312 
  }
313 
  Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
 313 
 
314 
  ExDevice->BWTR[Bank]   = 0x0FFFFFFFU;
 314 
  Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
315 
 
 315 
  ExDevice->BWTR[Bank]   = 0x0FFFFFFFU;
316 
  return HAL_OK;
 316 
 
317 
}
 317 
  return HAL_OK;
318 
 
 318 
}
319 
/**
 319 
 
320 
  * @brief  Initialize the FSMC_NORSRAM Timing according to the specified
 320 
/**
321 
  *         parameters in the FSMC_NORSRAM_TimingTypeDef
 321 
  * @brief  Initialize the FSMC_NORSRAM Timing according to the specified
322 
  * @param  Device Pointer to NORSRAM device instance
 322 
  *         parameters in the FSMC_NORSRAM_TimingTypeDef
323 
  * @param  Timing Pointer to NORSRAM Timing structure
 323 
  * @param  Device Pointer to NORSRAM device instance
324 
  * @param  Bank NORSRAM bank number
 324 
  * @param  Timing Pointer to NORSRAM Timing structure
325 
  * @retval HAL status
 325 
  * @param  Bank NORSRAM bank number
326 
  */
 326 
  * @retval HAL status
327 
HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device,
 327 
  */
328 
                                          FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
 328 
HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device,
329 
{
 329 
                                          FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
330 
 
 330 
{
331 
  /* Check the parameters */
 331 
 
332 
  assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
 332 
  /* Check the parameters */
333 
  assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
 333 
  assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
334 
  assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
 334 
  assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
335 
  assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
 335 
  assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
336 
  assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
 336 
  assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
337 
  assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
 337 
  assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
338 
  assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
 338 
  assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
339 
  assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
 339 
  assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
340 
  assert_param(IS_FSMC_NORSRAM_BANK(Bank));
 340 
  assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
341 
 
 341 
  assert_param(IS_FSMC_NORSRAM_BANK(Bank));
342 
  /* Set FSMC_NORSRAM device timing parameters */
 342 
 
343 
  MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime                                  |
 343 
  /* Set FSMC_NORSRAM device timing parameters */
344 
                                                       ((Timing->AddressHoldTime)        << FSMC_BTRx_ADDHLD_Pos)  |
 344 
  MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime                                  |
345 
                                                       ((Timing->DataSetupTime)          << FSMC_BTRx_DATAST_Pos)  |
 345 
                                                       ((Timing->AddressHoldTime)        << FSMC_BTRx_ADDHLD_Pos)  |
346 
                                                       ((Timing->BusTurnAroundDuration)  << FSMC_BTRx_BUSTURN_Pos) |
 346 
                                                       ((Timing->DataSetupTime)          << FSMC_BTRx_DATAST_Pos)  |
347 
                                                       (((Timing->CLKDivision) - 1U)     << FSMC_BTRx_CLKDIV_Pos)  |
 347 
                                                       ((Timing->BusTurnAroundDuration)  << FSMC_BTRx_BUSTURN_Pos) |
348 
                                                       (((Timing->DataLatency) - 2U)     << FSMC_BTRx_DATLAT_Pos)  |
 348 
                                                       (((Timing->CLKDivision) - 1U)     << FSMC_BTRx_CLKDIV_Pos)  |
349 
                                                       (Timing->AccessMode)));
 349 
                                                       (((Timing->DataLatency) - 2U)     << FSMC_BTRx_DATLAT_Pos)  |
350 
 
 350 
                                                       (Timing->AccessMode)));
351 
  return HAL_OK;
 351 
 
352 
}
 352 
  return HAL_OK;
353 
 
 353 
}
354 
/**
 354 
 
355 
  * @brief  Initialize the FSMC_NORSRAM Extended mode Timing according to the specified
 355 
/**
356 
  *         parameters in the FSMC_NORSRAM_TimingTypeDef
 356 
  * @brief  Initialize the FSMC_NORSRAM Extended mode Timing according to the specified
357 
  * @param  Device Pointer to NORSRAM device instance
 357 
  *         parameters in the FSMC_NORSRAM_TimingTypeDef
358 
  * @param  Timing Pointer to NORSRAM Timing structure
 358 
  * @param  Device Pointer to NORSRAM device instance
359 
  * @param  Bank NORSRAM bank number
 359 
  * @param  Timing Pointer to NORSRAM Timing structure
360 
  * @param  ExtendedMode FSMC Extended Mode
 360 
  * @param  Bank NORSRAM bank number
361 
  *          This parameter can be one of the following values:
 361 
  * @param  ExtendedMode FSMC Extended Mode
362 
  *            @arg FSMC_EXTENDED_MODE_DISABLE
 362 
  *          This parameter can be one of the following values:
363 
  *            @arg FSMC_EXTENDED_MODE_ENABLE
 363 
  *            @arg FSMC_EXTENDED_MODE_DISABLE
364 
  * @retval HAL status
 364 
  *            @arg FSMC_EXTENDED_MODE_ENABLE
365 
  */
 365 
  * @retval HAL status
366 
HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device,
 366 
  */
367 
                                                   FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
 367 
HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device,
368 
                                                   uint32_t ExtendedMode)
 368 
                                                   FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
369 
{
 369 
                                                   uint32_t ExtendedMode)
370 
  /* Check the parameters */
 370 
{
371 
  assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode));
 371 
  /* Check the parameters */
372 
 
 372 
  assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode));
373 
  /* Set NORSRAM device timing register for write configuration, if extended mode is used */
 373 
 
374 
  if (ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
 374 
  /* Set NORSRAM device timing register for write configuration, if extended mode is used */
375 
  {
 375 
  if (ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
376 
    /* Check the parameters */
 376 
  {
377 
    assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device));
 377 
    /* Check the parameters */
378 
    assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
 378 
    assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device));
379 
    assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
 379 
    assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
380 
    assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
 380 
    assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
381 
#if defined(FSMC_BWTRx_BUSTURN)
 381 
    assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
382 
    assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
 382 
#if defined(FSMC_BWTRx_BUSTURN)
383 
#else
 383 
    assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
384 
    assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
 384 
#else
385 
    assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
 385 
    assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
386 
#endif /* FSMC_BWTRx_BUSTURN */
 386 
    assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
387 
    assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
 387 
#endif /* FSMC_BWTRx_BUSTURN */
388 
    assert_param(IS_FSMC_NORSRAM_BANK(Bank));
 388 
    assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
389 
 
 389 
    assert_param(IS_FSMC_NORSRAM_BANK(Bank));
390 
    /* Set NORSRAM device timing register for write configuration, if extended mode is used */
 390 
 
391 
#if defined(FSMC_BWTRx_BUSTURN)
 391 
    /* Set NORSRAM device timing register for write configuration, if extended mode is used */
392 
    MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                                    |
 392 
#if defined(FSMC_BWTRx_BUSTURN)
393 
                                                     ((Timing->AddressHoldTime)        << FSMC_BWTRx_ADDHLD_Pos)  |
 393 
    MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                                    |
394 
                                                     ((Timing->DataSetupTime)          << FSMC_BWTRx_DATAST_Pos)  |
 394 
                                                     ((Timing->AddressHoldTime)        << FSMC_BWTRx_ADDHLD_Pos)  |
395 
                                                     Timing->AccessMode                                          |
 395 
                                                     ((Timing->DataSetupTime)          << FSMC_BWTRx_DATAST_Pos)  |
396 
                                                     ((Timing->BusTurnAroundDuration)  << FSMC_BWTRx_BUSTURN_Pos)));
 396 
                                                     Timing->AccessMode                                          |
397 
#else
 397 
                                                     ((Timing->BusTurnAroundDuration)  << FSMC_BWTRx_BUSTURN_Pos)));
398 
    MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                                    |
 398 
#else
399 
                                                     ((Timing->AddressHoldTime)        << FSMC_BWTRx_ADDHLD_Pos)  |
 399 
    MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                                    |
400 
                                                     ((Timing->DataSetupTime)          << FSMC_BWTRx_DATAST_Pos)  |
 400 
                                                     ((Timing->AddressHoldTime)        << FSMC_BWTRx_ADDHLD_Pos)  |
401 
                                                     Timing->AccessMode                                          |
 401 
                                                     ((Timing->DataSetupTime)          << FSMC_BWTRx_DATAST_Pos)  |
402 
                                                     (((Timing->CLKDivision) - 1U)     << FSMC_BWTRx_CLKDIV_Pos)  |
 402 
                                                     Timing->AccessMode                                          |
403 
                                                     (((Timing->DataLatency) - 2U)     << FSMC_BWTRx_DATLAT_Pos)));
 403 
                                                     (((Timing->CLKDivision) - 1U)     << FSMC_BWTRx_CLKDIV_Pos)  |
404 
#endif /* FSMC_BWTRx_BUSTURN */
 404 
                                                     (((Timing->DataLatency) - 2U)     << FSMC_BWTRx_DATLAT_Pos)));
405 
  }
 405 
#endif /* FSMC_BWTRx_BUSTURN */
406 
  else
 406 
  }
407 
  {
 407 
  else
408 
    Device->BWTR[Bank] = 0x0FFFFFFFU;
 408 
  {
409 
  }
 409 
    Device->BWTR[Bank] = 0x0FFFFFFFU;
410 
 
 410 
  }
411 
  return HAL_OK;
 411 
 
412 
}
 412 
  return HAL_OK;
413 
/**
 413 
}
414 
  * @}
 414 
/**
415 
  */
 415 
  * @}
416 
 
 416 
  */
417 
/** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group2
 417 
 
418 
  *  @brief   management functions
 418 
/** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group2
419 
  *
 419 
  *  @brief   management functions
420 
@verbatim
 420 
  *
421 
  ==============================================================================
 421 
@verbatim
422 
                      ##### FSMC_NORSRAM Control functions #####
 422 
  ==============================================================================
423 
  ==============================================================================
 423 
                      ##### FSMC_NORSRAM Control functions #####
424 
  [..]
 424 
  ==============================================================================
425 
    This subsection provides a set of functions allowing to control dynamically
 425 
  [..]
426 
    the FSMC NORSRAM interface.
 426 
    This subsection provides a set of functions allowing to control dynamically
427 
 
 427 
    the FSMC NORSRAM interface.
428 
@endverbatim
 428 
 
429 
  * @{
 429 
@endverbatim
430 
  */
 430 
  * @{
431 
 
 431 
  */
432 
/**
 432 
 
433 
  * @brief  Enables dynamically FSMC_NORSRAM write operation.
 433 
/**
434 
  * @param  Device Pointer to NORSRAM device instance
 434 
  * @brief  Enables dynamically FSMC_NORSRAM write operation.
435 
  * @param  Bank NORSRAM bank number
 435 
  * @param  Device Pointer to NORSRAM device instance
436 
  * @retval HAL status
 436 
  * @param  Bank NORSRAM bank number
437 
  */
 437 
  * @retval HAL status
438 
HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
 438 
  */
439 
{
 439 
HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
440 
  /* Check the parameters */
 440 
{
441 
  assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
 441 
  /* Check the parameters */
442 
  assert_param(IS_FSMC_NORSRAM_BANK(Bank));
 442 
  assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
443 
 
 443 
  assert_param(IS_FSMC_NORSRAM_BANK(Bank));
444 
  /* Enable write operation */
 444 
 
445 
  SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
 445 
  /* Enable write operation */
446 
 
 446 
  SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
447 
  return HAL_OK;
 447 
 
448 
}
 448 
  return HAL_OK;
449 
 
 449 
}
450 
/**
 450 
 
451 
  * @brief  Disables dynamically FSMC_NORSRAM write operation.
 451 
/**
452 
  * @param  Device Pointer to NORSRAM device instance
 452 
  * @brief  Disables dynamically FSMC_NORSRAM write operation.
453 
  * @param  Bank NORSRAM bank number
 453 
  * @param  Device Pointer to NORSRAM device instance
454 
  * @retval HAL status
 454 
  * @param  Bank NORSRAM bank number
455 
  */
 455 
  * @retval HAL status
456 
HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
 456 
  */
457 
{
 457 
HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
458 
  /* Check the parameters */
 458 
{
459 
  assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
 459 
  /* Check the parameters */
460 
  assert_param(IS_FSMC_NORSRAM_BANK(Bank));
 460 
  assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
461 
 
 461 
  assert_param(IS_FSMC_NORSRAM_BANK(Bank));
462 
  /* Disable write operation */
 462 
 
463 
  CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
 463 
  /* Disable write operation */
464 
 
 464 
  CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
465 
  return HAL_OK;
 465 
 
466 
}
 466 
  return HAL_OK;
467 
 
 467 
}
468 
/**
 468 
 
469 
  * @}
 469 
/**
470 
  */
 470 
  * @}
471 
 
 471 
  */
472 
/**
 472 
 
473 
  * @}
 473 
/**
474 
  */
 474 
  * @}
475 
#endif /* FSMC_BANK1 */
 475 
  */
476 
 
 476 
#endif /* FSMC_BANK1 */
477 
#if defined(FSMC_BANK3)
 477 
 
478 
 
 478 
#if defined(FSMC_BANK3)
479 
/** @defgroup FSMC_LL_Exported_Functions_NAND FSMC Low Layer NAND Exported Functions
 479 
 
480 
  * @brief    NAND Controller functions
 480 
/** @defgroup FSMC_LL_Exported_Functions_NAND FSMC Low Layer NAND Exported Functions
481 
  *
 481 
  * @brief    NAND Controller functions
482 
  @verbatim
 482 
  *
483 
  ==============================================================================
 483 
  @verbatim
484 
                    ##### How to use NAND device driver #####
 484 
  ==============================================================================
485 
  ==============================================================================
 485 
                    ##### How to use NAND device driver #####
486 
  [..]
 486 
  ==============================================================================
487 
    This driver contains a set of APIs to interface with the FSMC NAND banks in order
 487 
  [..]
488 
    to run the NAND external devices.
 488 
    This driver contains a set of APIs to interface with the FSMC NAND banks in order
489 
 
 489 
    to run the NAND external devices.
490 
    (+) FSMC NAND bank reset using the function FSMC_NAND_DeInit()
 490 
 
491 
    (+) FSMC NAND bank control configuration using the function FSMC_NAND_Init()
 491 
    (+) FSMC NAND bank reset using the function FSMC_NAND_DeInit()
492 
    (+) FSMC NAND bank common space timing configuration using the function
 492 
    (+) FSMC NAND bank control configuration using the function FSMC_NAND_Init()
493 
        FSMC_NAND_CommonSpace_Timing_Init()
 493 
    (+) FSMC NAND bank common space timing configuration using the function
494 
    (+) FSMC NAND bank attribute space timing configuration using the function
 494 
        FSMC_NAND_CommonSpace_Timing_Init()
495 
        FSMC_NAND_AttributeSpace_Timing_Init()
 495 
    (+) FSMC NAND bank attribute space timing configuration using the function
496 
    (+) FSMC NAND bank enable/disable ECC correction feature using the functions
 496 
        FSMC_NAND_AttributeSpace_Timing_Init()
497 
        FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable()
 497 
    (+) FSMC NAND bank enable/disable ECC correction feature using the functions
498 
    (+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC()
 498 
        FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable()
499 
 
 499 
    (+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC()
500 
@endverbatim
 500 
 
501 
  * @{
 501 
@endverbatim
502 
  */
 502 
  * @{
503 
 
 503 
  */
504 
/** @defgroup FSMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
 504 
 
505 
  *  @brief    Initialization and Configuration functions
 505 
/** @defgroup FSMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
506 
  *
 506 
  *  @brief    Initialization and Configuration functions
507 
@verbatim
 507 
  *
508 
  ==============================================================================
 508 
@verbatim
509 
              ##### Initialization and de_initialization functions #####
 509 
  ==============================================================================
510 
  ==============================================================================
 510 
              ##### Initialization and de_initialization functions #####
511 
  [..]
 511 
  ==============================================================================
512 
    This section provides functions allowing to:
 512 
  [..]
513 
    (+) Initialize and configure the FSMC NAND interface
 513 
    This section provides functions allowing to:
514 
    (+) De-initialize the FSMC NAND interface
 514 
    (+) Initialize and configure the FSMC NAND interface
515 
    (+) Configure the FSMC clock and associated GPIOs
 515 
    (+) De-initialize the FSMC NAND interface
516 
 
 516 
    (+) Configure the FSMC clock and associated GPIOs
517 
@endverbatim
 517 
 
518 
  * @{
 518 
@endverbatim
519 
  */
 519 
  * @{
520 
 
 520 
  */
521 
/**
 521 
 
522 
  * @brief  Initializes the FSMC_NAND device according to the specified
 522 
/**
523 
  *         control parameters in the FSMC_NAND_HandleTypeDef
 523 
  * @brief  Initializes the FSMC_NAND device according to the specified
524 
  * @param  Device Pointer to NAND device instance
 524 
  *         control parameters in the FSMC_NAND_HandleTypeDef
525 
  * @param  Init Pointer to NAND Initialization structure
 525 
  * @param  Device Pointer to NAND device instance
526 
  * @retval HAL status
 526 
  * @param  Init Pointer to NAND Initialization structure
527 
  */
 527 
  * @retval HAL status
528 
HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init)
 528 
  */
529 
{
 529 
HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init)
530 
  /* Check the parameters */
 530 
{
531 
  assert_param(IS_FSMC_NAND_DEVICE(Device));
 531 
  /* Check the parameters */
532 
  assert_param(IS_FSMC_NAND_BANK(Init->NandBank));
 532 
  assert_param(IS_FSMC_NAND_DEVICE(Device));
533 
  assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
 533 
  assert_param(IS_FSMC_NAND_BANK(Init->NandBank));
534 
  assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
 534 
  assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
535 
  assert_param(IS_FSMC_ECC_STATE(Init->EccComputation));
 535 
  assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
536 
  assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize));
 536 
  assert_param(IS_FSMC_ECC_STATE(Init->EccComputation));
537 
  assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
 537 
  assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize));
538 
  assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
 538 
  assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
539 
 
 539 
  assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
540 
  /* Set NAND device control parameters */
 540 
 
541 
  if (Init->NandBank == FSMC_NAND_BANK2)
 541 
  /* Set NAND device control parameters */
542 
  {
 542 
  if (Init->NandBank == FSMC_NAND_BANK2)
543 
    /* NAND bank 2 registers configuration */
 543 
  {
544 
    MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature                                      |
 544 
    /* NAND bank 2 registers configuration */
545 
                                              FSMC_PCR_MEMORY_TYPE_NAND                               |
 545 
    MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature                                      |
546 
                                              Init->MemoryDataWidth                                  |
 546 
                                              FSMC_PCR_MEMORY_TYPE_NAND                               |
547 
                                              Init->EccComputation                                   |
 547 
                                              Init->MemoryDataWidth                                  |
548 
                                              Init->ECCPageSize                                      |
 548 
                                              Init->EccComputation                                   |
549 
                                              ((Init->TCLRSetupTime) << FSMC_PCRx_TCLR_Pos)  |
 549 
                                              Init->ECCPageSize                                      |
550 
                                              ((Init->TARSetupTime)  << FSMC_PCRx_TAR_Pos)));
 550 
                                              ((Init->TCLRSetupTime) << FSMC_PCRx_TCLR_Pos)  |
551 
  }
 551 
                                              ((Init->TARSetupTime)  << FSMC_PCRx_TAR_Pos)));
552 
  else
 552 
  }
553 
  {
 553 
  else
554 
    /* NAND bank 3 registers configuration */
 554 
  {
555 
    MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature                                      |
 555 
    /* NAND bank 3 registers configuration */
556 
                                              FSMC_PCR_MEMORY_TYPE_NAND                               |
 556 
    MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature                                      |
557 
                                              Init->MemoryDataWidth                                  |
 557 
                                              FSMC_PCR_MEMORY_TYPE_NAND                               |
558 
                                              Init->EccComputation                                   |
 558 
                                              Init->MemoryDataWidth                                  |
559 
                                              Init->ECCPageSize                                      |
 559 
                                              Init->EccComputation                                   |
560 
                                              ((Init->TCLRSetupTime) << FSMC_PCRx_TCLR_Pos)  |
 560 
                                              Init->ECCPageSize                                      |
561 
                                              ((Init->TARSetupTime)  << FSMC_PCRx_TAR_Pos)));
 561 
                                              ((Init->TCLRSetupTime) << FSMC_PCRx_TCLR_Pos)  |
562 
  }
 562 
                                              ((Init->TARSetupTime)  << FSMC_PCRx_TAR_Pos)));
563 
 
 563 
  }
564 
  return HAL_OK;
 564 
 
565 
}
 565 
  return HAL_OK;
566 
 
 566 
}
567 
/**
 567 
 
568 
  * @brief  Initializes the FSMC_NAND Common space Timing according to the specified
 568 
/**
569 
  *         parameters in the FSMC_NAND_PCC_TimingTypeDef
 569 
  * @brief  Initializes the FSMC_NAND Common space Timing according to the specified
570 
  * @param  Device Pointer to NAND device instance
 570 
  *         parameters in the FSMC_NAND_PCC_TimingTypeDef
571 
  * @param  Timing Pointer to NAND timing structure
 571 
  * @param  Device Pointer to NAND device instance
572 
  * @param  Bank NAND bank number
 572 
  * @param  Timing Pointer to NAND timing structure
573 
  * @retval HAL status
 573 
  * @param  Bank NAND bank number
574 
  */
 574 
  * @retval HAL status
575 
HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
 575 
  */
576 
                                                   FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
 576 
HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
577 
{
 577 
                                                   FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
578 
  /* Check the parameters */
 578 
{
579 
  assert_param(IS_FSMC_NAND_DEVICE(Device));
 579 
  /* Check the parameters */
580 
  assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
 580 
  assert_param(IS_FSMC_NAND_DEVICE(Device));
581 
  assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
 581 
  assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
582 
  assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
 582 
  assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
583 
  assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
 583 
  assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
584 
  assert_param(IS_FSMC_NAND_BANK(Bank));
 584 
  assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
585 
 
 585 
  assert_param(IS_FSMC_NAND_BANK(Bank));
586 
  /* Set FSMC_NAND device timing parameters */
 586 
 
587 
  if (Bank == FSMC_NAND_BANK2)
 587 
  /* Set FSMC_NAND device timing parameters */
588 
  {
 588 
  if (Bank == FSMC_NAND_BANK2)
589 
    /* NAND bank 2 registers configuration */
 589 
  {
590 
    MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime                                             |
 590 
    /* NAND bank 2 registers configuration */
591 
                                                ((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos) |
 591 
    MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime                                             |
592 
                                                ((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos) |
 592 
                                                ((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos) |
593 
                                                ((Timing->HiZSetupTime)  << FSMC_PMEMx_MEMHIZx_Pos)));
 593 
                                                ((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos) |
594 
  }
 594 
                                                ((Timing->HiZSetupTime)  << FSMC_PMEMx_MEMHIZx_Pos)));
595 
  else
 595 
  }
596 
  {
 596 
  else
597 
    /* NAND bank 3 registers configuration */
 597 
  {
598 
    MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime                                             |
 598 
    /* NAND bank 3 registers configuration */
599 
                                                ((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos) |
 599 
    MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime                                             |
600 
                                                ((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos) |
 600 
                                                ((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos) |
601 
                                                ((Timing->HiZSetupTime)  << FSMC_PMEMx_MEMHIZx_Pos)));
 601 
                                                ((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos) |
602 
  }
 602 
                                                ((Timing->HiZSetupTime)  << FSMC_PMEMx_MEMHIZx_Pos)));
603 
 
 603 
  }
604 
  return HAL_OK;
 604 
 
605 
}
 605 
  return HAL_OK;
606 
 
 606 
}
607 
/**
 607 
 
608 
  * @brief  Initializes the FSMC_NAND Attribute space Timing according to the specified
 608 
/**
609 
  *         parameters in the FSMC_NAND_PCC_TimingTypeDef
 609 
  * @brief  Initializes the FSMC_NAND Attribute space Timing according to the specified
610 
  * @param  Device Pointer to NAND device instance
 610 
  *         parameters in the FSMC_NAND_PCC_TimingTypeDef
611 
  * @param  Timing Pointer to NAND timing structure
 611 
  * @param  Device Pointer to NAND device instance
612 
  * @param  Bank NAND bank number
 612 
  * @param  Timing Pointer to NAND timing structure
613 
  * @retval HAL status
 613 
  * @param  Bank NAND bank number
614 
  */
 614 
  * @retval HAL status
615 
HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
 615 
  */
616 
                                                      FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
 616 
HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
617 
{
 617 
                                                      FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
618 
  /* Check the parameters */
 618 
{
619 
  assert_param(IS_FSMC_NAND_DEVICE(Device));
 619 
  /* Check the parameters */
620 
  assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
 620 
  assert_param(IS_FSMC_NAND_DEVICE(Device));
621 
  assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
 621 
  assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
622 
  assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
 622 
  assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
623 
  assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
 623 
  assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
624 
  assert_param(IS_FSMC_NAND_BANK(Bank));
 624 
  assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
625 
 
 625 
  assert_param(IS_FSMC_NAND_BANK(Bank));
626 
  /* Set FSMC_NAND device timing parameters */
 626 
 
627 
  if (Bank == FSMC_NAND_BANK2)
 627 
  /* Set FSMC_NAND device timing parameters */
628 
  {
 628 
  if (Bank == FSMC_NAND_BANK2)
629 
    /* NAND bank 2 registers configuration */
 629 
  {
630 
    MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime                                             |
 630 
    /* NAND bank 2 registers configuration */
631 
                                                ((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos) |
 631 
    MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime                                             |
632 
                                                ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos) |
 632 
                                                ((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos) |
633 
                                                ((Timing->HiZSetupTime)  << FSMC_PATTx_ATTHIZx_Pos)));
 633 
                                                ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos) |
634 
  }
 634 
                                                ((Timing->HiZSetupTime)  << FSMC_PATTx_ATTHIZx_Pos)));
635 
  else
 635 
  }
636 
  {
 636 
  else
637 
    /* NAND bank 3 registers configuration */
 637 
  {
638 
    MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime                                             |
 638 
    /* NAND bank 3 registers configuration */
639 
                                                ((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos) |
 639 
    MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime                                             |
640 
                                                ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos) |
 640 
                                                ((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos) |
641 
                                                ((Timing->HiZSetupTime)  << FSMC_PATTx_ATTHIZx_Pos)));
 641 
                                                ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos) |
642 
  }
 642 
                                                ((Timing->HiZSetupTime)  << FSMC_PATTx_ATTHIZx_Pos)));
643 
 
 643 
  }
644 
  return HAL_OK;
 644 
 
645 
}
 645 
  return HAL_OK;
646 
 
 646 
}
647 
/**
 647 
 
648 
  * @brief  DeInitializes the FSMC_NAND device
 648 
/**
649 
  * @param  Device Pointer to NAND device instance
 649 
  * @brief  DeInitializes the FSMC_NAND device
650 
  * @param  Bank NAND bank number
 650 
  * @param  Device Pointer to NAND device instance
651 
  * @retval HAL status
 651 
  * @param  Bank NAND bank number
652 
  */
 652 
  * @retval HAL status
653 
HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
 653 
  */
654 
{
 654 
HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
655 
  /* Check the parameters */
 655 
{
656 
  assert_param(IS_FSMC_NAND_DEVICE(Device));
 656 
  /* Check the parameters */
657 
  assert_param(IS_FSMC_NAND_BANK(Bank));
 657 
  assert_param(IS_FSMC_NAND_DEVICE(Device));
658 
 
 658 
  assert_param(IS_FSMC_NAND_BANK(Bank));
659 
  /* Disable the NAND Bank */
 659 
 
660 
  __FSMC_NAND_DISABLE(Device, Bank);
 660 
  /* Disable the NAND Bank */
661 
 
 661 
  __FSMC_NAND_DISABLE(Device, Bank);
662 
  /* De-initialize the NAND Bank */
 662 
 
663 
  if (Bank == FSMC_NAND_BANK2)
 663 
  /* De-initialize the NAND Bank */
664 
  {
 664 
  if (Bank == FSMC_NAND_BANK2)
665 
    /* Set the FSMC_NAND_BANK2 registers to their reset values */
 665 
  {
666 
    WRITE_REG(Device->PCR2,  0x00000018U);
 666 
    /* Set the FSMC_NAND_BANK2 registers to their reset values */
667 
    WRITE_REG(Device->SR2,   0x00000040U);
 667 
    WRITE_REG(Device->PCR2,  0x00000018U);
668 
    WRITE_REG(Device->PMEM2, 0xFCFCFCFCU);
 668 
    WRITE_REG(Device->SR2,   0x00000040U);
669 
    WRITE_REG(Device->PATT2, 0xFCFCFCFCU);
 669 
    WRITE_REG(Device->PMEM2, 0xFCFCFCFCU);
670 
  }
 670 
    WRITE_REG(Device->PATT2, 0xFCFCFCFCU);
671 
  /* FSMC_Bank3_NAND */
 671 
  }
672 
  else
 672 
  /* FSMC_Bank3_NAND */
673 
  {
 673 
  else
674 
    /* Set the FSMC_NAND_BANK3 registers to their reset values */
 674 
  {
675 
    WRITE_REG(Device->PCR3,  0x00000018U);
 675 
    /* Set the FSMC_NAND_BANK3 registers to their reset values */
676 
    WRITE_REG(Device->SR3,   0x00000040U);
 676 
    WRITE_REG(Device->PCR3,  0x00000018U);
677 
    WRITE_REG(Device->PMEM3, 0xFCFCFCFCU);
 677 
    WRITE_REG(Device->SR3,   0x00000040U);
678 
    WRITE_REG(Device->PATT3, 0xFCFCFCFCU);
 678 
    WRITE_REG(Device->PMEM3, 0xFCFCFCFCU);
679 
  }
 679 
    WRITE_REG(Device->PATT3, 0xFCFCFCFCU);
680 
 
 680 
  }
681 
  return HAL_OK;
 681 
 
682 
}
 682 
  return HAL_OK;
683 
 
 683 
}
684 
/**
 684 
 
685 
  * @}
 685 
/**
686 
  */
 686 
  * @}
687 
 
 687 
  */
688 
/** @defgroup HAL_FSMC_NAND_Group2 Peripheral Control functions
 688 
 
689 
  *  @brief   management functions
 689 
/** @defgroup HAL_FSMC_NAND_Group2 Peripheral Control functions
690 
  *
 690 
  *  @brief   management functions
691 
@verbatim
 691 
  *
692 
  ==============================================================================
 692 
@verbatim
693 
                       ##### FSMC_NAND Control functions #####
 693 
  ==============================================================================
694 
  ==============================================================================
 694 
                       ##### FSMC_NAND Control functions #####
695 
  [..]
 695 
  ==============================================================================
696 
    This subsection provides a set of functions allowing to control dynamically
 696 
  [..]
697 
    the FSMC NAND interface.
 697 
    This subsection provides a set of functions allowing to control dynamically
698 
 
 698 
    the FSMC NAND interface.
699 
@endverbatim
 699 
 
700 
  * @{
 700 
@endverbatim
701 
  */
 701 
  * @{
702 
 
 702 
  */
703 
 
 703 
 
704 
/**
 704 
 
705 
  * @brief  Enables dynamically FSMC_NAND ECC feature.
 705 
/**
706 
  * @param  Device Pointer to NAND device instance
 706 
  * @brief  Enables dynamically FSMC_NAND ECC feature.
707 
  * @param  Bank NAND bank number
 707 
  * @param  Device Pointer to NAND device instance
708 
  * @retval HAL status
 708 
  * @param  Bank NAND bank number
709 
  */
 709 
  * @retval HAL status
710 
HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
 710 
  */
711 
{
 711 
HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
712 
  /* Check the parameters */
 712 
{
713 
  assert_param(IS_FSMC_NAND_DEVICE(Device));
 713 
  /* Check the parameters */
714 
  assert_param(IS_FSMC_NAND_BANK(Bank));
 714 
  assert_param(IS_FSMC_NAND_DEVICE(Device));
715 
 
 715 
  assert_param(IS_FSMC_NAND_BANK(Bank));
716 
  /* Enable ECC feature */
 716 
 
717 
  if (Bank == FSMC_NAND_BANK2)
 717 
  /* Enable ECC feature */
718 
  {
 718 
  if (Bank == FSMC_NAND_BANK2)
719 
    SET_BIT(Device->PCR2, FSMC_PCRx_ECCEN);
 719 
  {
720 
  }
 720 
    SET_BIT(Device->PCR2, FSMC_PCRx_ECCEN);
721 
  else
 721 
  }
722 
  {
 722 
  else
723 
    SET_BIT(Device->PCR3, FSMC_PCRx_ECCEN);
 723 
  {
724 
  }
 724 
    SET_BIT(Device->PCR3, FSMC_PCRx_ECCEN);
725 
 
 725 
  }
726 
  return HAL_OK;
 726 
 
727 
}
 727 
  return HAL_OK;
728 
 
 728 
}
729 
 
 729 
 
730 
/**
 730 
 
731 
  * @brief  Disables dynamically FSMC_NAND ECC feature.
 731 
/**
732 
  * @param  Device Pointer to NAND device instance
 732 
  * @brief  Disables dynamically FSMC_NAND ECC feature.
733 
  * @param  Bank NAND bank number
 733 
  * @param  Device Pointer to NAND device instance
734 
  * @retval HAL status
 734 
  * @param  Bank NAND bank number
735 
  */
 735 
  * @retval HAL status
736 
HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
 736 
  */
737 
{
 737 
HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
738 
  /* Check the parameters */
 738 
{
739 
  assert_param(IS_FSMC_NAND_DEVICE(Device));
 739 
  /* Check the parameters */
740 
  assert_param(IS_FSMC_NAND_BANK(Bank));
 740 
  assert_param(IS_FSMC_NAND_DEVICE(Device));
741 
 
 741 
  assert_param(IS_FSMC_NAND_BANK(Bank));
742 
  /* Disable ECC feature */
 742 
 
743 
  if (Bank == FSMC_NAND_BANK2)
 743 
  /* Disable ECC feature */
744 
  {
 744 
  if (Bank == FSMC_NAND_BANK2)
745 
    CLEAR_BIT(Device->PCR2, FSMC_PCRx_ECCEN);
 745 
  {
746 
  }
 746 
    CLEAR_BIT(Device->PCR2, FSMC_PCRx_ECCEN);
747 
  else
 747 
  }
748 
  {
 748 
  else
749 
    CLEAR_BIT(Device->PCR3, FSMC_PCRx_ECCEN);
 749 
  {
750 
  }
 750 
    CLEAR_BIT(Device->PCR3, FSMC_PCRx_ECCEN);
751 
 
 751 
  }
752 
  return HAL_OK;
 752 
 
753 
}
 753 
  return HAL_OK;
754 
 
 754 
}
755 
/**
 755 
 
756 
  * @brief  Disables dynamically FSMC_NAND ECC feature.
 756 
/**
757 
  * @param  Device Pointer to NAND device instance
 757 
  * @brief  Disables dynamically FSMC_NAND ECC feature.
758 
  * @param  ECCval Pointer to ECC value
 758 
  * @param  Device Pointer to NAND device instance
759 
  * @param  Bank NAND bank number
 759 
  * @param  ECCval Pointer to ECC value
760 
  * @param  Timeout Timeout wait value
 760 
  * @param  Bank NAND bank number
761 
  * @retval HAL status
 761 
  * @param  Timeout Timeout wait value
762 
  */
 762 
  * @retval HAL status
763 
HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
 763 
  */
764 
                                  uint32_t Timeout)
 764 
HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
765 
{
 765 
                                  uint32_t Timeout)
766 
  uint32_t tickstart;
 766 
{
767 
 
 767 
  uint32_t tickstart;
768 
  /* Check the parameters */
 768 
 
769 
  assert_param(IS_FSMC_NAND_DEVICE(Device));
 769 
  /* Check the parameters */
770 
  assert_param(IS_FSMC_NAND_BANK(Bank));
 770 
  assert_param(IS_FSMC_NAND_DEVICE(Device));
771 
 
 771 
  assert_param(IS_FSMC_NAND_BANK(Bank));
772 
  /* Get tick */
 772 
 
773 
  tickstart = HAL_GetTick();
 773 
  /* Get tick */
774 
 
 774 
  tickstart = HAL_GetTick();
775 
  /* Wait until FIFO is empty */
 775 
 
776 
  while (__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)
 776 
  /* Wait until FIFO is empty */
777 
  {
 777 
  while (__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)
778 
    /* Check for the Timeout */
 778 
  {
779 
    if (Timeout != HAL_MAX_DELAY)
 779 
    /* Check for the Timeout */
780 
    {
 780 
    if (Timeout != HAL_MAX_DELAY)
781 
      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
 781 
    {
782 
      {
 782 
      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
783 
        return HAL_TIMEOUT;
 783 
      {
784 
      }
 784 
        return HAL_TIMEOUT;
785 
    }
 785 
      }
786 
  }
 786 
    }
787 
 
 787 
  }
788 
  if (Bank == FSMC_NAND_BANK2)
 788 
 
789 
  {
 789 
  if (Bank == FSMC_NAND_BANK2)
790 
    /* Get the ECCR2 register value */
 790 
  {
791 
    *ECCval = (uint32_t)Device->ECCR2;
 791 
    /* Get the ECCR2 register value */
792 
  }
 792 
    *ECCval = (uint32_t)Device->ECCR2;
793 
  else
 793 
  }
794 
  {
 794 
  else
795 
    /* Get the ECCR3 register value */
 795 
  {
796 
    *ECCval = (uint32_t)Device->ECCR3;
 796 
    /* Get the ECCR3 register value */
797 
  }
 797 
    *ECCval = (uint32_t)Device->ECCR3;
798 
 
 798 
  }
799 
  return HAL_OK;
 799 
 
800 
}
 800 
  return HAL_OK;
801 
 
 801 
}
802 
/**
 802 
 
803 
  * @}
 803 
/**
804 
  */
 804 
  * @}
805 
#endif /* FSMC_BANK3 */
 805 
  */
806 
 
 806 
#endif /* FSMC_BANK3 */
807 
#if defined(FSMC_BANK4)
 807 
 
808 
 
 808 
#if defined(FSMC_BANK4)
809 
/** @addtogroup FSMC_LL_PCCARD
 809 
 
810 
  * @brief    PCCARD Controller functions
 810 
/** @addtogroup FSMC_LL_PCCARD
811 
  *
 811 
  * @brief    PCCARD Controller functions
812 
  @verbatim
 812 
  *
813 
  ==============================================================================
 813 
  @verbatim
814 
                    ##### How to use PCCARD device driver #####
 814 
  ==============================================================================
815 
  ==============================================================================
 815 
                    ##### How to use PCCARD device driver #####
816 
  [..]
 816 
  ==============================================================================
817 
    This driver contains a set of APIs to interface with the FSMC PCCARD bank in order
 817 
  [..]
818 
    to run the PCCARD/compact flash external devices.
 818 
    This driver contains a set of APIs to interface with the FSMC PCCARD bank in order
819 
 
 819 
    to run the PCCARD/compact flash external devices.
820 
    (+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit()
 820 
 
821 
    (+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init()
 821 
    (+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit()
822 
    (+) FSMC PCCARD bank common space timing configuration using the function
 822 
    (+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init()
823 
        FSMC_PCCARD_CommonSpace_Timing_Init()
 823 
    (+) FSMC PCCARD bank common space timing configuration using the function
824 
    (+) FSMC PCCARD bank attribute space timing configuration using the function
 824 
        FSMC_PCCARD_CommonSpace_Timing_Init()
825 
        FSMC_PCCARD_AttributeSpace_Timing_Init()
 825 
    (+) FSMC PCCARD bank attribute space timing configuration using the function
826 
    (+) FSMC PCCARD bank IO space timing configuration using the function
 826 
        FSMC_PCCARD_AttributeSpace_Timing_Init()
827 
        FSMC_PCCARD_IOSpace_Timing_Init()
 827 
    (+) FSMC PCCARD bank IO space timing configuration using the function
828 
@endverbatim
 828 
        FSMC_PCCARD_IOSpace_Timing_Init()
829 
  * @{
 829 
@endverbatim
830 
  */
 830 
  * @{
831 
 
 831 
  */
832 
/** @addtogroup FSMC_LL_PCCARD_Private_Functions_Group1
 832 
 
833 
  *  @brief    Initialization and Configuration functions
 833 
/** @addtogroup FSMC_LL_PCCARD_Private_Functions_Group1
834 
  *
 834 
  *  @brief    Initialization and Configuration functions
835 
@verbatim
 835 
  *
836 
  ==============================================================================
 836 
@verbatim
837 
              ##### Initialization and de_initialization functions #####
 837 
  ==============================================================================
838 
  ==============================================================================
 838 
              ##### Initialization and de_initialization functions #####
839 
  [..]
 839 
  ==============================================================================
840 
    This section provides functions allowing to:
 840 
  [..]
841 
    (+) Initialize and configure the FSMC PCCARD interface
 841 
    This section provides functions allowing to:
842 
    (+) De-initialize the FSMC PCCARD interface
 842 
    (+) Initialize and configure the FSMC PCCARD interface
843 
    (+) Configure the FSMC clock and associated GPIOs
 843 
    (+) De-initialize the FSMC PCCARD interface
844 
 
 844 
    (+) Configure the FSMC clock and associated GPIOs
845 
@endverbatim
 845 
 
846 
  * @{
 846 
@endverbatim
847 
  */
 847 
  * @{
848 
 
 848 
  */
849 
/**
 849 
 
850 
  * @brief  Initializes the FSMC_PCCARD device according to the specified
 850 
/**
851 
  *         control parameters in the FSMC_PCCARD_HandleTypeDef
 851 
  * @brief  Initializes the FSMC_PCCARD device according to the specified
852 
  * @param  Device Pointer to PCCARD device instance
 852 
  *         control parameters in the FSMC_PCCARD_HandleTypeDef
853 
  * @param  Init Pointer to PCCARD Initialization structure
 853 
  * @param  Device Pointer to PCCARD device instance
854 
  * @retval HAL status
 854 
  * @param  Init Pointer to PCCARD Initialization structure
855 
  */
 855 
  * @retval HAL status
856 
HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init)
 856 
  */
857 
{
 857 
HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init)
858 
  /* Check the parameters */
 858 
{
859 
  assert_param(IS_FSMC_PCCARD_DEVICE(Device));
 859 
  /* Check the parameters */
860 
#if defined(FSMC_BANK3)
 860 
  assert_param(IS_FSMC_PCCARD_DEVICE(Device));
861 
  assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
 861 
#if defined(FSMC_BANK3)
862 
  assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
 862 
  assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
863 
  assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
 863 
  assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
864 
#endif /* FSMC_BANK3 */
 864 
  assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
865 
 
 865 
#endif /* FSMC_BANK3 */
866 
  /* Set FSMC_PCCARD device control parameters */
 866 
 
867 
  MODIFY_REG(Device->PCR4,
 867 
  /* Set FSMC_PCCARD device control parameters */
868 
             (FSMC_PCRx_PTYP                                          |
 868 
  MODIFY_REG(Device->PCR4,
869 
              FSMC_PCRx_PWAITEN                                       |
 869 
             (FSMC_PCRx_PTYP                                          |
870 
              FSMC_PCRx_PWID                                          |
 870 
              FSMC_PCRx_PWAITEN                                       |
871 
              FSMC_PCRx_TCLR                                          |
 871 
              FSMC_PCRx_PWID                                          |
872 
              FSMC_PCRx_TAR),
 872 
              FSMC_PCRx_TCLR                                          |
873 
             (FSMC_PCR_MEMORY_TYPE_PCCARD                             |
 873 
              FSMC_PCRx_TAR),
874 
              Init->Waitfeature                                      |
 874 
             (FSMC_PCR_MEMORY_TYPE_PCCARD                             |
875 
              FSMC_NAND_PCC_MEM_BUS_WIDTH_16                          |
 875 
              Init->Waitfeature                                      |
876 
              (Init->TCLRSetupTime << FSMC_PCRx_TCLR_Pos)   |
 876 
              FSMC_NAND_PCC_MEM_BUS_WIDTH_16                          |
877 
              (Init->TARSetupTime  << FSMC_PCRx_TAR_Pos)));
 877 
              (Init->TCLRSetupTime << FSMC_PCRx_TCLR_Pos)   |
878 
 
 878 
              (Init->TARSetupTime  << FSMC_PCRx_TAR_Pos)));
879 
  return HAL_OK;
 879 
 
880 
}
 880 
  return HAL_OK;
881 
 
 881 
}
882 
/**
 882 
 
883 
  * @brief  Initializes the FSMC_PCCARD Common space Timing according to the specified
 883 
/**
884 
  *         parameters in the FSMC_NAND_PCC_TimingTypeDef
 884 
  * @brief  Initializes the FSMC_PCCARD Common space Timing according to the specified
885 
  * @param  Device Pointer to PCCARD device instance
 885 
  *         parameters in the FSMC_NAND_PCC_TimingTypeDef
886 
  * @param  Timing Pointer to PCCARD timing structure
 886 
  * @param  Device Pointer to PCCARD device instance
887 
  * @retval HAL status
 887 
  * @param  Timing Pointer to PCCARD timing structure
888 
  */
 888 
  * @retval HAL status
889 
HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
 889 
  */
890 
                                                              FSMC_NAND_PCC_TimingTypeDef *Timing)
 890 
HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
891 
{
 891 
                                                              FSMC_NAND_PCC_TimingTypeDef *Timing)
892 
  /* Check the parameters */
 892 
{
893 
  assert_param(IS_FSMC_PCCARD_DEVICE(Device));
 893 
  /* Check the parameters */
894 
#if defined(FSMC_BANK3)
 894 
  assert_param(IS_FSMC_PCCARD_DEVICE(Device));
895 
  assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
 895 
#if defined(FSMC_BANK3)
896 
  assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
 896 
  assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
897 
  assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
 897 
  assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
898 
  assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
 898 
  assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
899 
#endif /* FSMC_BANK3 */
 899 
  assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
900 
 
 900 
#endif /* FSMC_BANK3 */
901 
  /* Set PCCARD timing parameters */
 901 
 
902 
  MODIFY_REG(Device->PMEM4, PMEM_CLEAR_MASK,
 902 
  /* Set PCCARD timing parameters */
903 
             (Timing->SetupTime                                              |
 903 
  MODIFY_REG(Device->PMEM4, PMEM_CLEAR_MASK,
904 
              ((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos)  |
 904 
             (Timing->SetupTime                                              |
905 
              ((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos)  |
 905 
              ((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos)  |
906 
              ((Timing->HiZSetupTime)  << FSMC_PMEMx_MEMHIZx_Pos)));
 906 
              ((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos)  |
907 
 
 907 
              ((Timing->HiZSetupTime)  << FSMC_PMEMx_MEMHIZx_Pos)));
908 
  return HAL_OK;
 908 
 
909 
}
 909 
  return HAL_OK;
910 
 
 910 
}
911 
/**
 911 
 
912 
  * @brief  Initializes the FSMC_PCCARD Attribute space Timing according to the specified
 912 
/**
913 
  *         parameters in the FSMC_NAND_PCC_TimingTypeDef
 913 
  * @brief  Initializes the FSMC_PCCARD Attribute space Timing according to the specified
914 
  * @param  Device Pointer to PCCARD device instance
 914 
  *         parameters in the FSMC_NAND_PCC_TimingTypeDef
915 
  * @param  Timing Pointer to PCCARD timing structure
 915 
  * @param  Device Pointer to PCCARD device instance
916 
  * @retval HAL status
 916 
  * @param  Timing Pointer to PCCARD timing structure
917 
  */
 917 
  * @retval HAL status
918 
HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
 918 
  */
919 
                                                                 FSMC_NAND_PCC_TimingTypeDef *Timing)
 919 
HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
920 
{
 920 
                                                                 FSMC_NAND_PCC_TimingTypeDef *Timing)
921 
  /* Check the parameters */
 921 
{
922 
  assert_param(IS_FSMC_PCCARD_DEVICE(Device));
 922 
  /* Check the parameters */
923 
#if defined(FSMC_BANK3)
 923 
  assert_param(IS_FSMC_PCCARD_DEVICE(Device));
924 
  assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
 924 
#if defined(FSMC_BANK3)
925 
  assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
 925 
  assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
926 
  assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
 926 
  assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
927 
  assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
 927 
  assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
928 
#endif /* FSMC_BANK3 */
 928 
  assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
929 
 
 929 
#endif /* FSMC_BANK3 */
930 
  /* Set PCCARD timing parameters */
 930 
 
931 
  MODIFY_REG(Device->PATT4, PATT_CLEAR_MASK,
 931 
  /* Set PCCARD timing parameters */
932 
             (Timing->SetupTime                                              |
 932 
  MODIFY_REG(Device->PATT4, PATT_CLEAR_MASK,
933 
              ((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos)  |
 933 
             (Timing->SetupTime                                              |
934 
              ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos)  |
 934 
              ((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos)  |
935 
              ((Timing->HiZSetupTime)  << FSMC_PATTx_ATTHIZx_Pos)));
 935 
              ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos)  |
936 
 
 936 
              ((Timing->HiZSetupTime)  << FSMC_PATTx_ATTHIZx_Pos)));
937 
  return HAL_OK;
 937 
 
938 
}
 938 
  return HAL_OK;
939 
 
 939 
}
940 
/**
 940 
 
941 
  * @brief  Initializes the FSMC_PCCARD IO space Timing according to the specified
 941 
/**
942 
  *         parameters in the FSMC_NAND_PCC_TimingTypeDef
 942 
  * @brief  Initializes the FSMC_PCCARD IO space Timing according to the specified
943 
  * @param  Device Pointer to PCCARD device instance
 943 
  *         parameters in the FSMC_NAND_PCC_TimingTypeDef
944 
  * @param  Timing Pointer to PCCARD timing structure
 944 
  * @param  Device Pointer to PCCARD device instance
945 
  * @retval HAL status
 945 
  * @param  Timing Pointer to PCCARD timing structure
946 
  */
 946 
  * @retval HAL status
947 
HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
 947 
  */
948 
                                                          FSMC_NAND_PCC_TimingTypeDef *Timing)
 948 
HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
949 
{
 949 
                                                          FSMC_NAND_PCC_TimingTypeDef *Timing)
950 
  /* Check the parameters */
 950 
{
951 
  assert_param(IS_FSMC_PCCARD_DEVICE(Device));
 951 
  /* Check the parameters */
952 
#if defined(FSMC_BANK3)
 952 
  assert_param(IS_FSMC_PCCARD_DEVICE(Device));
953 
  assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
 953 
#if defined(FSMC_BANK3)
954 
  assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
 954 
  assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
955 
  assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
 955 
  assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
956 
  assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
 956 
  assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
957 
#endif /* FSMC_BANK3 */
 957 
  assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
958 
 
 958 
#endif /* FSMC_BANK3 */
959 
  /* Set FSMC_PCCARD device timing parameters */
 959 
 
960 
  MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK,
 960 
  /* Set FSMC_PCCARD device timing parameters */
961 
             (Timing->SetupTime                                           |
 961 
  MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK,
962 
              (Timing->WaitSetupTime   << FSMC_PIO4_IOWAIT4_Pos) |
 962 
             (Timing->SetupTime                                           |
963 
              (Timing->HoldSetupTime   << FSMC_PIO4_IOHOLD4_Pos) |
 963 
              (Timing->WaitSetupTime   << FSMC_PIO4_IOWAIT4_Pos) |
964 
              (Timing->HiZSetupTime    << FSMC_PIO4_IOHIZ4_Pos)));
 964 
              (Timing->HoldSetupTime   << FSMC_PIO4_IOHOLD4_Pos) |
965 
 
 965 
              (Timing->HiZSetupTime    << FSMC_PIO4_IOHIZ4_Pos)));
966 
  return HAL_OK;
 966 
 
967 
}
 967 
  return HAL_OK;
968 
 
 968 
}
969 
/**
 969 
 
970 
  * @brief  DeInitializes the FSMC_PCCARD device
 970 
/**
971 
  * @param  Device Pointer to PCCARD device instance
 971 
  * @brief  DeInitializes the FSMC_PCCARD device
972 
  * @retval HAL status
 972 
  * @param  Device Pointer to PCCARD device instance
973 
  */
 973 
  * @retval HAL status
974 
HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
 974 
  */
975 
{
 975 
HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
976 
  /* Check the parameters */
 976 
{
977 
  assert_param(IS_FSMC_PCCARD_DEVICE(Device));
 977 
  /* Check the parameters */
978 
 
 978 
  assert_param(IS_FSMC_PCCARD_DEVICE(Device));
979 
  /* Disable the FSMC_PCCARD device */
 979 
 
980 
  __FSMC_PCCARD_DISABLE(Device);
 980 
  /* Disable the FSMC_PCCARD device */
981 
 
 981 
  __FSMC_PCCARD_DISABLE(Device);
982 
  /* De-initialize the FSMC_PCCARD device */
 982 
 
983 
  Device->PCR4    = 0x00000018U;
 983 
  /* De-initialize the FSMC_PCCARD device */
984 
  Device->SR4     = 0x00000040U;
 984 
  Device->PCR4    = 0x00000018U;
985 
  Device->PMEM4   = 0xFCFCFCFCU;
 985 
  Device->SR4     = 0x00000040U;
986 
  Device->PATT4   = 0xFCFCFCFCU;
 986 
  Device->PMEM4   = 0xFCFCFCFCU;
987 
  Device->PIO4    = 0xFCFCFCFCU;
 987 
  Device->PATT4   = 0xFCFCFCFCU;
988 
 
 988 
  Device->PIO4    = 0xFCFCFCFCU;
989 
  return HAL_OK;
 989 
 
990 
}
 990 
  return HAL_OK;
991 
 
 991 
}
992 
/**
 992 
 
993 
  * @}
 993 
/**
994 
  */
 994 
  * @}
995 
#endif /* FSMC_BANK4 */
 995 
  */
996 
 
 996 
#endif /* FSMC_BANK4 */
997 
 
 997 
 
998 
/**
 998 
 
999 
  * @}
 999 
/**
1000 
  */
 1000 
  * @}
1001 
 
 1001 
  */
1002 
/**
 1002 
 
1003 
  * @}
 1003 
/**
1004 
  */
 1004 
  * @}
1005 
 
 1005 
  */
1006 
#endif /* HAL_NOR_MODULE_ENABLED */
 1006 
 
1007 
/**
 1007 
#endif /* HAL_NOR_MODULE_ENABLED */
1008 
  * @}
 1008 
/**
1009 
  */
 1009 
  * @}
1010 
/**
 1010 
  */
1011 
  * @}
 1011 
/**
1012 
  */
 1012 
  * @}
1013 
 
 1013 
  */
1014 
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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