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| 1 | /** |
1 | /** |
| 2 | ****************************************************************************** |
2 | ****************************************************************************** |
| 3 | * @file stm32f1xx_ll_adc.c |
3 | * @file stm32f1xx_ll_adc.c |
| 4 | * @author MCD Application Team |
4 | * @author MCD Application Team |
| 5 | * @brief ADC LL module driver |
5 | * @brief ADC LL module driver |
| 6 | ****************************************************************************** |
6 | ****************************************************************************** |
| 7 | * @attention |
7 | * @attention |
| 8 | * |
8 | * |
| 9 | * <h2><center>© Copyright (c) 2017 STMicroelectronics. |
9 | * Copyright (c) 2017 STMicroelectronics. |
| 10 | * All rights reserved.</center></h2> |
10 | * All rights reserved. |
| 11 | * |
11 | * |
| 12 | * This software component is licensed by ST under BSD 3-Clause license, |
12 | * This software is licensed under terms that can be found in the LICENSE file |
| 13 | * the "License"; You may not use this file except in compliance with the |
13 | * in the root directory of this software component. |
| 14 | * License. You may obtain a copy of the License at: |
14 | * If no LICENSE file comes with this software, it is provided AS-IS. |
| 15 | * opensource.org/licenses/BSD-3-Clause |
15 | * |
| 16 | * |
16 | ****************************************************************************** |
| 17 | ****************************************************************************** |
17 | */ |
| 18 | */ |
18 | |
| 19 | 19 | #if defined(USE_FULL_LL_DRIVER) |
|
| 20 | #if defined(USE_FULL_LL_DRIVER) |
20 | |
| 21 | 21 | /* Includes ------------------------------------------------------------------*/ |
|
| 22 | /* Includes ------------------------------------------------------------------*/ |
22 | #include "stm32f1xx_ll_adc.h" |
| 23 | #include "stm32f1xx_ll_adc.h" |
23 | #include "stm32f1xx_ll_bus.h" |
| 24 | #include "stm32f1xx_ll_bus.h" |
24 | |
| 25 | 25 | #ifdef USE_FULL_ASSERT |
|
| 26 | #ifdef USE_FULL_ASSERT |
26 | #include "stm32_assert.h" |
| 27 | #include "stm32_assert.h" |
27 | #else |
| 28 | #else |
28 | #define assert_param(expr) ((void)0U) |
| 29 | #define assert_param(expr) ((void)0U) |
29 | #endif |
| 30 | #endif |
30 | |
| 31 | 31 | /** @addtogroup STM32F1xx_LL_Driver |
|
| 32 | /** @addtogroup STM32F1xx_LL_Driver |
32 | * @{ |
| 33 | * @{ |
33 | */ |
| 34 | */ |
34 | |
| 35 | 35 | #if defined (ADC1) || defined (ADC2) || defined (ADC3) |
|
| 36 | #if defined (ADC1) || defined (ADC2) || defined (ADC3) |
36 | |
| 37 | 37 | /** @addtogroup ADC_LL ADC |
|
| 38 | /** @addtogroup ADC_LL ADC |
38 | * @{ |
| 39 | * @{ |
39 | */ |
| 40 | */ |
40 | |
| 41 | 41 | /* Private types -------------------------------------------------------------*/ |
|
| 42 | /* Private types -------------------------------------------------------------*/ |
42 | /* Private variables ---------------------------------------------------------*/ |
| 43 | /* Private variables ---------------------------------------------------------*/ |
43 | /* Private constants ---------------------------------------------------------*/ |
| 44 | /* Private constants ---------------------------------------------------------*/ |
44 | /* Private macros ------------------------------------------------------------*/ |
| 45 | /* Private macros ------------------------------------------------------------*/ |
45 | |
| 46 | 46 | /** @addtogroup ADC_LL_Private_Macros |
|
| 47 | /** @addtogroup ADC_LL_Private_Macros |
47 | * @{ |
| 48 | * @{ |
48 | */ |
| 49 | */ |
49 | |
| 50 | 50 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
|
| 51 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
51 | /* common to several ADC instances. */ |
| 52 | /* common to several ADC instances. */ |
52 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
| 53 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
53 | /* ADC instance. */ |
| 54 | /* ADC instance. */ |
54 | #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \ |
| 55 | #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \ |
55 | ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \ |
| 56 | ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \ |
56 | || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \ |
| 57 | || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \ |
57 | ) |
| 58 | ) |
58 | |
| 59 | 59 | #define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \ |
|
| 60 | #define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \ |
60 | ( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \ |
| 61 | ( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \ |
61 | || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) \ |
| 62 | || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) \ |
62 | ) |
| 63 | ) |
63 | |
| 64 | 64 | #define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \ |
|
| 65 | #define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \ |
65 | ( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \ |
| 66 | ( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \ |
66 | || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) \ |
| 67 | || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) \ |
67 | ) |
| 68 | ) |
68 | |
| 69 | 69 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
|
| 70 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
70 | /* ADC group regular */ |
| 71 | /* ADC group regular */ |
71 | #if defined(ADC3) |
| 72 | #if defined(ADC3) |
72 | #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \ |
| 73 | #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \ |
73 | ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \ |
| 74 | ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \ |
74 | ? ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ |
| 75 | ? ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ |
75 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ |
| 76 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ |
76 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ |
| 77 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ |
77 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ |
| 78 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ |
78 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ |
| 79 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ |
79 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ |
| 80 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ |
80 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ |
| 81 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ |
81 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ |
| 82 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ |
82 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ |
| 83 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ |
83 | ) \ |
| 84 | ) \ |
84 | : \ |
| 85 | : \ |
85 | ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ |
| 86 | ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ |
86 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ |
| 87 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ |
87 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \ |
| 88 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \ |
88 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \ |
| 89 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \ |
89 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \ |
| 90 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \ |
90 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3) \ |
| 91 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3) \ |
91 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH1) \ |
| 92 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH1) \ |
92 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH3) \ |
| 93 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH3) \ |
93 | ) \ |
| 94 | ) \ |
94 | ) |
| 95 | ) |
95 | #else |
| 96 | #else |
96 | #if defined (STM32F101xE) || defined (STM32F105xC) || defined (STM32F107xC) |
| 97 | #if defined (STM32F101xE) || defined (STM32F105xC) || defined (STM32F107xC) |
97 | #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \ |
| 98 | #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \ |
98 | ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ |
| 99 | ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ |
99 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ |
| 100 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ |
100 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ |
| 101 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ |
101 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ |
| 102 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ |
102 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ |
| 103 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ |
103 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ |
| 104 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ |
104 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ |
| 105 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ |
105 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ |
| 106 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ |
106 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ |
| 107 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ |
107 | ) |
| 108 | ) |
108 | #else |
| 109 | #else |
109 | #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \ |
| 110 | #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \ |
110 | ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ |
| 111 | ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ |
111 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ |
| 112 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ |
112 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ |
| 113 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ |
113 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ |
| 114 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ |
114 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ |
| 115 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ |
115 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ |
| 116 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ |
116 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ |
| 117 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ |
117 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ |
| 118 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ |
118 | ) |
| 119 | ) |
119 | #endif |
| 120 | #endif |
120 | #endif |
| 121 | #endif |
121 | #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \ |
| 122 | #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \ |
122 | ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \ |
| 123 | ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \ |
123 | || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \ |
| 124 | || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \ |
124 | ) |
| 125 | ) |
125 | |
| 126 | 126 | #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \ |
|
| 127 | #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \ |
127 | ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \ |
| 128 | ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \ |
128 | || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \ |
| 129 | || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \ |
129 | ) |
| 130 | ) |
130 | |
| 131 | 131 | #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \ |
|
| 132 | #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \ |
132 | ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \ |
| 133 | ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \ |
133 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \ |
| 134 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \ |
134 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \ |
| 135 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \ |
135 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \ |
| 136 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \ |
136 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \ |
| 137 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \ |
137 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \ |
| 138 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \ |
138 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \ |
| 139 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \ |
139 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \ |
| 140 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \ |
140 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \ |
| 141 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \ |
141 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \ |
| 142 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \ |
142 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \ |
| 143 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \ |
143 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \ |
| 144 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \ |
144 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \ |
| 145 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \ |
145 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \ |
| 146 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \ |
146 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \ |
| 147 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \ |
147 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \ |
| 148 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \ |
148 | ) |
| 149 | ) |
149 | |
| 150 | 150 | #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \ |
|
| 151 | #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \ |
151 | ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \ |
| 152 | ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \ |
152 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \ |
| 153 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \ |
153 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \ |
| 154 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \ |
154 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \ |
| 155 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \ |
155 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \ |
| 156 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \ |
156 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \ |
| 157 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \ |
157 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \ |
| 158 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \ |
158 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \ |
| 159 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \ |
159 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \ |
| 160 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \ |
160 | ) |
| 161 | ) |
161 | |
| 162 | 162 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
|
| 163 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
163 | /* ADC group injected */ |
| 164 | /* ADC group injected */ |
164 | #if defined(ADC3) |
| 165 | #if defined(ADC3) |
165 | #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \ |
| 166 | #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \ |
166 | ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \ |
| 167 | ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \ |
167 | ? ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ |
| 168 | ? ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ |
168 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ |
| 169 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ |
169 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ |
| 170 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ |
170 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ |
| 171 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ |
171 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ |
| 172 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ |
172 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ |
| 173 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ |
173 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ |
| 174 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ |
174 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ |
| 175 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ |
175 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ |
| 176 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ |
176 | ) \ |
| 177 | ) \ |
177 | : \ |
| 178 | : \ |
178 | ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ |
| 179 | ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ |
179 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ |
| 180 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ |
180 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ |
| 181 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ |
181 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \ |
| 182 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \ |
182 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \ |
| 183 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \ |
183 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3) \ |
| 184 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3) \ |
184 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_TRGO) \ |
| 185 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_TRGO) \ |
185 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_CH4) \ |
| 186 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_CH4) \ |
186 | ) \ |
| 187 | ) \ |
187 | ) |
| 188 | ) |
188 | #else |
| 189 | #else |
189 | #if defined (STM32F101xE) || defined (STM32F105xC) || defined (STM32F107xC) |
| 190 | #if defined (STM32F101xE) || defined (STM32F105xC) || defined (STM32F107xC) |
190 | #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \ |
| 191 | #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \ |
191 | ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ |
| 192 | ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ |
192 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ |
| 193 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ |
193 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ |
| 194 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ |
194 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ |
| 195 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ |
195 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ |
| 196 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ |
196 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ |
| 197 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ |
197 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ |
| 198 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ |
198 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ |
| 199 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ |
199 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ |
| 200 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ |
200 | ) |
| 201 | ) |
201 | #else |
| 202 | #else |
202 | #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \ |
| 203 | #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \ |
203 | ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ |
| 204 | ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ |
204 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ |
| 205 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ |
205 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ |
| 206 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ |
206 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ |
| 207 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ |
207 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ |
| 208 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ |
208 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ |
| 209 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ |
209 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ |
| 210 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ |
210 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ |
| 211 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ |
211 | ) |
| 212 | ) |
212 | #endif |
| 213 | #endif |
213 | #endif |
| 214 | #endif |
214 | #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \ |
| 215 | #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \ |
215 | ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \ |
| 216 | ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \ |
216 | || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \ |
| 217 | || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \ |
217 | ) |
| 218 | ) |
218 | |
| 219 | 219 | #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \ |
|
| 220 | #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \ |
220 | ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \ |
| 221 | ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \ |
221 | || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \ |
| 222 | || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \ |
222 | || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \ |
| 223 | || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \ |
223 | || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \ |
| 224 | || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \ |
224 | ) |
| 225 | ) |
225 | |
| 226 | 226 | #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \ |
|
| 227 | #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \ |
227 | ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \ |
| 228 | ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \ |
228 | || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \ |
| 229 | || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \ |
229 | ) |
| 230 | ) |
230 | |
| 231 | 231 | #if defined(ADC_MULTIMODE_SUPPORT) |
|
| 232 | #if defined(ADC_MULTIMODE_SUPPORT) |
232 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
| 233 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
233 | /* multimode. */ |
| 234 | /* multimode. */ |
234 | #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \ |
| 235 | #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \ |
235 | ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \ |
| 236 | ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \ |
236 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \ |
| 237 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \ |
237 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL_FAST) \ |
| 238 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL_FAST) \ |
238 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL_SLOW) \ |
| 239 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL_SLOW) \ |
239 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \ |
| 240 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \ |
240 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \ |
| 241 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \ |
241 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \ |
| 242 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \ |
242 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \ |
| 243 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \ |
243 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM) \ |
| 244 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM) \ |
244 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM) \ |
| 245 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM) \ |
245 | ) |
| 246 | ) |
246 | |
| 247 | 247 | #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \ |
|
| 248 | #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \ |
248 | ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \ |
| 249 | ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \ |
249 | || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \ |
| 250 | || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \ |
250 | || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \ |
| 251 | || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \ |
251 | ) |
| 252 | ) |
252 | |
| 253 | 253 | #endif /* ADC_MULTIMODE_SUPPORT */ |
|
| 254 | #endif /* ADC_MULTIMODE_SUPPORT */ |
254 | /** |
| 255 | /** |
255 | * @} |
| 256 | * @} |
256 | */ |
| 257 | */ |
257 | |
| 258 | 258 | ||
| 259 | 259 | /* Private function prototypes -----------------------------------------------*/ |
|
| 260 | /* Private function prototypes -----------------------------------------------*/ |
260 | |
| 261 | 261 | /* Exported functions --------------------------------------------------------*/ |
|
| 262 | /* Exported functions --------------------------------------------------------*/ |
262 | /** @addtogroup ADC_LL_Exported_Functions |
| 263 | /** @addtogroup ADC_LL_Exported_Functions |
263 | * @{ |
| 264 | * @{ |
264 | */ |
| 265 | */ |
265 | |
| 266 | 266 | /** @addtogroup ADC_LL_EF_Init |
|
| 267 | /** @addtogroup ADC_LL_EF_Init |
267 | * @{ |
| 268 | * @{ |
268 | */ |
| 269 | */ |
269 | |
| 270 | 270 | /** |
|
| 271 | /** |
271 | * @brief De-initialize registers of all ADC instances belonging to |
| 272 | * @brief De-initialize registers of all ADC instances belonging to |
272 | * the same ADC common instance to their default reset values. |
| 273 | * the same ADC common instance to their default reset values. |
273 | * @param ADCxy_COMMON ADC common instance |
| 274 | * @param ADCxy_COMMON ADC common instance |
274 | * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) |
| 275 | * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) |
275 | * @retval An ErrorStatus enumeration value: |
| 276 | * @retval An ErrorStatus enumeration value: |
276 | * - SUCCESS: ADC common registers are de-initialized |
| 277 | * - SUCCESS: ADC common registers are de-initialized |
277 | * - ERROR: not applicable |
| 278 | * - ERROR: not applicable |
278 | */ |
| 279 | */ |
279 | ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) |
| 280 | ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) |
280 | { |
| 281 | { |
281 | /* Check the parameters */ |
| 282 | /* Check the parameters */ |
282 | assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); |
| 283 | assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); |
283 | |
| 284 | 284 | /* Force reset of ADC clock (core clock) */ |
|
| 285 | /* Force reset of ADC clock (core clock) */ |
285 | LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC1); |
| 286 | LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC1); |
286 | |
| 287 | 287 | /* Release reset of ADC clock (core clock) */ |
|
| 288 | /* Release reset of ADC clock (core clock) */ |
288 | LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC1); |
| 289 | LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC1); |
289 | |
| 290 | 290 | return SUCCESS; |
|
| 291 | return SUCCESS; |
291 | } |
| 292 | } |
292 | |
| 293 | 293 | /** |
|
| 294 | /** |
294 | * @brief Initialize some features of ADC common parameters |
| 295 | * @brief Initialize some features of ADC common parameters |
295 | * (all ADC instances belonging to the same ADC common instance) |
| 296 | * (all ADC instances belonging to the same ADC common instance) |
296 | * and multimode (for devices with several ADC instances available). |
| 297 | * and multimode (for devices with several ADC instances available). |
297 | * @note The setting of ADC common parameters is conditioned to |
| 298 | * @note The setting of ADC common parameters is conditioned to |
298 | * ADC instances state: |
| 299 | * ADC instances state: |
299 | * All ADC instances belonging to the same ADC common instance |
| 300 | * All ADC instances belonging to the same ADC common instance |
300 | * must be disabled. |
| 301 | * must be disabled. |
301 | * @param ADCxy_COMMON ADC common instance |
| 302 | * @param ADCxy_COMMON ADC common instance |
302 | * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) |
| 303 | * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) |
303 | * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure |
| 304 | * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure |
304 | * @retval An ErrorStatus enumeration value: |
| 305 | * @retval An ErrorStatus enumeration value: |
305 | * - SUCCESS: ADC common registers are initialized |
| 306 | * - SUCCESS: ADC common registers are initialized |
306 | * - ERROR: ADC common registers are not initialized |
| 307 | * - ERROR: ADC common registers are not initialized |
307 | */ |
| 308 | */ |
308 | ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) |
| 309 | ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) |
309 | { |
| 310 | { |
310 | ErrorStatus status = SUCCESS; |
| 311 | ErrorStatus status = SUCCESS; |
311 | |
| 312 | 312 | /* Check the parameters */ |
|
| 313 | /* Check the parameters */ |
313 | assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); |
| 314 | assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); |
314 | #if defined(ADC_MULTIMODE_SUPPORT) |
| 315 | #if defined(ADC_MULTIMODE_SUPPORT) |
315 | assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode)); |
| 316 | assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode)); |
316 | #endif /* ADC_MULTIMODE_SUPPORT */ |
| 317 | #endif /* ADC_MULTIMODE_SUPPORT */ |
317 | |
| 318 | 318 | /* Note: Hardware constraint (refer to description of functions */ |
|
| 319 | /* Note: Hardware constraint (refer to description of functions */ |
319 | /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */ |
| 320 | /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */ |
320 | /* On this STM32 series, setting of these features is conditioned to */ |
| 321 | /* On this STM32 serie, setting of these features is conditioned to */ |
321 | /* ADC state: */ |
| 322 | /* ADC state: */ |
322 | /* All ADC instances of the ADC common group must be disabled. */ |
| 323 | /* All ADC instances of the ADC common group must be disabled. */ |
323 | if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U) |
| 324 | if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U) |
324 | { |
| 325 | { |
325 | /* Configuration of ADC hierarchical scope: */ |
| 326 | /* Configuration of ADC hierarchical scope: */ |
326 | /* - common to several ADC */ |
| 327 | /* - common to several ADC */ |
327 | /* (all ADC instances belonging to the same ADC common instance) */ |
| 328 | /* (all ADC instances belonging to the same ADC common instance) */ |
328 | /* - multimode (if several ADC instances available on the */ |
| 329 | /* - multimode (if several ADC instances available on the */ |
329 | /* selected device) */ |
| 330 | /* selected device) */ |
330 | /* - Set ADC multimode configuration */ |
| 331 | /* - Set ADC multimode configuration */ |
331 | /* - Set ADC multimode DMA transfer */ |
| 332 | /* - Set ADC multimode DMA transfer */ |
332 | /* - Set ADC multimode: delay between 2 sampling phases */ |
| 333 | /* - Set ADC multimode: delay between 2 sampling phases */ |
333 | #if defined(ADC_MULTIMODE_SUPPORT) |
| 334 | #if defined(ADC_MULTIMODE_SUPPORT) |
334 | if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) |
| 335 | if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) |
335 | { |
| 336 | { |
336 | MODIFY_REG(ADCxy_COMMON->CR1, |
| 337 | MODIFY_REG(ADCxy_COMMON->CR1, |
337 | ADC_CR1_DUALMOD, |
| 338 | ADC_CR1_DUALMOD, |
338 | ADC_CommonInitStruct->Multimode |
| 339 | ADC_CommonInitStruct->Multimode |
339 | ); |
| 340 | ); |
340 | } |
| 341 | } |
341 | else |
| 342 | else |
342 | { |
| 343 | { |
343 | MODIFY_REG(ADCxy_COMMON->CR1, |
| 344 | MODIFY_REG(ADCxy_COMMON->CR1, |
344 | ADC_CR1_DUALMOD, |
| 345 | ADC_CR1_DUALMOD, |
345 | LL_ADC_MULTI_INDEPENDENT |
| 346 | LL_ADC_MULTI_INDEPENDENT |
346 | ); |
| 347 | ); |
347 | } |
| 348 | } |
348 | #endif |
| 349 | #endif |
349 | } |
| 350 | } |
350 | else |
| 351 | else |
351 | { |
| 352 | { |
352 | /* Initialization error: One or several ADC instances belonging to */ |
| 353 | /* Initialization error: One or several ADC instances belonging to */ |
353 | /* the same ADC common instance are not disabled. */ |
| 354 | /* the same ADC common instance are not disabled. */ |
354 | status = ERROR; |
| 355 | status = ERROR; |
355 | } |
| 356 | } |
356 | |
| 357 | 357 | return status; |
|
| 358 | return status; |
358 | } |
| 359 | } |
359 | |
| 360 | 360 | /** |
|
| 361 | /** |
361 | * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value. |
| 362 | * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value. |
362 | * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure |
| 363 | * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure |
363 | * whose fields will be set to default values. |
| 364 | * whose fields will be set to default values. |
364 | * @retval None |
| 365 | * @retval None |
365 | */ |
| 366 | */ |
366 | void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) |
| 367 | void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) |
367 | { |
| 368 | { |
368 | /* Set ADC_CommonInitStruct fields to default values */ |
| 369 | /* Set ADC_CommonInitStruct fields to default values */ |
369 | /* Set fields of ADC common */ |
| 370 | /* Set fields of ADC common */ |
370 | /* (all ADC instances belonging to the same ADC common instance) */ |
| 371 | /* (all ADC instances belonging to the same ADC common instance) */ |
371 | |
| 372 | 372 | #if defined(ADC_MULTIMODE_SUPPORT) |
|
| 373 | #if defined(ADC_MULTIMODE_SUPPORT) |
373 | /* Set fields of ADC multimode */ |
| 374 | /* Set fields of ADC multimode */ |
374 | ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT; |
| 375 | ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT; |
375 | #endif /* ADC_MULTIMODE_SUPPORT */ |
| 376 | #endif /* ADC_MULTIMODE_SUPPORT */ |
376 | } |
| 377 | } |
377 | |
| 378 | 378 | /** |
|
| 379 | /** |
379 | * @brief De-initialize registers of the selected ADC instance |
| 380 | * @brief De-initialize registers of the selected ADC instance |
380 | * to their default reset values. |
| 381 | * to their default reset values. |
381 | * @note To reset all ADC instances quickly (perform a hard reset), |
| 382 | * @note To reset all ADC instances quickly (perform a hard reset), |
382 | * use function @ref LL_ADC_CommonDeInit(). |
| 383 | * use function @ref LL_ADC_CommonDeInit(). |
383 | * @param ADCx ADC instance |
| 384 | * @param ADCx ADC instance |
384 | * @retval An ErrorStatus enumeration value: |
| 385 | * @retval An ErrorStatus enumeration value: |
385 | * - SUCCESS: ADC registers are de-initialized |
| 386 | * - SUCCESS: ADC registers are de-initialized |
386 | * - ERROR: ADC registers are not de-initialized |
| 387 | * - ERROR: ADC registers are not de-initialized |
387 | */ |
| 388 | */ |
388 | ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) |
| 389 | ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) |
389 | { |
| 390 | { |
390 | ErrorStatus status = SUCCESS; |
| 391 | ErrorStatus status = SUCCESS; |
391 | |
| 392 | 392 | /* Check the parameters */ |
|
| 393 | /* Check the parameters */ |
393 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
| 394 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
394 | |
| 395 | 395 | /* Disable ADC instance if not already disabled. */ |
|
| 396 | /* Disable ADC instance if not already disabled. */ |
396 | if(LL_ADC_IsEnabled(ADCx) == 1U) |
| 397 | if(LL_ADC_IsEnabled(ADCx) == 1U) |
397 | { |
| 398 | { |
398 | /* Set ADC group regular trigger source to SW start to ensure to not */ |
| 399 | /* Set ADC group regular trigger source to SW start to ensure to not */ |
399 | /* have an external trigger event occurring during the conversion stop */ |
| 400 | /* have an external trigger event occurring during the conversion stop */ |
400 | /* ADC disable process. */ |
| 401 | /* ADC disable process. */ |
401 | LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE); |
| 402 | LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE); |
402 | |
| 403 | 403 | /* Set ADC group injected trigger source to SW start to ensure to not */ |
|
| 404 | /* Set ADC group injected trigger source to SW start to ensure to not */ |
404 | /* have an external trigger event occurring during the conversion stop */ |
| 405 | /* have an external trigger event occurring during the conversion stop */ |
405 | /* ADC disable process. */ |
| 406 | /* ADC disable process. */ |
406 | LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE); |
| 407 | LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE); |
407 | |
| 408 | 408 | /* Disable the ADC instance */ |
|
| 409 | /* Disable the ADC instance */ |
409 | LL_ADC_Disable(ADCx); |
| 410 | LL_ADC_Disable(ADCx); |
410 | } |
| 411 | } |
411 | |
| 412 | 412 | /* Check whether ADC state is compliant with expected state */ |
|
| 413 | /* Check whether ADC state is compliant with expected state */ |
413 | /* (hardware requirements of bits state to reset registers below) */ |
| 414 | /* (hardware requirements of bits state to reset registers below) */ |
414 | if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0U) |
| 415 | if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0U) |
415 | { |
| 416 | { |
416 | /* ========== Reset ADC registers ========== */ |
| 417 | /* ========== Reset ADC registers ========== */ |
417 | /* Reset register SR */ |
| 418 | /* Reset register SR */ |
418 | CLEAR_BIT(ADCx->SR, |
| 419 | CLEAR_BIT(ADCx->SR, |
419 | ( LL_ADC_FLAG_STRT |
| 420 | ( LL_ADC_FLAG_STRT |
420 | | LL_ADC_FLAG_JSTRT |
| 421 | | LL_ADC_FLAG_JSTRT |
421 | | LL_ADC_FLAG_EOS |
| 422 | | LL_ADC_FLAG_EOS |
422 | | LL_ADC_FLAG_JEOS |
| 423 | | LL_ADC_FLAG_JEOS |
423 | | LL_ADC_FLAG_AWD1 ) |
| 424 | | LL_ADC_FLAG_AWD1 ) |
424 | ); |
| 425 | ); |
425 | |
| 426 | 426 | /* Reset register CR1 */ |
|
| 427 | /* Reset register CR1 */ |
427 | #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) |
| 428 | #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) |
428 | |
| 429 | 429 | CLEAR_BIT(ADCx->CR1, |
|
| 430 | CLEAR_BIT(ADCx->CR1, |
430 | ( ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DUALMOD |
| 431 | ( ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DUALMOD |
431 | | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN |
| 432 | | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN |
432 | | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN |
| 433 | | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN |
433 | | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE |
| 434 | | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE |
434 | | ADC_CR1_AWDCH ) |
| 435 | | ADC_CR1_AWDCH ) |
435 | ); |
| 436 | ); |
436 | #else |
| 437 | #else |
437 | |
| 438 | 438 | CLEAR_BIT(ADCx->CR1, |
|
| 439 | CLEAR_BIT(ADCx->CR1, |
439 | ( ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DISCNUM |
| 440 | ( ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DISCNUM |
440 | | ADC_CR1_JDISCEN | ADC_CR1_DISCEN | ADC_CR1_JAUTO |
| 441 | | ADC_CR1_JDISCEN | ADC_CR1_DISCEN | ADC_CR1_JAUTO |
441 | | ADC_CR1_AWDSGL | ADC_CR1_SCAN | ADC_CR1_JEOCIE |
| 442 | | ADC_CR1_AWDSGL | ADC_CR1_SCAN | ADC_CR1_JEOCIE |
442 | | ADC_CR1_AWDIE | ADC_CR1_EOCIE | ADC_CR1_AWDCH ) |
| 443 | | ADC_CR1_AWDIE | ADC_CR1_EOCIE | ADC_CR1_AWDCH ) |
443 | ); |
| 444 | ); |
444 | #endif |
| 445 | #endif |
445 | |
| 446 | 446 | /* Reset register CR2 */ |
|
| 447 | /* Reset register CR2 */ |
447 | CLEAR_BIT(ADCx->CR2, |
| 448 | CLEAR_BIT(ADCx->CR2, |
448 | ( ADC_CR2_TSVREFE |
| 449 | ( ADC_CR2_TSVREFE |
449 | | ADC_CR2_SWSTART | ADC_CR2_EXTTRIG | ADC_CR2_EXTSEL |
| 450 | | ADC_CR2_SWSTART | ADC_CR2_EXTTRIG | ADC_CR2_EXTSEL |
450 | | ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL |
| 451 | | ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL |
451 | | ADC_CR2_ALIGN | ADC_CR2_DMA |
| 452 | | ADC_CR2_ALIGN | ADC_CR2_DMA |
452 | | ADC_CR2_RSTCAL | ADC_CR2_CAL |
| 453 | | ADC_CR2_RSTCAL | ADC_CR2_CAL |
453 | | ADC_CR2_CONT | ADC_CR2_ADON ) |
| 454 | | ADC_CR2_CONT | ADC_CR2_ADON ) |
454 | ); |
| 455 | ); |
455 | |
| 456 | 456 | /* Reset register SMPR1 */ |
|
| 457 | /* Reset register SMPR1 */ |
457 | CLEAR_BIT(ADCx->SMPR1, |
| 458 | CLEAR_BIT(ADCx->SMPR1, |
458 | ( ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16 |
| 459 | ( ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16 |
459 | | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13 |
| 460 | | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13 |
460 | | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10) |
| 461 | | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10) |
461 | ); |
| 462 | ); |
462 | |
| 463 | 463 | /* Reset register SMPR2 */ |
|
| 464 | /* Reset register SMPR2 */ |
464 | CLEAR_BIT(ADCx->SMPR2, |
| 465 | CLEAR_BIT(ADCx->SMPR2, |
465 | ( ADC_SMPR2_SMP9 |
| 466 | ( ADC_SMPR2_SMP9 |
466 | | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6 |
| 467 | | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6 |
467 | | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3 |
| 468 | | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3 |
468 | | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0) |
| 469 | | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0) |
469 | ); |
| 470 | ); |
470 | |
| 471 | 471 | /* Reset register JOFR1 */ |
|
| 472 | /* Reset register JOFR1 */ |
472 | CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1); |
| 473 | CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1); |
473 | /* Reset register JOFR2 */ |
| 474 | /* Reset register JOFR2 */ |
474 | CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2); |
| 475 | CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2); |
475 | /* Reset register JOFR3 */ |
| 476 | /* Reset register JOFR3 */ |
476 | CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3); |
| 477 | CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3); |
477 | /* Reset register JOFR4 */ |
| 478 | /* Reset register JOFR4 */ |
478 | CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4); |
| 479 | CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4); |
479 | |
| 480 | 480 | /* Reset register HTR */ |
|
| 481 | /* Reset register HTR */ |
481 | SET_BIT(ADCx->HTR, ADC_HTR_HT); |
| 482 | SET_BIT(ADCx->HTR, ADC_HTR_HT); |
482 | /* Reset register LTR */ |
| 483 | /* Reset register LTR */ |
483 | CLEAR_BIT(ADCx->LTR, ADC_LTR_LT); |
| 484 | CLEAR_BIT(ADCx->LTR, ADC_LTR_LT); |
484 | |
| 485 | 485 | /* Reset register SQR1 */ |
|
| 486 | /* Reset register SQR1 */ |
486 | CLEAR_BIT(ADCx->SQR1, |
| 487 | CLEAR_BIT(ADCx->SQR1, |
487 | ( ADC_SQR1_L |
| 488 | ( ADC_SQR1_L |
488 | | ADC_SQR1_SQ16 |
| 489 | | ADC_SQR1_SQ16 |
489 | | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13) |
| 490 | | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13) |
490 | ); |
| 491 | ); |
491 | |
| 492 | 492 | /* Reset register SQR2 */ |
|
| 493 | /* Reset register SQR2 */ |
493 | CLEAR_BIT(ADCx->SQR2, |
| 494 | CLEAR_BIT(ADCx->SQR2, |
494 | ( ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 |
| 495 | ( ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 |
495 | | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7) |
| 496 | | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7) |
496 | ); |
| 497 | ); |
497 | |
| 498 | 498 | /* Reset register SQR3 */ |
|
| 499 | /* Reset register SQR3 */ |
499 | CLEAR_BIT(ADCx->SQR3, |
| 500 | CLEAR_BIT(ADCx->SQR3, |
500 | ( ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4 |
| 501 | ( ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4 |
501 | | ADC_SQR3_SQ3 | ADC_SQR3_SQ2 | ADC_SQR3_SQ1) |
| 502 | | ADC_SQR3_SQ3 | ADC_SQR3_SQ2 | ADC_SQR3_SQ1) |
502 | ); |
| 503 | ); |
503 | |
| 504 | 504 | /* Reset register JSQR */ |
|
| 505 | /* Reset register JSQR */ |
505 | CLEAR_BIT(ADCx->JSQR, |
| 506 | CLEAR_BIT(ADCx->JSQR, |
506 | ( ADC_JSQR_JL |
| 507 | ( ADC_JSQR_JL |
507 | | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 |
| 508 | | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 |
508 | | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ) |
| 509 | | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ) |
509 | ); |
| 510 | ); |
510 | |
| 511 | 511 | /* Reset register DR */ |
|
| 512 | /* Reset register DR */ |
512 | /* bits in access mode read only, no direct reset applicable */ |
| 513 | /* bits in access mode read only, no direct reset applicable */ |
513 | |
| 514 | 514 | /* Reset registers JDR1, JDR2, JDR3, JDR4 */ |
|
| 515 | /* Reset registers JDR1, JDR2, JDR3, JDR4 */ |
515 | /* bits in access mode read only, no direct reset applicable */ |
| 516 | /* bits in access mode read only, no direct reset applicable */ |
516 | |
| 517 | 517 | } |
|
| 518 | } |
518 | |
| 519 | 519 | return status; |
|
| 520 | return status; |
520 | } |
| 521 | } |
521 | |
| 522 | 522 | /** |
|
| 523 | /** |
523 | * @brief Initialize some features of ADC instance. |
| 524 | * @brief Initialize some features of ADC instance. |
524 | * @note These parameters have an impact on ADC scope: ADC instance. |
| 525 | * @note These parameters have an impact on ADC scope: ADC instance. |
525 | * Affects both group regular and group injected (availability |
| 526 | * Affects both group regular and group injected (availability |
526 | * of ADC group injected depends on STM32 families). |
| 527 | * of ADC group injected depends on STM32 families). |
527 | * Refer to corresponding unitary functions into |
| 528 | * Refer to corresponding unitary functions into |
528 | * @ref ADC_LL_EF_Configuration_ADC_Instance . |
| 529 | * @ref ADC_LL_EF_Configuration_ADC_Instance . |
529 | * @note The setting of these parameters by function @ref LL_ADC_Init() |
| 530 | * @note The setting of these parameters by function @ref LL_ADC_Init() |
530 | * is conditioned to ADC state: |
| 531 | * is conditioned to ADC state: |
531 | * ADC instance must be disabled. |
| 532 | * ADC instance must be disabled. |
532 | * This condition is applied to all ADC features, for efficiency |
| 533 | * This condition is applied to all ADC features, for efficiency |
533 | * and compatibility over all STM32 families. However, the different |
| 534 | * and compatibility over all STM32 families. However, the different |
534 | * features can be set under different ADC state conditions |
| 535 | * features can be set under different ADC state conditions |
535 | * (setting possible with ADC enabled without conversion on going, |
| 536 | * (setting possible with ADC enabled without conversion on going, |
536 | * ADC enabled with conversion on going, ...) |
| 537 | * ADC enabled with conversion on going, ...) |
537 | * Each feature can be updated afterwards with a unitary function |
| 538 | * Each feature can be updated afterwards with a unitary function |
538 | * and potentially with ADC in a different state than disabled, |
| 539 | * and potentially with ADC in a different state than disabled, |
539 | * refer to description of each function for setting |
| 540 | * refer to description of each function for setting |
540 | * conditioned to ADC state. |
| 541 | * conditioned to ADC state. |
541 | * @note After using this function, some other features must be configured |
| 542 | * @note After using this function, some other features must be configured |
542 | * using LL unitary functions. |
| 543 | * using LL unitary functions. |
543 | * The minimum configuration remaining to be done is: |
| 544 | * The minimum configuration remaining to be done is: |
544 | * - Set ADC group regular or group injected sequencer: |
| 545 | * - Set ADC group regular or group injected sequencer: |
545 | * map channel on the selected sequencer rank. |
| 546 | * map channel on the selected sequencer rank. |
546 | * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). |
| 547 | * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). |
547 | * - Set ADC channel sampling time |
| 548 | * - Set ADC channel sampling time |
548 | * Refer to function LL_ADC_SetChannelSamplingTime(); |
| 549 | * Refer to function LL_ADC_SetChannelSamplingTime(); |
549 | * @param ADCx ADC instance |
| 550 | * @param ADCx ADC instance |
550 | * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure |
| 551 | * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure |
551 | * @retval An ErrorStatus enumeration value: |
| 552 | * @retval An ErrorStatus enumeration value: |
552 | * - SUCCESS: ADC registers are initialized |
| 553 | * - SUCCESS: ADC registers are initialized |
553 | * - ERROR: ADC registers are not initialized |
| 554 | * - ERROR: ADC registers are not initialized |
554 | */ |
| 555 | */ |
555 | ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) |
| 556 | ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) |
556 | { |
| 557 | { |
557 | ErrorStatus status = SUCCESS; |
| 558 | ErrorStatus status = SUCCESS; |
558 | |
| 559 | 559 | /* Check the parameters */ |
|
| 560 | /* Check the parameters */ |
560 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
| 561 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
561 | |
| 562 | 562 | assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment)); |
|
| 563 | assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment)); |
563 | assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode)); |
| 564 | assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode)); |
564 | |
| 565 | 565 | /* Note: Hardware constraint (refer to description of this function): */ |
|
| 566 | /* Note: Hardware constraint (refer to description of this function): */ |
566 | /* ADC instance must be disabled. */ |
| 567 | /* ADC instance must be disabled. */ |
567 | if(LL_ADC_IsEnabled(ADCx) == 0U) |
| 568 | if(LL_ADC_IsEnabled(ADCx) == 0U) |
568 | { |
| 569 | { |
569 | /* Configuration of ADC hierarchical scope: */ |
| 570 | /* Configuration of ADC hierarchical scope: */ |
570 | /* - ADC instance */ |
| 571 | /* - ADC instance */ |
571 | /* - Set ADC conversion data alignment */ |
| 572 | /* - Set ADC conversion data alignment */ |
572 | MODIFY_REG(ADCx->CR1, |
| 573 | MODIFY_REG(ADCx->CR1, |
573 | ADC_CR1_SCAN |
| 574 | ADC_CR1_SCAN |
574 | , |
| 575 | , |
575 | ADC_InitStruct->SequencersScanMode |
| 576 | ADC_InitStruct->SequencersScanMode |
576 | ); |
| 577 | ); |
577 | |
| 578 | 578 | MODIFY_REG(ADCx->CR2, |
|
| 579 | MODIFY_REG(ADCx->CR2, |
579 | ADC_CR2_ALIGN |
| 580 | ADC_CR2_ALIGN |
580 | , |
| 581 | , |
581 | ADC_InitStruct->DataAlignment |
| 582 | ADC_InitStruct->DataAlignment |
582 | ); |
| 583 | ); |
583 | |
| 584 | 584 | } |
|
| 585 | } |
585 | else |
| 586 | else |
586 | { |
| 587 | { |
587 | /* Initialization error: ADC instance is not disabled. */ |
| 588 | /* Initialization error: ADC instance is not disabled. */ |
588 | status = ERROR; |
| 589 | status = ERROR; |
589 | } |
| 590 | } |
590 | return status; |
| 591 | return status; |
591 | } |
| 592 | } |
592 | |
| 593 | 593 | /** |
|
| 594 | /** |
594 | * @brief Set each @ref LL_ADC_InitTypeDef field to default value. |
| 595 | * @brief Set each @ref LL_ADC_InitTypeDef field to default value. |
595 | * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure |
| 596 | * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure |
596 | * whose fields will be set to default values. |
| 597 | * whose fields will be set to default values. |
597 | * @retval None |
| 598 | * @retval None |
598 | */ |
| 599 | */ |
599 | void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) |
| 600 | void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) |
600 | { |
| 601 | { |
601 | /* Set ADC_InitStruct fields to default values */ |
| 602 | /* Set ADC_InitStruct fields to default values */ |
602 | /* Set fields of ADC instance */ |
| 603 | /* Set fields of ADC instance */ |
603 | ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; |
| 604 | ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; |
604 | |
| 605 | 605 | /* Enable scan mode to have a generic behavior with ADC of other */ |
|
| 606 | /* Enable scan mode to have a generic behavior with ADC of other */ |
606 | /* STM32 families, without this setting available: */ |
| 607 | /* STM32 families, without this setting available: */ |
607 | /* ADC group regular sequencer and ADC group injected sequencer depend */ |
| 608 | /* ADC group regular sequencer and ADC group injected sequencer depend */ |
608 | /* only of their own configuration. */ |
| 609 | /* only of their own configuration. */ |
609 | ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE; |
| 610 | ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE; |
610 | |
| 611 | 611 | } |
|
| 612 | } |
612 | |
| 613 | 613 | /** |
|
| 614 | /** |
614 | * @brief Initialize some features of ADC group regular. |
| 615 | * @brief Initialize some features of ADC group regular. |
615 | * @note These parameters have an impact on ADC scope: ADC group regular. |
| 616 | * @note These parameters have an impact on ADC scope: ADC group regular. |
616 | * Refer to corresponding unitary functions into |
| 617 | * Refer to corresponding unitary functions into |
617 | * @ref ADC_LL_EF_Configuration_ADC_Group_Regular |
| 618 | * @ref ADC_LL_EF_Configuration_ADC_Group_Regular |
618 | * (functions with prefix "REG"). |
| 619 | * (functions with prefix "REG"). |
619 | * @note The setting of these parameters by function @ref LL_ADC_Init() |
| 620 | * @note The setting of these parameters by function @ref LL_ADC_Init() |
620 | * is conditioned to ADC state: |
| 621 | * is conditioned to ADC state: |
621 | * ADC instance must be disabled. |
| 622 | * ADC instance must be disabled. |
622 | * This condition is applied to all ADC features, for efficiency |
| 623 | * This condition is applied to all ADC features, for efficiency |
623 | * and compatibility over all STM32 families. However, the different |
| 624 | * and compatibility over all STM32 families. However, the different |
624 | * features can be set under different ADC state conditions |
| 625 | * features can be set under different ADC state conditions |
625 | * (setting possible with ADC enabled without conversion on going, |
| 626 | * (setting possible with ADC enabled without conversion on going, |
626 | * ADC enabled with conversion on going, ...) |
| 627 | * ADC enabled with conversion on going, ...) |
627 | * Each feature can be updated afterwards with a unitary function |
| 628 | * Each feature can be updated afterwards with a unitary function |
628 | * and potentially with ADC in a different state than disabled, |
| 629 | * and potentially with ADC in a different state than disabled, |
629 | * refer to description of each function for setting |
| 630 | * refer to description of each function for setting |
630 | * conditioned to ADC state. |
| 631 | * conditioned to ADC state. |
631 | * @note After using this function, other features must be configured |
| 632 | * @note After using this function, other features must be configured |
632 | * using LL unitary functions. |
| 633 | * using LL unitary functions. |
633 | * The minimum configuration remaining to be done is: |
| 634 | * The minimum configuration remaining to be done is: |
634 | * - Set ADC group regular or group injected sequencer: |
| 635 | * - Set ADC group regular or group injected sequencer: |
635 | * map channel on the selected sequencer rank. |
| 636 | * map channel on the selected sequencer rank. |
636 | * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). |
| 637 | * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). |
637 | * - Set ADC channel sampling time |
| 638 | * - Set ADC channel sampling time |
638 | * Refer to function LL_ADC_SetChannelSamplingTime(); |
| 639 | * Refer to function LL_ADC_SetChannelSamplingTime(); |
639 | * @param ADCx ADC instance |
| 640 | * @param ADCx ADC instance |
640 | * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure |
| 641 | * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure |
641 | * @retval An ErrorStatus enumeration value: |
| 642 | * @retval An ErrorStatus enumeration value: |
642 | * - SUCCESS: ADC registers are initialized |
| 643 | * - SUCCESS: ADC registers are initialized |
643 | * - ERROR: ADC registers are not initialized |
| 644 | * - ERROR: ADC registers are not initialized |
644 | */ |
| 645 | */ |
645 | ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) |
| 646 | ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) |
646 | { |
| 647 | { |
647 | ErrorStatus status = SUCCESS; |
| 648 | ErrorStatus status = SUCCESS; |
648 | |
| 649 | 649 | /* Check the parameters */ |
|
| 650 | /* Check the parameters */ |
650 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
| 651 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
651 | #if defined(ADC3) |
| 652 | #if defined(ADC3) |
652 | assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADCx, ADC_REG_InitStruct->TriggerSource)); |
| 653 | assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADCx, ADC_REG_InitStruct->TriggerSource)); |
653 | #else |
| 654 | #else |
654 | assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource)); |
| 655 | assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource)); |
655 | #endif |
| 656 | #endif |
656 | assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength)); |
| 657 | assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength)); |
657 | if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) |
| 658 | if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) |
658 | { |
| 659 | { |
659 | assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); |
| 660 | assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); |
660 | } |
| 661 | } |
661 | assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); |
| 662 | assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); |
662 | assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); |
| 663 | assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); |
663 | |
| 664 | 664 | /* ADC group regular continuous mode and discontinuous mode */ |
|
| 665 | /* ADC group regular continuous mode and discontinuous mode */ |
665 | /* can not be enabled simultenaeously */ |
| 666 | /* can not be enabled simultenaeously */ |
666 | assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE) |
| 667 | assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE) |
667 | || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE)); |
| 668 | || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE)); |
668 | |
| 669 | 669 | /* Note: Hardware constraint (refer to description of this function): */ |
|
| 670 | /* Note: Hardware constraint (refer to description of this function): */ |
670 | /* ADC instance must be disabled. */ |
| 671 | /* ADC instance must be disabled. */ |
671 | if(LL_ADC_IsEnabled(ADCx) == 0U) |
| 672 | if(LL_ADC_IsEnabled(ADCx) == 0U) |
672 | { |
| 673 | { |
673 | /* Configuration of ADC hierarchical scope: */ |
| 674 | /* Configuration of ADC hierarchical scope: */ |
674 | /* - ADC group regular */ |
| 675 | /* - ADC group regular */ |
675 | /* - Set ADC group regular trigger source */ |
| 676 | /* - Set ADC group regular trigger source */ |
676 | /* - Set ADC group regular sequencer length */ |
| 677 | /* - Set ADC group regular sequencer length */ |
677 | /* - Set ADC group regular sequencer discontinuous mode */ |
| 678 | /* - Set ADC group regular sequencer discontinuous mode */ |
678 | /* - Set ADC group regular continuous mode */ |
| 679 | /* - Set ADC group regular continuous mode */ |
679 | /* - Set ADC group regular conversion data transfer: no transfer or */ |
| 680 | /* - Set ADC group regular conversion data transfer: no transfer or */ |
680 | /* transfer by DMA, and DMA requests mode */ |
| 681 | /* transfer by DMA, and DMA requests mode */ |
681 | /* Note: On this STM32 series, ADC trigger edge is set when starting */ |
| 682 | /* Note: On this STM32 serie, ADC trigger edge is set when starting */ |
682 | /* ADC conversion. */ |
| 683 | /* ADC conversion. */ |
683 | /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */ |
| 684 | /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */ |
684 | if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) |
| 685 | if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) |
685 | { |
| 686 | { |
686 | MODIFY_REG(ADCx->CR1, |
| 687 | MODIFY_REG(ADCx->CR1, |
687 | ADC_CR1_DISCEN |
| 688 | ADC_CR1_DISCEN |
688 | | ADC_CR1_DISCNUM |
| 689 | | ADC_CR1_DISCNUM |
689 | , |
| 690 | , |
690 | ADC_REG_InitStruct->SequencerLength |
| 691 | ADC_REG_InitStruct->SequencerLength |
691 | | ADC_REG_InitStruct->SequencerDiscont |
| 692 | | ADC_REG_InitStruct->SequencerDiscont |
692 | ); |
| 693 | ); |
693 | } |
| 694 | } |
694 | else |
| 695 | else |
695 | { |
| 696 | { |
696 | MODIFY_REG(ADCx->CR1, |
| 697 | MODIFY_REG(ADCx->CR1, |
697 | ADC_CR1_DISCEN |
| 698 | ADC_CR1_DISCEN |
698 | | ADC_CR1_DISCNUM |
| 699 | | ADC_CR1_DISCNUM |
699 | , |
| 700 | , |
700 | ADC_REG_InitStruct->SequencerLength |
| 701 | ADC_REG_InitStruct->SequencerLength |
701 | | LL_ADC_REG_SEQ_DISCONT_DISABLE |
| 702 | | LL_ADC_REG_SEQ_DISCONT_DISABLE |
702 | ); |
| 703 | ); |
703 | } |
| 704 | } |
704 | |
| 705 | 705 | MODIFY_REG(ADCx->CR2, |
|
| 706 | MODIFY_REG(ADCx->CR2, |
706 | ADC_CR2_EXTSEL |
| 707 | ADC_CR2_EXTSEL |
707 | | ADC_CR2_CONT |
| 708 | | ADC_CR2_CONT |
708 | | ADC_CR2_DMA |
| 709 | | ADC_CR2_DMA |
709 | , |
| 710 | , |
710 | ADC_REG_InitStruct->TriggerSource |
| 711 | ADC_REG_InitStruct->TriggerSource |
711 | | ADC_REG_InitStruct->ContinuousMode |
| 712 | | ADC_REG_InitStruct->ContinuousMode |
712 | | ADC_REG_InitStruct->DMATransfer |
| 713 | | ADC_REG_InitStruct->DMATransfer |
713 | ); |
| 714 | ); |
714 | |
| 715 | 715 | /* Set ADC group regular sequencer length and scan direction */ |
|
| 716 | /* Set ADC group regular sequencer length and scan direction */ |
716 | /* Note: Hardware constraint (refer to description of this function): */ |
| 717 | /* Note: Hardware constraint (refer to description of this function): */ |
717 | /* Note: If ADC instance feature scan mode is disabled */ |
| 718 | /* Note: If ADC instance feature scan mode is disabled */ |
718 | /* (refer to ADC instance initialization structure */ |
| 719 | /* (refer to ADC instance initialization structure */ |
719 | /* parameter @ref SequencersScanMode */ |
| 720 | /* parameter @ref SequencersScanMode */ |
720 | /* or function @ref LL_ADC_SetSequencersScanMode() ), */ |
| 721 | /* or function @ref LL_ADC_SetSequencersScanMode() ), */ |
721 | /* this parameter is discarded. */ |
| 722 | /* this parameter is discarded. */ |
722 | LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength); |
| 723 | LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength); |
723 | } |
| 724 | } |
724 | else |
| 725 | else |
725 | { |
| 726 | { |
726 | /* Initialization error: ADC instance is not disabled. */ |
| 727 | /* Initialization error: ADC instance is not disabled. */ |
727 | status = ERROR; |
| 728 | status = ERROR; |
728 | } |
| 729 | } |
729 | return status; |
| 730 | return status; |
730 | } |
| 731 | } |
731 | |
| 732 | 732 | /** |
|
| 733 | /** |
733 | * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value. |
| 734 | * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value. |
734 | * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure |
| 735 | * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure |
735 | * whose fields will be set to default values. |
| 736 | * whose fields will be set to default values. |
736 | * @retval None |
| 737 | * @retval None |
737 | */ |
| 738 | */ |
738 | void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) |
| 739 | void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) |
739 | { |
| 740 | { |
740 | /* Set ADC_REG_InitStruct fields to default values */ |
| 741 | /* Set ADC_REG_InitStruct fields to default values */ |
741 | /* Set fields of ADC group regular */ |
| 742 | /* Set fields of ADC group regular */ |
742 | /* Note: On this STM32 series, ADC trigger edge is set when starting */ |
| 743 | /* Note: On this STM32 serie, ADC trigger edge is set when starting */ |
743 | /* ADC conversion. */ |
| 744 | /* ADC conversion. */ |
744 | /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */ |
| 745 | /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */ |
745 | ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; |
| 746 | ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; |
746 | ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE; |
| 747 | ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE; |
747 | ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE; |
| 748 | ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE; |
748 | ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE; |
| 749 | ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE; |
749 | ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE; |
| 750 | ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE; |
750 | } |
| 751 | } |
751 | |
| 752 | 752 | /** |
|
| 753 | /** |
753 | * @brief Initialize some features of ADC group injected. |
| 754 | * @brief Initialize some features of ADC group injected. |
754 | * @note These parameters have an impact on ADC scope: ADC group injected. |
| 755 | * @note These parameters have an impact on ADC scope: ADC group injected. |
755 | * Refer to corresponding unitary functions into |
| 756 | * Refer to corresponding unitary functions into |
756 | * @ref ADC_LL_EF_Configuration_ADC_Group_Regular |
| 757 | * @ref ADC_LL_EF_Configuration_ADC_Group_Regular |
757 | * (functions with prefix "INJ"). |
| 758 | * (functions with prefix "INJ"). |
758 | * @note The setting of these parameters by function @ref LL_ADC_Init() |
| 759 | * @note The setting of these parameters by function @ref LL_ADC_Init() |
759 | * is conditioned to ADC state: |
| 760 | * is conditioned to ADC state: |
760 | * ADC instance must be disabled. |
| 761 | * ADC instance must be disabled. |
761 | * This condition is applied to all ADC features, for efficiency |
| 762 | * This condition is applied to all ADC features, for efficiency |
762 | * and compatibility over all STM32 families. However, the different |
| 763 | * and compatibility over all STM32 families. However, the different |
763 | * features can be set under different ADC state conditions |
| 764 | * features can be set under different ADC state conditions |
764 | * (setting possible with ADC enabled without conversion on going, |
| 765 | * (setting possible with ADC enabled without conversion on going, |
765 | * ADC enabled with conversion on going, ...) |
| 766 | * ADC enabled with conversion on going, ...) |
766 | * Each feature can be updated afterwards with a unitary function |
| 767 | * Each feature can be updated afterwards with a unitary function |
767 | * and potentially with ADC in a different state than disabled, |
| 768 | * and potentially with ADC in a different state than disabled, |
768 | * refer to description of each function for setting |
| 769 | * refer to description of each function for setting |
769 | * conditioned to ADC state. |
| 770 | * conditioned to ADC state. |
770 | * @note After using this function, other features must be configured |
| 771 | * @note After using this function, other features must be configured |
771 | * using LL unitary functions. |
| 772 | * using LL unitary functions. |
772 | * The minimum configuration remaining to be done is: |
| 773 | * The minimum configuration remaining to be done is: |
773 | * - Set ADC group injected sequencer: |
| 774 | * - Set ADC group injected sequencer: |
774 | * map channel on the selected sequencer rank. |
| 775 | * map channel on the selected sequencer rank. |
775 | * Refer to function @ref LL_ADC_INJ_SetSequencerRanks(). |
| 776 | * Refer to function @ref LL_ADC_INJ_SetSequencerRanks(). |
776 | * - Set ADC channel sampling time |
| 777 | * - Set ADC channel sampling time |
777 | * Refer to function LL_ADC_SetChannelSamplingTime(); |
| 778 | * Refer to function LL_ADC_SetChannelSamplingTime(); |
778 | * @param ADCx ADC instance |
| 779 | * @param ADCx ADC instance |
779 | * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure |
| 780 | * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure |
780 | * @retval An ErrorStatus enumeration value: |
| 781 | * @retval An ErrorStatus enumeration value: |
781 | * - SUCCESS: ADC registers are initialized |
| 782 | * - SUCCESS: ADC registers are initialized |
782 | * - ERROR: ADC registers are not initialized |
| 783 | * - ERROR: ADC registers are not initialized |
783 | */ |
| 784 | */ |
784 | ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) |
| 785 | ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) |
785 | { |
| 786 | { |
786 | ErrorStatus status = SUCCESS; |
| 787 | ErrorStatus status = SUCCESS; |
787 | |
| 788 | 788 | /* Check the parameters */ |
|
| 789 | /* Check the parameters */ |
789 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
| 790 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
790 | #if defined(ADC3) |
| 791 | #if defined(ADC3) |
791 | assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADCx, ADC_INJ_InitStruct->TriggerSource)); |
| 792 | assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADCx, ADC_INJ_InitStruct->TriggerSource)); |
792 | #else |
| 793 | #else |
793 | assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource)); |
| 794 | assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource)); |
794 | #endif |
| 795 | #endif |
795 | assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength)); |
| 796 | assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength)); |
796 | if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) |
| 797 | if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) |
797 | { |
| 798 | { |
798 | assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont)); |
| 799 | assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont)); |
799 | } |
| 800 | } |
800 | assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto)); |
| 801 | assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto)); |
801 | |
| 802 | 802 | /* Note: Hardware constraint (refer to description of this function): */ |
|
| 803 | /* Note: Hardware constraint (refer to description of this function): */ |
803 | /* ADC instance must be disabled. */ |
| 804 | /* ADC instance must be disabled. */ |
804 | if(LL_ADC_IsEnabled(ADCx) == 0U) |
| 805 | if(LL_ADC_IsEnabled(ADCx) == 0U) |
805 | { |
| 806 | { |
806 | /* Configuration of ADC hierarchical scope: */ |
| 807 | /* Configuration of ADC hierarchical scope: */ |
807 | /* - ADC group injected */ |
| 808 | /* - ADC group injected */ |
808 | /* - Set ADC group injected trigger source */ |
| 809 | /* - Set ADC group injected trigger source */ |
809 | /* - Set ADC group injected sequencer length */ |
| 810 | /* - Set ADC group injected sequencer length */ |
810 | /* - Set ADC group injected sequencer discontinuous mode */ |
| 811 | /* - Set ADC group injected sequencer discontinuous mode */ |
811 | /* - Set ADC group injected conversion trigger: independent or */ |
| 812 | /* - Set ADC group injected conversion trigger: independent or */ |
812 | /* from ADC group regular */ |
| 813 | /* from ADC group regular */ |
813 | /* Note: On this STM32 series, ADC trigger edge is set when starting */ |
| 814 | /* Note: On this STM32 serie, ADC trigger edge is set when starting */ |
814 | /* ADC conversion. */ |
| 815 | /* ADC conversion. */ |
815 | /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */ |
| 816 | /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */ |
816 | if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) |
| 817 | if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) |
817 | { |
| 818 | { |
818 | MODIFY_REG(ADCx->CR1, |
| 819 | MODIFY_REG(ADCx->CR1, |
819 | ADC_CR1_JDISCEN |
| 820 | ADC_CR1_JDISCEN |
820 | | ADC_CR1_JAUTO |
| 821 | | ADC_CR1_JAUTO |
821 | , |
| 822 | , |
822 | ADC_INJ_InitStruct->SequencerDiscont |
| 823 | ADC_INJ_InitStruct->SequencerDiscont |
823 | | ADC_INJ_InitStruct->TrigAuto |
| 824 | | ADC_INJ_InitStruct->TrigAuto |
824 | ); |
| 825 | ); |
825 | } |
| 826 | } |
826 | else |
| 827 | else |
827 | { |
| 828 | { |
828 | MODIFY_REG(ADCx->CR1, |
| 829 | MODIFY_REG(ADCx->CR1, |
829 | ADC_CR1_JDISCEN |
| 830 | ADC_CR1_JDISCEN |
830 | | ADC_CR1_JAUTO |
| 831 | | ADC_CR1_JAUTO |
831 | , |
| 832 | , |
832 | LL_ADC_REG_SEQ_DISCONT_DISABLE |
| 833 | LL_ADC_REG_SEQ_DISCONT_DISABLE |
833 | | ADC_INJ_InitStruct->TrigAuto |
| 834 | | ADC_INJ_InitStruct->TrigAuto |
834 | ); |
| 835 | ); |
835 | } |
| 836 | } |
836 | |
| 837 | 837 | MODIFY_REG(ADCx->CR2, |
|
| 838 | MODIFY_REG(ADCx->CR2, |
838 | ADC_CR2_JEXTSEL |
| 839 | ADC_CR2_JEXTSEL |
839 | , |
| 840 | , |
840 | ADC_INJ_InitStruct->TriggerSource |
| 841 | ADC_INJ_InitStruct->TriggerSource |
841 | ); |
| 842 | ); |
842 | |
| 843 | 843 | /* Note: Hardware constraint (refer to description of this function): */ |
|
| 844 | /* Note: Hardware constraint (refer to description of this function): */ |
844 | /* Note: If ADC instance feature scan mode is disabled */ |
| 845 | /* Note: If ADC instance feature scan mode is disabled */ |
845 | /* (refer to ADC instance initialization structure */ |
| 846 | /* (refer to ADC instance initialization structure */ |
846 | /* parameter @ref SequencersScanMode */ |
| 847 | /* parameter @ref SequencersScanMode */ |
847 | /* or function @ref LL_ADC_SetSequencersScanMode() ), */ |
| 848 | /* or function @ref LL_ADC_SetSequencersScanMode() ), */ |
848 | /* this parameter is discarded. */ |
| 849 | /* this parameter is discarded. */ |
849 | LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength); |
| 850 | LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength); |
850 | } |
| 851 | } |
851 | else |
| 852 | else |
852 | { |
| 853 | { |
853 | /* Initialization error: ADC instance is not disabled. */ |
| 854 | /* Initialization error: ADC instance is not disabled. */ |
854 | status = ERROR; |
| 855 | status = ERROR; |
855 | } |
| 856 | } |
856 | return status; |
| 857 | return status; |
857 | } |
| 858 | } |
858 | |
| 859 | 859 | /** |
|
| 860 | /** |
860 | * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value. |
| 861 | * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value. |
861 | * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure |
| 862 | * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure |
862 | * whose fields will be set to default values. |
| 863 | * whose fields will be set to default values. |
863 | * @retval None |
| 864 | * @retval None |
864 | */ |
| 865 | */ |
865 | void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) |
| 866 | void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) |
866 | { |
| 867 | { |
867 | /* Set ADC_INJ_InitStruct fields to default values */ |
| 868 | /* Set ADC_INJ_InitStruct fields to default values */ |
868 | /* Set fields of ADC group injected */ |
| 869 | /* Set fields of ADC group injected */ |
869 | ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE; |
| 870 | ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE; |
870 | ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE; |
| 871 | ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE; |
871 | ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE; |
| 872 | ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE; |
872 | ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT; |
| 873 | ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT; |
873 | } |
| 874 | } |
874 | |
| 875 | 875 | /** |
|
| 876 | /** |
876 | * @} |
| 877 | * @} |
877 | */ |
| 878 | */ |
878 | |
| 879 | 879 | /** |
|
| 880 | /** |
880 | * @} |
| 881 | * @} |
881 | */ |
| 882 | */ |
882 | |
| 883 | 883 | /** |
|
| 884 | /** |
884 | * @} |
| 885 | * @} |
885 | */ |
| 886 | */ |
886 | |
| 887 | 887 | #endif /* ADC1 || ADC2 || ADC3 */ |
|
| 888 | #endif /* ADC1 || ADC2 || ADC3 */ |
888 | |
| 889 | 889 | /** |
|
| 890 | /** |
890 | * @} |
| 891 | * @} |
891 | */ |
| 892 | */ |
892 | |
| 893 | 893 | #endif /* USE_FULL_LL_DRIVER */ |
|
| 894 | #endif /* USE_FULL_LL_DRIVER */ |
- | |
| 895 | - | ||
| 896 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
- | |