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5 | * @brief TIM HAL module driver. |
5 | * @brief TIM HAL module driver. |
6 | * This file provides firmware functions to manage the following |
6 | * This file provides firmware functions to manage the following |
7 | * functionalities of the Timer Extended peripheral: |
7 | * functionalities of the Timer Extended peripheral: |
8 | * + Time Hall Sensor Interface Initialization |
8 | * + Time Hall Sensor Interface Initialization |
9 | * + Time Hall Sensor Interface Start |
9 | * + Time Hall Sensor Interface Start |
10 | * + Time Complementary signal bread and dead time configuration |
10 | * + Time Complementary signal break and dead time configuration |
11 | * + Time Master and Slave synchronization configuration |
11 | * + Time Master and Slave synchronization configuration |
12 | * + Timer remapping capabilities configuration |
12 | * + Timer remapping capabilities configuration |
13 | @verbatim |
13 | @verbatim |
14 | ============================================================================== |
14 | ============================================================================== |
15 | ##### TIMER Extended features ##### |
15 | ##### TIMER Extended features ##### |
Line 28... | Line 28... | ||
28 | 28 | ||
29 | ##### How to use this driver ##### |
29 | ##### How to use this driver ##### |
30 | ============================================================================== |
30 | ============================================================================== |
31 | [..] |
31 | [..] |
32 | (#) Initialize the TIM low level resources by implementing the following functions |
32 | (#) Initialize the TIM low level resources by implementing the following functions |
33 | depending from feature used : |
33 | depending on the selected feature: |
34 | (++) Complementary Output Compare : HAL_TIM_OC_MspInit() |
- | |
35 | (++) Complementary PWM generation : HAL_TIM_PWM_MspInit() |
- | |
36 | (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit() |
- | |
37 | (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit() |
34 | (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit() |
38 | 35 | ||
39 | (#) Initialize the TIM low level resources : |
36 | (#) Initialize the TIM low level resources : |
40 | (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); |
37 | (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); |
41 | (##) TIM pins configuration |
38 | (##) TIM pins configuration |
Line 48... | Line 45... | ||
48 | HAL_TIM_ConfigClockSource, the clock configuration should be done before |
45 | HAL_TIM_ConfigClockSource, the clock configuration should be done before |
49 | any start function. |
46 | any start function. |
50 | 47 | ||
51 | (#) Configure the TIM in the desired functioning mode using one of the |
48 | (#) Configure the TIM in the desired functioning mode using one of the |
52 | initialization function of this driver: |
49 | initialization function of this driver: |
53 | (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the |
50 | (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the |
54 | Timer Hall Sensor Interface and the commutation event with the corresponding |
51 | Timer Hall Sensor Interface and the commutation event with the corresponding |
55 | Interrupt and DMA request if needed (Note that One Timer is used to interface |
52 | Interrupt and DMA request if needed (Note that One Timer is used to interface |
56 | with the Hall sensor Interface and another Timer should be used to use |
53 | with the Hall sensor Interface and another Timer should be used to use |
57 | the commutation event). |
54 | the commutation event). |
58 | 55 | ||
59 | (#) Activate the TIM peripheral using one of the start functions: |
56 | (#) Activate the TIM peripheral using one of the start functions: |
60 | (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT() |
57 | (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT() |
61 | (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT() |
58 | (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT() |
62 | (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() |
59 | (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() |
63 | (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(). |
60 | (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(). |
64 | 61 | ||
65 | - | ||
66 | @endverbatim |
62 | @endverbatim |
67 | ****************************************************************************** |
63 | ****************************************************************************** |
68 | * @attention |
64 | * @attention |
69 | * |
65 | * |
70 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
66 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
71 | * |
- | |
72 | * Redistribution and use in source and binary forms, with or without modification, |
- | |
73 | * are permitted provided that the following conditions are met: |
- | |
74 | * 1. Redistributions of source code must retain the above copyright notice, |
- | |
75 | * this list of conditions and the following disclaimer. |
- | |
76 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
- | |
77 | * this list of conditions and the following disclaimer in the documentation |
- | |
78 | * and/or other materials provided with the distribution. |
- | |
79 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
- | |
80 | * may be used to endorse or promote products derived from this software |
- | |
81 | * without specific prior written permission. |
67 | * All rights reserved.</center></h2> |
82 | * |
68 | * |
83 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
69 | * This software component is licensed by ST under BSD 3-Clause license, |
84 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
- | |
85 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
- | |
86 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
- | |
87 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
- | |
88 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
70 | * the "License"; You may not use this file except in compliance with the |
89 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
71 | * License. You may obtain a copy of the License at: |
90 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
- | |
91 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
- | |
92 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
72 | * opensource.org/licenses/BSD-3-Clause |
93 | * |
73 | * |
94 | ****************************************************************************** |
74 | ****************************************************************************** |
95 | */ |
75 | */ |
96 | 76 | ||
97 | /* Includes ------------------------------------------------------------------*/ |
77 | /* Includes ------------------------------------------------------------------*/ |
98 | #include "stm32f1xx_hal.h" |
78 | #include "stm32f1xx_hal.h" |
99 | 79 | ||
100 | /** @addtogroup STM32F1xx_HAL_Driver |
80 | /** @addtogroup STM32F1xx_HAL_Driver |
Line 108... | Line 88... | ||
108 | 88 | ||
109 | #ifdef HAL_TIM_MODULE_ENABLED |
89 | #ifdef HAL_TIM_MODULE_ENABLED |
110 | 90 | ||
111 | /* Private typedef -----------------------------------------------------------*/ |
91 | /* Private typedef -----------------------------------------------------------*/ |
112 | /* Private define ------------------------------------------------------------*/ |
92 | /* Private define ------------------------------------------------------------*/ |
113 | /* Private macro -------------------------------------------------------------*/ |
93 | /* Private macros ------------------------------------------------------------*/ |
114 | /* Private variables ---------------------------------------------------------*/ |
94 | /* Private variables ---------------------------------------------------------*/ |
115 | /* Private function prototypes -----------------------------------------------*/ |
95 | /* Private function prototypes -----------------------------------------------*/ |
- | 96 | static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma); |
|
- | 97 | static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma); |
|
- | 98 | static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); |
|
116 | 99 | ||
117 | #if defined (STM32F100xB) || defined (STM32F100xE) || \ |
- | |
118 | defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \ |
- | |
119 | defined (STM32F105xC) || defined (STM32F107xC) |
- | |
120 | /** @defgroup TIMEx_Private_Functions TIMEx Private Functions |
- | |
121 | * @{ |
- | |
122 | */ |
- | |
123 | static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState); |
- | |
124 | /** |
- | |
125 | * @} |
- | |
126 | */ |
- | |
127 | #endif /* defined(STM32F100xB) || defined(STM32F100xE) || */ |
- | |
128 | /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */ |
- | |
129 | /* defined(STM32F105xC) || defined(STM32F107xC) */ |
- | |
130 | - | ||
131 | /* Exported functions ---------------------------------------------------------*/ |
100 | /* Exported functions --------------------------------------------------------*/ |
132 | - | ||
133 | /** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions |
101 | /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions |
134 | * @{ |
102 | * @{ |
135 | */ |
103 | */ |
136 | 104 | ||
137 | - | ||
138 | /** @defgroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions |
105 | /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions |
139 | * @brief Timer Hall Sensor functions |
106 | * @brief Timer Hall Sensor functions |
140 | * |
107 | * |
141 | @verbatim |
108 | @verbatim |
142 | ============================================================================== |
109 | ============================================================================== |
143 | ##### Timer Hall Sensor functions ##### |
110 | ##### Timer Hall Sensor functions ##### |
144 | ============================================================================== |
111 | ============================================================================== |
145 | [..] |
112 | [..] |
Line 155... | Line 122... | ||
155 | 122 | ||
156 | @endverbatim |
123 | @endverbatim |
157 | * @{ |
124 | * @{ |
158 | */ |
125 | */ |
159 | /** |
126 | /** |
160 | * @brief Initializes the TIM Hall Sensor Interface and create the associated handle. |
127 | * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. |
- | 128 | * @note When the timer instance is initialized in Hall Sensor Interface mode, |
|
- | 129 | * timer channels 1 and channel 2 are reserved and cannot be used for |
|
- | 130 | * other purpose. |
|
161 | * @param htim : TIM Encoder Interface handle |
131 | * @param htim TIM Hall Sensor Interface handle |
162 | * @param sConfig : TIM Hall Sensor configuration structure |
132 | * @param sConfig TIM Hall Sensor configuration structure |
163 | * @retval HAL status |
133 | * @retval HAL status |
164 | */ |
134 | */ |
165 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig) |
135 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig) |
166 | { |
136 | { |
167 | TIM_OC_InitTypeDef OC_Config; |
137 | TIM_OC_InitTypeDef OC_Config; |
168 | 138 | ||
169 | /* Check the TIM handle allocation */ |
139 | /* Check the TIM handle allocation */ |
170 | if(htim == NULL) |
140 | if (htim == NULL) |
171 | { |
141 | { |
172 | return HAL_ERROR; |
142 | return HAL_ERROR; |
173 | } |
143 | } |
174 | 144 | ||
- | 145 | /* Check the parameters */ |
|
175 | assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); |
146 | assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); |
176 | assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); |
147 | assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); |
177 | assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); |
148 | assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); |
178 | assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); |
149 | assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); |
179 | assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); |
150 | assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); |
180 | assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); |
151 | assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); |
181 | assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); |
152 | assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); |
182 | 153 | ||
183 | if(htim->State == HAL_TIM_STATE_RESET) |
154 | if (htim->State == HAL_TIM_STATE_RESET) |
184 | { |
155 | { |
185 | /* Allocate lock resource and initialize it */ |
156 | /* Allocate lock resource and initialize it */ |
186 | htim->Lock = HAL_UNLOCKED; |
157 | htim->Lock = HAL_UNLOCKED; |
- | 158 | ||
- | 159 | #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
|
- | 160 | /* Reset interrupt callbacks to legacy week callbacks */ |
|
- | 161 | TIM_ResetCallback(htim); |
|
- | 162 | ||
- | 163 | if (htim->HallSensor_MspInitCallback == NULL) |
|
187 | 164 | { |
|
- | 165 | htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; |
|
- | 166 | } |
|
- | 167 | /* Init the low level hardware : GPIO, CLOCK, NVIC */ |
|
- | 168 | htim->HallSensor_MspInitCallback(htim); |
|
- | 169 | #else |
|
188 | /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ |
170 | /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ |
189 | HAL_TIMEx_HallSensor_MspInit(htim); |
171 | HAL_TIMEx_HallSensor_MspInit(htim); |
- | 172 | #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
|
190 | } |
173 | } |
191 | 174 | ||
192 | /* Set the TIM state */ |
175 | /* Set the TIM state */ |
193 | htim->State= HAL_TIM_STATE_BUSY; |
176 | htim->State = HAL_TIM_STATE_BUSY; |
194 | 177 | ||
195 | /* Configure the Time base in the Encoder Mode */ |
178 | /* Configure the Time base in the Encoder Mode */ |
196 | TIM_Base_SetConfig(htim->Instance, &htim->Init); |
179 | TIM_Base_SetConfig(htim->Instance, &htim->Init); |
197 | 180 | ||
198 | /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ |
181 | /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ |
Line 228... | Line 211... | ||
228 | /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 |
211 | /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 |
229 | register to 101 */ |
212 | register to 101 */ |
230 | htim->Instance->CR2 &= ~TIM_CR2_MMS; |
213 | htim->Instance->CR2 &= ~TIM_CR2_MMS; |
231 | htim->Instance->CR2 |= TIM_TRGO_OC2REF; |
214 | htim->Instance->CR2 |= TIM_TRGO_OC2REF; |
232 | 215 | ||
- | 216 | /* Initialize the DMA burst operation state */ |
|
- | 217 | htim->DMABurstState = HAL_DMA_BURST_STATE_READY; |
|
- | 218 | ||
- | 219 | /* Initialize the TIM channels state */ |
|
- | 220 | TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); |
|
- | 221 | TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); |
|
- | 222 | TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); |
|
- | 223 | TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); |
|
- | 224 | ||
233 | /* Initialize the TIM state*/ |
225 | /* Initialize the TIM state*/ |
234 | htim->State= HAL_TIM_STATE_READY; |
226 | htim->State = HAL_TIM_STATE_READY; |
235 | 227 | ||
236 | return HAL_OK; |
228 | return HAL_OK; |
237 | } |
229 | } |
238 | 230 | ||
239 | /** |
231 | /** |
240 | * @brief DeInitializes the TIM Hall Sensor interface |
232 | * @brief DeInitializes the TIM Hall Sensor interface |
241 | * @param htim : TIM Hall Sensor handle |
233 | * @param htim TIM Hall Sensor Interface handle |
242 | * @retval HAL status |
234 | * @retval HAL status |
243 | */ |
235 | */ |
244 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) |
236 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) |
245 | { |
237 | { |
246 | /* Check the parameters */ |
238 | /* Check the parameters */ |
Line 249... | Line 241... | ||
249 | htim->State = HAL_TIM_STATE_BUSY; |
241 | htim->State = HAL_TIM_STATE_BUSY; |
250 | 242 | ||
251 | /* Disable the TIM Peripheral Clock */ |
243 | /* Disable the TIM Peripheral Clock */ |
252 | __HAL_TIM_DISABLE(htim); |
244 | __HAL_TIM_DISABLE(htim); |
253 | 245 | ||
- | 246 | #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
|
- | 247 | if (htim->HallSensor_MspDeInitCallback == NULL) |
|
- | 248 | { |
|
- | 249 | htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; |
|
- | 250 | } |
|
- | 251 | /* DeInit the low level hardware */ |
|
- | 252 | htim->HallSensor_MspDeInitCallback(htim); |
|
- | 253 | #else |
|
254 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ |
254 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ |
255 | HAL_TIMEx_HallSensor_MspDeInit(htim); |
255 | HAL_TIMEx_HallSensor_MspDeInit(htim); |
- | 256 | #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
|
- | 257 | ||
- | 258 | /* Change the DMA burst operation state */ |
|
- | 259 | htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; |
|
- | 260 | ||
- | 261 | /* Change the TIM channels state */ |
|
- | 262 | TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); |
|
- | 263 | TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); |
|
- | 264 | TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); |
|
- | 265 | TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); |
|
256 | 266 | ||
257 | /* Change TIM state */ |
267 | /* Change TIM state */ |
258 | htim->State = HAL_TIM_STATE_RESET; |
268 | htim->State = HAL_TIM_STATE_RESET; |
259 | 269 | ||
260 | /* Release Lock */ |
270 | /* Release Lock */ |
Line 263... | Line 273... | ||
263 | return HAL_OK; |
273 | return HAL_OK; |
264 | } |
274 | } |
265 | 275 | ||
266 | /** |
276 | /** |
267 | * @brief Initializes the TIM Hall Sensor MSP. |
277 | * @brief Initializes the TIM Hall Sensor MSP. |
268 | * @param htim : TIM handle |
278 | * @param htim TIM Hall Sensor Interface handle |
269 | * @retval None |
279 | * @retval None |
270 | */ |
280 | */ |
271 | __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) |
281 | __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) |
272 | { |
282 | { |
273 | /* Prevent unused argument(s) compilation warning */ |
283 | /* Prevent unused argument(s) compilation warning */ |
274 | UNUSED(htim); |
284 | UNUSED(htim); |
- | 285 | ||
275 | /* NOTE : This function Should not be modified, when the callback is needed, |
286 | /* NOTE : This function should not be modified, when the callback is needed, |
276 | the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file |
287 | the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file |
277 | */ |
288 | */ |
278 | } |
289 | } |
279 | 290 | ||
280 | /** |
291 | /** |
281 | * @brief DeInitializes TIM Hall Sensor MSP. |
292 | * @brief DeInitializes TIM Hall Sensor MSP. |
282 | * @param htim : TIM handle |
293 | * @param htim TIM Hall Sensor Interface handle |
283 | * @retval None |
294 | * @retval None |
284 | */ |
295 | */ |
285 | __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) |
296 | __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) |
286 | { |
297 | { |
287 | /* Prevent unused argument(s) compilation warning */ |
298 | /* Prevent unused argument(s) compilation warning */ |
288 | UNUSED(htim); |
299 | UNUSED(htim); |
- | 300 | ||
289 | /* NOTE : This function Should not be modified, when the callback is needed, |
301 | /* NOTE : This function should not be modified, when the callback is needed, |
290 | the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file |
302 | the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file |
291 | */ |
303 | */ |
292 | } |
304 | } |
293 | 305 | ||
294 | /** |
306 | /** |
295 | * @brief Starts the TIM Hall Sensor Interface. |
307 | * @brief Starts the TIM Hall Sensor Interface. |
296 | * @param htim : TIM Hall Sensor handle |
308 | * @param htim TIM Hall Sensor Interface handle |
297 | * @retval HAL status |
309 | * @retval HAL status |
298 | */ |
310 | */ |
299 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) |
311 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) |
300 | { |
312 | { |
- | 313 | uint32_t tmpsmcr; |
|
- | 314 | HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); |
|
- | 315 | HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); |
|
- | 316 | HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); |
|
- | 317 | HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); |
|
- | 318 | ||
301 | /* Check the parameters */ |
319 | /* Check the parameters */ |
302 | assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); |
320 | assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); |
- | 321 | ||
- | 322 | /* Check the TIM channels state */ |
|
- | 323 | if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) |
|
- | 324 | || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) |
|
- | 325 | || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) |
|
- | 326 | || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) |
|
- | 327 | { |
|
- | 328 | return HAL_ERROR; |
|
- | 329 | } |
|
- | 330 | ||
- | 331 | /* Set the TIM channels state */ |
|
- | 332 | TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); |
|
- | 333 | TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); |
|
- | 334 | TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); |
|
- | 335 | TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); |
|
303 | 336 | ||
304 | /* Enable the Input Capture channel 1 |
337 | /* Enable the Input Capture channel 1 |
305 | (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ |
338 | (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ |
306 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); |
339 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); |
307 | 340 | ||
- | 341 | /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ |
|
- | 342 | if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) |
|
- | 343 | { |
|
- | 344 | tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; |
|
- | 345 | if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) |
|
- | 346 | { |
|
308 | /* Enable the Peripheral */ |
347 | __HAL_TIM_ENABLE(htim); |
- | 348 | } |
|
- | 349 | } |
|
- | 350 | else |
|
- | 351 | { |
|
309 | __HAL_TIM_ENABLE(htim); |
352 | __HAL_TIM_ENABLE(htim); |
- | 353 | } |
|
310 | 354 | ||
311 | /* Return function status */ |
355 | /* Return function status */ |
312 | return HAL_OK; |
356 | return HAL_OK; |
313 | } |
357 | } |
314 | 358 | ||
315 | /** |
359 | /** |
316 | * @brief Stops the TIM Hall sensor Interface. |
360 | * @brief Stops the TIM Hall sensor Interface. |
317 | * @param htim : TIM Hall Sensor handle |
361 | * @param htim TIM Hall Sensor Interface handle |
318 | * @retval HAL status |
362 | * @retval HAL status |
319 | */ |
363 | */ |
320 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) |
364 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) |
321 | { |
365 | { |
322 | /* Check the parameters */ |
366 | /* Check the parameters */ |
323 | assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); |
367 | assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); |
324 | 368 | ||
325 | /* Disable the Input Capture channel 1 |
369 | /* Disable the Input Capture channels 1, 2 and 3 |
326 | (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ |
370 | (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ |
327 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); |
371 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); |
328 | 372 | ||
329 | /* Disable the Peripheral */ |
373 | /* Disable the Peripheral */ |
330 | __HAL_TIM_DISABLE(htim); |
374 | __HAL_TIM_DISABLE(htim); |
331 | 375 | ||
- | 376 | /* Set the TIM channels state */ |
|
- | 377 | TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); |
|
- | 378 | TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); |
|
- | 379 | TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); |
|
- | 380 | TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); |
|
- | 381 | ||
332 | /* Return function status */ |
382 | /* Return function status */ |
333 | return HAL_OK; |
383 | return HAL_OK; |
334 | } |
384 | } |
335 | 385 | ||
336 | /** |
386 | /** |
337 | * @brief Starts the TIM Hall Sensor Interface in interrupt mode. |
387 | * @brief Starts the TIM Hall Sensor Interface in interrupt mode. |
338 | * @param htim : TIM Hall Sensor handle |
388 | * @param htim TIM Hall Sensor Interface handle |
339 | * @retval HAL status |
389 | * @retval HAL status |
340 | */ |
390 | */ |
341 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) |
391 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) |
342 | { |
392 | { |
- | 393 | uint32_t tmpsmcr; |
|
- | 394 | HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); |
|
- | 395 | HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); |
|
- | 396 | HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); |
|
- | 397 | HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); |
|
- | 398 | ||
343 | /* Check the parameters */ |
399 | /* Check the parameters */ |
344 | assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); |
400 | assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); |
- | 401 | ||
- | 402 | /* Check the TIM channels state */ |
|
- | 403 | if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) |
|
- | 404 | || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) |
|
- | 405 | || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) |
|
- | 406 | || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) |
|
- | 407 | { |
|
- | 408 | return HAL_ERROR; |
|
- | 409 | } |
|
- | 410 | ||
- | 411 | /* Set the TIM channels state */ |
|
- | 412 | TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); |
|
- | 413 | TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); |
|
- | 414 | TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); |
|
- | 415 | TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); |
|
345 | 416 | ||
346 | /* Enable the capture compare Interrupts 1 event */ |
417 | /* Enable the capture compare Interrupts 1 event */ |
347 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); |
418 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); |
348 | 419 | ||
349 | /* Enable the Input Capture channel 1 |
420 | /* Enable the Input Capture channel 1 |
350 | (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ |
421 | (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ |
351 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); |
422 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); |
352 | 423 | ||
- | 424 | /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ |
|
- | 425 | if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) |
|
- | 426 | { |
|
- | 427 | tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; |
|
- | 428 | if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) |
|
- | 429 | { |
|
353 | /* Enable the Peripheral */ |
430 | __HAL_TIM_ENABLE(htim); |
- | 431 | } |
|
- | 432 | } |
|
- | 433 | else |
|
- | 434 | { |
|
354 | __HAL_TIM_ENABLE(htim); |
435 | __HAL_TIM_ENABLE(htim); |
- | 436 | } |
|
355 | 437 | ||
356 | /* Return function status */ |
438 | /* Return function status */ |
357 | return HAL_OK; |
439 | return HAL_OK; |
358 | } |
440 | } |
359 | 441 | ||
360 | /** |
442 | /** |
361 | * @brief Stops the TIM Hall Sensor Interface in interrupt mode. |
443 | * @brief Stops the TIM Hall Sensor Interface in interrupt mode. |
362 | * @param htim : TIM handle |
444 | * @param htim TIM Hall Sensor Interface handle |
363 | * @retval HAL status |
445 | * @retval HAL status |
364 | */ |
446 | */ |
365 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) |
447 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) |
366 | { |
448 | { |
367 | /* Check the parameters */ |
449 | /* Check the parameters */ |
368 | assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); |
450 | assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); |
369 | 451 | ||
370 | /* Disable the Input Capture channel 1 |
452 | /* Disable the Input Capture channel 1 |
371 | (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ |
453 | (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ |
372 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); |
454 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); |
373 | 455 | ||
374 | /* Disable the capture compare Interrupts event */ |
456 | /* Disable the capture compare Interrupts event */ |
375 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); |
457 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); |
376 | 458 | ||
377 | /* Disable the Peripheral */ |
459 | /* Disable the Peripheral */ |
378 | __HAL_TIM_DISABLE(htim); |
460 | __HAL_TIM_DISABLE(htim); |
379 | 461 | ||
- | 462 | /* Set the TIM channels state */ |
|
- | 463 | TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); |
|
- | 464 | TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); |
|
- | 465 | TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); |
|
- | 466 | TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); |
|
- | 467 | ||
380 | /* Return function status */ |
468 | /* Return function status */ |
381 | return HAL_OK; |
469 | return HAL_OK; |
382 | } |
470 | } |
383 | 471 | ||
384 | /** |
472 | /** |
385 | * @brief Starts the TIM Hall Sensor Interface in DMA mode. |
473 | * @brief Starts the TIM Hall Sensor Interface in DMA mode. |
386 | * @param htim : TIM Hall Sensor handle |
474 | * @param htim TIM Hall Sensor Interface handle |
387 | * @param pData : The destination Buffer address. |
475 | * @param pData The destination Buffer address. |
388 | * @param Length : The length of data to be transferred from TIM peripheral to memory. |
476 | * @param Length The length of data to be transferred from TIM peripheral to memory. |
389 | * @retval HAL status |
477 | * @retval HAL status |
390 | */ |
478 | */ |
391 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) |
479 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) |
392 | { |
480 | { |
- | 481 | uint32_t tmpsmcr; |
|
- | 482 | HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); |
|
- | 483 | HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); |
|
- | 484 | ||
393 | /* Check the parameters */ |
485 | /* Check the parameters */ |
394 | assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); |
486 | assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); |
395 | 487 | ||
- | 488 | /* Set the TIM channel state */ |
|
396 | if((htim->State == HAL_TIM_STATE_BUSY)) |
489 | if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) |
- | 490 | || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) |
|
397 | { |
491 | { |
398 | return HAL_BUSY; |
492 | return HAL_BUSY; |
399 | } |
493 | } |
400 | else if((htim->State == HAL_TIM_STATE_READY)) |
494 | else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) |
- | 495 | && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) |
|
401 | { |
496 | { |
402 | if(((uint32_t)pData == 0U) && (Length > 0U)) |
497 | if ((pData == NULL) && (Length > 0U)) |
403 | { |
498 | { |
404 | return HAL_ERROR; |
499 | return HAL_ERROR; |
405 | } |
500 | } |
406 | else |
501 | else |
407 | { |
502 | { |
408 | htim->State = HAL_TIM_STATE_BUSY; |
503 | TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); |
- | 504 | TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); |
|
409 | } |
505 | } |
410 | } |
506 | } |
- | 507 | else |
|
- | 508 | { |
|
- | 509 | return HAL_ERROR; |
|
- | 510 | } |
|
- | 511 | ||
411 | /* Enable the Input Capture channel 1 |
512 | /* Enable the Input Capture channel 1 |
412 | (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ |
513 | (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ |
413 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); |
514 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); |
414 | 515 | ||
415 | /* Set the DMA Input Capture 1 Callback */ |
516 | /* Set the DMA Input Capture 1 Callbacks */ |
416 | htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; |
517 | htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; |
- | 518 | htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; |
|
417 | /* Set the DMA error callback */ |
519 | /* Set the DMA error callback */ |
418 | htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; |
520 | htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; |
419 | 521 | ||
420 | /* Enable the DMA channel for Capture 1*/ |
522 | /* Enable the DMA channel for Capture 1*/ |
421 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); |
523 | if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) |
422 | 524 | { |
|
- | 525 | /* Return error status */ |
|
- | 526 | return HAL_ERROR; |
|
- | 527 | } |
|
423 | /* Enable the capture compare 1 Interrupt */ |
528 | /* Enable the capture compare 1 Interrupt */ |
424 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); |
529 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); |
425 | 530 | ||
- | 531 | /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ |
|
- | 532 | if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) |
|
- | 533 | { |
|
- | 534 | tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; |
|
- | 535 | if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) |
|
- | 536 | { |
|
426 | /* Enable the Peripheral */ |
537 | __HAL_TIM_ENABLE(htim); |
- | 538 | } |
|
- | 539 | } |
|
- | 540 | else |
|
- | 541 | { |
|
427 | __HAL_TIM_ENABLE(htim); |
542 | __HAL_TIM_ENABLE(htim); |
- | 543 | } |
|
428 | 544 | ||
429 | /* Return function status */ |
545 | /* Return function status */ |
430 | return HAL_OK; |
546 | return HAL_OK; |
431 | } |
547 | } |
432 | 548 | ||
433 | /** |
549 | /** |
434 | * @brief Stops the TIM Hall Sensor Interface in DMA mode. |
550 | * @brief Stops the TIM Hall Sensor Interface in DMA mode. |
435 | * @param htim : TIM handle |
551 | * @param htim TIM Hall Sensor Interface handle |
436 | * @retval HAL status |
552 | * @retval HAL status |
437 | */ |
553 | */ |
438 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) |
554 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) |
439 | { |
555 | { |
440 | /* Check the parameters */ |
556 | /* Check the parameters */ |
441 | assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); |
557 | assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); |
442 | 558 | ||
443 | /* Disable the Input Capture channel 1 |
559 | /* Disable the Input Capture channel 1 |
444 | (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ |
560 | (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ |
445 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); |
561 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); |
446 | 562 | ||
447 | 563 | ||
448 | /* Disable the capture compare Interrupts 1 event */ |
564 | /* Disable the capture compare Interrupts 1 event */ |
449 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); |
565 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); |
450 | 566 | ||
- | 567 | (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); |
|
- | 568 | ||
451 | /* Disable the Peripheral */ |
569 | /* Disable the Peripheral */ |
452 | __HAL_TIM_DISABLE(htim); |
570 | __HAL_TIM_DISABLE(htim); |
453 | 571 | ||
- | 572 | /* Set the TIM channel state */ |
|
- | 573 | TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); |
|
- | 574 | TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); |
|
- | 575 | ||
454 | /* Return function status */ |
576 | /* Return function status */ |
455 | return HAL_OK; |
577 | return HAL_OK; |
456 | } |
578 | } |
457 | 579 | ||
458 | /** |
580 | /** |
459 | * @} |
581 | * @} |
460 | */ |
582 | */ |
461 | 583 | ||
462 | #if defined (STM32F100xB) || defined (STM32F100xE) || \ |
- | |
463 | defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \ |
- | |
464 | defined (STM32F105xC) || defined (STM32F107xC) |
- | |
465 | - | ||
466 | /** @defgroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions |
584 | /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions |
467 | * @brief Timer Complementary Output Compare functions |
585 | * @brief Timer Complementary Output Compare functions |
468 | * |
586 | * |
469 | @verbatim |
587 | @verbatim |
470 | ============================================================================== |
588 | ============================================================================== |
471 | ##### Timer Complementary Output Compare functions ##### |
589 | ##### Timer Complementary Output Compare functions ##### |
472 | ============================================================================== |
590 | ============================================================================== |
473 | [..] |
591 | [..] |
Line 484... | Line 602... | ||
484 | */ |
602 | */ |
485 | 603 | ||
486 | /** |
604 | /** |
487 | * @brief Starts the TIM Output Compare signal generation on the complementary |
605 | * @brief Starts the TIM Output Compare signal generation on the complementary |
488 | * output. |
606 | * output. |
489 | * @param htim : TIM Output Compare handle |
607 | * @param htim TIM Output Compare handle |
490 | * @param Channel : TIM Channel to be enabled |
608 | * @param Channel TIM Channel to be enabled |
491 | * This parameter can be one of the following values: |
609 | * This parameter can be one of the following values: |
492 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
610 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
493 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
611 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
494 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
612 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
495 | * @retval HAL status |
613 | * @retval HAL status |
496 | */ |
614 | */ |
497 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) |
615 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) |
498 | { |
616 | { |
- | 617 | uint32_t tmpsmcr; |
|
- | 618 | ||
499 | /* Check the parameters */ |
619 | /* Check the parameters */ |
500 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); |
620 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); |
501 | 621 | ||
- | 622 | /* Check the TIM complementary channel state */ |
|
- | 623 | if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) |
|
- | 624 | { |
|
- | 625 | return HAL_ERROR; |
|
- | 626 | } |
|
- | 627 | ||
- | 628 | /* Set the TIM complementary channel state */ |
|
- | 629 | TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); |
|
- | 630 | ||
502 | /* Enable the Capture compare channel N */ |
631 | /* Enable the Capture compare channel N */ |
503 | TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); |
632 | TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); |
504 | 633 | ||
505 | /* Enable the Main Ouput */ |
634 | /* Enable the Main Output */ |
506 | __HAL_TIM_MOE_ENABLE(htim); |
635 | __HAL_TIM_MOE_ENABLE(htim); |
507 | 636 | ||
- | 637 | /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ |
|
- | 638 | if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) |
|
- | 639 | { |
|
- | 640 | tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; |
|
- | 641 | if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) |
|
- | 642 | { |
|
508 | /* Enable the Peripheral */ |
643 | __HAL_TIM_ENABLE(htim); |
- | 644 | } |
|
- | 645 | } |
|
- | 646 | else |
|
- | 647 | { |
|
509 | __HAL_TIM_ENABLE(htim); |
648 | __HAL_TIM_ENABLE(htim); |
- | 649 | } |
|
510 | 650 | ||
511 | /* Return function status */ |
651 | /* Return function status */ |
512 | return HAL_OK; |
652 | return HAL_OK; |
513 | } |
653 | } |
514 | 654 | ||
515 | /** |
655 | /** |
516 | * @brief Stops the TIM Output Compare signal generation on the complementary |
656 | * @brief Stops the TIM Output Compare signal generation on the complementary |
517 | * output. |
657 | * output. |
518 | * @param htim : TIM handle |
658 | * @param htim TIM handle |
519 | * @param Channel : TIM Channel to be disabled |
659 | * @param Channel TIM Channel to be disabled |
520 | * This parameter can be one of the following values: |
660 | * This parameter can be one of the following values: |
521 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
661 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
522 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
662 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
523 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
663 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
524 | * @retval HAL status |
664 | * @retval HAL status |
Line 529... | Line 669... | ||
529 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); |
669 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); |
530 | 670 | ||
531 | /* Disable the Capture compare channel N */ |
671 | /* Disable the Capture compare channel N */ |
532 | TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); |
672 | TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); |
533 | 673 | ||
534 | /* Disable the Main Ouput */ |
674 | /* Disable the Main Output */ |
535 | __HAL_TIM_MOE_DISABLE(htim); |
675 | __HAL_TIM_MOE_DISABLE(htim); |
536 | 676 | ||
537 | /* Disable the Peripheral */ |
677 | /* Disable the Peripheral */ |
538 | __HAL_TIM_DISABLE(htim); |
678 | __HAL_TIM_DISABLE(htim); |
539 | 679 | ||
- | 680 | /* Set the TIM complementary channel state */ |
|
- | 681 | TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); |
|
- | 682 | ||
540 | /* Return function status */ |
683 | /* Return function status */ |
541 | return HAL_OK; |
684 | return HAL_OK; |
542 | } |
685 | } |
543 | 686 | ||
544 | /** |
687 | /** |
545 | * @brief Starts the TIM Output Compare signal generation in interrupt mode |
688 | * @brief Starts the TIM Output Compare signal generation in interrupt mode |
546 | * on the complementary output. |
689 | * on the complementary output. |
547 | * @param htim : TIM OC handle |
690 | * @param htim TIM OC handle |
548 | * @param Channel : TIM Channel to be enabled |
691 | * @param Channel TIM Channel to be enabled |
549 | * This parameter can be one of the following values: |
692 | * This parameter can be one of the following values: |
550 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
693 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
551 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
694 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
552 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
695 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
553 | * @retval HAL status |
696 | * @retval HAL status |
554 | */ |
697 | */ |
555 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) |
698 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) |
556 | { |
699 | { |
- | 700 | uint32_t tmpsmcr; |
|
- | 701 | ||
557 | /* Check the parameters */ |
702 | /* Check the parameters */ |
558 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); |
703 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); |
559 | 704 | ||
- | 705 | /* Check the TIM complementary channel state */ |
|
- | 706 | if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) |
|
- | 707 | { |
|
- | 708 | return HAL_ERROR; |
|
- | 709 | } |
|
- | 710 | ||
- | 711 | /* Set the TIM complementary channel state */ |
|
- | 712 | TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); |
|
- | 713 | ||
560 | switch (Channel) |
714 | switch (Channel) |
561 | { |
715 | { |
562 | case TIM_CHANNEL_1: |
716 | case TIM_CHANNEL_1: |
563 | { |
717 | { |
564 | /* Enable the TIM Output Compare interrupt */ |
718 | /* Enable the TIM Output Compare interrupt */ |
565 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); |
719 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); |
- | 720 | break; |
|
566 | } |
721 | } |
567 | break; |
- | |
568 | 722 | ||
569 | case TIM_CHANNEL_2: |
723 | case TIM_CHANNEL_2: |
570 | { |
724 | { |
571 | /* Enable the TIM Output Compare interrupt */ |
725 | /* Enable the TIM Output Compare interrupt */ |
572 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); |
726 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); |
- | 727 | break; |
|
573 | } |
728 | } |
574 | break; |
- | |
575 | 729 | ||
576 | case TIM_CHANNEL_3: |
730 | case TIM_CHANNEL_3: |
577 | { |
731 | { |
578 | /* Enable the TIM Output Compare interrupt */ |
732 | /* Enable the TIM Output Compare interrupt */ |
579 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); |
733 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); |
- | 734 | break; |
|
580 | } |
735 | } |
581 | break; |
736 | |
582 | 737 | ||
583 | default: |
738 | default: |
584 | break; |
739 | break; |
585 | } |
740 | } |
586 | 741 | ||
587 | /* Enable the TIM Break interrupt */ |
742 | /* Enable the TIM Break interrupt */ |
588 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); |
743 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); |
589 | 744 | ||
590 | /* Enable the Capture compare channel N */ |
745 | /* Enable the Capture compare channel N */ |
591 | TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); |
746 | TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); |
592 | 747 | ||
593 | /* Enable the Main Ouput */ |
748 | /* Enable the Main Output */ |
594 | __HAL_TIM_MOE_ENABLE(htim); |
749 | __HAL_TIM_MOE_ENABLE(htim); |
595 | 750 | ||
- | 751 | /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ |
|
- | 752 | if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) |
|
- | 753 | { |
|
- | 754 | tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; |
|
- | 755 | if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) |
|
- | 756 | { |
|
596 | /* Enable the Peripheral */ |
757 | __HAL_TIM_ENABLE(htim); |
- | 758 | } |
|
- | 759 | } |
|
- | 760 | else |
|
- | 761 | { |
|
597 | __HAL_TIM_ENABLE(htim); |
762 | __HAL_TIM_ENABLE(htim); |
- | 763 | } |
|
598 | 764 | ||
599 | /* Return function status */ |
765 | /* Return function status */ |
600 | return HAL_OK; |
766 | return HAL_OK; |
601 | } |
767 | } |
602 | 768 | ||
603 | /** |
769 | /** |
604 | * @brief Stops the TIM Output Compare signal generation in interrupt mode |
770 | * @brief Stops the TIM Output Compare signal generation in interrupt mode |
605 | * on the complementary output. |
771 | * on the complementary output. |
606 | * @param htim : TIM Output Compare handle |
772 | * @param htim TIM Output Compare handle |
607 | * @param Channel : TIM Channel to be disabled |
773 | * @param Channel TIM Channel to be disabled |
608 | * This parameter can be one of the following values: |
774 | * This parameter can be one of the following values: |
609 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
775 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
610 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
776 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
611 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
777 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
612 | * @retval HAL status |
778 | * @retval HAL status |
613 | */ |
779 | */ |
614 | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) |
780 | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) |
615 | { |
781 | { |
616 | uint32_t tmpccer = 0U; |
782 | uint32_t tmpccer; |
617 | - | ||
618 | /* Check the parameters */ |
783 | /* Check the parameters */ |
619 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); |
784 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); |
620 | 785 | ||
621 | switch (Channel) |
786 | switch (Channel) |
622 | { |
787 | { |
623 | case TIM_CHANNEL_1: |
788 | case TIM_CHANNEL_1: |
624 | { |
789 | { |
625 | /* Disable the TIM Output Compare interrupt */ |
790 | /* Disable the TIM Output Compare interrupt */ |
626 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); |
791 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); |
- | 792 | break; |
|
627 | } |
793 | } |
628 | break; |
- | |
629 | 794 | ||
630 | case TIM_CHANNEL_2: |
795 | case TIM_CHANNEL_2: |
631 | { |
796 | { |
632 | /* Disable the TIM Output Compare interrupt */ |
797 | /* Disable the TIM Output Compare interrupt */ |
633 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); |
798 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); |
- | 799 | break; |
|
634 | } |
800 | } |
635 | break; |
- | |
636 | 801 | ||
637 | case TIM_CHANNEL_3: |
802 | case TIM_CHANNEL_3: |
638 | { |
803 | { |
639 | /* Disable the TIM Output Compare interrupt */ |
804 | /* Disable the TIM Output Compare interrupt */ |
640 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); |
805 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); |
- | 806 | break; |
|
641 | } |
807 | } |
642 | break; |
- | |
643 | 808 | ||
644 | default: |
809 | default: |
645 | break; |
810 | break; |
646 | } |
811 | } |
647 | 812 | ||
648 | /* Disable the Capture compare channel N */ |
813 | /* Disable the Capture compare channel N */ |
649 | TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); |
814 | TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); |
650 | 815 | ||
651 | /* Disable the TIM Break interrupt (only if no more channel is active) */ |
816 | /* Disable the TIM Break interrupt (only if no more channel is active) */ |
652 | tmpccer = htim->Instance->CCER; |
817 | tmpccer = htim->Instance->CCER; |
653 | if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET) |
818 | if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) |
654 | { |
819 | { |
655 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); |
820 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); |
656 | } |
821 | } |
657 | 822 | ||
658 | /* Disable the Main Ouput */ |
823 | /* Disable the Main Output */ |
659 | __HAL_TIM_MOE_DISABLE(htim); |
824 | __HAL_TIM_MOE_DISABLE(htim); |
660 | 825 | ||
661 | /* Disable the Peripheral */ |
826 | /* Disable the Peripheral */ |
662 | __HAL_TIM_DISABLE(htim); |
827 | __HAL_TIM_DISABLE(htim); |
663 | 828 | ||
- | 829 | /* Set the TIM complementary channel state */ |
|
- | 830 | TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); |
|
- | 831 | ||
664 | /* Return function status */ |
832 | /* Return function status */ |
665 | return HAL_OK; |
833 | return HAL_OK; |
666 | } |
834 | } |
667 | 835 | ||
668 | /** |
836 | /** |
669 | * @brief Starts the TIM Output Compare signal generation in DMA mode |
837 | * @brief Starts the TIM Output Compare signal generation in DMA mode |
670 | * on the complementary output. |
838 | * on the complementary output. |
671 | * @param htim : TIM Output Compare handle |
839 | * @param htim TIM Output Compare handle |
672 | * @param Channel : TIM Channel to be enabled |
840 | * @param Channel TIM Channel to be enabled |
673 | * This parameter can be one of the following values: |
841 | * This parameter can be one of the following values: |
674 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
842 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
675 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
843 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
676 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
844 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
677 | * @param pData : The source Buffer address. |
845 | * @param pData The source Buffer address. |
678 | * @param Length : The length of data to be transferred from memory to TIM peripheral |
846 | * @param Length The length of data to be transferred from memory to TIM peripheral |
679 | * @retval HAL status |
847 | * @retval HAL status |
680 | */ |
848 | */ |
681 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) |
849 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) |
682 | { |
850 | { |
- | 851 | uint32_t tmpsmcr; |
|
- | 852 | ||
683 | /* Check the parameters */ |
853 | /* Check the parameters */ |
684 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); |
854 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); |
685 | 855 | ||
- | 856 | /* Set the TIM complementary channel state */ |
|
686 | if((htim->State == HAL_TIM_STATE_BUSY)) |
857 | if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) |
687 | { |
858 | { |
688 | return HAL_BUSY; |
859 | return HAL_BUSY; |
689 | } |
860 | } |
690 | else if((htim->State == HAL_TIM_STATE_READY)) |
861 | else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) |
691 | { |
862 | { |
692 | if(((uint32_t)pData == 0U) && (Length > 0U)) |
863 | if ((pData == NULL) && (Length > 0U)) |
693 | { |
864 | { |
694 | return HAL_ERROR; |
865 | return HAL_ERROR; |
695 | } |
866 | } |
696 | else |
867 | else |
697 | { |
868 | { |
698 | htim->State = HAL_TIM_STATE_BUSY; |
869 | TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); |
699 | } |
870 | } |
700 | } |
871 | } |
- | 872 | else |
|
- | 873 | { |
|
- | 874 | return HAL_ERROR; |
|
- | 875 | } |
|
- | 876 | ||
701 | switch (Channel) |
877 | switch (Channel) |
702 | { |
878 | { |
703 | case TIM_CHANNEL_1: |
879 | case TIM_CHANNEL_1: |
704 | { |
880 | { |
705 | /* Set the DMA Period elapsed callback */ |
881 | /* Set the DMA compare callbacks */ |
706 | htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; |
882 | htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; |
- | 883 | htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; |
|
707 | 884 | ||
708 | /* Set the DMA error callback */ |
885 | /* Set the DMA error callback */ |
709 | htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; |
886 | htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; |
710 | 887 | ||
711 | /* Enable the DMA channel */ |
888 | /* Enable the DMA channel */ |
712 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); |
889 | if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) |
- | 890 | { |
|
- | 891 | /* Return error status */ |
|
- | 892 | return HAL_ERROR; |
|
713 | 893 | } |
|
714 | /* Enable the TIM Output Compare DMA request */ |
894 | /* Enable the TIM Output Compare DMA request */ |
715 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); |
895 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); |
- | 896 | break; |
|
716 | } |
897 | } |
717 | break; |
- | |
718 | 898 | ||
719 | case TIM_CHANNEL_2: |
899 | case TIM_CHANNEL_2: |
720 | { |
900 | { |
721 | /* Set the DMA Period elapsed callback */ |
901 | /* Set the DMA compare callbacks */ |
722 | htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; |
902 | htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; |
- | 903 | htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; |
|
723 | 904 | ||
724 | /* Set the DMA error callback */ |
905 | /* Set the DMA error callback */ |
725 | htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; |
906 | htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; |
726 | 907 | ||
727 | /* Enable the DMA channel */ |
908 | /* Enable the DMA channel */ |
728 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); |
909 | if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) |
- | 910 | { |
|
- | 911 | /* Return error status */ |
|
- | 912 | return HAL_ERROR; |
|
729 | 913 | } |
|
730 | /* Enable the TIM Output Compare DMA request */ |
914 | /* Enable the TIM Output Compare DMA request */ |
731 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); |
915 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); |
- | 916 | break; |
|
732 | } |
917 | } |
733 | break; |
- | |
734 | 918 | ||
735 | case TIM_CHANNEL_3: |
919 | case TIM_CHANNEL_3: |
736 | { |
920 | { |
737 | /* Set the DMA Period elapsed callback */ |
921 | /* Set the DMA compare callbacks */ |
738 | htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; |
922 | htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; |
- | 923 | htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; |
|
739 | 924 | ||
740 | /* Set the DMA error callback */ |
925 | /* Set the DMA error callback */ |
741 | htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; |
926 | htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; |
742 | 927 | ||
743 | /* Enable the DMA channel */ |
928 | /* Enable the DMA channel */ |
744 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); |
929 | if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) |
- | 930 | { |
|
- | 931 | /* Return error status */ |
|
- | 932 | return HAL_ERROR; |
|
745 | 933 | } |
|
746 | /* Enable the TIM Output Compare DMA request */ |
934 | /* Enable the TIM Output Compare DMA request */ |
747 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); |
935 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); |
- | 936 | break; |
|
748 | } |
937 | } |
749 | break; |
- | |
750 | 938 | ||
751 | default: |
939 | default: |
752 | break; |
940 | break; |
753 | } |
941 | } |
754 | 942 | ||
755 | /* Enable the Capture compare channel N */ |
943 | /* Enable the Capture compare channel N */ |
756 | TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); |
944 | TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); |
757 | 945 | ||
758 | /* Enable the Main Ouput */ |
946 | /* Enable the Main Output */ |
759 | __HAL_TIM_MOE_ENABLE(htim); |
947 | __HAL_TIM_MOE_ENABLE(htim); |
760 | 948 | ||
- | 949 | /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ |
|
- | 950 | if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) |
|
- | 951 | { |
|
- | 952 | tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; |
|
- | 953 | if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) |
|
- | 954 | { |
|
761 | /* Enable the Peripheral */ |
955 | __HAL_TIM_ENABLE(htim); |
- | 956 | } |
|
- | 957 | } |
|
- | 958 | else |
|
- | 959 | { |
|
762 | __HAL_TIM_ENABLE(htim); |
960 | __HAL_TIM_ENABLE(htim); |
- | 961 | } |
|
763 | 962 | ||
764 | /* Return function status */ |
963 | /* Return function status */ |
765 | return HAL_OK; |
964 | return HAL_OK; |
766 | } |
965 | } |
767 | 966 | ||
768 | /** |
967 | /** |
769 | * @brief Stops the TIM Output Compare signal generation in DMA mode |
968 | * @brief Stops the TIM Output Compare signal generation in DMA mode |
770 | * on the complementary output. |
969 | * on the complementary output. |
771 | * @param htim : TIM Output Compare handle |
970 | * @param htim TIM Output Compare handle |
772 | * @param Channel : TIM Channel to be disabled |
971 | * @param Channel TIM Channel to be disabled |
773 | * This parameter can be one of the following values: |
972 | * This parameter can be one of the following values: |
774 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
973 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
775 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
974 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
776 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
975 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
777 | * @retval HAL status |
976 | * @retval HAL status |
Line 785... | Line 984... | ||
785 | { |
984 | { |
786 | case TIM_CHANNEL_1: |
985 | case TIM_CHANNEL_1: |
787 | { |
986 | { |
788 | /* Disable the TIM Output Compare DMA request */ |
987 | /* Disable the TIM Output Compare DMA request */ |
789 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); |
988 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); |
- | 989 | (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); |
|
- | 990 | break; |
|
790 | } |
991 | } |
791 | break; |
- | |
792 | 992 | ||
793 | case TIM_CHANNEL_2: |
993 | case TIM_CHANNEL_2: |
794 | { |
994 | { |
795 | /* Disable the TIM Output Compare DMA request */ |
995 | /* Disable the TIM Output Compare DMA request */ |
796 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); |
996 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); |
- | 997 | (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); |
|
- | 998 | break; |
|
797 | } |
999 | } |
798 | break; |
- | |
799 | 1000 | ||
800 | case TIM_CHANNEL_3: |
1001 | case TIM_CHANNEL_3: |
801 | { |
1002 | { |
802 | /* Disable the TIM Output Compare DMA request */ |
1003 | /* Disable the TIM Output Compare DMA request */ |
803 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); |
1004 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); |
- | 1005 | (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); |
|
- | 1006 | break; |
|
804 | } |
1007 | } |
805 | break; |
- | |
806 | 1008 | ||
807 | default: |
1009 | default: |
808 | break; |
1010 | break; |
809 | } |
1011 | } |
810 | 1012 | ||
811 | /* Disable the Capture compare channel N */ |
1013 | /* Disable the Capture compare channel N */ |
812 | TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); |
1014 | TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); |
813 | 1015 | ||
814 | /* Disable the Main Ouput */ |
1016 | /* Disable the Main Output */ |
815 | __HAL_TIM_MOE_DISABLE(htim); |
1017 | __HAL_TIM_MOE_DISABLE(htim); |
816 | 1018 | ||
817 | /* Disable the Peripheral */ |
1019 | /* Disable the Peripheral */ |
818 | __HAL_TIM_DISABLE(htim); |
1020 | __HAL_TIM_DISABLE(htim); |
819 | 1021 | ||
820 | /* Change the htim state */ |
1022 | /* Set the TIM complementary channel state */ |
821 | htim->State = HAL_TIM_STATE_READY; |
1023 | TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); |
822 | 1024 | ||
823 | /* Return function status */ |
1025 | /* Return function status */ |
824 | return HAL_OK; |
1026 | return HAL_OK; |
825 | } |
1027 | } |
826 | 1028 | ||
827 | /** |
1029 | /** |
828 | * @} |
1030 | * @} |
829 | */ |
1031 | */ |
830 | 1032 | ||
831 | /** @defgroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions |
1033 | /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions |
832 | * @brief Timer Complementary PWM functions |
1034 | * @brief Timer Complementary PWM functions |
833 | * |
1035 | * |
834 | @verbatim |
1036 | @verbatim |
835 | ============================================================================== |
1037 | ============================================================================== |
836 | ##### Timer Complementary PWM functions ##### |
1038 | ##### Timer Complementary PWM functions ##### |
837 | ============================================================================== |
1039 | ============================================================================== |
838 | [..] |
1040 | [..] |
Line 858... | Line 1060... | ||
858 | * @{ |
1060 | * @{ |
859 | */ |
1061 | */ |
860 | 1062 | ||
861 | /** |
1063 | /** |
862 | * @brief Starts the PWM signal generation on the complementary output. |
1064 | * @brief Starts the PWM signal generation on the complementary output. |
863 | * @param htim : TIM handle |
1065 | * @param htim TIM handle |
864 | * @param Channel : TIM Channel to be enabled |
1066 | * @param Channel TIM Channel to be enabled |
865 | * This parameter can be one of the following values: |
1067 | * This parameter can be one of the following values: |
866 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
1068 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
867 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
1069 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
868 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
1070 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
869 | * @retval HAL status |
1071 | * @retval HAL status |
870 | */ |
1072 | */ |
871 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) |
1073 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) |
872 | { |
1074 | { |
- | 1075 | uint32_t tmpsmcr; |
|
- | 1076 | ||
873 | /* Check the parameters */ |
1077 | /* Check the parameters */ |
874 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); |
1078 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); |
875 | 1079 | ||
- | 1080 | /* Check the TIM complementary channel state */ |
|
- | 1081 | if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) |
|
- | 1082 | { |
|
- | 1083 | return HAL_ERROR; |
|
- | 1084 | } |
|
- | 1085 | ||
- | 1086 | /* Set the TIM complementary channel state */ |
|
- | 1087 | TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); |
|
- | 1088 | ||
876 | /* Enable the complementary PWM output */ |
1089 | /* Enable the complementary PWM output */ |
877 | TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); |
1090 | TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); |
878 | 1091 | ||
879 | /* Enable the Main Ouput */ |
1092 | /* Enable the Main Output */ |
880 | __HAL_TIM_MOE_ENABLE(htim); |
1093 | __HAL_TIM_MOE_ENABLE(htim); |
881 | 1094 | ||
- | 1095 | /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ |
|
- | 1096 | if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) |
|
- | 1097 | { |
|
- | 1098 | tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; |
|
- | 1099 | if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) |
|
- | 1100 | { |
|
882 | /* Enable the Peripheral */ |
1101 | __HAL_TIM_ENABLE(htim); |
- | 1102 | } |
|
- | 1103 | } |
|
- | 1104 | else |
|
- | 1105 | { |
|
883 | __HAL_TIM_ENABLE(htim); |
1106 | __HAL_TIM_ENABLE(htim); |
- | 1107 | } |
|
884 | 1108 | ||
885 | /* Return function status */ |
1109 | /* Return function status */ |
886 | return HAL_OK; |
1110 | return HAL_OK; |
887 | } |
1111 | } |
888 | 1112 | ||
889 | /** |
1113 | /** |
890 | * @brief Stops the PWM signal generation on the complementary output. |
1114 | * @brief Stops the PWM signal generation on the complementary output. |
891 | * @param htim : TIM handle |
1115 | * @param htim TIM handle |
892 | * @param Channel : TIM Channel to be disabled |
1116 | * @param Channel TIM Channel to be disabled |
893 | * This parameter can be one of the following values: |
1117 | * This parameter can be one of the following values: |
894 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
1118 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
895 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
1119 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
896 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
1120 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
897 | * @retval HAL status |
1121 | * @retval HAL status |
Line 902... | Line 1126... | ||
902 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); |
1126 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); |
903 | 1127 | ||
904 | /* Disable the complementary PWM output */ |
1128 | /* Disable the complementary PWM output */ |
905 | TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); |
1129 | TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); |
906 | 1130 | ||
907 | /* Disable the Main Ouput */ |
1131 | /* Disable the Main Output */ |
908 | __HAL_TIM_MOE_DISABLE(htim); |
1132 | __HAL_TIM_MOE_DISABLE(htim); |
909 | 1133 | ||
910 | /* Disable the Peripheral */ |
1134 | /* Disable the Peripheral */ |
911 | __HAL_TIM_DISABLE(htim); |
1135 | __HAL_TIM_DISABLE(htim); |
912 | 1136 | ||
- | 1137 | /* Set the TIM complementary channel state */ |
|
- | 1138 | TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); |
|
- | 1139 | ||
913 | /* Return function status */ |
1140 | /* Return function status */ |
914 | return HAL_OK; |
1141 | return HAL_OK; |
915 | } |
1142 | } |
916 | 1143 | ||
917 | /** |
1144 | /** |
918 | * @brief Starts the PWM signal generation in interrupt mode on the |
1145 | * @brief Starts the PWM signal generation in interrupt mode on the |
919 | * complementary output. |
1146 | * complementary output. |
920 | * @param htim : TIM handle |
1147 | * @param htim TIM handle |
921 | * @param Channel : TIM Channel to be disabled |
1148 | * @param Channel TIM Channel to be disabled |
922 | * This parameter can be one of the following values: |
1149 | * This parameter can be one of the following values: |
923 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
1150 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
924 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
1151 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
925 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
1152 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
926 | * @retval HAL status |
1153 | * @retval HAL status |
927 | */ |
1154 | */ |
928 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) |
1155 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) |
929 | { |
1156 | { |
- | 1157 | uint32_t tmpsmcr; |
|
- | 1158 | ||
930 | /* Check the parameters */ |
1159 | /* Check the parameters */ |
931 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); |
1160 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); |
932 | 1161 | ||
- | 1162 | /* Check the TIM complementary channel state */ |
|
- | 1163 | if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) |
|
- | 1164 | { |
|
- | 1165 | return HAL_ERROR; |
|
- | 1166 | } |
|
- | 1167 | ||
- | 1168 | /* Set the TIM complementary channel state */ |
|
- | 1169 | TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); |
|
- | 1170 | ||
933 | switch (Channel) |
1171 | switch (Channel) |
934 | { |
1172 | { |
935 | case TIM_CHANNEL_1: |
1173 | case TIM_CHANNEL_1: |
936 | { |
1174 | { |
937 | /* Enable the TIM Capture/Compare 1 interrupt */ |
1175 | /* Enable the TIM Capture/Compare 1 interrupt */ |
938 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); |
1176 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); |
- | 1177 | break; |
|
939 | } |
1178 | } |
940 | break; |
- | |
941 | 1179 | ||
942 | case TIM_CHANNEL_2: |
1180 | case TIM_CHANNEL_2: |
943 | { |
1181 | { |
944 | /* Enable the TIM Capture/Compare 2 interrupt */ |
1182 | /* Enable the TIM Capture/Compare 2 interrupt */ |
945 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); |
1183 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); |
- | 1184 | break; |
|
946 | } |
1185 | } |
947 | break; |
- | |
948 | 1186 | ||
949 | case TIM_CHANNEL_3: |
1187 | case TIM_CHANNEL_3: |
950 | { |
1188 | { |
951 | /* Enable the TIM Capture/Compare 3 interrupt */ |
1189 | /* Enable the TIM Capture/Compare 3 interrupt */ |
952 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); |
1190 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); |
- | 1191 | break; |
|
953 | } |
1192 | } |
954 | break; |
- | |
955 | 1193 | ||
956 | default: |
1194 | default: |
957 | break; |
1195 | break; |
958 | } |
1196 | } |
959 | 1197 | ||
960 | /* Enable the TIM Break interrupt */ |
1198 | /* Enable the TIM Break interrupt */ |
961 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); |
1199 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); |
962 | 1200 | ||
963 | /* Enable the complementary PWM output */ |
1201 | /* Enable the complementary PWM output */ |
964 | TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); |
1202 | TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); |
965 | 1203 | ||
966 | /* Enable the Main Ouput */ |
1204 | /* Enable the Main Output */ |
967 | __HAL_TIM_MOE_ENABLE(htim); |
1205 | __HAL_TIM_MOE_ENABLE(htim); |
968 | 1206 | ||
- | 1207 | /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ |
|
- | 1208 | if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) |
|
- | 1209 | { |
|
- | 1210 | tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; |
|
- | 1211 | if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) |
|
- | 1212 | { |
|
969 | /* Enable the Peripheral */ |
1213 | __HAL_TIM_ENABLE(htim); |
- | 1214 | } |
|
- | 1215 | } |
|
- | 1216 | else |
|
- | 1217 | { |
|
970 | __HAL_TIM_ENABLE(htim); |
1218 | __HAL_TIM_ENABLE(htim); |
- | 1219 | } |
|
971 | 1220 | ||
972 | /* Return function status */ |
1221 | /* Return function status */ |
973 | return HAL_OK; |
1222 | return HAL_OK; |
974 | } |
1223 | } |
975 | 1224 | ||
976 | /** |
1225 | /** |
977 | * @brief Stops the PWM signal generation in interrupt mode on the |
1226 | * @brief Stops the PWM signal generation in interrupt mode on the |
978 | * complementary output. |
1227 | * complementary output. |
979 | * @param htim : TIM handle |
1228 | * @param htim TIM handle |
980 | * @param Channel : TIM Channel to be disabled |
1229 | * @param Channel TIM Channel to be disabled |
981 | * This parameter can be one of the following values: |
1230 | * This parameter can be one of the following values: |
982 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
1231 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
983 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
1232 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
984 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
1233 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
985 | * @retval HAL status |
1234 | * @retval HAL status |
986 | */ |
1235 | */ |
987 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) |
1236 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) |
988 | { |
1237 | { |
989 | uint32_t tmpccer = 0U; |
1238 | uint32_t tmpccer; |
990 | 1239 | ||
991 | /* Check the parameters */ |
1240 | /* Check the parameters */ |
992 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); |
1241 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); |
993 | 1242 | ||
994 | switch (Channel) |
1243 | switch (Channel) |
995 | { |
1244 | { |
996 | case TIM_CHANNEL_1: |
1245 | case TIM_CHANNEL_1: |
997 | { |
1246 | { |
998 | /* Disable the TIM Capture/Compare 1 interrupt */ |
1247 | /* Disable the TIM Capture/Compare 1 interrupt */ |
999 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); |
1248 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); |
- | 1249 | break; |
|
1000 | } |
1250 | } |
1001 | break; |
- | |
1002 | 1251 | ||
1003 | case TIM_CHANNEL_2: |
1252 | case TIM_CHANNEL_2: |
1004 | { |
1253 | { |
1005 | /* Disable the TIM Capture/Compare 2 interrupt */ |
1254 | /* Disable the TIM Capture/Compare 2 interrupt */ |
1006 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); |
1255 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); |
- | 1256 | break; |
|
1007 | } |
1257 | } |
1008 | break; |
- | |
1009 | 1258 | ||
1010 | case TIM_CHANNEL_3: |
1259 | case TIM_CHANNEL_3: |
1011 | { |
1260 | { |
1012 | /* Disable the TIM Capture/Compare 3 interrupt */ |
1261 | /* Disable the TIM Capture/Compare 3 interrupt */ |
1013 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); |
1262 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); |
- | 1263 | break; |
|
1014 | } |
1264 | } |
1015 | break; |
- | |
1016 | 1265 | ||
1017 | default: |
1266 | default: |
1018 | break; |
1267 | break; |
1019 | } |
1268 | } |
1020 | 1269 | ||
1021 | /* Disable the complementary PWM output */ |
1270 | /* Disable the complementary PWM output */ |
1022 | TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); |
1271 | TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); |
1023 | 1272 | ||
1024 | /* Disable the TIM Break interrupt (only if no more channel is active) */ |
1273 | /* Disable the TIM Break interrupt (only if no more channel is active) */ |
1025 | tmpccer = htim->Instance->CCER; |
1274 | tmpccer = htim->Instance->CCER; |
1026 | if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET) |
1275 | if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) |
1027 | { |
1276 | { |
1028 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); |
1277 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); |
1029 | } |
1278 | } |
1030 | 1279 | ||
1031 | /* Disable the Main Ouput */ |
1280 | /* Disable the Main Output */ |
1032 | __HAL_TIM_MOE_DISABLE(htim); |
1281 | __HAL_TIM_MOE_DISABLE(htim); |
1033 | 1282 | ||
1034 | /* Disable the Peripheral */ |
1283 | /* Disable the Peripheral */ |
1035 | __HAL_TIM_DISABLE(htim); |
1284 | __HAL_TIM_DISABLE(htim); |
1036 | 1285 | ||
- | 1286 | /* Set the TIM complementary channel state */ |
|
- | 1287 | TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); |
|
- | 1288 | ||
1037 | /* Return function status */ |
1289 | /* Return function status */ |
1038 | return HAL_OK; |
1290 | return HAL_OK; |
1039 | } |
1291 | } |
1040 | 1292 | ||
1041 | /** |
1293 | /** |
1042 | * @brief Starts the TIM PWM signal generation in DMA mode on the |
1294 | * @brief Starts the TIM PWM signal generation in DMA mode on the |
1043 | * complementary output |
1295 | * complementary output |
1044 | * @param htim : TIM handle |
1296 | * @param htim TIM handle |
1045 | * @param Channel : TIM Channel to be enabled |
1297 | * @param Channel TIM Channel to be enabled |
1046 | * This parameter can be one of the following values: |
1298 | * This parameter can be one of the following values: |
1047 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
1299 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
1048 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
1300 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
1049 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
1301 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
1050 | * @param pData : The source Buffer address. |
1302 | * @param pData The source Buffer address. |
1051 | * @param Length : The length of data to be transferred from memory to TIM peripheral |
1303 | * @param Length The length of data to be transferred from memory to TIM peripheral |
1052 | * @retval HAL status |
1304 | * @retval HAL status |
1053 | */ |
1305 | */ |
1054 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) |
1306 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) |
1055 | { |
1307 | { |
- | 1308 | uint32_t tmpsmcr; |
|
- | 1309 | ||
1056 | /* Check the parameters */ |
1310 | /* Check the parameters */ |
1057 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); |
1311 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); |
1058 | 1312 | ||
- | 1313 | /* Set the TIM complementary channel state */ |
|
1059 | if((htim->State == HAL_TIM_STATE_BUSY)) |
1314 | if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) |
1060 | { |
1315 | { |
1061 | return HAL_BUSY; |
1316 | return HAL_BUSY; |
1062 | } |
1317 | } |
1063 | else if((htim->State == HAL_TIM_STATE_READY)) |
1318 | else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) |
1064 | { |
1319 | { |
1065 | if(((uint32_t)pData == 0U) && (Length > 0U)) |
1320 | if ((pData == NULL) && (Length > 0U)) |
1066 | { |
1321 | { |
1067 | return HAL_ERROR; |
1322 | return HAL_ERROR; |
1068 | } |
1323 | } |
1069 | else |
1324 | else |
1070 | { |
1325 | { |
1071 | htim->State = HAL_TIM_STATE_BUSY; |
1326 | TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); |
1072 | } |
1327 | } |
1073 | } |
1328 | } |
- | 1329 | else |
|
- | 1330 | { |
|
- | 1331 | return HAL_ERROR; |
|
- | 1332 | } |
|
- | 1333 | ||
1074 | switch (Channel) |
1334 | switch (Channel) |
1075 | { |
1335 | { |
1076 | case TIM_CHANNEL_1: |
1336 | case TIM_CHANNEL_1: |
1077 | { |
1337 | { |
1078 | /* Set the DMA Period elapsed callback */ |
1338 | /* Set the DMA compare callbacks */ |
1079 | htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; |
1339 | htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; |
- | 1340 | htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; |
|
1080 | 1341 | ||
1081 | /* Set the DMA error callback */ |
1342 | /* Set the DMA error callback */ |
1082 | htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; |
1343 | htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; |
1083 | 1344 | ||
1084 | /* Enable the DMA channel */ |
1345 | /* Enable the DMA channel */ |
1085 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); |
1346 | if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) |
- | 1347 | { |
|
- | 1348 | /* Return error status */ |
|
- | 1349 | return HAL_ERROR; |
|
1086 | 1350 | } |
|
1087 | /* Enable the TIM Capture/Compare 1 DMA request */ |
1351 | /* Enable the TIM Capture/Compare 1 DMA request */ |
1088 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); |
1352 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); |
- | 1353 | break; |
|
1089 | } |
1354 | } |
1090 | break; |
- | |
1091 | 1355 | ||
1092 | case TIM_CHANNEL_2: |
1356 | case TIM_CHANNEL_2: |
1093 | { |
1357 | { |
1094 | /* Set the DMA Period elapsed callback */ |
1358 | /* Set the DMA compare callbacks */ |
1095 | htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; |
1359 | htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; |
- | 1360 | htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; |
|
1096 | 1361 | ||
1097 | /* Set the DMA error callback */ |
1362 | /* Set the DMA error callback */ |
1098 | htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; |
1363 | htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; |
1099 | 1364 | ||
1100 | /* Enable the DMA channel */ |
1365 | /* Enable the DMA channel */ |
1101 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); |
1366 | if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) |
- | 1367 | { |
|
- | 1368 | /* Return error status */ |
|
- | 1369 | return HAL_ERROR; |
|
1102 | 1370 | } |
|
1103 | /* Enable the TIM Capture/Compare 2 DMA request */ |
1371 | /* Enable the TIM Capture/Compare 2 DMA request */ |
1104 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); |
1372 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); |
- | 1373 | break; |
|
1105 | } |
1374 | } |
1106 | break; |
- | |
1107 | 1375 | ||
1108 | case TIM_CHANNEL_3: |
1376 | case TIM_CHANNEL_3: |
1109 | { |
1377 | { |
1110 | /* Set the DMA Period elapsed callback */ |
1378 | /* Set the DMA compare callbacks */ |
1111 | htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; |
1379 | htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; |
- | 1380 | htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; |
|
1112 | 1381 | ||
1113 | /* Set the DMA error callback */ |
1382 | /* Set the DMA error callback */ |
1114 | htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; |
1383 | htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; |
1115 | 1384 | ||
1116 | /* Enable the DMA channel */ |
1385 | /* Enable the DMA channel */ |
1117 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); |
1386 | if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) |
- | 1387 | { |
|
- | 1388 | /* Return error status */ |
|
- | 1389 | return HAL_ERROR; |
|
1118 | 1390 | } |
|
1119 | /* Enable the TIM Capture/Compare 3 DMA request */ |
1391 | /* Enable the TIM Capture/Compare 3 DMA request */ |
1120 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); |
1392 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); |
- | 1393 | break; |
|
1121 | } |
1394 | } |
1122 | break; |
- | |
1123 | 1395 | ||
1124 | default: |
1396 | default: |
1125 | break; |
1397 | break; |
1126 | } |
1398 | } |
1127 | 1399 | ||
1128 | /* Enable the complementary PWM output */ |
1400 | /* Enable the complementary PWM output */ |
1129 | TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); |
1401 | TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); |
1130 | 1402 | ||
1131 | /* Enable the Main Ouput */ |
1403 | /* Enable the Main Output */ |
1132 | __HAL_TIM_MOE_ENABLE(htim); |
1404 | __HAL_TIM_MOE_ENABLE(htim); |
1133 | 1405 | ||
- | 1406 | /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ |
|
- | 1407 | if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) |
|
- | 1408 | { |
|
- | 1409 | tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; |
|
- | 1410 | if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) |
|
- | 1411 | { |
|
1134 | /* Enable the Peripheral */ |
1412 | __HAL_TIM_ENABLE(htim); |
- | 1413 | } |
|
- | 1414 | } |
|
- | 1415 | else |
|
- | 1416 | { |
|
1135 | __HAL_TIM_ENABLE(htim); |
1417 | __HAL_TIM_ENABLE(htim); |
- | 1418 | } |
|
1136 | 1419 | ||
1137 | /* Return function status */ |
1420 | /* Return function status */ |
1138 | return HAL_OK; |
1421 | return HAL_OK; |
1139 | } |
1422 | } |
1140 | 1423 | ||
1141 | /** |
1424 | /** |
1142 | * @brief Stops the TIM PWM signal generation in DMA mode on the complementary |
1425 | * @brief Stops the TIM PWM signal generation in DMA mode on the complementary |
1143 | * output |
1426 | * output |
1144 | * @param htim : TIM handle |
1427 | * @param htim TIM handle |
1145 | * @param Channel : TIM Channel to be disabled |
1428 | * @param Channel TIM Channel to be disabled |
1146 | * This parameter can be one of the following values: |
1429 | * This parameter can be one of the following values: |
1147 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
1430 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
1148 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
1431 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
1149 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
1432 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
1150 | * @retval HAL status |
1433 | * @retval HAL status |
Line 1158... | Line 1441... | ||
1158 | { |
1441 | { |
1159 | case TIM_CHANNEL_1: |
1442 | case TIM_CHANNEL_1: |
1160 | { |
1443 | { |
1161 | /* Disable the TIM Capture/Compare 1 DMA request */ |
1444 | /* Disable the TIM Capture/Compare 1 DMA request */ |
1162 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); |
1445 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); |
- | 1446 | (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); |
|
- | 1447 | break; |
|
1163 | } |
1448 | } |
1164 | break; |
- | |
1165 | 1449 | ||
1166 | case TIM_CHANNEL_2: |
1450 | case TIM_CHANNEL_2: |
1167 | { |
1451 | { |
1168 | /* Disable the TIM Capture/Compare 2 DMA request */ |
1452 | /* Disable the TIM Capture/Compare 2 DMA request */ |
1169 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); |
1453 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); |
- | 1454 | (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); |
|
- | 1455 | break; |
|
1170 | } |
1456 | } |
1171 | break; |
- | |
1172 | 1457 | ||
1173 | case TIM_CHANNEL_3: |
1458 | case TIM_CHANNEL_3: |
1174 | { |
1459 | { |
1175 | /* Disable the TIM Capture/Compare 3 DMA request */ |
1460 | /* Disable the TIM Capture/Compare 3 DMA request */ |
1176 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); |
1461 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); |
- | 1462 | (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); |
|
- | 1463 | break; |
|
1177 | } |
1464 | } |
1178 | break; |
- | |
1179 | 1465 | ||
1180 | default: |
1466 | default: |
1181 | break; |
1467 | break; |
1182 | } |
1468 | } |
1183 | 1469 | ||
1184 | /* Disable the complementary PWM output */ |
1470 | /* Disable the complementary PWM output */ |
1185 | TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); |
1471 | TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); |
1186 | 1472 | ||
1187 | /* Disable the Main Ouput */ |
1473 | /* Disable the Main Output */ |
1188 | __HAL_TIM_MOE_DISABLE(htim); |
1474 | __HAL_TIM_MOE_DISABLE(htim); |
1189 | 1475 | ||
1190 | /* Disable the Peripheral */ |
1476 | /* Disable the Peripheral */ |
1191 | __HAL_TIM_DISABLE(htim); |
1477 | __HAL_TIM_DISABLE(htim); |
1192 | 1478 | ||
1193 | /* Change the htim state */ |
1479 | /* Set the TIM complementary channel state */ |
1194 | htim->State = HAL_TIM_STATE_READY; |
1480 | TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); |
1195 | 1481 | ||
1196 | /* Return function status */ |
1482 | /* Return function status */ |
1197 | return HAL_OK; |
1483 | return HAL_OK; |
1198 | } |
1484 | } |
1199 | 1485 | ||
1200 | /** |
1486 | /** |
1201 | * @} |
1487 | * @} |
1202 | */ |
1488 | */ |
1203 | 1489 | ||
1204 | /** @defgroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions |
1490 | /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions |
1205 | * @brief Timer Complementary One Pulse functions |
1491 | * @brief Timer Complementary One Pulse functions |
1206 | * |
1492 | * |
1207 | @verbatim |
1493 | @verbatim |
1208 | ============================================================================== |
1494 | ============================================================================== |
1209 | ##### Timer Complementary One Pulse functions ##### |
1495 | ##### Timer Complementary One Pulse functions ##### |
1210 | ============================================================================== |
1496 | ============================================================================== |
1211 | [..] |
1497 | [..] |
Line 1218... | Line 1504... | ||
1218 | @endverbatim |
1504 | @endverbatim |
1219 | * @{ |
1505 | * @{ |
1220 | */ |
1506 | */ |
1221 | 1507 | ||
1222 | /** |
1508 | /** |
1223 | * @brief Starts the TIM One Pulse signal generation on the complemetary |
1509 | * @brief Starts the TIM One Pulse signal generation on the complementary |
1224 | * output. |
1510 | * output. |
1225 | * @param htim : TIM One Pulse handle |
1511 | * @param htim TIM One Pulse handle |
1226 | * @param OutputChannel : TIM Channel to be enabled |
1512 | * @param OutputChannel TIM Channel to be enabled |
1227 | * This parameter can be one of the following values: |
1513 | * This parameter can be one of the following values: |
1228 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
1514 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
1229 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
1515 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
1230 | * @retval HAL status |
1516 | * @retval HAL status |
1231 | */ |
1517 | */ |
1232 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) |
1518 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) |
1233 | { |
1519 | { |
- | 1520 | uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; |
|
- | 1521 | HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel); |
|
- | 1522 | HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel); |
|
- | 1523 | ||
1234 | /* Check the parameters */ |
1524 | /* Check the parameters */ |
1235 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); |
1525 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); |
1236 | 1526 | ||
- | 1527 | /* Check the TIM channels state */ |
|
- | 1528 | if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY) |
|
- | 1529 | || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY)) |
|
- | 1530 | { |
|
- | 1531 | return HAL_ERROR; |
|
- | 1532 | } |
|
- | 1533 | ||
- | 1534 | /* Set the TIM channels state */ |
|
- | 1535 | TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY); |
|
- | 1536 | TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY); |
|
- | 1537 | ||
1237 | /* Enable the complementary One Pulse output */ |
1538 | /* Enable the complementary One Pulse output channel and the Input Capture channel */ |
1238 | TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); |
1539 | TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); |
- | 1540 | TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); |
|
1239 | 1541 | ||
1240 | /* Enable the Main Ouput */ |
1542 | /* Enable the Main Output */ |
1241 | __HAL_TIM_MOE_ENABLE(htim); |
1543 | __HAL_TIM_MOE_ENABLE(htim); |
1242 | 1544 | ||
1243 | /* Return function status */ |
1545 | /* Return function status */ |
1244 | return HAL_OK; |
1546 | return HAL_OK; |
1245 | } |
1547 | } |
1246 | 1548 | ||
1247 | /** |
1549 | /** |
1248 | * @brief Stops the TIM One Pulse signal generation on the complementary |
1550 | * @brief Stops the TIM One Pulse signal generation on the complementary |
1249 | * output. |
1551 | * output. |
1250 | * @param htim : TIM One Pulse handle |
1552 | * @param htim TIM One Pulse handle |
1251 | * @param OutputChannel : TIM Channel to be disabled |
1553 | * @param OutputChannel TIM Channel to be disabled |
1252 | * This parameter can be one of the following values: |
1554 | * This parameter can be one of the following values: |
1253 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
1555 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
1254 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
1556 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
1255 | * @retval HAL status |
1557 | * @retval HAL status |
1256 | */ |
1558 | */ |
1257 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) |
1559 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) |
1258 | { |
1560 | { |
- | 1561 | uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; |
|
1259 | 1562 | ||
1260 | /* Check the parameters */ |
1563 | /* Check the parameters */ |
1261 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); |
1564 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); |
1262 | 1565 | ||
1263 | /* Disable the complementary One Pulse output */ |
1566 | /* Disable the complementary One Pulse output channel and the Input Capture channel */ |
1264 | TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); |
1567 | TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); |
- | 1568 | TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); |
|
1265 | 1569 | ||
1266 | /* Disable the Main Ouput */ |
1570 | /* Disable the Main Output */ |
1267 | __HAL_TIM_MOE_DISABLE(htim); |
1571 | __HAL_TIM_MOE_DISABLE(htim); |
1268 | 1572 | ||
1269 | /* Disable the Peripheral */ |
1573 | /* Disable the Peripheral */ |
1270 | __HAL_TIM_DISABLE(htim); |
1574 | __HAL_TIM_DISABLE(htim); |
1271 | 1575 | ||
- | 1576 | /* Set the TIM channels state */ |
|
- | 1577 | TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY); |
|
- | 1578 | TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY); |
|
- | 1579 | ||
1272 | /* Return function status */ |
1580 | /* Return function status */ |
1273 | return HAL_OK; |
1581 | return HAL_OK; |
1274 | } |
1582 | } |
1275 | 1583 | ||
1276 | /** |
1584 | /** |
1277 | * @brief Starts the TIM One Pulse signal generation in interrupt mode on the |
1585 | * @brief Starts the TIM One Pulse signal generation in interrupt mode on the |
1278 | * complementary channel. |
1586 | * complementary channel. |
1279 | * @param htim : TIM One Pulse handle |
1587 | * @param htim TIM One Pulse handle |
1280 | * @param OutputChannel : TIM Channel to be enabled |
1588 | * @param OutputChannel TIM Channel to be enabled |
1281 | * This parameter can be one of the following values: |
1589 | * This parameter can be one of the following values: |
1282 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
1590 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
1283 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
1591 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
1284 | * @retval HAL status |
1592 | * @retval HAL status |
1285 | */ |
1593 | */ |
1286 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) |
1594 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) |
1287 | { |
1595 | { |
- | 1596 | uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; |
|
- | 1597 | HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel); |
|
- | 1598 | HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel); |
|
- | 1599 | ||
1288 | /* Check the parameters */ |
1600 | /* Check the parameters */ |
1289 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); |
1601 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); |
1290 | 1602 | ||
- | 1603 | /* Check the TIM channels state */ |
|
- | 1604 | if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY) |
|
- | 1605 | || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY)) |
|
- | 1606 | { |
|
- | 1607 | return HAL_ERROR; |
|
- | 1608 | } |
|
- | 1609 | ||
- | 1610 | /* Set the TIM channels state */ |
|
- | 1611 | TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY); |
|
- | 1612 | TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY); |
|
- | 1613 | ||
1291 | /* Enable the TIM Capture/Compare 1 interrupt */ |
1614 | /* Enable the TIM Capture/Compare 1 interrupt */ |
1292 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); |
1615 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); |
1293 | 1616 | ||
1294 | /* Enable the TIM Capture/Compare 2 interrupt */ |
1617 | /* Enable the TIM Capture/Compare 2 interrupt */ |
1295 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); |
1618 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); |
1296 | 1619 | ||
1297 | /* Enable the complementary One Pulse output */ |
1620 | /* Enable the complementary One Pulse output channel and the Input Capture channel */ |
1298 | TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); |
1621 | TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); |
- | 1622 | TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); |
|
1299 | 1623 | ||
1300 | /* Enable the Main Ouput */ |
1624 | /* Enable the Main Output */ |
1301 | __HAL_TIM_MOE_ENABLE(htim); |
1625 | __HAL_TIM_MOE_ENABLE(htim); |
1302 | 1626 | ||
1303 | /* Return function status */ |
1627 | /* Return function status */ |
1304 | return HAL_OK; |
1628 | return HAL_OK; |
1305 | } |
1629 | } |
1306 | 1630 | ||
1307 | /** |
1631 | /** |
1308 | * @brief Stops the TIM One Pulse signal generation in interrupt mode on the |
1632 | * @brief Stops the TIM One Pulse signal generation in interrupt mode on the |
1309 | * complementary channel. |
1633 | * complementary channel. |
1310 | * @param htim : TIM One Pulse handle |
1634 | * @param htim TIM One Pulse handle |
1311 | * @param OutputChannel : TIM Channel to be disabled |
1635 | * @param OutputChannel TIM Channel to be disabled |
1312 | * This parameter can be one of the following values: |
1636 | * This parameter can be one of the following values: |
1313 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
1637 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
1314 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
1638 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
1315 | * @retval HAL status |
1639 | * @retval HAL status |
1316 | */ |
1640 | */ |
1317 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) |
1641 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) |
1318 | { |
1642 | { |
- | 1643 | uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; |
|
- | 1644 | ||
1319 | /* Check the parameters */ |
1645 | /* Check the parameters */ |
1320 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); |
1646 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); |
1321 | 1647 | ||
1322 | /* Disable the TIM Capture/Compare 1 interrupt */ |
1648 | /* Disable the TIM Capture/Compare 1 interrupt */ |
1323 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); |
1649 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); |
1324 | 1650 | ||
1325 | /* Disable the TIM Capture/Compare 2 interrupt */ |
1651 | /* Disable the TIM Capture/Compare 2 interrupt */ |
1326 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); |
1652 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); |
1327 | 1653 | ||
1328 | /* Disable the complementary One Pulse output */ |
1654 | /* Disable the complementary One Pulse output channel and the Input Capture channel */ |
1329 | TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); |
1655 | TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); |
- | 1656 | TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); |
|
1330 | 1657 | ||
1331 | /* Disable the Main Ouput */ |
1658 | /* Disable the Main Output */ |
1332 | __HAL_TIM_MOE_DISABLE(htim); |
1659 | __HAL_TIM_MOE_DISABLE(htim); |
1333 | 1660 | ||
1334 | /* Disable the Peripheral */ |
1661 | /* Disable the Peripheral */ |
1335 | __HAL_TIM_DISABLE(htim); |
1662 | __HAL_TIM_DISABLE(htim); |
1336 | 1663 | ||
- | 1664 | /* Set the TIM channels state */ |
|
- | 1665 | TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY); |
|
- | 1666 | TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY); |
|
- | 1667 | ||
1337 | /* Return function status */ |
1668 | /* Return function status */ |
1338 | return HAL_OK; |
1669 | return HAL_OK; |
1339 | } |
1670 | } |
1340 | 1671 | ||
1341 | /** |
1672 | /** |
1342 | * @} |
1673 | * @} |
1343 | */ |
1674 | */ |
1344 | 1675 | ||
1345 | #endif /* defined(STM32F100xB) || defined(STM32F100xE) || */ |
- | |
1346 | /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */ |
- | |
1347 | /* defined(STM32F105xC) || defined(STM32F107xC) */ |
- | |
1348 | - | ||
1349 | /** @defgroup TIMEx_Exported_Functions_Group5 Peripheral Control functions |
1676 | /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions |
1350 | * @brief Peripheral Control functions |
1677 | * @brief Peripheral Control functions |
1351 | * |
1678 | * |
1352 | @verbatim |
1679 | @verbatim |
1353 | ============================================================================== |
1680 | ============================================================================== |
1354 | ##### Peripheral Control functions ##### |
1681 | ##### Peripheral Control functions ##### |
1355 | ============================================================================== |
1682 | ============================================================================== |
1356 | [..] |
1683 | [..] |
1357 | This section provides functions allowing to: |
1684 | This section provides functions allowing to: |
1358 | (+) Configure the commutation event in case of use of the Hall sensor interface. |
1685 | (+) Configure the commutation event in case of use of the Hall sensor interface. |
- | 1686 | (+) Configure Output channels for OC and PWM mode. |
|
- | 1687 | ||
1359 | (+) Configure Complementary channels, break features and dead time. |
1688 | (+) Configure Complementary channels, break features and dead time. |
1360 | (+) Configure Master synchronization. |
1689 | (+) Configure Master synchronization. |
- | 1690 | (+) Configure timer remapping capabilities. |
|
1361 | 1691 | ||
1362 | @endverbatim |
1692 | @endverbatim |
1363 | * @{ |
1693 | * @{ |
1364 | */ |
1694 | */ |
1365 | 1695 | ||
1366 | #if defined (STM32F100xB) || defined (STM32F100xE) || \ |
- | |
1367 | defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \ |
- | |
1368 | defined (STM32F105xC) || defined (STM32F107xC) |
- | |
1369 | - | ||
1370 | /** |
1696 | /** |
1371 | * @brief Configure the TIM commutation event sequence. |
1697 | * @brief Configure the TIM commutation event sequence. |
1372 | * @note: this function is mandatory to use the commutation event in order to |
1698 | * @note This function is mandatory to use the commutation event in order to |
1373 | * update the configuration at each commutation detection on the TRGI input of the Timer, |
1699 | * update the configuration at each commutation detection on the TRGI input of the Timer, |
1374 | * the typical use of this feature is with the use of another Timer(interface Timer) |
1700 | * the typical use of this feature is with the use of another Timer(interface Timer) |
1375 | * configured in Hall sensor interface, this interface Timer will generate the |
1701 | * configured in Hall sensor interface, this interface Timer will generate the |
1376 | * commutation at its TRGO output (connected to Timer used in this function) each time |
1702 | * commutation at its TRGO output (connected to Timer used in this function) each time |
1377 | * the TI1 of the Interface Timer detect a commutation at its input TI1. |
1703 | * the TI1 of the Interface Timer detect a commutation at its input TI1. |
1378 | * @param htim : TIM handle |
1704 | * @param htim TIM handle |
1379 | * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor |
1705 | * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor |
1380 | * This parameter can be one of the following values: |
1706 | * This parameter can be one of the following values: |
1381 | * @arg TIM_TS_ITR0: Internal trigger 0 selected |
1707 | * @arg TIM_TS_ITR0: Internal trigger 0 selected |
1382 | * @arg TIM_TS_ITR1: Internal trigger 1 selected |
1708 | * @arg TIM_TS_ITR1: Internal trigger 1 selected |
1383 | * @arg TIM_TS_ITR2: Internal trigger 2 selected |
1709 | * @arg TIM_TS_ITR2: Internal trigger 2 selected |
1384 | * @arg TIM_TS_ITR3: Internal trigger 3 selected |
1710 | * @arg TIM_TS_ITR3: Internal trigger 3 selected |
1385 | * @arg TIM_TS_NONE: No trigger is needed |
1711 | * @arg TIM_TS_NONE: No trigger is needed |
1386 | * @param CommutationSource : the Commutation Event source |
1712 | * @param CommutationSource the Commutation Event source |
1387 | * This parameter can be one of the following values: |
1713 | * This parameter can be one of the following values: |
1388 | * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer |
1714 | * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer |
1389 | * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit |
1715 | * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit |
1390 | * @retval HAL status |
1716 | * @retval HAL status |
1391 | */ |
1717 | */ |
1392 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) |
1718 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, |
- | 1719 | uint32_t CommutationSource) |
|
1393 | { |
1720 | { |
1394 | /* Check the parameters */ |
1721 | /* Check the parameters */ |
1395 | assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); |
1722 | assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); |
1396 | assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); |
1723 | assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); |
1397 | 1724 | ||
Line 1409... | Line 1736... | ||
1409 | htim->Instance->CR2 |= TIM_CR2_CCPC; |
1736 | htim->Instance->CR2 |= TIM_CR2_CCPC; |
1410 | /* Select the Commutation event source */ |
1737 | /* Select the Commutation event source */ |
1411 | htim->Instance->CR2 &= ~TIM_CR2_CCUS; |
1738 | htim->Instance->CR2 &= ~TIM_CR2_CCUS; |
1412 | htim->Instance->CR2 |= CommutationSource; |
1739 | htim->Instance->CR2 |= CommutationSource; |
1413 | 1740 | ||
- | 1741 | /* Disable Commutation Interrupt */ |
|
- | 1742 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); |
|
- | 1743 | ||
- | 1744 | /* Disable Commutation DMA request */ |
|
- | 1745 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); |
|
- | 1746 | ||
1414 | __HAL_UNLOCK(htim); |
1747 | __HAL_UNLOCK(htim); |
1415 | 1748 | ||
1416 | return HAL_OK; |
1749 | return HAL_OK; |
1417 | } |
1750 | } |
1418 | 1751 | ||
1419 | /** |
1752 | /** |
1420 | * @brief Configure the TIM commutation event sequence with interrupt. |
1753 | * @brief Configure the TIM commutation event sequence with interrupt. |
1421 | * @note: this function is mandatory to use the commutation event in order to |
1754 | * @note This function is mandatory to use the commutation event in order to |
1422 | * update the configuration at each commutation detection on the TRGI input of the Timer, |
1755 | * update the configuration at each commutation detection on the TRGI input of the Timer, |
1423 | * the typical use of this feature is with the use of another Timer(interface Timer) |
1756 | * the typical use of this feature is with the use of another Timer(interface Timer) |
1424 | * configured in Hall sensor interface, this interface Timer will generate the |
1757 | * configured in Hall sensor interface, this interface Timer will generate the |
1425 | * commutation at its TRGO output (connected to Timer used in this function) each time |
1758 | * commutation at its TRGO output (connected to Timer used in this function) each time |
1426 | * the TI1 of the Interface Timer detect a commutation at its input TI1. |
1759 | * the TI1 of the Interface Timer detect a commutation at its input TI1. |
1427 | * @param htim : TIM handle |
1760 | * @param htim TIM handle |
1428 | * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor |
1761 | * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor |
1429 | * This parameter can be one of the following values: |
1762 | * This parameter can be one of the following values: |
1430 | * @arg TIM_TS_ITR0: Internal trigger 0 selected |
1763 | * @arg TIM_TS_ITR0: Internal trigger 0 selected |
1431 | * @arg TIM_TS_ITR1: Internal trigger 1 selected |
1764 | * @arg TIM_TS_ITR1: Internal trigger 1 selected |
1432 | * @arg TIM_TS_ITR2: Internal trigger 2 selected |
1765 | * @arg TIM_TS_ITR2: Internal trigger 2 selected |
1433 | * @arg TIM_TS_ITR3: Internal trigger 3 selected |
1766 | * @arg TIM_TS_ITR3: Internal trigger 3 selected |
1434 | * @arg TIM_TS_NONE: No trigger is needed |
1767 | * @arg TIM_TS_NONE: No trigger is needed |
1435 | * @param CommutationSource : the Commutation Event source |
1768 | * @param CommutationSource the Commutation Event source |
1436 | * This parameter can be one of the following values: |
1769 | * This parameter can be one of the following values: |
1437 | * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer |
1770 | * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer |
1438 | * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit |
1771 | * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit |
1439 | * @retval HAL status |
1772 | * @retval HAL status |
1440 | */ |
1773 | */ |
1441 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) |
1774 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, |
- | 1775 | uint32_t CommutationSource) |
|
1442 | { |
1776 | { |
1443 | /* Check the parameters */ |
1777 | /* Check the parameters */ |
1444 | assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); |
1778 | assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); |
1445 | assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); |
1779 | assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); |
1446 | 1780 | ||
Line 1458... | Line 1792... | ||
1458 | htim->Instance->CR2 |= TIM_CR2_CCPC; |
1792 | htim->Instance->CR2 |= TIM_CR2_CCPC; |
1459 | /* Select the Commutation event source */ |
1793 | /* Select the Commutation event source */ |
1460 | htim->Instance->CR2 &= ~TIM_CR2_CCUS; |
1794 | htim->Instance->CR2 &= ~TIM_CR2_CCUS; |
1461 | htim->Instance->CR2 |= CommutationSource; |
1795 | htim->Instance->CR2 |= CommutationSource; |
1462 | 1796 | ||
- | 1797 | /* Disable Commutation DMA request */ |
|
- | 1798 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); |
|
- | 1799 | ||
1463 | /* Enable the Commutation Interrupt Request */ |
1800 | /* Enable the Commutation Interrupt */ |
1464 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); |
1801 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); |
1465 | 1802 | ||
1466 | __HAL_UNLOCK(htim); |
1803 | __HAL_UNLOCK(htim); |
1467 | 1804 | ||
1468 | return HAL_OK; |
1805 | return HAL_OK; |
1469 | } |
1806 | } |
1470 | 1807 | ||
1471 | /** |
1808 | /** |
1472 | * @brief Configure the TIM commutation event sequence with DMA. |
1809 | * @brief Configure the TIM commutation event sequence with DMA. |
1473 | * @note: this function is mandatory to use the commutation event in order to |
1810 | * @note This function is mandatory to use the commutation event in order to |
1474 | * update the configuration at each commutation detection on the TRGI input of the Timer, |
1811 | * update the configuration at each commutation detection on the TRGI input of the Timer, |
1475 | * the typical use of this feature is with the use of another Timer(interface Timer) |
1812 | * the typical use of this feature is with the use of another Timer(interface Timer) |
1476 | * configured in Hall sensor interface, this interface Timer will generate the |
1813 | * configured in Hall sensor interface, this interface Timer will generate the |
1477 | * commutation at its TRGO output (connected to Timer used in this function) each time |
1814 | * commutation at its TRGO output (connected to Timer used in this function) each time |
1478 | * the TI1 of the Interface Timer detect a commutation at its input TI1. |
1815 | * the TI1 of the Interface Timer detect a commutation at its input TI1. |
1479 | * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set |
1816 | * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set |
1480 | * @param htim : TIM handle |
1817 | * @param htim TIM handle |
1481 | * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor |
1818 | * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor |
1482 | * This parameter can be one of the following values: |
1819 | * This parameter can be one of the following values: |
1483 | * @arg TIM_TS_ITR0: Internal trigger 0 selected |
1820 | * @arg TIM_TS_ITR0: Internal trigger 0 selected |
1484 | * @arg TIM_TS_ITR1: Internal trigger 1 selected |
1821 | * @arg TIM_TS_ITR1: Internal trigger 1 selected |
1485 | * @arg TIM_TS_ITR2: Internal trigger 2 selected |
1822 | * @arg TIM_TS_ITR2: Internal trigger 2 selected |
1486 | * @arg TIM_TS_ITR3: Internal trigger 3 selected |
1823 | * @arg TIM_TS_ITR3: Internal trigger 3 selected |
1487 | * @arg TIM_TS_NONE: No trigger is needed |
1824 | * @arg TIM_TS_NONE: No trigger is needed |
1488 | * @param CommutationSource : the Commutation Event source |
1825 | * @param CommutationSource the Commutation Event source |
1489 | * This parameter can be one of the following values: |
1826 | * This parameter can be one of the following values: |
1490 | * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer |
1827 | * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer |
1491 | * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit |
1828 | * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit |
1492 | * @retval HAL status |
1829 | * @retval HAL status |
1493 | */ |
1830 | */ |
1494 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) |
1831 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, |
- | 1832 | uint32_t CommutationSource) |
|
1495 | { |
1833 | { |
1496 | /* Check the parameters */ |
1834 | /* Check the parameters */ |
1497 | assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); |
1835 | assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); |
1498 | assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); |
1836 | assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); |
1499 | 1837 | ||
Line 1514... | Line 1852... | ||
1514 | htim->Instance->CR2 |= CommutationSource; |
1852 | htim->Instance->CR2 |= CommutationSource; |
1515 | 1853 | ||
1516 | /* Enable the Commutation DMA Request */ |
1854 | /* Enable the Commutation DMA Request */ |
1517 | /* Set the DMA Commutation Callback */ |
1855 | /* Set the DMA Commutation Callback */ |
1518 | htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; |
1856 | htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; |
- | 1857 | htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; |
|
1519 | /* Set the DMA error callback */ |
1858 | /* Set the DMA error callback */ |
1520 | htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; |
1859 | htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; |
1521 | 1860 | ||
- | 1861 | /* Disable Commutation Interrupt */ |
|
- | 1862 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); |
|
- | 1863 | ||
1522 | /* Enable the Commutation DMA Request */ |
1864 | /* Enable the Commutation DMA Request */ |
1523 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); |
1865 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); |
1524 | 1866 | ||
1525 | __HAL_UNLOCK(htim); |
1867 | __HAL_UNLOCK(htim); |
1526 | 1868 | ||
1527 | return HAL_OK; |
1869 | return HAL_OK; |
1528 | } |
1870 | } |
1529 | 1871 | ||
1530 | /** |
1872 | /** |
- | 1873 | * @brief Configures the TIM in master mode. |
|
- | 1874 | * @param htim TIM handle. |
|
- | 1875 | * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that |
|
- | 1876 | * contains the selected trigger output (TRGO) and the Master/Slave |
|
- | 1877 | * mode. |
|
- | 1878 | * @retval HAL status |
|
- | 1879 | */ |
|
- | 1880 | HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, |
|
- | 1881 | TIM_MasterConfigTypeDef *sMasterConfig) |
|
- | 1882 | { |
|
- | 1883 | uint32_t tmpcr2; |
|
- | 1884 | uint32_t tmpsmcr; |
|
- | 1885 | ||
- | 1886 | /* Check the parameters */ |
|
- | 1887 | assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); |
|
- | 1888 | assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); |
|
- | 1889 | assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); |
|
- | 1890 | ||
- | 1891 | /* Check input state */ |
|
- | 1892 | __HAL_LOCK(htim); |
|
- | 1893 | ||
- | 1894 | /* Change the handler state */ |
|
- | 1895 | htim->State = HAL_TIM_STATE_BUSY; |
|
- | 1896 | ||
- | 1897 | /* Get the TIMx CR2 register value */ |
|
- | 1898 | tmpcr2 = htim->Instance->CR2; |
|
- | 1899 | ||
- | 1900 | /* Get the TIMx SMCR register value */ |
|
- | 1901 | tmpsmcr = htim->Instance->SMCR; |
|
- | 1902 | ||
- | 1903 | /* Reset the MMS Bits */ |
|
- | 1904 | tmpcr2 &= ~TIM_CR2_MMS; |
|
- | 1905 | /* Select the TRGO source */ |
|
- | 1906 | tmpcr2 |= sMasterConfig->MasterOutputTrigger; |
|
- | 1907 | ||
- | 1908 | /* Update TIMx CR2 */ |
|
- | 1909 | htim->Instance->CR2 = tmpcr2; |
|
- | 1910 | ||
- | 1911 | if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) |
|
- | 1912 | { |
|
- | 1913 | /* Reset the MSM Bit */ |
|
- | 1914 | tmpsmcr &= ~TIM_SMCR_MSM; |
|
- | 1915 | /* Set master mode */ |
|
- | 1916 | tmpsmcr |= sMasterConfig->MasterSlaveMode; |
|
- | 1917 | ||
- | 1918 | /* Update TIMx SMCR */ |
|
- | 1919 | htim->Instance->SMCR = tmpsmcr; |
|
- | 1920 | } |
|
- | 1921 | ||
- | 1922 | /* Change the htim state */ |
|
- | 1923 | htim->State = HAL_TIM_STATE_READY; |
|
- | 1924 | ||
- | 1925 | __HAL_UNLOCK(htim); |
|
- | 1926 | ||
- | 1927 | return HAL_OK; |
|
- | 1928 | } |
|
- | 1929 | ||
- | 1930 | /** |
|
1531 | * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State |
1931 | * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State |
1532 | * and the AOE(automatic output enable). |
1932 | * and the AOE(automatic output enable). |
1533 | * @param htim : TIM handle |
1933 | * @param htim TIM handle |
1534 | * @param sBreakDeadTimeConfig : pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that |
1934 | * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that |
1535 | * contains the BDTR Register configuration information for the TIM peripheral. |
1935 | * contains the BDTR Register configuration information for the TIM peripheral. |
- | 1936 | * @note Interrupts can be generated when an active level is detected on the |
|
- | 1937 | * break input, the break 2 input or the system break input. Break |
|
- | 1938 | * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. |
|
1536 | * @retval HAL status |
1939 | * @retval HAL status |
1537 | */ |
1940 | */ |
1538 | HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, |
1941 | HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, |
1539 | TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) |
1942 | TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) |
1540 | { |
1943 | { |
- | 1944 | /* Keep this variable initialized to 0 as it is used to configure BDTR register */ |
|
1541 | uint32_t tmpbdtr = 0U; |
1945 | uint32_t tmpbdtr = 0U; |
1542 | 1946 | ||
1543 | /* Check the parameters */ |
1947 | /* Check the parameters */ |
1544 | assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); |
1948 | assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); |
1545 | assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); |
1949 | assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); |
Line 1548... | Line 1952... | ||
1548 | assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); |
1952 | assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); |
1549 | assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); |
1953 | assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); |
1550 | assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); |
1954 | assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); |
1551 | assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); |
1955 | assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); |
1552 | 1956 | ||
1553 | /* Process Locked */ |
1957 | /* Check input state */ |
1554 | __HAL_LOCK(htim); |
1958 | __HAL_LOCK(htim); |
1555 | 1959 | ||
1556 | /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, |
1960 | /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, |
1557 | the OSSI State, the dead time value and the Automatic Output Enable Bit */ |
1961 | the OSSI State, the dead time value and the Automatic Output Enable Bit */ |
1558 | 1962 | ||
Line 1562... | Line 1966... | ||
1562 | MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); |
1966 | MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); |
1563 | MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); |
1967 | MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); |
1564 | MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); |
1968 | MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); |
1565 | MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); |
1969 | MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); |
1566 | MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); |
1970 | MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); |
1567 | MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput); |
- | |
- | 1971 | ||
1568 | 1972 | ||
1569 | /* Set TIMx_BDTR */ |
1973 | /* Set TIMx_BDTR */ |
1570 | htim->Instance->BDTR = tmpbdtr; |
1974 | htim->Instance->BDTR = tmpbdtr; |
1571 | 1975 | ||
1572 | __HAL_UNLOCK(htim); |
1976 | __HAL_UNLOCK(htim); |
1573 | 1977 | ||
1574 | return HAL_OK; |
1978 | return HAL_OK; |
1575 | } |
1979 | } |
1576 | 1980 | ||
1577 | #endif /* defined(STM32F100xB) || defined(STM32F100xE) || */ |
- | |
1578 | /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */ |
- | |
1579 | /* defined(STM32F105xC) || defined(STM32F107xC) */ |
- | |
1580 | - | ||
1581 | /** |
1981 | /** |
1582 | * @brief Configures the TIM in master mode. |
1982 | * @brief Configures the TIMx Remapping input capabilities. |
1583 | * @param htim : TIM handle. |
1983 | * @param htim TIM handle. |
1584 | * @param sMasterConfig : pointer to a TIM_MasterConfigTypeDef structure that |
1984 | * @param Remap specifies the TIM remapping source. |
1585 | * contains the selected trigger output (TRGO) and the Master/Slave |
- | |
1586 | * mode. |
1985 | * |
1587 | * @retval HAL status |
1986 | * @retval HAL status |
1588 | */ |
1987 | */ |
1589 | HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig) |
1988 | HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) |
1590 | { |
1989 | { |
1591 | /* Check the parameters */ |
1990 | /* Prevent unused argument(s) compilation warning */ |
1592 | assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); |
- | |
1593 | assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); |
- | |
1594 | assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); |
- | |
1595 | - | ||
1596 | __HAL_LOCK(htim); |
1991 | UNUSED(htim); |
1597 | - | ||
1598 | htim->State = HAL_TIM_STATE_BUSY; |
- | |
1599 | - | ||
1600 | /* Reset the MMS Bits */ |
- | |
1601 | htim->Instance->CR2 &= ~TIM_CR2_MMS; |
- | |
1602 | /* Select the TRGO source */ |
- | |
1603 | htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger; |
- | |
1604 | - | ||
1605 | /* Reset the MSM Bit */ |
- | |
1606 | htim->Instance->SMCR &= ~TIM_SMCR_MSM; |
- | |
1607 | /* Set or Reset the MSM Bit */ |
- | |
1608 | htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode; |
- | |
1609 | - | ||
1610 | htim->State = HAL_TIM_STATE_READY; |
- | |
1611 | - | ||
1612 | __HAL_UNLOCK(htim); |
1992 | UNUSED(Remap); |
1613 | 1993 | ||
1614 | return HAL_OK; |
1994 | return HAL_OK; |
1615 | } |
1995 | } |
1616 | 1996 | ||
1617 | /** |
1997 | /** |
1618 | * @} |
1998 | * @} |
1619 | */ |
1999 | */ |
1620 | 2000 | ||
1621 | /** @defgroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions |
2001 | /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions |
1622 | * @brief Extension Callbacks functions |
2002 | * @brief Extended Callbacks functions |
1623 | * |
2003 | * |
1624 | @verbatim |
2004 | @verbatim |
1625 | ============================================================================== |
2005 | ============================================================================== |
1626 | ##### Extension Callbacks functions ##### |
2006 | ##### Extended Callbacks functions ##### |
1627 | ============================================================================== |
2007 | ============================================================================== |
1628 | [..] |
2008 | [..] |
1629 | This section provides Extension TIM callback functions: |
2009 | This section provides Extended TIM callback functions: |
1630 | (+) Timer Commutation callback |
2010 | (+) Timer Commutation callback |
1631 | (+) Timer Break callback |
2011 | (+) Timer Break callback |
1632 | 2012 | ||
1633 | @endverbatim |
2013 | @endverbatim |
1634 | * @{ |
2014 | * @{ |
1635 | */ |
2015 | */ |
1636 | 2016 | ||
1637 | /** |
2017 | /** |
1638 | * @brief Hall commutation changed callback in non blocking mode |
2018 | * @brief Hall commutation changed callback in non-blocking mode |
1639 | * @param htim : TIM handle |
2019 | * @param htim TIM handle |
1640 | * @retval None |
2020 | * @retval None |
1641 | */ |
2021 | */ |
1642 | __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim) |
2022 | __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) |
1643 | { |
2023 | { |
1644 | /* Prevent unused argument(s) compilation warning */ |
2024 | /* Prevent unused argument(s) compilation warning */ |
1645 | UNUSED(htim); |
2025 | UNUSED(htim); |
- | 2026 | ||
1646 | /* NOTE : This function Should not be modified, when the callback is needed, |
2027 | /* NOTE : This function should not be modified, when the callback is needed, |
1647 | the HAL_TIMEx_CommutationCallback could be implemented in the user file |
2028 | the HAL_TIMEx_CommutCallback could be implemented in the user file |
1648 | */ |
2029 | */ |
1649 | } |
2030 | } |
1650 | - | ||
1651 | /** |
2031 | /** |
1652 | * @brief Hall Break detection callback in non blocking mode |
2032 | * @brief Hall commutation changed half complete callback in non-blocking mode |
1653 | * @param htim : TIM handle |
2033 | * @param htim TIM handle |
1654 | * @retval None |
2034 | * @retval None |
1655 | */ |
2035 | */ |
1656 | __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) |
2036 | __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) |
1657 | { |
2037 | { |
1658 | /* Prevent unused argument(s) compilation warning */ |
2038 | /* Prevent unused argument(s) compilation warning */ |
1659 | UNUSED(htim); |
2039 | UNUSED(htim); |
- | 2040 | ||
1660 | /* NOTE : This function Should not be modified, when the callback is needed, |
2041 | /* NOTE : This function should not be modified, when the callback is needed, |
1661 | the HAL_TIMEx_BreakCallback could be implemented in the user file |
2042 | the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file |
1662 | */ |
2043 | */ |
1663 | } |
2044 | } |
1664 | 2045 | ||
1665 | /** |
2046 | /** |
1666 | * @brief TIM DMA Commutation callback. |
2047 | * @brief Hall Break detection callback in non-blocking mode |
1667 | * @param hdma : pointer to DMA handle. |
2048 | * @param htim TIM handle |
1668 | * @retval None |
2049 | * @retval None |
1669 | */ |
2050 | */ |
1670 | void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) |
2051 | __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) |
1671 | { |
2052 | { |
1672 | TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
2053 | /* Prevent unused argument(s) compilation warning */ |
1673 | - | ||
1674 | htim->State= HAL_TIM_STATE_READY; |
2054 | UNUSED(htim); |
1675 | 2055 | ||
- | 2056 | /* NOTE : This function should not be modified, when the callback is needed, |
|
1676 | HAL_TIMEx_CommutationCallback(htim); |
2057 | the HAL_TIMEx_BreakCallback could be implemented in the user file |
- | 2058 | */ |
|
1677 | } |
2059 | } |
1678 | - | ||
1679 | /** |
2060 | /** |
1680 | * @} |
2061 | * @} |
1681 | */ |
2062 | */ |
1682 | 2063 | ||
1683 | #if defined (STM32F100xB) || defined (STM32F100xE) || \ |
- | |
1684 | defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \ |
- | |
1685 | defined (STM32F105xC) || defined (STM32F107xC) |
- | |
1686 | - | ||
1687 | /** @defgroup TIMEx_Exported_Functions_Group7 Extension Peripheral State functions |
2064 | /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions |
1688 | * @brief Extension Peripheral State functions |
2065 | * @brief Extended Peripheral State functions |
1689 | * |
2066 | * |
1690 | @verbatim |
2067 | @verbatim |
1691 | ============================================================================== |
2068 | ============================================================================== |
1692 | ##### Extension Peripheral State functions ##### |
2069 | ##### Extended Peripheral State functions ##### |
1693 | ============================================================================== |
2070 | ============================================================================== |
1694 | [..] |
2071 | [..] |
1695 | This subsection permit to get in run-time the status of the peripheral |
2072 | This subsection permits to get in run-time the status of the peripheral |
1696 | and the data flow. |
2073 | and the data flow. |
1697 | 2074 | ||
1698 | @endverbatim |
2075 | @endverbatim |
1699 | * @{ |
2076 | * @{ |
1700 | */ |
2077 | */ |
1701 | 2078 | ||
1702 | /** |
2079 | /** |
1703 | * @brief Return the TIM Hall Sensor interface state |
2080 | * @brief Return the TIM Hall Sensor interface handle state. |
1704 | * @param htim : TIM Hall Sensor handle |
2081 | * @param htim TIM Hall Sensor handle |
1705 | * @retval HAL state |
2082 | * @retval HAL state |
1706 | */ |
2083 | */ |
1707 | HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) |
2084 | HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) |
1708 | { |
2085 | { |
1709 | return htim->State; |
2086 | return htim->State; |
1710 | } |
2087 | } |
1711 | 2088 | ||
1712 | /** |
2089 | /** |
- | 2090 | * @brief Return actual state of the TIM complementary channel. |
|
1713 | * @} |
2091 | * @param htim TIM handle |
- | 2092 | * @param ChannelN TIM Complementary channel |
|
- | 2093 | * This parameter can be one of the following values: |
|
- | 2094 | * @arg TIM_CHANNEL_1: TIM Channel 1 |
|
- | 2095 | * @arg TIM_CHANNEL_2: TIM Channel 2 |
|
- | 2096 | * @arg TIM_CHANNEL_3: TIM Channel 3 |
|
- | 2097 | * @retval TIM Complementary channel state |
|
1714 | */ |
2098 | */ |
1715 | #endif /* defined(STM32F100xB) || defined(STM32F100xE) || */ |
2099 | HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN) |
- | 2100 | { |
|
1716 | /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */ |
2101 | HAL_TIM_ChannelStateTypeDef channel_state; |
- | 2102 | ||
- | 2103 | /* Check the parameters */ |
|
1717 | /* defined(STM32F105xC) || defined(STM32F107xC) */ |
2104 | assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN)); |
1718 | 2105 | ||
- | 2106 | channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN); |
|
- | 2107 | ||
- | 2108 | return channel_state; |
|
- | 2109 | } |
|
1719 | /** |
2110 | /** |
1720 | * @} |
2111 | * @} |
1721 | */ |
2112 | */ |
1722 | 2113 | ||
1723 | #if defined (STM32F100xB) || defined (STM32F100xE) || \ |
- | |
1724 | defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \ |
- | |
- | 2114 | /** |
|
1725 | defined (STM32F105xC) || defined (STM32F107xC) |
2115 | * @} |
- | 2116 | */ |
|
1726 | 2117 | ||
- | 2118 | /* Private functions ---------------------------------------------------------*/ |
|
1727 | /** @addtogroup TIMEx_Private_Functions |
2119 | /** @defgroup TIMEx_Private_Functions TIMEx Private Functions |
1728 | * @{ |
2120 | * @{ |
1729 | */ |
2121 | */ |
1730 | 2122 | ||
1731 | /** |
2123 | /** |
- | 2124 | * @brief TIM DMA Commutation callback. |
|
- | 2125 | * @param hdma pointer to DMA handle. |
|
- | 2126 | * @retval None |
|
- | 2127 | */ |
|
- | 2128 | void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) |
|
- | 2129 | { |
|
- | 2130 | TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; |
|
- | 2131 | ||
- | 2132 | /* Change the htim state */ |
|
- | 2133 | htim->State = HAL_TIM_STATE_READY; |
|
- | 2134 | ||
- | 2135 | #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
|
- | 2136 | htim->CommutationCallback(htim); |
|
- | 2137 | #else |
|
- | 2138 | HAL_TIMEx_CommutCallback(htim); |
|
- | 2139 | #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
|
- | 2140 | } |
|
- | 2141 | ||
- | 2142 | /** |
|
- | 2143 | * @brief TIM DMA Commutation half complete callback. |
|
- | 2144 | * @param hdma pointer to DMA handle. |
|
- | 2145 | * @retval None |
|
- | 2146 | */ |
|
- | 2147 | void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) |
|
- | 2148 | { |
|
- | 2149 | TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; |
|
- | 2150 | ||
- | 2151 | /* Change the htim state */ |
|
- | 2152 | htim->State = HAL_TIM_STATE_READY; |
|
- | 2153 | ||
- | 2154 | #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
|
- | 2155 | htim->CommutationHalfCpltCallback(htim); |
|
- | 2156 | #else |
|
- | 2157 | HAL_TIMEx_CommutHalfCpltCallback(htim); |
|
- | 2158 | #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
|
- | 2159 | } |
|
- | 2160 | ||
- | 2161 | ||
- | 2162 | /** |
|
- | 2163 | * @brief TIM DMA Delay Pulse complete callback (complementary channel). |
|
- | 2164 | * @param hdma pointer to DMA handle. |
|
- | 2165 | * @retval None |
|
- | 2166 | */ |
|
- | 2167 | static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) |
|
- | 2168 | { |
|
- | 2169 | TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; |
|
- | 2170 | ||
- | 2171 | if (hdma == htim->hdma[TIM_DMA_ID_CC1]) |
|
- | 2172 | { |
|
- | 2173 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; |
|
- | 2174 | ||
- | 2175 | if (hdma->Init.Mode == DMA_NORMAL) |
|
- | 2176 | { |
|
- | 2177 | TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); |
|
- | 2178 | } |
|
- | 2179 | } |
|
- | 2180 | else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) |
|
- | 2181 | { |
|
- | 2182 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; |
|
- | 2183 | ||
- | 2184 | if (hdma->Init.Mode == DMA_NORMAL) |
|
- | 2185 | { |
|
- | 2186 | TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); |
|
- | 2187 | } |
|
- | 2188 | } |
|
- | 2189 | else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) |
|
- | 2190 | { |
|
- | 2191 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; |
|
- | 2192 | ||
- | 2193 | if (hdma->Init.Mode == DMA_NORMAL) |
|
- | 2194 | { |
|
- | 2195 | TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); |
|
- | 2196 | } |
|
- | 2197 | } |
|
- | 2198 | else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) |
|
- | 2199 | { |
|
- | 2200 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; |
|
- | 2201 | ||
- | 2202 | if (hdma->Init.Mode == DMA_NORMAL) |
|
- | 2203 | { |
|
- | 2204 | TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); |
|
- | 2205 | } |
|
- | 2206 | } |
|
- | 2207 | else |
|
- | 2208 | { |
|
- | 2209 | /* nothing to do */ |
|
- | 2210 | } |
|
- | 2211 | ||
- | 2212 | #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
|
- | 2213 | htim->PWM_PulseFinishedCallback(htim); |
|
- | 2214 | #else |
|
- | 2215 | HAL_TIM_PWM_PulseFinishedCallback(htim); |
|
- | 2216 | #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
|
- | 2217 | ||
- | 2218 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; |
|
- | 2219 | } |
|
- | 2220 | ||
- | 2221 | /** |
|
- | 2222 | * @brief TIM DMA error callback (complementary channel) |
|
- | 2223 | * @param hdma pointer to DMA handle. |
|
- | 2224 | * @retval None |
|
- | 2225 | */ |
|
- | 2226 | static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) |
|
- | 2227 | { |
|
- | 2228 | TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; |
|
- | 2229 | ||
- | 2230 | if (hdma == htim->hdma[TIM_DMA_ID_CC1]) |
|
- | 2231 | { |
|
- | 2232 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; |
|
- | 2233 | TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); |
|
- | 2234 | } |
|
- | 2235 | else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) |
|
- | 2236 | { |
|
- | 2237 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; |
|
- | 2238 | TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); |
|
- | 2239 | } |
|
- | 2240 | else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) |
|
- | 2241 | { |
|
- | 2242 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; |
|
- | 2243 | TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); |
|
- | 2244 | } |
|
- | 2245 | else |
|
- | 2246 | { |
|
- | 2247 | /* nothing to do */ |
|
- | 2248 | } |
|
- | 2249 | ||
- | 2250 | #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
|
- | 2251 | htim->ErrorCallback(htim); |
|
- | 2252 | #else |
|
- | 2253 | HAL_TIM_ErrorCallback(htim); |
|
- | 2254 | #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
|
- | 2255 | ||
- | 2256 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; |
|
- | 2257 | } |
|
- | 2258 | ||
- | 2259 | /** |
|
1732 | * @brief Enables or disables the TIM Capture Compare Channel xN. |
2260 | * @brief Enables or disables the TIM Capture Compare Channel xN. |
1733 | * @param TIMx to select the TIM peripheral |
2261 | * @param TIMx to select the TIM peripheral |
1734 | * @param Channel : specifies the TIM Channel |
2262 | * @param Channel specifies the TIM Channel |
1735 | * This parameter can be one of the following values: |
2263 | * This parameter can be one of the following values: |
1736 | * @arg TIM_Channel_1: TIM Channel 1 |
2264 | * @arg TIM_CHANNEL_1: TIM Channel 1 |
1737 | * @arg TIM_Channel_2: TIM Channel 2 |
2265 | * @arg TIM_CHANNEL_2: TIM Channel 2 |
1738 | * @arg TIM_Channel_3: TIM Channel 3 |
2266 | * @arg TIM_CHANNEL_3: TIM Channel 3 |
1739 | * @param ChannelNState : specifies the TIM Channel CCxNE bit new state. |
2267 | * @param ChannelNState specifies the TIM Channel CCxNE bit new state. |
1740 | * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. |
2268 | * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. |
1741 | * @retval None |
2269 | * @retval None |
1742 | */ |
2270 | */ |
1743 | static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState) |
2271 | static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState) |
1744 | { |
2272 | { |
1745 | uint32_t tmp = 0U; |
2273 | uint32_t tmp; |
1746 | 2274 | ||
1747 | tmp = TIM_CCER_CC1NE << Channel; |
2275 | tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ |
1748 | 2276 | ||
1749 | /* Reset the CCxNE Bit */ |
2277 | /* Reset the CCxNE Bit */ |
1750 | TIMx->CCER &= ~tmp; |
2278 | TIMx->CCER &= ~tmp; |
1751 | 2279 | ||
1752 | /* Set or reset the CCxNE Bit */ |
2280 | /* Set or reset the CCxNE Bit */ |
1753 | TIMx->CCER |= (uint32_t)(ChannelNState << Channel); |
2281 | TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ |
1754 | } |
2282 | } |
1755 | - | ||
1756 | /** |
2283 | /** |
1757 | * @} |
2284 | * @} |
1758 | */ |
2285 | */ |
1759 | 2286 | ||
1760 | #endif /* defined(STM32F100xB) || defined(STM32F100xE) || */ |
- | |
1761 | /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */ |
- | |
1762 | /* defined(STM32F105xC) || defined(STM32F107xC) */ |
- | |
1763 | - | ||
1764 | #endif /* HAL_TIM_MODULE_ENABLED */ |
2287 | #endif /* HAL_TIM_MODULE_ENABLED */ |
1765 | /** |
2288 | /** |
1766 | * @} |
2289 | * @} |
1767 | */ |
2290 | */ |
1768 | 2291 |