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/**
 1 
/**
2 
  ******************************************************************************
 2 
  ******************************************************************************
3 
  * @file    stm32f1xx_hal_sram.c
 3 
  * @file    stm32f1xx_hal_sram.c
4 
  * @author  MCD Application Team
 4 
  * @author  MCD Application Team
5 
  * @brief   SRAM HAL module driver.
 5 
  * @brief   SRAM HAL module driver.
6 
  *          This file provides a generic firmware to drive SRAM memories
 6 
  *          This file provides a generic firmware to drive SRAM memories
7 
  *          mounted as external device.
 7 
  *          mounted as external device.
8 
  *
 8 
  *
9 
  @verbatim
 9 
  ******************************************************************************
10 
  ==============================================================================
 10 
  * @attention
11 
                          ##### How to use this driver #####
 11 
  *
12 
  ==============================================================================
 12 
  * Copyright (c) 2016 STMicroelectronics.
13 
  [..]
 13 
  * All rights reserved.
14 
    This driver is a generic layered driver which contains a set of APIs used to
 14 
  *
15 
    control SRAM memories. It uses the FSMC layer functions to interface
 15 
  * This software is licensed under terms that can be found in the LICENSE file
16 
    with SRAM devices.
 16 
  * in the root directory of this software component.
17 
    The following sequence should be followed to configure the FSMC to interface
 17 
  * If no LICENSE file comes with this software, it is provided AS-IS.
18 
    with SRAM/PSRAM memories:
 18 
  *
19 
 
 19 
  ******************************************************************************
20 
   (#) Declare a SRAM_HandleTypeDef handle structure, for example:
 20 
  @verbatim
21 
          SRAM_HandleTypeDef  hsram; and:
 21 
  ==============================================================================
22 
 
 22 
                          ##### How to use this driver #####
23 
       (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
 23 
  ==============================================================================
24 
            values of the structure member.
 24 
  [..]
25 
 
 25 
    This driver is a generic layered driver which contains a set of APIs used to
26 
       (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
 26 
    control SRAM memories. It uses the FSMC layer functions to interface
27 
            base register instance for NOR or SRAM device
 27 
    with SRAM devices.
28 
 
 28 
    The following sequence should be followed to configure the FSMC to interface
29 
       (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
 29 
    with SRAM/PSRAM memories:
30 
            base register instance for NOR or SRAM extended mode
 30 
 
31 
 
 31 
   (#) Declare a SRAM_HandleTypeDef handle structure, for example:
32 
   (#) Declare two FSMC_NORSRAM_TimingTypeDef structures, for both normal and extended
 32 
          SRAM_HandleTypeDef  hsram; and:
33 
       mode timings; for example:
 33 
 
34 
          FSMC_NORSRAM_TimingTypeDef  Timing and FSMC_NORSRAM_TimingTypeDef  ExTiming;
 34 
       (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
35 
      and fill its fields with the allowed values of the structure member.
 35 
            values of the structure member.
36 
 
 36 
 
37 
   (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
 37 
       (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
38 
       performs the following sequence:
 38 
            base register instance for NOR or SRAM device
39 
 
 39 
 
40 
       (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
 40 
       (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
41 
       (##) Control register configuration using the FSMC NORSRAM interface function
 41 
            base register instance for NOR or SRAM extended mode
42 
            FSMC_NORSRAM_Init()
 42 
 
43 
       (##) Timing register configuration using the FSMC NORSRAM interface function
 43 
   (#) Declare two FSMC_NORSRAM_TimingTypeDef structures, for both normal and extended
44 
            FSMC_NORSRAM_Timing_Init()
 44 
       mode timings; for example:
45 
       (##) Extended mode Timing register configuration using the FSMC NORSRAM interface function
 45 
          FSMC_NORSRAM_TimingTypeDef  Timing and FSMC_NORSRAM_TimingTypeDef  ExTiming;
46 
            FSMC_NORSRAM_Extended_Timing_Init()
 46 
      and fill its fields with the allowed values of the structure member.
47 
       (##) Enable the SRAM device using the macro __FSMC_NORSRAM_ENABLE()
 47 
 
48 
 
 48 
   (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
49 
   (#) At this stage you can perform read/write accesses from/to the memory connected
 49 
       performs the following sequence:
50 
       to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
 50 
 
51 
       following APIs:
 51 
       (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
52 
       (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
 52 
       (##) Control register configuration using the FSMC NORSRAM interface function
53 
       (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
 53 
            FSMC_NORSRAM_Init()
54 
 
 54 
       (##) Timing register configuration using the FSMC NORSRAM interface function
55 
   (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
 55 
            FSMC_NORSRAM_Timing_Init()
56 
       HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
 56 
       (##) Extended mode Timing register configuration using the FSMC NORSRAM interface function
57 
 
 57 
            FSMC_NORSRAM_Extended_Timing_Init()
58 
   (#) You can continuously monitor the SRAM device HAL state by calling the function
 58 
       (##) Enable the SRAM device using the macro __FSMC_NORSRAM_ENABLE()
59 
       HAL_SRAM_GetState()
 59 
 
60 
 
 60 
   (#) At this stage you can perform read/write accesses from/to the memory connected
61 
       *** Callback registration ***
 61 
       to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
62 
    =============================================
 62 
       following APIs:
63 
    [..]
 63 
       (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
64 
      The compilation define  USE_HAL_SRAM_REGISTER_CALLBACKS when set to 1
 64 
       (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
65 
      allows the user to configure dynamically the driver callbacks.
 65 
 
66 
 
 66 
   (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
67 
      Use Functions @ref HAL_SRAM_RegisterCallback() to register a user callback,
 67 
       HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
68 
      it allows to register following callbacks:
 68 
 
69 
        (+) MspInitCallback    : SRAM MspInit.
 69 
   (#) You can continuously monitor the SRAM device HAL state by calling the function
70 
        (+) MspDeInitCallback  : SRAM MspDeInit.
 70 
       HAL_SRAM_GetState()
71 
      This function takes as parameters the HAL peripheral handle, the Callback ID
 71 
 
72 
      and a pointer to the user callback function.
 72 
       *** Callback registration ***
73 
 
 73 
    =============================================
74 
      Use function @ref HAL_SRAM_UnRegisterCallback() to reset a callback to the default
 74 
    [..]
75 
      weak (surcharged) function. It allows to reset following callbacks:
 75 
      The compilation define  USE_HAL_SRAM_REGISTER_CALLBACKS when set to 1
76 
        (+) MspInitCallback    : SRAM MspInit.
 76 
      allows the user to configure dynamically the driver callbacks.
77 
        (+) MspDeInitCallback  : SRAM MspDeInit.
 77 
 
78 
      This function) takes as parameters the HAL peripheral handle and the Callback ID.
 78 
      Use Functions HAL_SRAM_RegisterCallback() to register a user callback,
79 
 
 79 
      it allows to register following callbacks:
80 
      By default, after the @ref HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET
 80 
        (+) MspInitCallback    : SRAM MspInit.
81 
      all callbacks are reset to the corresponding legacy weak (surcharged) functions.
 81 
        (+) MspDeInitCallback  : SRAM MspDeInit.
82 
      Exception done for MspInit and MspDeInit callbacks that are respectively
 82 
      This function takes as parameters the HAL peripheral handle, the Callback ID
83 
      reset to the legacy weak (surcharged) functions in the @ref HAL_SRAM_Init
 83 
      and a pointer to the user callback function.
84 
      and @ref  HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand).
 84 
 
85 
      If not, MspInit or MspDeInit are not null, the @ref HAL_SRAM_Init and @ref HAL_SRAM_DeInit
 85 
      Use function HAL_SRAM_UnRegisterCallback() to reset a callback to the default
86 
      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
 86 
      weak (overridden) function. It allows to reset following callbacks:
87 
 
 87 
        (+) MspInitCallback    : SRAM MspInit.
88 
      Callbacks can be registered/unregistered in READY state only.
 88 
        (+) MspDeInitCallback  : SRAM MspDeInit.
89 
      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
 89 
      This function) takes as parameters the HAL peripheral handle and the Callback ID.
90 
      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
 90 
 
91 
      during the Init/DeInit.
 91 
      By default, after the HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET
92 
      In that case first register the MspInit/MspDeInit user callbacks
 92 
      all callbacks are reset to the corresponding legacy weak (overridden) functions.
93 
      using @ref HAL_SRAM_RegisterCallback before calling @ref HAL_SRAM_DeInit
 93 
      Exception done for MspInit and MspDeInit callbacks that are respectively
94 
      or @ref HAL_SRAM_Init function.
 94 
      reset to the legacy weak (overridden) functions in the HAL_SRAM_Init
95 
 
 95 
      and  HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand).
96 
      When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or
 96 
      If not, MspInit or MspDeInit are not null, the HAL_SRAM_Init and HAL_SRAM_DeInit
97 
      not defined, the callback registering feature is not available
 97 
      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
98 
      and weak (surcharged) callbacks are used.
 98 
 
99 
 
 99 
      Callbacks can be registered/unregistered in READY state only.
100 
  @endverbatim
 100 
      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
101 
  ******************************************************************************
 101 
      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
102 
  * @attention
 102 
      during the Init/DeInit.
103 
  *
 103 
      In that case first register the MspInit/MspDeInit user callbacks
104 
  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
 104 
      using HAL_SRAM_RegisterCallback before calling HAL_SRAM_DeInit
105 
  * All rights reserved.</center></h2>
 105 
      or HAL_SRAM_Init function.
106 
  *
 106 
 
107 
  * This software component is licensed by ST under BSD 3-Clause license,
 107 
      When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or
108 
  * the "License"; You may not use this file except in compliance with the
 108 
      not defined, the callback registering feature is not available
109 
  * License. You may obtain a copy of the License at:
 109 
      and weak (overridden) callbacks are used.
110 
  *                       opensource.org/licenses/BSD-3-Clause
 110 
 
111 
  *
 111 
  @endverbatim
112 
  ******************************************************************************
 112 
  ******************************************************************************
113 
  */
 113 
  */
114 
 
 114 
 
115 
/* Includes ------------------------------------------------------------------*/
 115 
/* Includes ------------------------------------------------------------------*/
116 
#include "stm32f1xx_hal.h"
 116 
#include "stm32f1xx_hal.h"
117 
 
 117 
 
118 
#if defined(FSMC_BANK1)
 118 
#if defined(FSMC_BANK1)
119 
 
 119 
 
120 
/** @addtogroup STM32F1xx_HAL_Driver
 120 
/** @addtogroup STM32F1xx_HAL_Driver
121 
  * @{
 121 
  * @{
122 
  */
 122 
  */
123 
 
 123 
 
124 
#ifdef HAL_SRAM_MODULE_ENABLED
 124 
#ifdef HAL_SRAM_MODULE_ENABLED
125 
 
 125 
 
126 
/** @defgroup SRAM SRAM
 126 
/** @defgroup SRAM SRAM
127 
  * @brief SRAM driver modules
 127 
  * @brief SRAM driver modules
128 
  * @{
 128 
  * @{
129 
  */
 129 
  */
130 
 
 130 
 
131 
/* Private typedef -----------------------------------------------------------*/
 131 
/* Private typedef -----------------------------------------------------------*/
132 
/* Private define ------------------------------------------------------------*/
 132 
/* Private define ------------------------------------------------------------*/
133 
/* Private macro -------------------------------------------------------------*/
 133 
/* Private macro -------------------------------------------------------------*/
134 
/* Private variables ---------------------------------------------------------*/
 134 
/* Private variables ---------------------------------------------------------*/
135 
/* Private function prototypes -----------------------------------------------*/
 135 
/* Private function prototypes -----------------------------------------------*/
136 
static void SRAM_DMACplt(DMA_HandleTypeDef *hdma);
 136 
/** @addtogroup SRAM_Private_Functions SRAM Private Functions
137 
static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma);
 137 
  * @{
138 
static void SRAM_DMAError(DMA_HandleTypeDef *hdma);
 138 
  */
139 
 
 139 
static void SRAM_DMACplt(DMA_HandleTypeDef *hdma);
140 
/* Exported functions --------------------------------------------------------*/
 140 
static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma);
141 
 
 141 
static void SRAM_DMAError(DMA_HandleTypeDef *hdma);
142 
/** @defgroup SRAM_Exported_Functions SRAM Exported Functions
 142 
/**
143 
  * @{
 143 
  * @}
144 
  */
 144 
  */
145 
 
 145 
 
146 
/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
 146 
/* Exported functions --------------------------------------------------------*/
147 
  * @brief    Initialization and Configuration functions.
 147 
 
148 
  *
 148 
/** @defgroup SRAM_Exported_Functions SRAM Exported Functions
149 
  @verbatim
 149 
  * @{
150 
  ==============================================================================
 150 
  */
151 
           ##### SRAM Initialization and de_initialization functions #####
 151 
 
152 
  ==============================================================================
 152 
/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
153 
    [..]  This section provides functions allowing to initialize/de-initialize
 153 
  * @brief    Initialization and Configuration functions.
154 
          the SRAM memory
 154 
  *
155 
 
 155 
  @verbatim
156 
@endverbatim
 156 
  ==============================================================================
157 
  * @{
 157 
           ##### SRAM Initialization and de_initialization functions #####
158 
  */
 158 
  ==============================================================================
159 
 
 159 
    [..]  This section provides functions allowing to initialize/de-initialize
160 
/**
 160 
          the SRAM memory
161 
  * @brief  Performs the SRAM device initialization sequence
 161 
 
162 
  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
 162 
@endverbatim
163 
  *                the configuration information for SRAM module.
 163 
  * @{
164 
  * @param  Timing Pointer to SRAM control timing structure
 164 
  */
165 
  * @param  ExtTiming Pointer to SRAM extended mode timing structure
 165 
 
166 
  * @retval HAL status
 166 
/**
167 
  */
 167 
  * @brief  Performs the SRAM device initialization sequence
168 
HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing,
 168 
  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
169 
                                FSMC_NORSRAM_TimingTypeDef *ExtTiming)
 169 
  *                the configuration information for SRAM module.
170 
{
 170 
  * @param  Timing Pointer to SRAM control timing structure
171 
  /* Check the SRAM handle parameter */
 171 
  * @param  ExtTiming Pointer to SRAM extended mode timing structure
172 
  if ((hsram == NULL) || (hsram->Init.BurstAccessMode == FSMC_BURST_ACCESS_MODE_ENABLE))
 172 
  * @retval HAL status
173 
  {
 173 
  */
174 
    return HAL_ERROR;
 174 
HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing,
175 
  }
 175 
                                FSMC_NORSRAM_TimingTypeDef *ExtTiming)
176 
 
 176 
{
177 
  if (hsram->State == HAL_SRAM_STATE_RESET)
 177 
  /* Check the SRAM handle parameter */
178 
  {
 178 
  if ((hsram == NULL) || (hsram->Init.BurstAccessMode == FSMC_BURST_ACCESS_MODE_ENABLE))
179 
    /* Allocate lock resource and initialize it */
 179 
  {
180 
    hsram->Lock = HAL_UNLOCKED;
 180 
    return HAL_ERROR;
181 
 
 181 
  }
182 
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
 182 
 
183 
    if (hsram->MspInitCallback == NULL)
 183 
  if (hsram->State == HAL_SRAM_STATE_RESET)
184 
    {
 184 
  {
185 
      hsram->MspInitCallback = HAL_SRAM_MspInit;
 185 
    /* Allocate lock resource and initialize it */
186 
    }
 186 
    hsram->Lock = HAL_UNLOCKED;
187 
    hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
 187 
 
188 
    hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
 188 
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
189 
 
 189 
    if (hsram->MspInitCallback == NULL)
190 
    /* Init the low level hardware */
 190 
    {
191 
    hsram->MspInitCallback(hsram);
 191 
      hsram->MspInitCallback = HAL_SRAM_MspInit;
192 
#else
 192 
    }
193 
    /* Initialize the low level hardware (MSP) */
 193 
    hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
194 
    HAL_SRAM_MspInit(hsram);
 194 
    hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
195 
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
 195 
 
196 
  }
 196 
    /* Init the low level hardware */
197 
 
 197 
    hsram->MspInitCallback(hsram);
198 
  /* Initialize SRAM control Interface */
 198 
#else
199 
  (void)FSMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
 199 
    /* Initialize the low level hardware (MSP) */
200 
 
 200 
    HAL_SRAM_MspInit(hsram);
201 
  /* Initialize SRAM timing Interface */
 201 
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
202 
  (void)FSMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
 202 
  }
203 
 
 203 
 
204 
  /* Initialize SRAM extended mode timing Interface */
 204 
  /* Initialize SRAM control Interface */
205 
  (void)FSMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,
 205 
  (void)FSMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
206 
                                         hsram->Init.ExtendedMode);
 206 
 
207 
 
 207 
  /* Initialize SRAM timing Interface */
208 
  /* Enable the NORSRAM device */
 208 
  (void)FSMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
209 
  __FSMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
 209 
 
210 
 
 210 
  /* Initialize SRAM extended mode timing Interface */
211 
  /* Initialize the SRAM controller state */
 211 
  (void)FSMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,
212 
  hsram->State = HAL_SRAM_STATE_READY;
 212 
                                         hsram->Init.ExtendedMode);
213 
 
 213 
 
214 
  return HAL_OK;
 214 
  /* Enable the NORSRAM device */
215 
}
 215 
  __FSMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
216 
 
 216 
 
217 
/**
 217 
  /* Initialize the SRAM controller state */
218 
  * @brief  Performs the SRAM device De-initialization sequence.
 218 
  hsram->State = HAL_SRAM_STATE_READY;
219 
  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
 219 
 
220 
  *                the configuration information for SRAM module.
 220 
  return HAL_OK;
221 
  * @retval HAL status
 221 
}
222 
  */
 222 
 
223 
HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
 223 
/**
224 
{
 224 
  * @brief  Performs the SRAM device De-initialization sequence.
225 
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
 225 
  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
226 
  if (hsram->MspDeInitCallback == NULL)
 226 
  *                the configuration information for SRAM module.
227 
  {
 227 
  * @retval HAL status
228 
    hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
 228 
  */
229 
  }
 229 
HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
230 
 
 230 
{
231 
  /* DeInit the low level hardware */
 231 
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
232 
  hsram->MspDeInitCallback(hsram);
 232 
  if (hsram->MspDeInitCallback == NULL)
233 
#else
 233 
  {
234 
  /* De-Initialize the low level hardware (MSP) */
 234 
    hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
235 
  HAL_SRAM_MspDeInit(hsram);
 235 
  }
236 
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
 236 
 
237 
 
 237 
  /* DeInit the low level hardware */
238 
  /* Configure the SRAM registers with their reset values */
 238 
  hsram->MspDeInitCallback(hsram);
239 
  (void)FSMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
 239 
#else
240 
 
 240 
  /* De-Initialize the low level hardware (MSP) */
241 
  /* Reset the SRAM controller state */
 241 
  HAL_SRAM_MspDeInit(hsram);
242 
  hsram->State = HAL_SRAM_STATE_RESET;
 242 
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
243 
 
 243 
 
244 
  /* Release Lock */
 244 
  /* Configure the SRAM registers with their reset values */
245 
  __HAL_UNLOCK(hsram);
 245 
  (void)FSMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
246 
 
 246 
 
247 
  return HAL_OK;
 247 
  /* Reset the SRAM controller state */
248 
}
 248 
  hsram->State = HAL_SRAM_STATE_RESET;
249 
 
 249 
 
250 
/**
 250 
  /* Release Lock */
251 
  * @brief  SRAM MSP Init.
 251 
  __HAL_UNLOCK(hsram);
252 
  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
 252 
 
253 
  *                the configuration information for SRAM module.
 253 
  return HAL_OK;
254 
  * @retval None
 254 
}
255 
  */
 255 
 
256 
__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
 256 
/**
257 
{
 257 
  * @brief  SRAM MSP Init.
258 
  /* Prevent unused argument(s) compilation warning */
 258 
  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
259 
  UNUSED(hsram);
 259 
  *                the configuration information for SRAM module.
260 
 
 260 
  * @retval None
261 
  /* NOTE : This function Should not be modified, when the callback is needed,
 261 
  */
262 
            the HAL_SRAM_MspInit could be implemented in the user file
 262 
__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
263 
   */
 263 
{
264 
}
 264 
  /* Prevent unused argument(s) compilation warning */
265 
 
 265 
  UNUSED(hsram);
266 
/**
 266 
 
267 
  * @brief  SRAM MSP DeInit.
 267 
  /* NOTE : This function Should not be modified, when the callback is needed,
268 
  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
 268 
            the HAL_SRAM_MspInit could be implemented in the user file
269 
  *                the configuration information for SRAM module.
 269 
   */
270 
  * @retval None
 270 
}
271 
  */
 271 
 
272 
__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
 272 
/**
273 
{
 273 
  * @brief  SRAM MSP DeInit.
274 
  /* Prevent unused argument(s) compilation warning */
 274 
  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
275 
  UNUSED(hsram);
 275 
  *                the configuration information for SRAM module.
276 
 
 276 
  * @retval None
277 
  /* NOTE : This function Should not be modified, when the callback is needed,
 277 
  */
278 
            the HAL_SRAM_MspDeInit could be implemented in the user file
 278 
__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
279 
   */
 279 
{
280 
}
 280 
  /* Prevent unused argument(s) compilation warning */
281 
 
 281 
  UNUSED(hsram);
282 
/**
 282 
 
283 
  * @brief  DMA transfer complete callback.
 283 
  /* NOTE : This function Should not be modified, when the callback is needed,
284 
  * @param  hdma pointer to a SRAM_HandleTypeDef structure that contains
 284 
            the HAL_SRAM_MspDeInit could be implemented in the user file
285 
  *                the configuration information for SRAM module.
 285 
   */
286 
  * @retval None
 286 
}
287 
  */
 287 
 
288 
__weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
 288 
/**
289 
{
 289 
  * @brief  DMA transfer complete callback.
290 
  /* Prevent unused argument(s) compilation warning */
 290 
  * @param  hdma pointer to a SRAM_HandleTypeDef structure that contains
291 
  UNUSED(hdma);
 291 
  *                the configuration information for SRAM module.
292 
 
 292 
  * @retval None
293 
  /* NOTE : This function Should not be modified, when the callback is needed,
 293 
  */
294 
            the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
 294 
__weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
295 
   */
 295 
{
296 
}
 296 
  /* Prevent unused argument(s) compilation warning */
297 
 
 297 
  UNUSED(hdma);
298 
/**
 298 
 
299 
  * @brief  DMA transfer complete error callback.
 299 
  /* NOTE : This function Should not be modified, when the callback is needed,
300 
  * @param  hdma pointer to a SRAM_HandleTypeDef structure that contains
 300 
            the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
301 
  *                the configuration information for SRAM module.
 301 
   */
302 
  * @retval None
 302 
}
303 
  */
 303 
 
304 
__weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
 304 
/**
305 
{
 305 
  * @brief  DMA transfer complete error callback.
306 
  /* Prevent unused argument(s) compilation warning */
 306 
  * @param  hdma pointer to a SRAM_HandleTypeDef structure that contains
307 
  UNUSED(hdma);
 307 
  *                the configuration information for SRAM module.
308 
 
 308 
  * @retval None
309 
  /* NOTE : This function Should not be modified, when the callback is needed,
 309 
  */
310 
            the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
 310 
__weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
311 
   */
 311 
{
312 
}
 312 
  /* Prevent unused argument(s) compilation warning */
313 
 
 313 
  UNUSED(hdma);
314 
/**
 314 
 
315 
  * @}
 315 
  /* NOTE : This function Should not be modified, when the callback is needed,
316 
  */
 316 
            the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
317 
 
 317 
   */
318 
/** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
 318 
}
319 
  * @brief    Input Output and memory control functions
 319 
 
320 
  *
 320 
/**
321 
  @verbatim
 321 
  * @}
322 
  ==============================================================================
 322 
  */
323 
                  ##### SRAM Input and Output functions #####
 323 
 
324 
  ==============================================================================
 324 
/** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
325 
  [..]
 325 
  * @brief    Input Output and memory control functions
326 
    This section provides functions allowing to use and control the SRAM memory
 326 
  *
327 
 
 327 
  @verbatim
328 
@endverbatim
 328 
  ==============================================================================
329 
  * @{
 329 
                  ##### SRAM Input and Output functions #####
330 
  */
 330 
  ==============================================================================
331 
 
 331 
  [..]
332 
/**
 332 
    This section provides functions allowing to use and control the SRAM memory
333 
  * @brief  Reads 8-bit buffer from SRAM memory.
 333 
 
334 
  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
 334 
@endverbatim
335 
  *                the configuration information for SRAM module.
 335 
  * @{
336 
  * @param  pAddress Pointer to read start address
 336 
  */
337 
  * @param  pDstBuffer Pointer to destination buffer
 337 
 
338 
  * @param  BufferSize Size of the buffer to read from memory
 338 
/**
339 
  * @retval HAL status
 339 
  * @brief  Reads 8-bit buffer from SRAM memory.
340 
  */
 340 
  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
341 
HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
 341 
  *                the configuration information for SRAM module.
342 
                                   uint32_t BufferSize)
 342 
  * @param  pAddress Pointer to read start address
343 
{
 343 
  * @param  pDstBuffer Pointer to destination buffer
344 
  uint32_t size;
 344 
  * @param  BufferSize Size of the buffer to read from memory
345 
  __IO uint8_t *psramaddress = (uint8_t *)pAddress;
 345 
  * @retval HAL status
346 
  uint8_t *pdestbuff = pDstBuffer;
 346 
  */
347 
  HAL_SRAM_StateTypeDef state = hsram->State;
 347 
HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
348 
 
 348 
                                   uint32_t BufferSize)
349 
  /* Check the SRAM controller state */
 349 
{
350 
  if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
 350 
  uint32_t size;
351 
  {
 351 
  __IO uint8_t *psramaddress = (uint8_t *)pAddress;
352 
    /* Process Locked */
 352 
  uint8_t *pdestbuff = pDstBuffer;
353 
    __HAL_LOCK(hsram);
 353 
  HAL_SRAM_StateTypeDef state = hsram->State;
354 
 
 354 
 
355 
    /* Update the SRAM controller state */
 355 
  /* Check the SRAM controller state */
356 
    hsram->State = HAL_SRAM_STATE_BUSY;
 356 
  if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
357 
 
 357 
  {
358 
    /* Read data from memory */
 358 
    /* Process Locked */
359 
    for (size = BufferSize; size != 0U; size--)
 359 
    __HAL_LOCK(hsram);
360 
    {
 360 
 
361 
      *pdestbuff = *psramaddress;
 361 
    /* Update the SRAM controller state */
362 
      pdestbuff++;
 362 
    hsram->State = HAL_SRAM_STATE_BUSY;
363 
      psramaddress++;
 363 
 
364 
    }
 364 
    /* Read data from memory */
365 
 
 365 
    for (size = BufferSize; size != 0U; size--)
366 
    /* Update the SRAM controller state */
 366 
    {
367 
    hsram->State = state;
 367 
      *pdestbuff = *psramaddress;
368 
 
 368 
      pdestbuff++;
369 
    /* Process unlocked */
 369 
      psramaddress++;
370 
    __HAL_UNLOCK(hsram);
 370 
    }
371 
  }
 371 
 
372 
  else
 372 
    /* Update the SRAM controller state */
373 
  {
 373 
    hsram->State = state;
374 
    return HAL_ERROR;
 374 
 
375 
  }
 375 
    /* Process unlocked */
376 
 
 376 
    __HAL_UNLOCK(hsram);
377 
  return HAL_OK;
 377 
  }
378 
}
 378 
  else
379 
 
 379 
  {
380 
/**
 380 
    return HAL_ERROR;
381 
  * @brief  Writes 8-bit buffer to SRAM memory.
 381 
  }
382 
  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
 382 
 
383 
  *                the configuration information for SRAM module.
 383 
  return HAL_OK;
384 
  * @param  pAddress Pointer to write start address
 384 
}
385 
  * @param  pSrcBuffer Pointer to source buffer to write
 385 
 
386 
  * @param  BufferSize Size of the buffer to write to memory
 386 
/**
387 
  * @retval HAL status
 387 
  * @brief  Writes 8-bit buffer to SRAM memory.
388 
  */
 388 
  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
389 
HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
 389 
  *                the configuration information for SRAM module.
390 
                                    uint32_t BufferSize)
 390 
  * @param  pAddress Pointer to write start address
391 
{
 391 
  * @param  pSrcBuffer Pointer to source buffer to write
392 
  uint32_t size;
 392 
  * @param  BufferSize Size of the buffer to write to memory
393 
  __IO uint8_t *psramaddress = (uint8_t *)pAddress;
 393 
  * @retval HAL status
394 
  uint8_t *psrcbuff = pSrcBuffer;
 394 
  */
395 
 
 395 
HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
396 
  /* Check the SRAM controller state */
 396 
                                    uint32_t BufferSize)
397 
  if (hsram->State == HAL_SRAM_STATE_READY)
 397 
{
398 
  {
 398 
  uint32_t size;
399 
    /* Process Locked */
 399 
  __IO uint8_t *psramaddress = (uint8_t *)pAddress;
400 
    __HAL_LOCK(hsram);
 400 
  uint8_t *psrcbuff = pSrcBuffer;
401 
 
 401 
 
402 
    /* Update the SRAM controller state */
 402 
  /* Check the SRAM controller state */
403 
    hsram->State = HAL_SRAM_STATE_BUSY;
 403 
  if (hsram->State == HAL_SRAM_STATE_READY)
404 
 
 404 
  {
405 
    /* Write data to memory */
 405 
    /* Process Locked */
406 
    for (size = BufferSize; size != 0U; size--)
 406 
    __HAL_LOCK(hsram);
407 
    {
 407 
 
408 
      *psramaddress = *psrcbuff;
 408 
    /* Update the SRAM controller state */
409 
      psrcbuff++;
 409 
    hsram->State = HAL_SRAM_STATE_BUSY;
410 
      psramaddress++;
 410 
 
411 
    }
 411 
    /* Write data to memory */
412 
 
 412 
    for (size = BufferSize; size != 0U; size--)
413 
    /* Update the SRAM controller state */
 413 
    {
414 
    hsram->State = HAL_SRAM_STATE_READY;
 414 
      *psramaddress = *psrcbuff;
415 
 
 415 
      psrcbuff++;
416 
    /* Process unlocked */
 416 
      psramaddress++;
417 
    __HAL_UNLOCK(hsram);
 417 
    }
418 
  }
 418 
 
419 
  else
 419 
    /* Update the SRAM controller state */
420 
  {
 420 
    hsram->State = HAL_SRAM_STATE_READY;
421 
    return HAL_ERROR;
 421 
 
422 
  }
 422 
    /* Process unlocked */
423 
 
 423 
    __HAL_UNLOCK(hsram);
424 
  return HAL_OK;
 424 
  }
425 
}
 425 
  else
426 
 
 426 
  {
427 
/**
 427 
    return HAL_ERROR;
428 
  * @brief  Reads 16-bit buffer from SRAM memory.
 428 
  }
429 
  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
 429 
 
430 
  *                the configuration information for SRAM module.
 430 
  return HAL_OK;
431 
  * @param  pAddress Pointer to read start address
 431 
}
432 
  * @param  pDstBuffer Pointer to destination buffer
 432 
 
433 
  * @param  BufferSize Size of the buffer to read from memory
 433 
/**
434 
  * @retval HAL status
 434 
  * @brief  Reads 16-bit buffer from SRAM memory.
435 
  */
 435 
  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
436 
HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
 436 
  *                the configuration information for SRAM module.
437 
                                    uint32_t BufferSize)
 437 
  * @param  pAddress Pointer to read start address
438 
{
 438 
  * @param  pDstBuffer Pointer to destination buffer
439 
  uint32_t size;
 439 
  * @param  BufferSize Size of the buffer to read from memory
440 
  __IO uint32_t *psramaddress = pAddress;
 440 
  * @retval HAL status
441 
  uint16_t *pdestbuff = pDstBuffer;
 441 
  */
442 
  uint8_t limit;
 442 
HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
443 
  HAL_SRAM_StateTypeDef state = hsram->State;
 443 
                                    uint32_t BufferSize)
444 
 
 444 
{
445 
  /* Check the SRAM controller state */
 445 
  uint32_t size;
446 
  if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
 446 
  __IO uint32_t *psramaddress = pAddress;
447 
  {
 447 
  uint16_t *pdestbuff = pDstBuffer;
448 
    /* Process Locked */
 448 
  uint8_t limit;
449 
    __HAL_LOCK(hsram);
 449 
  HAL_SRAM_StateTypeDef state = hsram->State;
450 
 
 450 
 
451 
    /* Update the SRAM controller state */
 451 
  /* Check the SRAM controller state */
452 
    hsram->State = HAL_SRAM_STATE_BUSY;
 452 
  if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
453 
 
 453 
  {
454 
    /* Check if the size is a 32-bits multiple */
 454 
    /* Process Locked */
455 
    limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
 455 
    __HAL_LOCK(hsram);
456 
 
 456 
 
457 
    /* Read data from memory */
 457 
    /* Update the SRAM controller state */
458 
    for (size = BufferSize; size != limit; size -= 2U)
 458 
    hsram->State = HAL_SRAM_STATE_BUSY;
459 
    {
 459 
 
460 
      *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
 460 
    /* Check if the size is a 32-bits multiple */
461 
      pdestbuff++;
 461 
    limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
462 
      *pdestbuff = (uint16_t)(((*psramaddress) & 0xFFFF0000U) >> 16U);
 462 
 
463 
      pdestbuff++;
 463 
    /* Read data from memory */
464 
      psramaddress++;
 464 
    for (size = BufferSize; size != limit; size -= 2U)
465 
    }
 465 
    {
466 
 
 466 
      *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
467 
    /* Read last 16-bits if size is not 32-bits multiple */
 467 
      pdestbuff++;
468 
    if (limit != 0U)
 468 
      *pdestbuff = (uint16_t)(((*psramaddress) & 0xFFFF0000U) >> 16U);
469 
    {
 469 
      pdestbuff++;
470 
      *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
 470 
      psramaddress++;
471 
    }
 471 
    }
472 
 
 472 
 
473 
    /* Update the SRAM controller state */
 473 
    /* Read last 16-bits if size is not 32-bits multiple */
474 
    hsram->State = state;
 474 
    if (limit != 0U)
475 
 
 475 
    {
476 
    /* Process unlocked */
 476 
      *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
477 
    __HAL_UNLOCK(hsram);
 477 
    }
478 
  }
 478 
 
479 
  else
 479 
    /* Update the SRAM controller state */
480 
  {
 480 
    hsram->State = state;
481 
    return HAL_ERROR;
 481 
 
482 
  }
 482 
    /* Process unlocked */
483 
 
 483 
    __HAL_UNLOCK(hsram);
484 
  return HAL_OK;
 484 
  }
485 
}
 485 
  else
486 
 
 486 
  {
487 
/**
 487 
    return HAL_ERROR;
488 
  * @brief  Writes 16-bit buffer to SRAM memory.
 488 
  }
489 
  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
 489 
 
490 
  *                the configuration information for SRAM module.
 490 
  return HAL_OK;
491 
  * @param  pAddress Pointer to write start address
 491 
}
492 
  * @param  pSrcBuffer Pointer to source buffer to write
 492 
 
493 
  * @param  BufferSize Size of the buffer to write to memory
 493 
/**
494 
  * @retval HAL status
 494 
  * @brief  Writes 16-bit buffer to SRAM memory.
495 
  */
 495 
  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
496 
HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
 496 
  *                the configuration information for SRAM module.
497 
                                     uint32_t BufferSize)
 497 
  * @param  pAddress Pointer to write start address
498 
{
 498 
  * @param  pSrcBuffer Pointer to source buffer to write
499 
  uint32_t size;
 499 
  * @param  BufferSize Size of the buffer to write to memory
500 
  __IO uint32_t *psramaddress = pAddress;
 500 
  * @retval HAL status
501 
  uint16_t *psrcbuff = pSrcBuffer;
 501 
  */
502 
  uint8_t limit;
 502 
HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
503 
 
 503 
                                     uint32_t BufferSize)
504 
  /* Check the SRAM controller state */
 504 
{
505 
  if (hsram->State == HAL_SRAM_STATE_READY)
 505 
  uint32_t size;
506 
  {
 506 
  __IO uint32_t *psramaddress = pAddress;
507 
    /* Process Locked */
 507 
  uint16_t *psrcbuff = pSrcBuffer;
508 
    __HAL_LOCK(hsram);
 508 
  uint8_t limit;
509 
 
 509 
 
510 
    /* Update the SRAM controller state */
 510 
  /* Check the SRAM controller state */
511 
    hsram->State = HAL_SRAM_STATE_BUSY;
 511 
  if (hsram->State == HAL_SRAM_STATE_READY)
512 
 
 512 
  {
513 
    /* Check if the size is a 32-bits multiple */
 513 
    /* Process Locked */
514 
    limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
 514 
    __HAL_LOCK(hsram);
515 
 
 515 
 
516 
    /* Write data to memory */
 516 
    /* Update the SRAM controller state */
517 
    for (size = BufferSize; size != limit; size -= 2U)
 517 
    hsram->State = HAL_SRAM_STATE_BUSY;
518 
    {
 518 
 
519 
      *psramaddress = (uint32_t)(*psrcbuff);
 519 
    /* Check if the size is a 32-bits multiple */
520 
      psrcbuff++;
 520 
    limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
521 
      *psramaddress |= ((uint32_t)(*psrcbuff) << 16U);
 521 
 
522 
      psrcbuff++;
 522 
    /* Write data to memory */
523 
      psramaddress++;
 523 
    for (size = BufferSize; size != limit; size -= 2U)
524 
    }
 524 
    {
525 
 
 525 
      *psramaddress = (uint32_t)(*psrcbuff);
526 
    /* Write last 16-bits if size is not 32-bits multiple */
 526 
      psrcbuff++;
527 
    if (limit != 0U)
 527 
      *psramaddress |= ((uint32_t)(*psrcbuff) << 16U);
528 
    {
 528 
      psrcbuff++;
529 
      *psramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psramaddress) & 0xFFFF0000U);
 529 
      psramaddress++;
530 
    }
 530 
    }
531 
 
 531 
 
532 
    /* Update the SRAM controller state */
 532 
    /* Write last 16-bits if size is not 32-bits multiple */
533 
    hsram->State = HAL_SRAM_STATE_READY;
 533 
    if (limit != 0U)
534 
 
 534 
    {
535 
    /* Process unlocked */
 535 
      *psramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psramaddress) & 0xFFFF0000U);
536 
    __HAL_UNLOCK(hsram);
 536 
    }
537 
  }
 537 
 
538 
  else
 538 
    /* Update the SRAM controller state */
539 
  {
 539 
    hsram->State = HAL_SRAM_STATE_READY;
540 
    return HAL_ERROR;
 540 
 
541 
  }
 541 
    /* Process unlocked */
542 
 
 542 
    __HAL_UNLOCK(hsram);
543 
  return HAL_OK;
 543 
  }
544 
}
 544 
  else
545 
 
 545 
  {
546 
/**
 546 
    return HAL_ERROR;
547 
  * @brief  Reads 32-bit buffer from SRAM memory.
 547 
  }
548 
  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
 548 
 
549 
  *                the configuration information for SRAM module.
 549 
  return HAL_OK;
550 
  * @param  pAddress Pointer to read start address
 550 
}
551 
  * @param  pDstBuffer Pointer to destination buffer
 551 
 
552 
  * @param  BufferSize Size of the buffer to read from memory
 552 
/**
553 
  * @retval HAL status
 553 
  * @brief  Reads 32-bit buffer from SRAM memory.
554 
  */
 554 
  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
555 
HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
 555 
  *                the configuration information for SRAM module.
556 
                                    uint32_t BufferSize)
 556 
  * @param  pAddress Pointer to read start address
557 
{
 557 
  * @param  pDstBuffer Pointer to destination buffer
558 
  uint32_t size;
 558 
  * @param  BufferSize Size of the buffer to read from memory
559 
  __IO uint32_t *psramaddress = pAddress;
 559 
  * @retval HAL status
560 
  uint32_t *pdestbuff = pDstBuffer;
 560 
  */
561 
  HAL_SRAM_StateTypeDef state = hsram->State;
 561 
HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
562 
 
 562 
                                    uint32_t BufferSize)
563 
  /* Check the SRAM controller state */
 563 
{
564 
  if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
 564 
  uint32_t size;
565 
  {
 565 
  __IO uint32_t *psramaddress = pAddress;
566 
    /* Process Locked */
 566 
  uint32_t *pdestbuff = pDstBuffer;
567 
    __HAL_LOCK(hsram);
 567 
  HAL_SRAM_StateTypeDef state = hsram->State;
568 
 
 568 
 
569 
    /* Update the SRAM controller state */
 569 
  /* Check the SRAM controller state */
570 
    hsram->State = HAL_SRAM_STATE_BUSY;
 570 
  if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
571 
 
 571 
  {
572 
    /* Read data from memory */
 572 
    /* Process Locked */
573 
    for (size = BufferSize; size != 0U; size--)
 573 
    __HAL_LOCK(hsram);
574 
    {
 574 
 
575 
      *pdestbuff = *psramaddress;
 575 
    /* Update the SRAM controller state */
576 
      pdestbuff++;
 576 
    hsram->State = HAL_SRAM_STATE_BUSY;
577 
      psramaddress++;
 577 
 
578 
    }
 578 
    /* Read data from memory */
579 
 
 579 
    for (size = BufferSize; size != 0U; size--)
580 
    /* Update the SRAM controller state */
 580 
    {
581 
    hsram->State = state;
 581 
      *pdestbuff = *psramaddress;
582 
 
 582 
      pdestbuff++;
583 
    /* Process unlocked */
 583 
      psramaddress++;
584 
    __HAL_UNLOCK(hsram);
 584 
    }
585 
  }
 585 
 
586 
  else
 586 
    /* Update the SRAM controller state */
587 
  {
 587 
    hsram->State = state;
588 
    return HAL_ERROR;
 588 
 
589 
  }
 589 
    /* Process unlocked */
590 
 
 590 
    __HAL_UNLOCK(hsram);
591 
  return HAL_OK;
 591 
  }
592 
}
 592 
  else
593 
 
 593 
  {
594 
/**
 594 
    return HAL_ERROR;
595 
  * @brief  Writes 32-bit buffer to SRAM memory.
 595 
  }
596 
  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
 596 
 
597 
  *                the configuration information for SRAM module.
 597 
  return HAL_OK;
598 
  * @param  pAddress Pointer to write start address
 598 
}
599 
  * @param  pSrcBuffer Pointer to source buffer to write
 599 
 
600 
  * @param  BufferSize Size of the buffer to write to memory
 600 
/**
601 
  * @retval HAL status
 601 
  * @brief  Writes 32-bit buffer to SRAM memory.
602 
  */
 602 
  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
603 
HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
 603 
  *                the configuration information for SRAM module.
604 
                                     uint32_t BufferSize)
 604 
  * @param  pAddress Pointer to write start address
605 
{
 605 
  * @param  pSrcBuffer Pointer to source buffer to write
606 
  uint32_t size;
 606 
  * @param  BufferSize Size of the buffer to write to memory
607 
  __IO uint32_t *psramaddress = pAddress;
 607 
  * @retval HAL status
608 
  uint32_t *psrcbuff = pSrcBuffer;
 608 
  */
609 
 
 609 
HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
610 
  /* Check the SRAM controller state */
 610 
                                     uint32_t BufferSize)
611 
  if (hsram->State == HAL_SRAM_STATE_READY)
 611 
{
612 
  {
 612 
  uint32_t size;
613 
    /* Process Locked */
 613 
  __IO uint32_t *psramaddress = pAddress;
614 
    __HAL_LOCK(hsram);
 614 
  uint32_t *psrcbuff = pSrcBuffer;
615 
 
 615 
 
616 
    /* Update the SRAM controller state */
 616 
  /* Check the SRAM controller state */
617 
    hsram->State = HAL_SRAM_STATE_BUSY;
 617 
  if (hsram->State == HAL_SRAM_STATE_READY)
618 
 
 618 
  {
619 
    /* Write data to memory */
 619 
    /* Process Locked */
620 
    for (size = BufferSize; size != 0U; size--)
 620 
    __HAL_LOCK(hsram);
621 
    {
 621 
 
622 
      *psramaddress = *psrcbuff;
 622 
    /* Update the SRAM controller state */
623 
      psrcbuff++;
 623 
    hsram->State = HAL_SRAM_STATE_BUSY;
624 
      psramaddress++;
 624 
 
625 
    }
 625 
    /* Write data to memory */
626 
 
 626 
    for (size = BufferSize; size != 0U; size--)
627 
    /* Update the SRAM controller state */
 627 
    {
628 
    hsram->State = HAL_SRAM_STATE_READY;
 628 
      *psramaddress = *psrcbuff;
629 
 
 629 
      psrcbuff++;
630 
    /* Process unlocked */
 630 
      psramaddress++;
631 
    __HAL_UNLOCK(hsram);
 631 
    }
632 
  }
 632 
 
633 
  else
 633 
    /* Update the SRAM controller state */
634 
  {
 634 
    hsram->State = HAL_SRAM_STATE_READY;
635 
    return HAL_ERROR;
 635 
 
636 
  }
 636 
    /* Process unlocked */
637 
 
 637 
    __HAL_UNLOCK(hsram);
638 
  return HAL_OK;
 638 
  }
639 
}
 639 
  else
640 
 
 640 
  {
641 
/**
 641 
    return HAL_ERROR;
642 
  * @brief  Reads a Words data from the SRAM memory using DMA transfer.
 642 
  }
643 
  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
 643 
 
644 
  *                the configuration information for SRAM module.
 644 
  return HAL_OK;
645 
  * @param  pAddress Pointer to read start address
 645 
}
646 
  * @param  pDstBuffer Pointer to destination buffer
 646 
 
647 
  * @param  BufferSize Size of the buffer to read from memory
 647 
/**
648 
  * @retval HAL status
 648 
  * @brief  Reads a Words data from the SRAM memory using DMA transfer.
649 
  */
 649 
  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
650 
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
 650 
  *                the configuration information for SRAM module.
651 
                                    uint32_t BufferSize)
 651 
  * @param  pAddress Pointer to read start address
652 
{
 652 
  * @param  pDstBuffer Pointer to destination buffer
653 
  HAL_StatusTypeDef status;
 653 
  * @param  BufferSize Size of the buffer to read from memory
654 
  HAL_SRAM_StateTypeDef state = hsram->State;
 654 
  * @retval HAL status
655 
 
 655 
  */
656 
  /* Check the SRAM controller state */
 656 
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
657 
  if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
 657 
                                    uint32_t BufferSize)
658 
  {
 658 
{
659 
    /* Process Locked */
 659 
  HAL_StatusTypeDef status;
660 
    __HAL_LOCK(hsram);
 660 
  HAL_SRAM_StateTypeDef state = hsram->State;
661 
 
 661 
 
662 
    /* Update the SRAM controller state */
 662 
  /* Check the SRAM controller state */
663 
    hsram->State = HAL_SRAM_STATE_BUSY;
 663 
  if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
664 
 
 664 
  {
665 
    /* Configure DMA user callbacks */
 665 
    /* Process Locked */
666 
    if (state == HAL_SRAM_STATE_READY)
 666 
    __HAL_LOCK(hsram);
667 
    {
 667 
 
668 
      hsram->hdma->XferCpltCallback = SRAM_DMACplt;
 668 
    /* Update the SRAM controller state */
669 
    }
 669 
    hsram->State = HAL_SRAM_STATE_BUSY;
670 
    else
 670 
 
671 
    {
 671 
    /* Configure DMA user callbacks */
672 
      hsram->hdma->XferCpltCallback = SRAM_DMACpltProt;
 672 
    if (state == HAL_SRAM_STATE_READY)
673 
    }
 673 
    {
674 
    hsram->hdma->XferErrorCallback = SRAM_DMAError;
 674 
      hsram->hdma->XferCpltCallback = SRAM_DMACplt;
675 
 
 675 
    }
676 
    /* Enable the DMA Stream */
 676 
    else
677 
    status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
 677 
    {
678 
 
 678 
      hsram->hdma->XferCpltCallback = SRAM_DMACpltProt;
679 
    /* Process unlocked */
 679 
    }
680 
    __HAL_UNLOCK(hsram);
 680 
    hsram->hdma->XferErrorCallback = SRAM_DMAError;
681 
  }
 681 
 
682 
  else
 682 
    /* Enable the DMA Stream */
683 
  {
 683 
    status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
684 
    status = HAL_ERROR;
 684 
 
685 
  }
 685 
    /* Process unlocked */
686 
 
 686 
    __HAL_UNLOCK(hsram);
687 
  return status;
 687 
  }
688 
}
 688 
  else
689 
 
 689 
  {
690 
/**
 690 
    status = HAL_ERROR;
691 
  * @brief  Writes a Words data buffer to SRAM memory using DMA transfer.
 691 
  }
692 
  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
 692 
 
693 
  *                the configuration information for SRAM module.
 693 
  return status;
694 
  * @param  pAddress Pointer to write start address
 694 
}
695 
  * @param  pSrcBuffer Pointer to source buffer to write
 695 
 
696 
  * @param  BufferSize Size of the buffer to write to memory
 696 
/**
697 
  * @retval HAL status
 697 
  * @brief  Writes a Words data buffer to SRAM memory using DMA transfer.
698 
  */
 698 
  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
699 
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
 699 
  *                the configuration information for SRAM module.
700 
                                     uint32_t BufferSize)
 700 
  * @param  pAddress Pointer to write start address
701 
{
 701 
  * @param  pSrcBuffer Pointer to source buffer to write
702 
  HAL_StatusTypeDef status;
 702 
  * @param  BufferSize Size of the buffer to write to memory
703 
 
 703 
  * @retval HAL status
704 
  /* Check the SRAM controller state */
 704 
  */
705 
  if (hsram->State == HAL_SRAM_STATE_READY)
 705 
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
706 
  {
 706 
                                     uint32_t BufferSize)
707 
    /* Process Locked */
 707 
{
708 
    __HAL_LOCK(hsram);
 708 
  HAL_StatusTypeDef status;
709 
 
 709 
 
710 
    /* Update the SRAM controller state */
 710 
  /* Check the SRAM controller state */
711 
    hsram->State = HAL_SRAM_STATE_BUSY;
 711 
  if (hsram->State == HAL_SRAM_STATE_READY)
712 
 
 712 
  {
713 
    /* Configure DMA user callbacks */
 713 
    /* Process Locked */
714 
    hsram->hdma->XferCpltCallback = SRAM_DMACplt;
 714 
    __HAL_LOCK(hsram);
715 
    hsram->hdma->XferErrorCallback = SRAM_DMAError;
 715 
 
716 
 
 716 
    /* Update the SRAM controller state */
717 
    /* Enable the DMA Stream */
 717 
    hsram->State = HAL_SRAM_STATE_BUSY;
718 
    status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
 718 
 
719 
 
 719 
    /* Configure DMA user callbacks */
720 
    /* Process unlocked */
 720 
    hsram->hdma->XferCpltCallback = SRAM_DMACplt;
721 
    __HAL_UNLOCK(hsram);
 721 
    hsram->hdma->XferErrorCallback = SRAM_DMAError;
722 
  }
 722 
 
723 
  else
 723 
    /* Enable the DMA Stream */
724 
  {
 724 
    status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
725 
    status = HAL_ERROR;
 725 
 
726 
  }
 726 
    /* Process unlocked */
727 
 
 727 
    __HAL_UNLOCK(hsram);
728 
  return status;
 728 
  }
729 
}
 729 
  else
730 
 
 730 
  {
731 
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
 731 
    status = HAL_ERROR;
732 
/**
 732 
  }
733 
  * @brief  Register a User SRAM Callback
 733 
 
734 
  *         To be used instead of the weak (surcharged) predefined callback
 734 
  return status;
735 
  * @param hsram : SRAM handle
 735 
}
736 
  * @param CallbackId : ID of the callback to be registered
 736 
 
737 
  *        This parameter can be one of the following values:
 737 
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
738 
  *          @arg @ref HAL_SRAM_MSP_INIT_CB_ID       SRAM MspInit callback ID
 738 
/**
739 
  *          @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID     SRAM MspDeInit callback ID
 739 
  * @brief  Register a User SRAM Callback
740 
  * @param pCallback : pointer to the Callback function
 740 
  *         To be used to override the weak predefined callback
741 
  * @retval status
 741 
  * @param hsram : SRAM handle
742 
  */
 742 
  * @param CallbackId : ID of the callback to be registered
743 
HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
 743 
  *        This parameter can be one of the following values:
744 
                                            pSRAM_CallbackTypeDef pCallback)
 744 
  *          @arg @ref HAL_SRAM_MSP_INIT_CB_ID       SRAM MspInit callback ID
745 
{
 745 
  *          @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID     SRAM MspDeInit callback ID
746 
  HAL_StatusTypeDef status = HAL_OK;
 746 
  * @param pCallback : pointer to the Callback function
747 
  HAL_SRAM_StateTypeDef state;
 747 
  * @retval status
748 
 
 748 
  */
749 
  if (pCallback == NULL)
 749 
HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
750 
  {
 750 
                                            pSRAM_CallbackTypeDef pCallback)
751 
    return HAL_ERROR;
 751 
{
752 
  }
 752 
  HAL_StatusTypeDef status = HAL_OK;
753 
 
 753 
  HAL_SRAM_StateTypeDef state;
754 
  /* Process locked */
 754 
 
755 
  __HAL_LOCK(hsram);
 755 
  if (pCallback == NULL)
756 
 
 756 
  {
757 
  state = hsram->State;
 757 
    return HAL_ERROR;
758 
  if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED))
 758 
  }
759 
  {
 759 
 
760 
    switch (CallbackId)
 760 
  state = hsram->State;
761 
    {
 761 
  if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED))
762 
      case HAL_SRAM_MSP_INIT_CB_ID :
 762 
  {
763 
        hsram->MspInitCallback = pCallback;
 763 
    switch (CallbackId)
764 
        break;
 764 
    {
765 
      case HAL_SRAM_MSP_DEINIT_CB_ID :
 765 
      case HAL_SRAM_MSP_INIT_CB_ID :
766 
        hsram->MspDeInitCallback = pCallback;
 766 
        hsram->MspInitCallback = pCallback;
767 
        break;
 767 
        break;
768 
      default :
 768 
      case HAL_SRAM_MSP_DEINIT_CB_ID :
769 
        /* update return status */
 769 
        hsram->MspDeInitCallback = pCallback;
770 
        status =  HAL_ERROR;
 770 
        break;
771 
        break;
 771 
      default :
772 
    }
 772 
        /* update return status */
773 
  }
 773 
        status =  HAL_ERROR;
774 
  else
 774 
        break;
775 
  {
 775 
    }
776 
    /* update return status */
 776 
  }
777 
    status =  HAL_ERROR;
 777 
  else
778 
  }
 778 
  {
779 
 
 779 
    /* update return status */
780 
  /* Release Lock */
 780 
    status =  HAL_ERROR;
781 
  __HAL_UNLOCK(hsram);
 781 
  }
782 
  return status;
 782 
 
783 
}
 783 
  return status;
784 
 
 784 
}
785 
/**
 785 
 
786 
  * @brief  Unregister a User SRAM Callback
 786 
/**
787 
  *         SRAM Callback is redirected to the weak (surcharged) predefined callback
 787 
  * @brief  Unregister a User SRAM Callback
788 
  * @param hsram : SRAM handle
 788 
  *         SRAM Callback is redirected to the weak predefined callback
789 
  * @param CallbackId : ID of the callback to be unregistered
 789 
  * @param hsram : SRAM handle
790 
  *        This parameter can be one of the following values:
 790 
  * @param CallbackId : ID of the callback to be unregistered
791 
  *          @arg @ref HAL_SRAM_MSP_INIT_CB_ID       SRAM MspInit callback ID
 791 
  *        This parameter can be one of the following values:
792 
  *          @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID     SRAM MspDeInit callback ID
 792 
  *          @arg @ref HAL_SRAM_MSP_INIT_CB_ID       SRAM MspInit callback ID
793 
  *          @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID  SRAM DMA Xfer Complete callback ID
 793 
  *          @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID     SRAM MspDeInit callback ID
794 
  *          @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID   SRAM DMA Xfer Error callback ID
 794 
  *          @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID  SRAM DMA Xfer Complete callback ID
795 
  * @retval status
 795 
  *          @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID   SRAM DMA Xfer Error callback ID
796 
  */
 796 
  * @retval status
797 
HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId)
 797 
  */
798 
{
 798 
HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId)
799 
  HAL_StatusTypeDef status = HAL_OK;
 799 
{
800 
  HAL_SRAM_StateTypeDef state;
 800 
  HAL_StatusTypeDef status = HAL_OK;
801 
 
 801 
  HAL_SRAM_StateTypeDef state;
802 
  /* Process locked */
 802 
 
803 
  __HAL_LOCK(hsram);
 803 
  state = hsram->State;
804 
 
 804 
  if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
805 
  state = hsram->State;
 805 
  {
806 
  if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
 806 
    switch (CallbackId)
807 
  {
 807 
    {
808 
    switch (CallbackId)
 808 
      case HAL_SRAM_MSP_INIT_CB_ID :
809 
    {
 809 
        hsram->MspInitCallback = HAL_SRAM_MspInit;
810 
      case HAL_SRAM_MSP_INIT_CB_ID :
 810 
        break;
811 
        hsram->MspInitCallback = HAL_SRAM_MspInit;
 811 
      case HAL_SRAM_MSP_DEINIT_CB_ID :
812 
        break;
 812 
        hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
813 
      case HAL_SRAM_MSP_DEINIT_CB_ID :
 813 
        break;
814 
        hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
 814 
      case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
815 
        break;
 815 
        hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
816 
      case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
 816 
        break;
817 
        hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
 817 
      case HAL_SRAM_DMA_XFER_ERR_CB_ID :
818 
        break;
 818 
        hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
819 
      case HAL_SRAM_DMA_XFER_ERR_CB_ID :
 819 
        break;
820 
        hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
 820 
      default :
821 
        break;
 821 
        /* update return status */
822 
      default :
 822 
        status =  HAL_ERROR;
823 
        /* update return status */
 823 
        break;
824 
        status =  HAL_ERROR;
 824 
    }
825 
        break;
 825 
  }
826 
    }
 826 
  else if (state == HAL_SRAM_STATE_RESET)
827 
  }
 827 
  {
828 
  else if (state == HAL_SRAM_STATE_RESET)
 828 
    switch (CallbackId)
829 
  {
 829 
    {
830 
    switch (CallbackId)
 830 
      case HAL_SRAM_MSP_INIT_CB_ID :
831 
    {
 831 
        hsram->MspInitCallback = HAL_SRAM_MspInit;
832 
      case HAL_SRAM_MSP_INIT_CB_ID :
 832 
        break;
833 
        hsram->MspInitCallback = HAL_SRAM_MspInit;
 833 
      case HAL_SRAM_MSP_DEINIT_CB_ID :
834 
        break;
 834 
        hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
835 
      case HAL_SRAM_MSP_DEINIT_CB_ID :
 835 
        break;
836 
        hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
 836 
      default :
837 
        break;
 837 
        /* update return status */
838 
      default :
 838 
        status =  HAL_ERROR;
839 
        /* update return status */
 839 
        break;
840 
        status =  HAL_ERROR;
 840 
    }
841 
        break;
 841 
  }
842 
    }
 842 
  else
843 
  }
 843 
  {
844 
  else
 844 
    /* update return status */
845 
  {
 845 
    status =  HAL_ERROR;
846 
    /* update return status */
 846 
  }
847 
    status =  HAL_ERROR;
 847 
 
848 
  }
 848 
  return status;
849 
 
 849 
}
850 
  /* Release Lock */
 850 
 
851 
  __HAL_UNLOCK(hsram);
 851 
/**
852 
  return status;
 852 
  * @brief  Register a User SRAM Callback for DMA transfers
853 
}
 853 
  *         To be used to override the weak predefined callback
854 
 
 854 
  * @param hsram : SRAM handle
855 
/**
 855 
  * @param CallbackId : ID of the callback to be registered
856 
  * @brief  Register a User SRAM Callback for DMA transfers
 856 
  *        This parameter can be one of the following values:
857 
  *         To be used instead of the weak (surcharged) predefined callback
 857 
  *          @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID  SRAM DMA Xfer Complete callback ID
858 
  * @param hsram : SRAM handle
 858 
  *          @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID   SRAM DMA Xfer Error callback ID
859 
  * @param CallbackId : ID of the callback to be registered
 859 
  * @param pCallback : pointer to the Callback function
860 
  *        This parameter can be one of the following values:
 860 
  * @retval status
861 
  *          @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID  SRAM DMA Xfer Complete callback ID
 861 
  */
862 
  *          @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID   SRAM DMA Xfer Error callback ID
 862 
HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
863 
  * @param pCallback : pointer to the Callback function
 863 
                                               pSRAM_DmaCallbackTypeDef pCallback)
864 
  * @retval status
 864 
{
865 
  */
 865 
  HAL_StatusTypeDef status = HAL_OK;
866 
HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
 866 
  HAL_SRAM_StateTypeDef state;
867 
                                               pSRAM_DmaCallbackTypeDef pCallback)
 867 
 
868 
{
 868 
  if (pCallback == NULL)
869 
  HAL_StatusTypeDef status = HAL_OK;
 869 
  {
870 
  HAL_SRAM_StateTypeDef state;
 870 
    return HAL_ERROR;
871 
 
 871 
  }
872 
  if (pCallback == NULL)
 872 
 
873 
  {
 873 
  /* Process locked */
874 
    return HAL_ERROR;
 874 
  __HAL_LOCK(hsram);
875 
  }
 875 
 
876 
 
 876 
  state = hsram->State;
877 
  /* Process locked */
 877 
  if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
878 
  __HAL_LOCK(hsram);
 878 
  {
879 
 
 879 
    switch (CallbackId)
880 
  state = hsram->State;
 880 
    {
881 
  if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
 881 
      case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
882 
  {
 882 
        hsram->DmaXferCpltCallback = pCallback;
883 
    switch (CallbackId)
 883 
        break;
884 
    {
 884 
      case HAL_SRAM_DMA_XFER_ERR_CB_ID :
885 
      case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
 885 
        hsram->DmaXferErrorCallback = pCallback;
886 
        hsram->DmaXferCpltCallback = pCallback;
 886 
        break;
887 
        break;
 887 
      default :
888 
      case HAL_SRAM_DMA_XFER_ERR_CB_ID :
 888 
        /* update return status */
889 
        hsram->DmaXferErrorCallback = pCallback;
 889 
        status =  HAL_ERROR;
890 
        break;
 890 
        break;
891 
      default :
 891 
    }
892 
        /* update return status */
 892 
  }
893 
        status =  HAL_ERROR;
 893 
  else
894 
        break;
 894 
  {
895 
    }
 895 
    /* update return status */
896 
  }
 896 
    status =  HAL_ERROR;
897 
  else
 897 
  }
898 
  {
 898 
 
899 
    /* update return status */
 899 
  /* Release Lock */
900 
    status =  HAL_ERROR;
 900 
  __HAL_UNLOCK(hsram);
901 
  }
 901 
  return status;
902 
 
 902 
}
903 
  /* Release Lock */
 903 
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
904 
  __HAL_UNLOCK(hsram);
 904 
 
905 
  return status;
 905 
/**
906 
}
 906 
  * @}
907 
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
 907 
  */
908 
 
 908 
 
909 
/**
 909 
/** @defgroup SRAM_Exported_Functions_Group3 Control functions
910 
  * @}
 910 
  *  @brief   Control functions
911 
  */
 911 
  *
912 
 
 912 
@verbatim
913 
/** @defgroup SRAM_Exported_Functions_Group3 Control functions
 913 
  ==============================================================================
914 
  *  @brief   Control functions
 914 
                        ##### SRAM Control functions #####
915 
  *
 915 
  ==============================================================================
916 
@verbatim
 916 
  [..]
917 
  ==============================================================================
 917 
    This subsection provides a set of functions allowing to control dynamically
918 
                        ##### SRAM Control functions #####
 918 
    the SRAM interface.
919 
  ==============================================================================
 919 
 
920 
  [..]
 920 
@endverbatim
921 
    This subsection provides a set of functions allowing to control dynamically
 921 
  * @{
922 
    the SRAM interface.
 922 
  */
923 
 
 923 
 
924 
@endverbatim
 924 
/**
925 
  * @{
 925 
  * @brief  Enables dynamically SRAM write operation.
926 
  */
 926 
  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
927 
 
 927 
  *                the configuration information for SRAM module.
928 
/**
 928 
  * @retval HAL status
929 
  * @brief  Enables dynamically SRAM write operation.
 929 
  */
930 
  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
 930 
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
931 
  *                the configuration information for SRAM module.
 931 
{
932 
  * @retval HAL status
 932 
  /* Check the SRAM controller state */
933 
  */
 933 
  if (hsram->State == HAL_SRAM_STATE_PROTECTED)
934 
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
 934 
  {
935 
{
 935 
    /* Process Locked */
936 
  /* Check the SRAM controller state */
 936 
    __HAL_LOCK(hsram);
937 
  if (hsram->State == HAL_SRAM_STATE_PROTECTED)
 937 
 
938 
  {
 938 
    /* Update the SRAM controller state */
939 
    /* Process Locked */
 939 
    hsram->State = HAL_SRAM_STATE_BUSY;
940 
    __HAL_LOCK(hsram);
 940 
 
941 
 
 941 
    /* Enable write operation */
942 
    /* Update the SRAM controller state */
 942 
    (void)FSMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
943 
    hsram->State = HAL_SRAM_STATE_BUSY;
 943 
 
944 
 
 944 
    /* Update the SRAM controller state */
945 
    /* Enable write operation */
 945 
    hsram->State = HAL_SRAM_STATE_READY;
946 
    (void)FSMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
 946 
 
947 
 
 947 
    /* Process unlocked */
948 
    /* Update the SRAM controller state */
 948 
    __HAL_UNLOCK(hsram);
949 
    hsram->State = HAL_SRAM_STATE_READY;
 949 
  }
950 
 
 950 
  else
951 
    /* Process unlocked */
 951 
  {
952 
    __HAL_UNLOCK(hsram);
 952 
    return HAL_ERROR;
953 
  }
 953 
  }
954 
  else
 954 
 
955 
  {
 955 
  return HAL_OK;
956 
    return HAL_ERROR;
 956 
}
957 
  }
 957 
 
958 
 
 958 
/**
959 
  return HAL_OK;
 959 
  * @brief  Disables dynamically SRAM write operation.
960 
}
 960 
  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
961 
 
 961 
  *                the configuration information for SRAM module.
962 
/**
 962 
  * @retval HAL status
963 
  * @brief  Disables dynamically SRAM write operation.
 963 
  */
964 
  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
 964 
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
965 
  *                the configuration information for SRAM module.
 965 
{
966 
  * @retval HAL status
 966 
  /* Check the SRAM controller state */
967 
  */
 967 
  if (hsram->State == HAL_SRAM_STATE_READY)
968 
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
 968 
  {
969 
{
 969 
    /* Process Locked */
970 
  /* Check the SRAM controller state */
 970 
    __HAL_LOCK(hsram);
971 
  if (hsram->State == HAL_SRAM_STATE_READY)
 971 
 
972 
  {
 972 
    /* Update the SRAM controller state */
973 
    /* Process Locked */
 973 
    hsram->State = HAL_SRAM_STATE_BUSY;
974 
    __HAL_LOCK(hsram);
 974 
 
975 
 
 975 
    /* Disable write operation */
976 
    /* Update the SRAM controller state */
 976 
    (void)FSMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
977 
    hsram->State = HAL_SRAM_STATE_BUSY;
 977 
 
978 
 
 978 
    /* Update the SRAM controller state */
979 
    /* Disable write operation */
 979 
    hsram->State = HAL_SRAM_STATE_PROTECTED;
980 
    (void)FSMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
 980 
 
981 
 
 981 
    /* Process unlocked */
982 
    /* Update the SRAM controller state */
 982 
    __HAL_UNLOCK(hsram);
983 
    hsram->State = HAL_SRAM_STATE_PROTECTED;
 983 
  }
984 
 
 984 
  else
985 
    /* Process unlocked */
 985 
  {
986 
    __HAL_UNLOCK(hsram);
 986 
    return HAL_ERROR;
987 
  }
 987 
  }
988 
  else
 988 
 
989 
  {
 989 
  return HAL_OK;
990 
    return HAL_ERROR;
 990 
}
991 
  }
 991 
 
992 
 
 992 
/**
993 
  return HAL_OK;
 993 
  * @}
994 
}
 994 
  */
995 
 
 995 
 
996 
/**
 996 
/** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
997 
  * @}
 997 
  *  @brief   Peripheral State functions
998 
  */
 998 
  *
999 
 
 999 
@verbatim
1000 
/** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
 1000 
  ==============================================================================
1001 
  *  @brief   Peripheral State functions
 1001 
                      ##### SRAM State functions #####
1002 
  *
 1002 
  ==============================================================================
1003 
@verbatim
 1003 
  [..]
1004 
  ==============================================================================
 1004 
    This subsection permits to get in run-time the status of the SRAM controller
1005 
                      ##### SRAM State functions #####
 1005 
    and the data flow.
1006 
  ==============================================================================
 1006 
 
1007 
  [..]
 1007 
@endverbatim
1008 
    This subsection permits to get in run-time the status of the SRAM controller
 1008 
  * @{
1009 
    and the data flow.
 1009 
  */
1010 
 
 1010 
 
1011 
@endverbatim
 1011 
/**
1012 
  * @{
 1012 
  * @brief  Returns the SRAM controller state
1013 
  */
 1013 
  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
1014 
 
 1014 
  *                the configuration information for SRAM module.
1015 
/**
 1015 
  * @retval HAL state
1016 
  * @brief  Returns the SRAM controller state
 1016 
  */
1017 
  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
 1017 
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram)
1018 
  *                the configuration information for SRAM module.
 1018 
{
1019 
  * @retval HAL state
 1019 
  return hsram->State;
1020 
  */
 1020 
}
1021 
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
 1021 
 
1022 
{
 1022 
/**
1023 
  return hsram->State;
 1023 
  * @}
1024 
}
 1024 
  */
1025 
 
 1025 
 
1026 
/**
 1026 
/**
1027 
  * @}
 1027 
  * @}
1028 
  */
 1028 
  */
1029 
 
 1029 
 
1030 
/**
 1030 
/** @addtogroup SRAM_Private_Functions SRAM Private Functions
1031 
  * @}
 1031 
  * @{
1032 
  */
 1032 
  */
1033 
 
 1033 
 
1034 
/**
 1034 
/**
1035 
  * @brief  DMA SRAM process complete callback.
 1035 
  * @brief  DMA SRAM process complete callback.
1036 
  * @param  hdma : DMA handle
 1036 
  * @param  hdma : DMA handle
1037 
  * @retval None
 1037 
  * @retval None
1038 
  */
 1038 
  */
1039 
static void SRAM_DMACplt(DMA_HandleTypeDef *hdma)
 1039 
static void SRAM_DMACplt(DMA_HandleTypeDef *hdma)
1040 
{
 1040 
{
1041 
  SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
 1041 
  SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
1042 
 
 1042 
 
1043 
  /* Disable the DMA channel */
 1043 
  /* Disable the DMA channel */
1044 
  __HAL_DMA_DISABLE(hdma);
 1044 
  __HAL_DMA_DISABLE(hdma);
1045 
 
 1045 
 
1046 
  /* Update the SRAM controller state */
 1046 
  /* Update the SRAM controller state */
1047 
  hsram->State = HAL_SRAM_STATE_READY;
 1047 
  hsram->State = HAL_SRAM_STATE_READY;
1048 
 
 1048 
 
1049 
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
 1049 
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
1050 
  hsram->DmaXferCpltCallback(hdma);
 1050 
  hsram->DmaXferCpltCallback(hdma);
1051 
#else
 1051 
#else
1052 
  HAL_SRAM_DMA_XferCpltCallback(hdma);
 1052 
  HAL_SRAM_DMA_XferCpltCallback(hdma);
1053 
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
 1053 
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
1054 
}
 1054 
}
1055 
 
 1055 
 
1056 
/**
 1056 
/**
1057 
  * @brief  DMA SRAM process complete callback.
 1057 
  * @brief  DMA SRAM process complete callback.
1058 
  * @param  hdma : DMA handle
 1058 
  * @param  hdma : DMA handle
1059 
  * @retval None
 1059 
  * @retval None
1060 
  */
 1060 
  */
1061 
static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
 1061 
static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
1062 
{
 1062 
{
1063 
  SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
 1063 
  SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
1064 
 
 1064 
 
1065 
  /* Disable the DMA channel */
 1065 
  /* Disable the DMA channel */
1066 
  __HAL_DMA_DISABLE(hdma);
 1066 
  __HAL_DMA_DISABLE(hdma);
1067 
 
 1067 
 
1068 
  /* Update the SRAM controller state */
 1068 
  /* Update the SRAM controller state */
1069 
  hsram->State = HAL_SRAM_STATE_PROTECTED;
 1069 
  hsram->State = HAL_SRAM_STATE_PROTECTED;
1070 
 
 1070 
 
1071 
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
 1071 
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
1072 
  hsram->DmaXferCpltCallback(hdma);
 1072 
  hsram->DmaXferCpltCallback(hdma);
1073 
#else
 1073 
#else
1074 
  HAL_SRAM_DMA_XferCpltCallback(hdma);
 1074 
  HAL_SRAM_DMA_XferCpltCallback(hdma);
1075 
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
 1075 
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
1076 
}
 1076 
}
1077 
 
 1077 
 
1078 
/**
 1078 
/**
1079 
  * @brief  DMA SRAM error callback.
 1079 
  * @brief  DMA SRAM error callback.
1080 
  * @param  hdma : DMA handle
 1080 
  * @param  hdma : DMA handle
1081 
  * @retval None
 1081 
  * @retval None
1082 
  */
 1082 
  */
1083 
static void SRAM_DMAError(DMA_HandleTypeDef *hdma)
 1083 
static void SRAM_DMAError(DMA_HandleTypeDef *hdma)
1084 
{
 1084 
{
1085 
  SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
 1085 
  SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
1086 
 
 1086 
 
1087 
  /* Disable the DMA channel */
 1087 
  /* Disable the DMA channel */
1088 
  __HAL_DMA_DISABLE(hdma);
 1088 
  __HAL_DMA_DISABLE(hdma);
1089 
 
 1089 
 
1090 
  /* Update the SRAM controller state */
 1090 
  /* Update the SRAM controller state */
1091 
  hsram->State = HAL_SRAM_STATE_ERROR;
 1091 
  hsram->State = HAL_SRAM_STATE_ERROR;
1092 
 
 1092 
 
1093 
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
 1093 
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
1094 
  hsram->DmaXferErrorCallback(hdma);
 1094 
  hsram->DmaXferErrorCallback(hdma);
1095 
#else
 1095 
#else
1096 
  HAL_SRAM_DMA_XferErrorCallback(hdma);
 1096 
  HAL_SRAM_DMA_XferErrorCallback(hdma);
1097 
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
 1097 
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
1098 
}
 1098 
}
1099 
 
 1099 
 
1100 
/**
 1100 
/**
1101 
  * @}
 1101 
  * @}
1102 
  */
 1102 
  */
1103 
 
 1103 
 
1104 
#endif /* HAL_SRAM_MODULE_ENABLED */
 1104 
/**
1105 
 
 1105 
  * @}
1106 
/**
 1106 
  */
1107 
  * @}
 1107 
 
1108 
  */
 1108 
#endif /* HAL_SRAM_MODULE_ENABLED */
1109 
 
 1109 
 
1110 
#endif /* FSMC_BANK1 */
 1110 
/**
1111 
 
 1111 
  * @}
1112 
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 1112 
  */
- 
 
 1113 
 
- 
 
 1114 
#endif /* FSMC_BANK1 */