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/**
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/**
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  ******************************************************************************
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  ******************************************************************************
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  * @file    stm32f1xx_hal_spi.c
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  * @file    stm32f1xx_hal_spi.c
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  * @author  MCD Application Team
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  * @author  MCD Application Team
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  * @brief   SPI HAL module driver.
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  * @brief   SPI HAL module driver.
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  *          This file provides firmware functions to manage the following
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  *          This file provides firmware functions to manage the following
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  *          functionalities of the Serial Peripheral Interface (SPI) peripheral:
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  *          functionalities of the Serial Peripheral Interface (SPI) peripheral:
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  *           + Initialization and de-initialization functions
 8 
  *           + Initialization and de-initialization functions
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  *           + IO operation functions
 9 
  *           + IO operation functions
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  *           + Peripheral Control functions
 10 
  *           + Peripheral Control functions
11 
  *           + Peripheral State functions
 11 
  *           + Peripheral State functions
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  *
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  ******************************************************************************
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  @verbatim
 13 
  * @attention
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  ==============================================================================
 14 
  *
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                        ##### How to use this driver #####
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  * Copyright (c) 2016 STMicroelectronics.
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  ==============================================================================
 16 
  * All rights reserved.
17 
    [..]
 17 
  *
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      The SPI HAL driver can be used as follows:
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  * This software is licensed under terms that can be found in the LICENSE file
19 
 
 19 
  * in the root directory of this software component.
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      (#) Declare a SPI_HandleTypeDef handle structure, for example:
 20 
  * If no LICENSE file comes with this software, it is provided AS-IS.
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          SPI_HandleTypeDef  hspi;
 21 
  *
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  ******************************************************************************
23 
      (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
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  @verbatim
24 
          (##) Enable the SPIx interface clock
 24 
  ==============================================================================
25 
          (##) SPI pins configuration
 25 
                        ##### How to use this driver #####
26 
              (+++) Enable the clock for the SPI GPIOs
 26 
  ==============================================================================
27 
              (+++) Configure these SPI pins as alternate function push-pull
 27 
    [..]
28 
          (##) NVIC configuration if you need to use interrupt process
 28 
      The SPI HAL driver can be used as follows:
29 
              (+++) Configure the SPIx interrupt priority
 29 
 
30 
              (+++) Enable the NVIC SPI IRQ handle
 30 
      (#) Declare a SPI_HandleTypeDef handle structure, for example:
31 
          (##) DMA Configuration if you need to use DMA process
 31 
          SPI_HandleTypeDef  hspi;
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              (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
 32 
 
33 
              (+++) Enable the DMAx clock
 33 
      (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
34 
              (+++) Configure the DMA handle parameters
 34 
          (##) Enable the SPIx interface clock
35 
              (+++) Configure the DMA Tx or Rx Stream/Channel
 35 
          (##) SPI pins configuration
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              (+++) Associate the initialized hdma_tx(or _rx)  handle to the hspi DMA Tx or Rx handle
 36 
              (+++) Enable the clock for the SPI GPIOs
37 
              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
 37 
              (+++) Configure these SPI pins as alternate function push-pull
38 
 
 38 
          (##) NVIC configuration if you need to use interrupt process
39 
      (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
 39 
              (+++) Configure the SPIx interrupt priority
40 
          management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
 40 
              (+++) Enable the NVIC SPI IRQ handle
41 
 
 41 
          (##) DMA Configuration if you need to use DMA process
42 
      (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
 42 
              (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
43 
          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
 43 
              (+++) Enable the DMAx clock
44 
              by calling the customized HAL_SPI_MspInit() API.
 44 
              (+++) Configure the DMA handle parameters
45 
     [..]
 45 
              (+++) Configure the DMA Tx or Rx Stream/Channel
46 
       Circular mode restriction:
 46 
              (+++) Associate the initialized hdma_tx(or _rx)  handle to the hspi DMA Tx or Rx handle
47 
      (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
 47 
              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
48 
          (##) Master 2Lines RxOnly
 48 
 
49 
          (##) Master 1Line Rx
 49 
      (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
50 
      (#) The CRC feature is not managed when the DMA circular mode is enabled
 50 
          management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
51 
      (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
 51 
 
52 
          the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
 52 
      (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
53 
     [..]
 53 
          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
54 
       Master Receive mode restriction:
 54 
              by calling the customized HAL_SPI_MspInit() API.
55 
      (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or
 55 
     [..]
56 
          bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
 56 
       Circular mode restriction:
57 
          does not initiate a new transfer the following procedure has to be respected:
 57 
      (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
58 
          (##) HAL_SPI_DeInit()
 58 
          (##) Master 2Lines RxOnly
59 
          (##) HAL_SPI_Init()
 59 
          (##) Master 1Line Rx
60 
     [..]
 60 
      (#) The CRC feature is not managed when the DMA circular mode is enabled
61 
       Callback registration:
 61 
      (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
62 
 
 62 
          the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
63 
      (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
 63 
     [..]
64 
          allows the user to configure dynamically the driver callbacks.
 64 
       Master Receive mode restriction:
65 
          Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
 65 
      (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or
66 
 
 66 
          bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
67 
          Function HAL_SPI_RegisterCallback() allows to register following callbacks:
 67 
          does not initiate a new transfer the following procedure has to be respected:
68 
            (++) TxCpltCallback        : SPI Tx Completed callback
 68 
          (##) HAL_SPI_DeInit()
69 
            (++) RxCpltCallback        : SPI Rx Completed callback
 69 
          (##) HAL_SPI_Init()
70 
            (++) TxRxCpltCallback      : SPI TxRx Completed callback
 70 
     [..]
71 
            (++) TxHalfCpltCallback    : SPI Tx Half Completed callback
 71 
       Callback registration:
72 
            (++) RxHalfCpltCallback    : SPI Rx Half Completed callback
 72 
 
73 
            (++) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback
 73 
      (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
74 
            (++) ErrorCallback         : SPI Error callback
 74 
          allows the user to configure dynamically the driver callbacks.
75 
            (++) AbortCpltCallback     : SPI Abort callback
 75 
          Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
76 
            (++) MspInitCallback       : SPI Msp Init callback
 76 
 
77 
            (++) MspDeInitCallback     : SPI Msp DeInit callback
 77 
          Function HAL_SPI_RegisterCallback() allows to register following callbacks:
78 
          This function takes as parameters the HAL peripheral handle, the Callback ID
 78 
            (++) TxCpltCallback        : SPI Tx Completed callback
79 
          and a pointer to the user callback function.
 79 
            (++) RxCpltCallback        : SPI Rx Completed callback
80 
 
 80 
            (++) TxRxCpltCallback      : SPI TxRx Completed callback
81 
 
 81 
            (++) TxHalfCpltCallback    : SPI Tx Half Completed callback
82 
      (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
 82 
            (++) RxHalfCpltCallback    : SPI Rx Half Completed callback
83 
          weak function.
 83 
            (++) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback
84 
          HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
 84 
            (++) ErrorCallback         : SPI Error callback
85 
          and the Callback ID.
 85 
            (++) AbortCpltCallback     : SPI Abort callback
86 
          This function allows to reset following callbacks:
 86 
            (++) MspInitCallback       : SPI Msp Init callback
87 
            (++) TxCpltCallback        : SPI Tx Completed callback
 87 
            (++) MspDeInitCallback     : SPI Msp DeInit callback
88 
            (++) RxCpltCallback        : SPI Rx Completed callback
 88 
          This function takes as parameters the HAL peripheral handle, the Callback ID
89 
            (++) TxRxCpltCallback      : SPI TxRx Completed callback
 89 
          and a pointer to the user callback function.
90 
            (++) TxHalfCpltCallback    : SPI Tx Half Completed callback
 90 
 
91 
            (++) RxHalfCpltCallback    : SPI Rx Half Completed callback
 91 
 
92 
            (++) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback
 92 
      (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
93 
            (++) ErrorCallback         : SPI Error callback
 93 
          weak function.
94 
            (++) AbortCpltCallback     : SPI Abort callback
 94 
          HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
95 
            (++) MspInitCallback       : SPI Msp Init callback
 95 
          and the Callback ID.
96 
            (++) MspDeInitCallback     : SPI Msp DeInit callback
 96 
          This function allows to reset following callbacks:
97 
 
 97 
            (++) TxCpltCallback        : SPI Tx Completed callback
98 
       [..]
 98 
            (++) RxCpltCallback        : SPI Rx Completed callback
99 
       By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
 99 
            (++) TxRxCpltCallback      : SPI TxRx Completed callback
100 
       all callbacks are set to the corresponding weak functions:
 100 
            (++) TxHalfCpltCallback    : SPI Tx Half Completed callback
101 
       examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
 101 
            (++) RxHalfCpltCallback    : SPI Rx Half Completed callback
102 
       Exception done for MspInit and MspDeInit functions that are
 102 
            (++) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback
103 
       reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
 103 
            (++) ErrorCallback         : SPI Error callback
104 
       these callbacks are null (not registered beforehand).
 104 
            (++) AbortCpltCallback     : SPI Abort callback
105 
       If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
 105 
            (++) MspInitCallback       : SPI Msp Init callback
106 
       keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
 106 
            (++) MspDeInitCallback     : SPI Msp DeInit callback
107 
 
 107 
 
108 
       [..]
 108 
       [..]
109 
       Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
 109 
       By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
110 
       Exception done MspInit/MspDeInit functions that can be registered/unregistered
 110 
       all callbacks are set to the corresponding weak functions:
111 
       in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
 111 
       examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
112 
       thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
 112 
       Exception done for MspInit and MspDeInit functions that are
113 
       Then, the user first registers the MspInit/MspDeInit user callbacks
 113 
       reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
114 
       using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
 114 
       these callbacks are null (not registered beforehand).
115 
       or HAL_SPI_Init() function.
 115 
       If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
116 
 
 116 
       keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
117 
       [..]
 117 
 
118 
       When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
 118 
       [..]
119 
       not defined, the callback registering feature is not available
 119 
       Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
120 
       and weak (surcharged) callbacks are used.
 120 
       Exception done MspInit/MspDeInit functions that can be registered/unregistered
121 
 
 121 
       in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
122 
     [..]
 122 
       thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
123 
       Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,
 123 
       Then, the user first registers the MspInit/MspDeInit user callbacks
124 
       the following table resume the max SPI frequency reached with data size 8bits/16bits,
 124 
       using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
125 
         according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.
 125 
       or HAL_SPI_Init() function.
126 
 
 126 
 
127 
  @endverbatim
 127 
       [..]
128 
 
 128 
       When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
129 
  Additional table :
 129 
       not defined, the callback registering feature is not available
130 
 
 130 
       and weak (surcharged) callbacks are used.
131 
       DataSize = SPI_DATASIZE_8BIT:
 131 
 
132 
       +----------------------------------------------------------------------------------------------+
 132 
     [..]
133 
       |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |
 133 
       Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,
134 
       | Process | Transfer mode  |---------------------|----------------------|----------------------|
 134 
       the following table resume the max SPI frequency reached with data size 8bits/16bits,
135 
       |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |
 135 
         according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.
136 
       |==============================================================================================|
 136 
 
137 
       |    T    |     Polling    | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
 137 
  @endverbatim
138 
       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
 138 
 
139 
       |    /    |     Interrupt  | Fpclk/4  | Fpclk/8  |    NA     |    NA    |    NA     |   NA     |
 139 
  Additional table :
140 
       |    R    |----------------|----------|----------|-----------|----------|-----------|----------|
 140 
 
141 
       |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
 141 
       DataSize = SPI_DATASIZE_8BIT:
142 
       |=========|================|==========|==========|===========|==========|===========|==========|
 142 
       +----------------------------------------------------------------------------------------------+
143 
       |         |     Polling    | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/64  | Fpclk/2  |
 143 
       |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |
144 
       |         |----------------|----------|----------|-----------|----------|-----------|----------|
 144 
       | Process | Transfer mode  |---------------------|----------------------|----------------------|
145 
       |    R    |     Interrupt  | Fpclk/8  | Fpclk/8  | Fpclk/64  | Fpclk/2  | Fpclk/64  | Fpclk/2  |
 145 
       |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |
146 
       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
 146 
       |==============================================================================================|
147 
       |         |       DMA      | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/128 | Fpclk/2  |
 147 
       |    T    |     Polling    | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
148 
       |=========|================|==========|==========|===========|==========|===========|==========|
 148 
       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
149 
       |         |     Polling    | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/2   | Fpclk/64 |
 149 
       |    /    |     Interrupt  | Fpclk/4  | Fpclk/8  |    NA     |    NA    |    NA     |   NA     |
150 
       |         |----------------|----------|----------|-----------|----------|-----------|----------|
 150 
       |    R    |----------------|----------|----------|-----------|----------|-----------|----------|
151 
       |    T    |     Interrupt  | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/2   | Fpclk/64 |
 151 
       |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
152 
       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
 152 
       |=========|================|==========|==========|===========|==========|===========|==========|
153 
       |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/128|
 153 
       |         |     Polling    | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/64  | Fpclk/2  |
154 
       +----------------------------------------------------------------------------------------------+
 154 
       |         |----------------|----------|----------|-----------|----------|-----------|----------|
155 
 
 155 
       |    R    |     Interrupt  | Fpclk/8  | Fpclk/8  | Fpclk/64  | Fpclk/2  | Fpclk/64  | Fpclk/2  |
156 
       DataSize = SPI_DATASIZE_16BIT:
 156 
       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
157 
       +----------------------------------------------------------------------------------------------+
 157 
       |         |       DMA      | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/128 | Fpclk/2  |
158 
       |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |
 158 
       |=========|================|==========|==========|===========|==========|===========|==========|
159 
       | Process | Transfer mode  |---------------------|----------------------|----------------------|
 159 
       |         |     Polling    | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/2   | Fpclk/64 |
160 
       |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |
 160 
       |         |----------------|----------|----------|-----------|----------|-----------|----------|
161 
       |==============================================================================================|
 161 
       |    T    |     Interrupt  | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/2   | Fpclk/64 |
162 
       |    T    |     Polling    | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
 162 
       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
163 
       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
 163 
       |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/128|
164 
       |    /    |     Interrupt  | Fpclk/4  | Fpclk/4  |    NA     |    NA    |    NA     |   NA     |
 164 
       +----------------------------------------------------------------------------------------------+
165 
       |    R    |----------------|----------|----------|-----------|----------|-----------|----------|
 165 
 
166 
       |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
 166 
       DataSize = SPI_DATASIZE_16BIT:
167 
       |=========|================|==========|==========|===========|==========|===========|==========|
 167 
       +----------------------------------------------------------------------------------------------+
168 
       |         |     Polling    | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/32  | Fpclk/2  |
 168 
       |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |
169 
       |         |----------------|----------|----------|-----------|----------|-----------|----------|
 169 
       | Process | Transfer mode  |---------------------|----------------------|----------------------|
170 
       |    R    |     Interrupt  | Fpclk/4  | Fpclk/4  | Fpclk/64  | Fpclk/2  | Fpclk/64  | Fpclk/2  |
 170 
       |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |
171 
       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
 171 
       |==============================================================================================|
172 
       |         |       DMA      | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/128 | Fpclk/2  |
 172 
       |    T    |     Polling    | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
173 
       |=========|================|==========|==========|===========|==========|===========|==========|
 173 
       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
174 
       |         |     Polling    | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/32 |
 174 
       |    /    |     Interrupt  | Fpclk/4  | Fpclk/4  |    NA     |    NA    |    NA     |   NA     |
175 
       |         |----------------|----------|----------|-----------|----------|-----------|----------|
 175 
       |    R    |----------------|----------|----------|-----------|----------|-----------|----------|
176 
       |    T    |     Interrupt  | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/64 |
 176 
       |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
177 
       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
 177 
       |=========|================|==========|==========|===========|==========|===========|==========|
178 
       |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/128|
 178 
       |         |     Polling    | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/32  | Fpclk/2  |
179 
       +----------------------------------------------------------------------------------------------+
 179 
       |         |----------------|----------|----------|-----------|----------|-----------|----------|
180 
       @note The max SPI frequency depend on SPI data size (8bits, 16bits),
 180 
       |    R    |     Interrupt  | Fpclk/4  | Fpclk/4  | Fpclk/64  | Fpclk/2  | Fpclk/64  | Fpclk/2  |
181 
             SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
 181 
       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
182 
       @note
 182 
       |         |       DMA      | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/128 | Fpclk/2  |
183 
            (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
 183 
       |=========|================|==========|==========|===========|==========|===========|==========|
184 
            (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
 184 
       |         |     Polling    | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/32 |
185 
            (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
 185 
       |         |----------------|----------|----------|-----------|----------|-----------|----------|
186 
 
 186 
       |    T    |     Interrupt  | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/64 |
187 
  ******************************************************************************
 187 
       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
188 
  * @attention
 188 
       |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/128|
189 
  *
 189 
       +----------------------------------------------------------------------------------------------+
190 
  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
 190 
       @note The max SPI frequency depend on SPI data size (8bits, 16bits),
191 
  * All rights reserved.</center></h2>
 191 
             SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
192 
  *
 192 
       @note
193 
  * This software component is licensed by ST under BSD 3-Clause license,
 193 
            (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
194 
  * the "License"; You may not use this file except in compliance with the
 194 
            (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
195 
  * License. You may obtain a copy of the License at:
 195 
            (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
196 
  *                        opensource.org/licenses/BSD-3-Clause
 196 
 
197 
  *
 197 
  */
198 
  ******************************************************************************
 198 
 
199 
  */
 199 
/* Includes ------------------------------------------------------------------*/
200 
 
 200 
#include "stm32f1xx_hal.h"
201 
/* Includes ------------------------------------------------------------------*/
 201 
 
202 
#include "stm32f1xx_hal.h"
 202 
/** @addtogroup STM32F1xx_HAL_Driver
203 
 
 203 
  * @{
204 
/** @addtogroup STM32F1xx_HAL_Driver
 204 
  */
205 
  * @{
 205 
 
206 
  */
 206 
/** @defgroup SPI SPI
207 
 
 207 
  * @brief SPI HAL module driver
208 
/** @defgroup SPI SPI
 208 
  * @{
209 
  * @brief SPI HAL module driver
 209 
  */
210 
  * @{
 210 
#ifdef HAL_SPI_MODULE_ENABLED
211 
  */
 211 
 
212 
#ifdef HAL_SPI_MODULE_ENABLED
 212 
/* Private typedef -----------------------------------------------------------*/
213 
 
 213 
/* Private defines -----------------------------------------------------------*/
214 
/* Private typedef -----------------------------------------------------------*/
 214 
#if (USE_SPI_CRC != 0U) && defined(SPI_CRC_ERROR_WORKAROUND_FEATURE)
215 
/* Private defines -----------------------------------------------------------*/
 215 
/* CRC WORKAROUND FEATURE: Variable used to determine if device is impacted by implementation
216 
#if (USE_SPI_CRC != 0U) && defined(SPI_CRC_ERROR_WORKAROUND_FEATURE)
 216 
 * of workaround related to wrong CRC errors detection on SPI2. Conditions in which this workaround
217 
/* CRC WORKAOUND FEATURE: Variable used to determine if device is impacted by implementation
 217 
 * has to be applied, are:
218 
 * of workaround related to wrong CRC errors detection on SPI2. Conditions in which this workaround
 218 
 *  - STM32F101CDE/STM32F103CDE
219 
 * has to be applied, are:
 219 
 *  - Revision ID : Z
220 
 *  - STM32F101CDE/STM32F103CDE
 220 
 *  - SPI2
221 
 *  - Revision ID : Z
 221 
 *  - In receive only mode, with CRC calculation enabled, at the end of the CRC reception,
222 
 *  - SPI2
 222 
 *     the software needs to check the CRCERR flag. If it is found set, read back the SPI_RXCRC:
223 
 *  - In receive only mode, with CRC calculation enabled, at the end of the CRC reception,
 223 
 *       + If the value is 0, the complete data transfer is successful.
224 
 *     the software needs to check the CRCERR flag. If it is found set, read back the SPI_RXCRC:
 224 
 *       + Otherwise, one or more errors have been detected during the data transfer by CPU or DMA.
225 
 *       + If the value is 0, the complete data transfer is successful.
 225 
 *    If CRCERR is found reset, the complete data transfer is considered successful.
226 
 *       + Otherwise, one or more errors have been detected during the data transfer by CPU or DMA.
 226 
 *
227 
 *    If CRCERR is found reset, the complete data transfer is considered successful.
 227 
 * Check RevisionID value for identifying if Device is Rev Z (0x0001) in order to enable workaround for
228 
 *
 228 
 * CRC errors wrongly detected
229 
 * Check RevisionID value for identifying if Device is Rev Z (0x0001) in order to enable workaround for
 229 
 */
230 
 * CRC errors wrongly detected
 230 
/* Pb is that ES_STM32F10xxCDE also identify an issue in Debug registers access while not in Debug mode
231 
 */
 231 
 * Revision ID information is only available in Debug mode, so Workaround could not be implemented
232 
/* Pb is that ES_STM32F10xxCDE also identify an issue in Debug registers access while not in Debug mode
 232 
 * to distinguish Rev Z devices (issue present) from more recent version (issue fixed).
233 
 * Revision ID information is only available in Debug mode, so Workaround could not be implemented
 233 
 * So, in case of Revision Z F101 or F103 devices, below define should be assigned to 1.
234 
 * to distinguish Rev Z devices (issue present) from more recent version (issue fixed).
 234 
 */
235 
 * So, in case of Revison Z F101 or F103 devices, below define should be assigned to 1.
 235 
#define  USE_SPI_CRC_ERROR_WORKAROUND   0U
236 
 */
 236 
#endif /* USE_SPI_CRC */
237 
#define  USE_SPI_CRC_ERROR_WORKAROUND   0U
 237 
/** @defgroup SPI_Private_Constants SPI Private Constants
238 
#endif
 238 
  * @{
239 
/** @defgroup SPI_Private_Constants SPI Private Constants
 239 
  */
240 
  * @{
 240 
#define SPI_DEFAULT_TIMEOUT 100U
241 
  */
 241 
/**
242 
#define SPI_DEFAULT_TIMEOUT 100U
 242 
  * @}
243 
/**
 243 
  */
244 
  * @}
 244 
 
245 
  */
 245 
/* Private macros ------------------------------------------------------------*/
246 
 
 246 
/* Private variables ---------------------------------------------------------*/
247 
/* Private macros ------------------------------------------------------------*/
 247 
/* Private function prototypes -----------------------------------------------*/
248 
/* Private variables ---------------------------------------------------------*/
 248 
/** @defgroup SPI_Private_Functions SPI Private Functions
249 
/* Private function prototypes -----------------------------------------------*/
 249 
  * @{
250 
/** @defgroup SPI_Private_Functions SPI Private Functions
 250 
  */
251 
  * @{
 251 
static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
252 
  */
 252 
static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
253 
static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
 253 
static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
254 
static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
 254 
static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
255 
static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
 255 
static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
256 
static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
 256 
static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
257 
static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
 257 
static void SPI_DMAError(DMA_HandleTypeDef *hdma);
258 
static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
 258 
static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
259 
static void SPI_DMAError(DMA_HandleTypeDef *hdma);
 259 
static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
260 
static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
 260 
static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
261 
static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
 261 
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
262 
static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
 262 
                                                       uint32_t Timeout, uint32_t Tickstart);
263 
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
 263 
static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
264 
                                                       uint32_t Timeout, uint32_t Tickstart);
 264 
static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
265 
static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
 265 
static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
266 
static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
 266 
static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
267 
static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
 267 
static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
268 
static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
 268 
static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
269 
static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
 269 
static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
270 
static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
 270 
static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
271 
static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
 271 
#if (USE_SPI_CRC != 0U)
272 
static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
 272 
static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
273 
#if (USE_SPI_CRC != 0U)
 273 
static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
274 
static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
 274 
static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
275 
static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
 275 
static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
276 
static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
 276 
#endif /* USE_SPI_CRC */
277 
static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
 277 
static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
278 
#endif /* USE_SPI_CRC */
 278 
static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
279 
static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
 279 
static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
280 
static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
 280 
static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
281 
static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
 281 
static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
282 
static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
 282 
static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
283 
static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
 283 
static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
284 
static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
 284 
/**
285 
static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
 285 
  * @}
286 
/**
 286 
  */
287 
  * @}
 287 
 
288 
  */
 288 
/* Exported functions --------------------------------------------------------*/
289 
 
 289 
/** @defgroup SPI_Exported_Functions SPI Exported Functions
290 
/* Exported functions --------------------------------------------------------*/
 290 
  * @{
291 
/** @defgroup SPI_Exported_Functions SPI Exported Functions
 291 
  */
292 
  * @{
 292 
 
293 
  */
 293 
/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
294 
 
 294 
  *  @brief    Initialization and Configuration functions
295 
/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
 295 
  *
296 
  *  @brief    Initialization and Configuration functions
 296 
@verbatim
297 
  *
 297 
 ===============================================================================
298 
@verbatim
 298 
              ##### Initialization and de-initialization functions #####
299 
 ===============================================================================
 299 
 ===============================================================================
300 
              ##### Initialization and de-initialization functions #####
 300 
    [..]  This subsection provides a set of functions allowing to initialize and
301 
 ===============================================================================
 301 
          de-initialize the SPIx peripheral:
302 
    [..]  This subsection provides a set of functions allowing to initialize and
 302 
 
303 
          de-initialize the SPIx peripheral:
 303 
      (+) User must implement HAL_SPI_MspInit() function in which he configures
304 
 
 304 
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
305 
      (+) User must implement HAL_SPI_MspInit() function in which he configures
 305 
 
306 
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
 306 
      (+) Call the function HAL_SPI_Init() to configure the selected device with
307 
 
 307 
          the selected configuration:
308 
      (+) Call the function HAL_SPI_Init() to configure the selected device with
 308 
        (++) Mode
309 
          the selected configuration:
 309 
        (++) Direction
310 
        (++) Mode
 310 
        (++) Data Size
311 
        (++) Direction
 311 
        (++) Clock Polarity and Phase
312 
        (++) Data Size
 312 
        (++) NSS Management
313 
        (++) Clock Polarity and Phase
 313 
        (++) BaudRate Prescaler
314 
        (++) NSS Management
 314 
        (++) FirstBit
315 
        (++) BaudRate Prescaler
 315 
        (++) TIMode
316 
        (++) FirstBit
 316 
        (++) CRC Calculation
317 
        (++) TIMode
 317 
        (++) CRC Polynomial if CRC enabled
318 
        (++) CRC Calculation
 318 
 
319 
        (++) CRC Polynomial if CRC enabled
 319 
      (+) Call the function HAL_SPI_DeInit() to restore the default configuration
320 
 
 320 
          of the selected SPIx peripheral.
321 
      (+) Call the function HAL_SPI_DeInit() to restore the default configuration
 321 
 
322 
          of the selected SPIx peripheral.
 322 
@endverbatim
323 
 
 323 
  * @{
324 
@endverbatim
 324 
  */
325 
  * @{
 325 
 
326 
  */
 326 
/**
327 
 
 327 
  * @brief  Initialize the SPI according to the specified parameters
328 
/**
 328 
  *         in the SPI_InitTypeDef and initialize the associated handle.
329 
  * @brief  Initialize the SPI according to the specified parameters
 329 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
330 
  *         in the SPI_InitTypeDef and initialize the associated handle.
 330 
  *               the configuration information for SPI module.
331 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 331 
  * @retval HAL status
332 
  *               the configuration information for SPI module.
 332 
  */
333 
  * @retval HAL status
 333 
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
334 
  */
 334 
{
335 
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
 335 
  /* Check the SPI handle allocation */
336 
{
 336 
  if (hspi == NULL)
337 
  /* Check the SPI handle allocation */
 337 
  {
338 
  if (hspi == NULL)
 338 
    return HAL_ERROR;
339 
  {
 339 
  }
340 
    return HAL_ERROR;
 340 
 
341 
  }
 341 
  /* Check the parameters */
342 
 
 342 
  assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
343 
  /* Check the parameters */
 343 
  assert_param(IS_SPI_MODE(hspi->Init.Mode));
344 
  assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
 344 
  assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
345 
  assert_param(IS_SPI_MODE(hspi->Init.Mode));
 345 
  assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
346 
  assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
 346 
  assert_param(IS_SPI_NSS(hspi->Init.NSS));
347 
  assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
 347 
  assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
348 
  assert_param(IS_SPI_NSS(hspi->Init.NSS));
 348 
  assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
349 
  assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
 349 
  /* TI mode is not supported on this device.
350 
  assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
 350 
     TIMode parameter is mandatory equal to SPI_TIMODE_DISABLE */
351 
  /* TI mode is not supported on this device.
 351 
  assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
352 
     TIMode parameter is mandatory equal to SPI_TIMODE_DISABLE */
 352 
  if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
353 
  assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
 353 
  {
354 
  if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
 354 
    assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
355 
  {
 355 
    assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
356 
    assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
 356 
 
357 
    assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
 357 
    if (hspi->Init.Mode == SPI_MODE_MASTER)
358 
 
 358 
    {
359 
    if (hspi->Init.Mode == SPI_MODE_MASTER)
 359 
      assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
360 
    {
 360 
    }
361 
      assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
 361 
    else
362 
    }
 362 
    {
363 
    else
 363 
      /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
364 
    {
 364 
      hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
365 
      /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
 365 
    }
366 
      hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
 366 
  }
367 
    }
 367 
  else
368 
  }
 368 
  {
369 
  else
 369 
    assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
370 
  {
 370 
 
371 
    assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
 371 
    /* Force polarity and phase to TI protocaol requirements */
372 
 
 372 
    hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
373 
    /* Force polarity and phase to TI protocaol requirements */
 373 
    hspi->Init.CLKPhase    = SPI_PHASE_1EDGE;
374 
    hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
 374 
  }
375 
    hspi->Init.CLKPhase    = SPI_PHASE_1EDGE;
 375 
#if (USE_SPI_CRC != 0U)
376 
  }
 376 
  assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
377 
#if (USE_SPI_CRC != 0U)
 377 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
378 
  assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
 378 
  {
379 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 379 
    assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
380 
  {
 380 
  }
381 
    assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
 381 
#else
382 
  }
 382 
  hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
383 
#else
 383 
#endif /* USE_SPI_CRC */
384 
  hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
 384 
 
385 
#endif /* USE_SPI_CRC */
 385 
  if (hspi->State == HAL_SPI_STATE_RESET)
386 
 
 386 
  {
387 
  if (hspi->State == HAL_SPI_STATE_RESET)
 387 
    /* Allocate lock resource and initialize it */
388 
  {
 388 
    hspi->Lock = HAL_UNLOCKED;
389 
    /* Allocate lock resource and initialize it */
 389 
 
390 
    hspi->Lock = HAL_UNLOCKED;
 390 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
391 
 
 391 
    /* Init the SPI Callback settings */
392 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 392 
    hspi->TxCpltCallback       = HAL_SPI_TxCpltCallback;       /* Legacy weak TxCpltCallback       */
393 
    /* Init the SPI Callback settings */
 393 
    hspi->RxCpltCallback       = HAL_SPI_RxCpltCallback;       /* Legacy weak RxCpltCallback       */
394 
    hspi->TxCpltCallback       = HAL_SPI_TxCpltCallback;       /* Legacy weak TxCpltCallback       */
 394 
    hspi->TxRxCpltCallback     = HAL_SPI_TxRxCpltCallback;     /* Legacy weak TxRxCpltCallback     */
395 
    hspi->RxCpltCallback       = HAL_SPI_RxCpltCallback;       /* Legacy weak RxCpltCallback       */
 395 
    hspi->TxHalfCpltCallback   = HAL_SPI_TxHalfCpltCallback;   /* Legacy weak TxHalfCpltCallback   */
396 
    hspi->TxRxCpltCallback     = HAL_SPI_TxRxCpltCallback;     /* Legacy weak TxRxCpltCallback     */
 396 
    hspi->RxHalfCpltCallback   = HAL_SPI_RxHalfCpltCallback;   /* Legacy weak RxHalfCpltCallback   */
397 
    hspi->TxHalfCpltCallback   = HAL_SPI_TxHalfCpltCallback;   /* Legacy weak TxHalfCpltCallback   */
 397 
    hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
398 
    hspi->RxHalfCpltCallback   = HAL_SPI_RxHalfCpltCallback;   /* Legacy weak RxHalfCpltCallback   */
 398 
    hspi->ErrorCallback        = HAL_SPI_ErrorCallback;        /* Legacy weak ErrorCallback        */
399 
    hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
 399 
    hspi->AbortCpltCallback    = HAL_SPI_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    */
400 
    hspi->ErrorCallback        = HAL_SPI_ErrorCallback;        /* Legacy weak ErrorCallback        */
 400 
 
401 
    hspi->AbortCpltCallback    = HAL_SPI_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    */
 401 
    if (hspi->MspInitCallback == NULL)
402 
 
 402 
    {
403 
    if (hspi->MspInitCallback == NULL)
 403 
      hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit  */
404 
    {
 404 
    }
405 
      hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit  */
 405 
 
406 
    }
 406 
    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
407 
 
 407 
    hspi->MspInitCallback(hspi);
408 
    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
 408 
#else
409 
    hspi->MspInitCallback(hspi);
 409 
    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
410 
#else
 410 
    HAL_SPI_MspInit(hspi);
411 
    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
 411 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
412 
    HAL_SPI_MspInit(hspi);
 412 
  }
413 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 413 
 
414 
  }
 414 
  hspi->State = HAL_SPI_STATE_BUSY;
415 
 
 415 
 
416 
  hspi->State = HAL_SPI_STATE_BUSY;
 416 
  /* Disable the selected SPI peripheral */
417 
 
 417 
  __HAL_SPI_DISABLE(hspi);
418 
  /* Disable the selected SPI peripheral */
 418 
 
419 
  __HAL_SPI_DISABLE(hspi);
 419 
  /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
420 
 
 420 
  /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
421 
  /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
 421 
  Communication speed, First bit and CRC calculation state */
422 
  /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
 422 
  WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
423 
  Communication speed, First bit and CRC calculation state */
 423 
                                  (hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) |
424 
  WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
 424 
                                  (hspi->Init.DataSize & SPI_CR1_DFF) |
425 
                                  (hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) |
 425 
                                  (hspi->Init.CLKPolarity & SPI_CR1_CPOL) |
426 
                                  (hspi->Init.DataSize & SPI_CR1_DFF) |
 426 
                                  (hspi->Init.CLKPhase & SPI_CR1_CPHA) |
427 
                                  (hspi->Init.CLKPolarity & SPI_CR1_CPOL) |
 427 
                                  (hspi->Init.NSS & SPI_CR1_SSM) |
428 
                                  (hspi->Init.CLKPhase & SPI_CR1_CPHA) |
 428 
                                  (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) |
429 
                                  (hspi->Init.NSS & SPI_CR1_SSM) |
 429 
                                  (hspi->Init.FirstBit  & SPI_CR1_LSBFIRST) |
430 
                                  (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) |
 430 
                                  (hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
431 
                                  (hspi->Init.FirstBit  & SPI_CR1_LSBFIRST) |
 431 
 
432 
                                  (hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
 432 
  /* Configure : NSS management */
433 
 
 433 
  WRITE_REG(hspi->Instance->CR2, ((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE));
434 
  /* Configure : NSS management */
 434 
 
435 
  WRITE_REG(hspi->Instance->CR2, ((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE));
 435 
#if (USE_SPI_CRC != 0U)
436 
 
 436 
  /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
437 
#if (USE_SPI_CRC != 0U)
 437 
  /* Configure : CRC Polynomial */
438 
  /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
 438 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
439 
  /* Configure : CRC Polynomial */
 439 
  {
440 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 440 
    WRITE_REG(hspi->Instance->CRCPR, (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk));
441 
  {
 441 
  }
442 
    WRITE_REG(hspi->Instance->CRCPR, (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk));
 442 
#endif /* USE_SPI_CRC */
443 
  }
 443 
 
444 
#endif /* USE_SPI_CRC */
 444 
#if defined(SPI_I2SCFGR_I2SMOD)
445 
 
 445 
  /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
446 
#if defined(SPI_I2SCFGR_I2SMOD)
 446 
  CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
447 
  /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
 447 
#endif /* SPI_I2SCFGR_I2SMOD */
448 
  CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
 448 
 
449 
#endif /* SPI_I2SCFGR_I2SMOD */
 449 
  hspi->ErrorCode = HAL_SPI_ERROR_NONE;
450 
 
 450 
  hspi->State     = HAL_SPI_STATE_READY;
451 
  hspi->ErrorCode = HAL_SPI_ERROR_NONE;
 451 
 
452 
  hspi->State     = HAL_SPI_STATE_READY;
 452 
  return HAL_OK;
453 
 
 453 
}
454 
  return HAL_OK;
 454 
 
455 
}
 455 
/**
456 
 
 456 
  * @brief  De-Initialize the SPI peripheral.
457 
/**
 457 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
458 
  * @brief  De-Initialize the SPI peripheral.
 458 
  *               the configuration information for SPI module.
459 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 459 
  * @retval HAL status
460 
  *               the configuration information for SPI module.
 460 
  */
461 
  * @retval HAL status
 461 
HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
462 
  */
 462 
{
463 
HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
 463 
  /* Check the SPI handle allocation */
464 
{
 464 
  if (hspi == NULL)
465 
  /* Check the SPI handle allocation */
 465 
  {
466 
  if (hspi == NULL)
 466 
    return HAL_ERROR;
467 
  {
 467 
  }
468 
    return HAL_ERROR;
 468 
 
469 
  }
 469 
  /* Check SPI Instance parameter */
470 
 
 470 
  assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
471 
  /* Check SPI Instance parameter */
 471 
 
472 
  assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
 472 
  hspi->State = HAL_SPI_STATE_BUSY;
473 
 
 473 
 
474 
  hspi->State = HAL_SPI_STATE_BUSY;
 474 
  /* Disable the SPI Peripheral Clock */
475 
 
 475 
  __HAL_SPI_DISABLE(hspi);
476 
  /* Disable the SPI Peripheral Clock */
 476 
 
477 
  __HAL_SPI_DISABLE(hspi);
 477 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
478 
 
 478 
  if (hspi->MspDeInitCallback == NULL)
479 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 479 
  {
480 
  if (hspi->MspDeInitCallback == NULL)
 480 
    hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit  */
481 
  {
 481 
  }
482 
    hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit  */
 482 
 
483 
  }
 483 
  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
484 
 
 484 
  hspi->MspDeInitCallback(hspi);
485 
  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
 485 
#else
486 
  hspi->MspDeInitCallback(hspi);
 486 
  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
487 
#else
 487 
  HAL_SPI_MspDeInit(hspi);
488 
  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
 488 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
489 
  HAL_SPI_MspDeInit(hspi);
 489 
 
490 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 490 
  hspi->ErrorCode = HAL_SPI_ERROR_NONE;
491 
 
 491 
  hspi->State = HAL_SPI_STATE_RESET;
492 
  hspi->ErrorCode = HAL_SPI_ERROR_NONE;
 492 
 
493 
  hspi->State = HAL_SPI_STATE_RESET;
 493 
  /* Release Lock */
494 
 
 494 
  __HAL_UNLOCK(hspi);
495 
  /* Release Lock */
 495 
 
496 
  __HAL_UNLOCK(hspi);
 496 
  return HAL_OK;
497 
 
 497 
}
498 
  return HAL_OK;
 498 
 
499 
}
 499 
/**
500 
 
 500 
  * @brief  Initialize the SPI MSP.
501 
/**
 501 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
502 
  * @brief  Initialize the SPI MSP.
 502 
  *               the configuration information for SPI module.
503 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 503 
  * @retval None
504 
  *               the configuration information for SPI module.
 504 
  */
505 
  * @retval None
 505 
__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
506 
  */
 506 
{
507 
__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
 507 
  /* Prevent unused argument(s) compilation warning */
508 
{
 508 
  UNUSED(hspi);
509 
  /* Prevent unused argument(s) compilation warning */
 509 
 
510 
  UNUSED(hspi);
 510 
  /* NOTE : This function should not be modified, when the callback is needed,
511 
 
 511 
            the HAL_SPI_MspInit should be implemented in the user file
512 
  /* NOTE : This function should not be modified, when the callback is needed,
 512 
   */
513 
            the HAL_SPI_MspInit should be implemented in the user file
 513 
}
514 
   */
 514 
 
515 
}
 515 
/**
516 
 
 516 
  * @brief  De-Initialize the SPI MSP.
517 
/**
 517 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
518 
  * @brief  De-Initialize the SPI MSP.
 518 
  *               the configuration information for SPI module.
519 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 519 
  * @retval None
520 
  *               the configuration information for SPI module.
 520 
  */
521 
  * @retval None
 521 
__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
522 
  */
 522 
{
523 
__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
 523 
  /* Prevent unused argument(s) compilation warning */
524 
{
 524 
  UNUSED(hspi);
525 
  /* Prevent unused argument(s) compilation warning */
 525 
 
526 
  UNUSED(hspi);
 526 
  /* NOTE : This function should not be modified, when the callback is needed,
527 
 
 527 
            the HAL_SPI_MspDeInit should be implemented in the user file
528 
  /* NOTE : This function should not be modified, when the callback is needed,
 528 
   */
529 
            the HAL_SPI_MspDeInit should be implemented in the user file
 529 
}
530 
   */
 530 
 
531 
}
 531 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
532 
 
 532 
/**
533 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 533 
  * @brief  Register a User SPI Callback
534 
/**
 534 
  *         To be used instead of the weak predefined callback
535 
  * @brief  Register a User SPI Callback
 535 
  * @param  hspi Pointer to a SPI_HandleTypeDef structure that contains
536 
  *         To be used instead of the weak predefined callback
 536 
  *                the configuration information for the specified SPI.
537 
  * @param  hspi Pointer to a SPI_HandleTypeDef structure that contains
 537 
  * @param  CallbackID ID of the callback to be registered
538 
  *                the configuration information for the specified SPI.
 538 
  * @param  pCallback pointer to the Callback function
539 
  * @param  CallbackID ID of the callback to be registered
 539 
  * @retval HAL status
540 
  * @param  pCallback pointer to the Callback function
 540 
  */
541 
  * @retval HAL status
 541 
HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
542 
  */
 542 
                                           pSPI_CallbackTypeDef pCallback)
543 
HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
 543 
{
544 
                                           pSPI_CallbackTypeDef pCallback)
 544 
  HAL_StatusTypeDef status = HAL_OK;
545 
{
 545 
 
546 
  HAL_StatusTypeDef status = HAL_OK;
 546 
  if (pCallback == NULL)
547 
 
 547 
  {
548 
  if (pCallback == NULL)
 548 
    /* Update the error code */
549 
  {
 549 
    hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;
550 
    /* Update the error code */
 550 
 
551 
    hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;
 551 
    return HAL_ERROR;
552 
 
 552 
  }
553 
    return HAL_ERROR;
 553 
  /* Process locked */
554 
  }
 554 
  __HAL_LOCK(hspi);
555 
  /* Process locked */
 555 
 
556 
  __HAL_LOCK(hspi);
 556 
  if (HAL_SPI_STATE_READY == hspi->State)
557 
 
 557 
  {
558 
  if (HAL_SPI_STATE_READY == hspi->State)
 558 
    switch (CallbackID)
559 
  {
 559 
    {
560 
    switch (CallbackID)
 560 
      case HAL_SPI_TX_COMPLETE_CB_ID :
561 
    {
 561 
        hspi->TxCpltCallback = pCallback;
562 
      case HAL_SPI_TX_COMPLETE_CB_ID :
 562 
        break;
563 
        hspi->TxCpltCallback = pCallback;
 563 
 
564 
        break;
 564 
      case HAL_SPI_RX_COMPLETE_CB_ID :
565 
 
 565 
        hspi->RxCpltCallback = pCallback;
566 
      case HAL_SPI_RX_COMPLETE_CB_ID :
 566 
        break;
567 
        hspi->RxCpltCallback = pCallback;
 567 
 
568 
        break;
 568 
      case HAL_SPI_TX_RX_COMPLETE_CB_ID :
569 
 
 569 
        hspi->TxRxCpltCallback = pCallback;
570 
      case HAL_SPI_TX_RX_COMPLETE_CB_ID :
 570 
        break;
571 
        hspi->TxRxCpltCallback = pCallback;
 571 
 
572 
        break;
 572 
      case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
573 
 
 573 
        hspi->TxHalfCpltCallback = pCallback;
574 
      case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
 574 
        break;
575 
        hspi->TxHalfCpltCallback = pCallback;
 575 
 
576 
        break;
 576 
      case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
577 
 
 577 
        hspi->RxHalfCpltCallback = pCallback;
578 
      case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
 578 
        break;
579 
        hspi->RxHalfCpltCallback = pCallback;
 579 
 
580 
        break;
 580 
      case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
581 
 
 581 
        hspi->TxRxHalfCpltCallback = pCallback;
582 
      case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
 582 
        break;
583 
        hspi->TxRxHalfCpltCallback = pCallback;
 583 
 
584 
        break;
 584 
      case HAL_SPI_ERROR_CB_ID :
585 
 
 585 
        hspi->ErrorCallback = pCallback;
586 
      case HAL_SPI_ERROR_CB_ID :
 586 
        break;
587 
        hspi->ErrorCallback = pCallback;
 587 
 
588 
        break;
 588 
      case HAL_SPI_ABORT_CB_ID :
589 
 
 589 
        hspi->AbortCpltCallback = pCallback;
590 
      case HAL_SPI_ABORT_CB_ID :
 590 
        break;
591 
        hspi->AbortCpltCallback = pCallback;
 591 
 
592 
        break;
 592 
      case HAL_SPI_MSPINIT_CB_ID :
593 
 
 593 
        hspi->MspInitCallback = pCallback;
594 
      case HAL_SPI_MSPINIT_CB_ID :
 594 
        break;
595 
        hspi->MspInitCallback = pCallback;
 595 
 
596 
        break;
 596 
      case HAL_SPI_MSPDEINIT_CB_ID :
597 
 
 597 
        hspi->MspDeInitCallback = pCallback;
598 
      case HAL_SPI_MSPDEINIT_CB_ID :
 598 
        break;
599 
        hspi->MspDeInitCallback = pCallback;
 599 
 
600 
        break;
 600 
      default :
601 
 
 601 
        /* Update the error code */
602 
      default :
 602 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
603 
        /* Update the error code */
 603 
 
604 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
 604 
        /* Return error status */
605 
 
 605 
        status =  HAL_ERROR;
606 
        /* Return error status */
 606 
        break;
607 
        status =  HAL_ERROR;
 607 
    }
608 
        break;
 608 
  }
609 
    }
 609 
  else if (HAL_SPI_STATE_RESET == hspi->State)
610 
  }
 610 
  {
611 
  else if (HAL_SPI_STATE_RESET == hspi->State)
 611 
    switch (CallbackID)
612 
  {
 612 
    {
613 
    switch (CallbackID)
 613 
      case HAL_SPI_MSPINIT_CB_ID :
614 
    {
 614 
        hspi->MspInitCallback = pCallback;
615 
      case HAL_SPI_MSPINIT_CB_ID :
 615 
        break;
616 
        hspi->MspInitCallback = pCallback;
 616 
 
617 
        break;
 617 
      case HAL_SPI_MSPDEINIT_CB_ID :
618 
 
 618 
        hspi->MspDeInitCallback = pCallback;
619 
      case HAL_SPI_MSPDEINIT_CB_ID :
 619 
        break;
620 
        hspi->MspDeInitCallback = pCallback;
 620 
 
621 
        break;
 621 
      default :
622 
 
 622 
        /* Update the error code */
623 
      default :
 623 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
624 
        /* Update the error code */
 624 
 
625 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
 625 
        /* Return error status */
626 
 
 626 
        status =  HAL_ERROR;
627 
        /* Return error status */
 627 
        break;
628 
        status =  HAL_ERROR;
 628 
    }
629 
        break;
 629 
  }
630 
    }
 630 
  else
631 
  }
 631 
  {
632 
  else
 632 
    /* Update the error code */
633 
  {
 633 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
634 
    /* Update the error code */
 634 
 
635 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
 635 
    /* Return error status */
636 
 
 636 
    status =  HAL_ERROR;
637 
    /* Return error status */
 637 
  }
638 
    status =  HAL_ERROR;
 638 
 
639 
  }
 639 
  /* Release Lock */
640 
 
 640 
  __HAL_UNLOCK(hspi);
641 
  /* Release Lock */
 641 
  return status;
642 
  __HAL_UNLOCK(hspi);
 642 
}
643 
  return status;
 643 
 
644 
}
 644 
/**
645 
 
 645 
  * @brief  Unregister an SPI Callback
646 
/**
 646 
  *         SPI callback is redirected to the weak predefined callback
647 
  * @brief  Unregister an SPI Callback
 647 
  * @param  hspi Pointer to a SPI_HandleTypeDef structure that contains
648 
  *         SPI callback is redirected to the weak predefined callback
 648 
  *                the configuration information for the specified SPI.
649 
  * @param  hspi Pointer to a SPI_HandleTypeDef structure that contains
 649 
  * @param  CallbackID ID of the callback to be unregistered
650 
  *                the configuration information for the specified SPI.
 650 
  * @retval HAL status
651 
  * @param  CallbackID ID of the callback to be unregistered
 651 
  */
652 
  * @retval HAL status
 652 
HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
653 
  */
 653 
{
654 
HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
 654 
  HAL_StatusTypeDef status = HAL_OK;
655 
{
 655 
 
656 
  HAL_StatusTypeDef status = HAL_OK;
 656 
  /* Process locked */
657 
 
 657 
  __HAL_LOCK(hspi);
658 
  /* Process locked */
 658 
 
659 
  __HAL_LOCK(hspi);
 659 
  if (HAL_SPI_STATE_READY == hspi->State)
660 
 
 660 
  {
661 
  if (HAL_SPI_STATE_READY == hspi->State)
 661 
    switch (CallbackID)
662 
  {
 662 
    {
663 
    switch (CallbackID)
 663 
      case HAL_SPI_TX_COMPLETE_CB_ID :
664 
    {
 664 
        hspi->TxCpltCallback = HAL_SPI_TxCpltCallback;             /* Legacy weak TxCpltCallback       */
665 
      case HAL_SPI_TX_COMPLETE_CB_ID :
 665 
        break;
666 
        hspi->TxCpltCallback = HAL_SPI_TxCpltCallback;             /* Legacy weak TxCpltCallback       */
 666 
 
667 
        break;
 667 
      case HAL_SPI_RX_COMPLETE_CB_ID :
668 
 
 668 
        hspi->RxCpltCallback = HAL_SPI_RxCpltCallback;             /* Legacy weak RxCpltCallback       */
669 
      case HAL_SPI_RX_COMPLETE_CB_ID :
 669 
        break;
670 
        hspi->RxCpltCallback = HAL_SPI_RxCpltCallback;             /* Legacy weak RxCpltCallback       */
 670 
 
671 
        break;
 671 
      case HAL_SPI_TX_RX_COMPLETE_CB_ID :
672 
 
 672 
        hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback;         /* Legacy weak TxRxCpltCallback     */
673 
      case HAL_SPI_TX_RX_COMPLETE_CB_ID :
 673 
        break;
674 
        hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback;         /* Legacy weak TxRxCpltCallback     */
 674 
 
675 
        break;
 675 
      case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
676 
 
 676 
        hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback;     /* Legacy weak TxHalfCpltCallback   */
677 
      case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
 677 
        break;
678 
        hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback;     /* Legacy weak TxHalfCpltCallback   */
 678 
 
679 
        break;
 679 
      case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
680 
 
 680 
        hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback;     /* Legacy weak RxHalfCpltCallback   */
681 
      case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
 681 
        break;
682 
        hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback;     /* Legacy weak RxHalfCpltCallback   */
 682 
 
683 
        break;
 683 
      case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
684 
 
 684 
        hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
685 
      case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
 685 
        break;
686 
        hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
 686 
 
687 
        break;
 687 
      case HAL_SPI_ERROR_CB_ID :
688 
 
 688 
        hspi->ErrorCallback = HAL_SPI_ErrorCallback;               /* Legacy weak ErrorCallback        */
689 
      case HAL_SPI_ERROR_CB_ID :
 689 
        break;
690 
        hspi->ErrorCallback = HAL_SPI_ErrorCallback;               /* Legacy weak ErrorCallback        */
 690 
 
691 
        break;
 691 
      case HAL_SPI_ABORT_CB_ID :
692 
 
 692 
        hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback;       /* Legacy weak AbortCpltCallback    */
693 
      case HAL_SPI_ABORT_CB_ID :
 693 
        break;
694 
        hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback;       /* Legacy weak AbortCpltCallback    */
 694 
 
695 
        break;
 695 
      case HAL_SPI_MSPINIT_CB_ID :
696 
 
 696 
        hspi->MspInitCallback = HAL_SPI_MspInit;                   /* Legacy weak MspInit              */
697 
      case HAL_SPI_MSPINIT_CB_ID :
 697 
        break;
698 
        hspi->MspInitCallback = HAL_SPI_MspInit;                   /* Legacy weak MspInit              */
 698 
 
699 
        break;
 699 
      case HAL_SPI_MSPDEINIT_CB_ID :
700 
 
 700 
        hspi->MspDeInitCallback = HAL_SPI_MspDeInit;               /* Legacy weak MspDeInit            */
701 
      case HAL_SPI_MSPDEINIT_CB_ID :
 701 
        break;
702 
        hspi->MspDeInitCallback = HAL_SPI_MspDeInit;               /* Legacy weak MspDeInit            */
 702 
 
703 
        break;
 703 
      default :
704 
 
 704 
        /* Update the error code */
705 
      default :
 705 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
706 
        /* Update the error code */
 706 
 
707 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
 707 
        /* Return error status */
708 
 
 708 
        status =  HAL_ERROR;
709 
        /* Return error status */
 709 
        break;
710 
        status =  HAL_ERROR;
 710 
    }
711 
        break;
 711 
  }
712 
    }
 712 
  else if (HAL_SPI_STATE_RESET == hspi->State)
713 
  }
 713 
  {
714 
  else if (HAL_SPI_STATE_RESET == hspi->State)
 714 
    switch (CallbackID)
715 
  {
 715 
    {
716 
    switch (CallbackID)
 716 
      case HAL_SPI_MSPINIT_CB_ID :
717 
    {
 717 
        hspi->MspInitCallback = HAL_SPI_MspInit;                   /* Legacy weak MspInit              */
718 
      case HAL_SPI_MSPINIT_CB_ID :
 718 
        break;
719 
        hspi->MspInitCallback = HAL_SPI_MspInit;                   /* Legacy weak MspInit              */
 719 
 
720 
        break;
 720 
      case HAL_SPI_MSPDEINIT_CB_ID :
721 
 
 721 
        hspi->MspDeInitCallback = HAL_SPI_MspDeInit;               /* Legacy weak MspDeInit            */
722 
      case HAL_SPI_MSPDEINIT_CB_ID :
 722 
        break;
723 
        hspi->MspDeInitCallback = HAL_SPI_MspDeInit;               /* Legacy weak MspDeInit            */
 723 
 
724 
        break;
 724 
      default :
725 
 
 725 
        /* Update the error code */
726 
      default :
 726 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
727 
        /* Update the error code */
 727 
 
728 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
 728 
        /* Return error status */
729 
 
 729 
        status =  HAL_ERROR;
730 
        /* Return error status */
 730 
        break;
731 
        status =  HAL_ERROR;
 731 
    }
732 
        break;
 732 
  }
733 
    }
 733 
  else
734 
  }
 734 
  {
735 
  else
 735 
    /* Update the error code */
736 
  {
 736 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
737 
    /* Update the error code */
 737 
 
738 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
 738 
    /* Return error status */
739 
 
 739 
    status =  HAL_ERROR;
740 
    /* Return error status */
 740 
  }
741 
    status =  HAL_ERROR;
 741 
 
742 
  }
 742 
  /* Release Lock */
743 
 
 743 
  __HAL_UNLOCK(hspi);
744 
  /* Release Lock */
 744 
  return status;
745 
  __HAL_UNLOCK(hspi);
 745 
}
746 
  return status;
 746 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
747 
}
 747 
/**
748 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 748 
  * @}
749 
/**
 749 
  */
750 
  * @}
 750 
 
751 
  */
 751 
/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
752 
 
 752 
  *  @brief   Data transfers functions
753 
/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
 753 
  *
754 
  *  @brief   Data transfers functions
 754 
@verbatim
755 
  *
 755 
  ==============================================================================
756 
@verbatim
 756 
                      ##### IO operation functions #####
757 
  ==============================================================================
 757 
 ===============================================================================
758 
                      ##### IO operation functions #####
 758 
 [..]
759 
 ===============================================================================
 759 
    This subsection provides a set of functions allowing to manage the SPI
760 
 [..]
 760 
    data transfers.
761 
    This subsection provides a set of functions allowing to manage the SPI
 761 
 
762 
    data transfers.
 762 
    [..] The SPI supports master and slave mode :
763 
 
 763 
 
764 
    [..] The SPI supports master and slave mode :
 764 
    (#) There are two modes of transfer:
765 
 
 765 
       (++) Blocking mode: The communication is performed in polling mode.
766 
    (#) There are two modes of transfer:
 766 
            The HAL status of all data processing is returned by the same function
767 
       (++) Blocking mode: The communication is performed in polling mode.
 767 
            after finishing transfer.
768 
            The HAL status of all data processing is returned by the same function
 768 
       (++) No-Blocking mode: The communication is performed using Interrupts
769 
            after finishing transfer.
 769 
            or DMA, These APIs return the HAL status.
770 
       (++) No-Blocking mode: The communication is performed using Interrupts
 770 
            The end of the data processing will be indicated through the
771 
            or DMA, These APIs return the HAL status.
 771 
            dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
772 
            The end of the data processing will be indicated through the
 772 
            using DMA mode.
773 
            dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
 773 
            The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
774 
            using DMA mode.
 774 
            will be executed respectively at the end of the transmit or Receive process
775 
            The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
 775 
            The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
776 
            will be executed respectively at the end of the transmit or Receive process
 776 
 
777 
            The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
 777 
    (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
778 
 
 778 
        exist for 1Line (simplex) and 2Lines (full duplex) modes.
779 
    (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
 779 
 
780 
        exist for 1Line (simplex) and 2Lines (full duplex) modes.
 780 
@endverbatim
781 
 
 781 
  * @{
782 
@endverbatim
 782 
  */
783 
  * @{
 783 
 
784 
  */
 784 
/**
785 
 
 785 
  * @brief  Transmit an amount of data in blocking mode.
786 
/**
 786 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
787 
  * @brief  Transmit an amount of data in blocking mode.
 787 
  *               the configuration information for SPI module.
788 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 788 
  * @param  pData pointer to data buffer
789 
  *               the configuration information for SPI module.
 789 
  * @param  Size amount of data to be sent
790 
  * @param  pData pointer to data buffer
 790 
  * @param  Timeout Timeout duration
791 
  * @param  Size amount of data to be sent
 791 
  * @retval HAL status
792 
  * @param  Timeout Timeout duration
 792 
  */
793 
  * @retval HAL status
 793 
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
794 
  */
 794 
{
795 
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 795 
  uint32_t tickstart;
796 
{
 796 
  HAL_StatusTypeDef errorcode = HAL_OK;
797 
  uint32_t tickstart;
 797 
  uint16_t initial_TxXferCount;
798 
  HAL_StatusTypeDef errorcode = HAL_OK;
 798 
 
799 
  uint16_t initial_TxXferCount;
 799 
  /* Check Direction parameter */
800 
 
 800 
  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
801 
  /* Check Direction parameter */
 801 
 
802 
  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
 802 
  /* Process Locked */
803 
 
 803 
  __HAL_LOCK(hspi);
804 
  /* Process Locked */
 804 
 
805 
  __HAL_LOCK(hspi);
 805 
  /* Init tickstart for timeout management*/
806 
 
 806 
  tickstart = HAL_GetTick();
807 
  /* Init tickstart for timeout management*/
 807 
  initial_TxXferCount = Size;
808 
  tickstart = HAL_GetTick();
 808 
 
809 
  initial_TxXferCount = Size;
 809 
  if (hspi->State != HAL_SPI_STATE_READY)
810 
 
 810 
  {
811 
  if (hspi->State != HAL_SPI_STATE_READY)
 811 
    errorcode = HAL_BUSY;
812 
  {
 812 
    goto error;
813 
    errorcode = HAL_BUSY;
 813 
  }
814 
    goto error;
 814 
 
815 
  }
 815 
  if ((pData == NULL) || (Size == 0U))
816 
 
 816 
  {
817 
  if ((pData == NULL) || (Size == 0U))
 817 
    errorcode = HAL_ERROR;
818 
  {
 818 
    goto error;
819 
    errorcode = HAL_ERROR;
 819 
  }
820 
    goto error;
 820 
 
821 
  }
 821 
  /* Set the transaction information */
822 
 
 822 
  hspi->State       = HAL_SPI_STATE_BUSY_TX;
823 
  /* Set the transaction information */
 823 
  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
824 
  hspi->State       = HAL_SPI_STATE_BUSY_TX;
 824 
  hspi->pTxBuffPtr  = (uint8_t *)pData;
825 
  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
 825 
  hspi->TxXferSize  = Size;
826 
  hspi->pTxBuffPtr  = (uint8_t *)pData;
 826 
  hspi->TxXferCount = Size;
827 
  hspi->TxXferSize  = Size;
 827 
 
828 
  hspi->TxXferCount = Size;
 828 
  /*Init field not used in handle to zero */
829 
 
 829 
  hspi->pRxBuffPtr  = (uint8_t *)NULL;
830 
  /*Init field not used in handle to zero */
 830 
  hspi->RxXferSize  = 0U;
831 
  hspi->pRxBuffPtr  = (uint8_t *)NULL;
 831 
  hspi->RxXferCount = 0U;
832 
  hspi->RxXferSize  = 0U;
 832 
  hspi->TxISR       = NULL;
833 
  hspi->RxXferCount = 0U;
 833 
  hspi->RxISR       = NULL;
834 
  hspi->TxISR       = NULL;
 834 
 
835 
  hspi->RxISR       = NULL;
 835 
  /* Configure communication direction : 1Line */
836 
 
 836 
  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
837 
  /* Configure communication direction : 1Line */
 837 
  {
838 
  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
 838 
    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
839 
  {
 839 
    __HAL_SPI_DISABLE(hspi);
840 
    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
 840 
    SPI_1LINE_TX(hspi);
841 
    __HAL_SPI_DISABLE(hspi);
 841 
  }
842 
    SPI_1LINE_TX(hspi);
 842 
 
843 
  }
 843 
#if (USE_SPI_CRC != 0U)
844 
 
 844 
  /* Reset CRC Calculation */
845 
#if (USE_SPI_CRC != 0U)
 845 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
846 
  /* Reset CRC Calculation */
 846 
  {
847 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 847 
    SPI_RESET_CRC(hspi);
848 
  {
 848 
  }
849 
    SPI_RESET_CRC(hspi);
 849 
#endif /* USE_SPI_CRC */
850 
  }
 850 
 
851 
#endif /* USE_SPI_CRC */
 851 
  /* Check if the SPI is already enabled */
852 
 
 852 
  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
853 
  /* Check if the SPI is already enabled */
 853 
  {
854 
  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
 854 
    /* Enable SPI peripheral */
855 
  {
 855 
    __HAL_SPI_ENABLE(hspi);
856 
    /* Enable SPI peripheral */
 856 
  }
857 
    __HAL_SPI_ENABLE(hspi);
 857 
 
858 
  }
 858 
  /* Transmit data in 16 Bit mode */
859 
 
 859 
  if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
860 
  /* Transmit data in 16 Bit mode */
 860 
  {
861 
  if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
 861 
    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
862 
  {
 862 
    {
863 
    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
 863 
      hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
864 
    {
 864 
      hspi->pTxBuffPtr += sizeof(uint16_t);
865 
      hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
 865 
      hspi->TxXferCount--;
866 
      hspi->pTxBuffPtr += sizeof(uint16_t);
 866 
    }
867 
      hspi->TxXferCount--;
 867 
    /* Transmit data in 16 Bit mode */
868 
    }
 868 
    while (hspi->TxXferCount > 0U)
869 
    /* Transmit data in 16 Bit mode */
 869 
    {
870 
    while (hspi->TxXferCount > 0U)
 870 
      /* Wait until TXE flag is set to send data */
871 
    {
 871 
      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
872 
      /* Wait until TXE flag is set to send data */
 872 
      {
873 
      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
 873 
        hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
874 
      {
 874 
        hspi->pTxBuffPtr += sizeof(uint16_t);
875 
        hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
 875 
        hspi->TxXferCount--;
876 
        hspi->pTxBuffPtr += sizeof(uint16_t);
 876 
      }
877 
        hspi->TxXferCount--;
 877 
      else
878 
      }
 878 
      {
879 
      else
 879 
        /* Timeout management */
880 
      {
 880 
        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
881 
        /* Timeout management */
 881 
        {
882 
        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
 882 
          errorcode = HAL_TIMEOUT;
883 
        {
 883 
          hspi->State = HAL_SPI_STATE_READY;
884 
          errorcode = HAL_TIMEOUT;
 884 
          goto error;
885 
          goto error;
 885 
        }
886 
        }
 886 
      }
887 
      }
 887 
    }
888 
    }
 888 
  }
889 
  }
 889 
  /* Transmit data in 8 Bit mode */
890 
  /* Transmit data in 8 Bit mode */
 890 
  else
891 
  else
 891 
  {
892 
  {
 892 
    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
893 
    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
 893 
    {
894 
    {
 894 
      *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
895 
      *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
 895 
      hspi->pTxBuffPtr += sizeof(uint8_t);
896 
      hspi->pTxBuffPtr += sizeof(uint8_t);
 896 
      hspi->TxXferCount--;
897 
      hspi->TxXferCount--;
 897 
    }
898 
    }
 898 
    while (hspi->TxXferCount > 0U)
899 
    while (hspi->TxXferCount > 0U)
 899 
    {
900 
    {
 900 
      /* Wait until TXE flag is set to send data */
901 
      /* Wait until TXE flag is set to send data */
 901 
      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
902 
      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
 902 
      {
903 
      {
 903 
        *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
904 
        *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
 904 
        hspi->pTxBuffPtr += sizeof(uint8_t);
905 
        hspi->pTxBuffPtr += sizeof(uint8_t);
 905 
        hspi->TxXferCount--;
906 
        hspi->TxXferCount--;
 906 
      }
907 
      }
 907 
      else
908 
      else
 908 
      {
909 
      {
 909 
        /* Timeout management */
910 
        /* Timeout management */
 910 
        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
911 
        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
 911 
        {
912 
        {
 912 
          errorcode = HAL_TIMEOUT;
913 
          errorcode = HAL_TIMEOUT;
 913 
          hspi->State = HAL_SPI_STATE_READY;
914 
          goto error;
 914 
          goto error;
915 
        }
 915 
        }
916 
      }
 916 
      }
917 
    }
 917 
    }
918 
  }
 918 
  }
919 
#if (USE_SPI_CRC != 0U)
 919 
#if (USE_SPI_CRC != 0U)
920 
  /* Enable CRC Transmission */
 920 
  /* Enable CRC Transmission */
921 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 921 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
922 
  {
 922 
  {
923 
    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
 923 
    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
924 
  }
 924 
  }
925 
#endif /* USE_SPI_CRC */
 925 
#endif /* USE_SPI_CRC */
926 
 
 926 
 
927 
  /* Check the end of the transaction */
 927 
  /* Check the end of the transaction */
928 
  if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
 928 
  if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
929 
  {
 929 
  {
930 
    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
 930 
    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
931 
  }
 931 
  }
932 
 
 932 
 
933 
  /* Clear overrun flag in 2 Lines communication mode because received is not read */
 933 
  /* Clear overrun flag in 2 Lines communication mode because received is not read */
934 
  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
 934 
  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
935 
  {
 935 
  {
936 
    __HAL_SPI_CLEAR_OVRFLAG(hspi);
 936 
    __HAL_SPI_CLEAR_OVRFLAG(hspi);
937 
  }
 937 
  }
938 
 
 938 
 
939 
  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
 939 
  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
940 
  {
 940 
  {
941 
    errorcode = HAL_ERROR;
 941 
    errorcode = HAL_ERROR;
942 
  }
 942 
  }
943 
 
 943 
  else
944 
error:
 944 
  {
945 
  hspi->State = HAL_SPI_STATE_READY;
 945 
    hspi->State = HAL_SPI_STATE_READY;
946 
  /* Process Unlocked */
 946 
  }
947 
  __HAL_UNLOCK(hspi);
 947 
 
948 
  return errorcode;
 948 
error:
949 
}
 949 
  /* Process Unlocked */
950 
 
 950 
  __HAL_UNLOCK(hspi);
951 
/**
 951 
  return errorcode;
952 
  * @brief  Receive an amount of data in blocking mode.
 952 
}
953 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 953 
 
954 
  *               the configuration information for SPI module.
 954 
/**
955 
  * @param  pData pointer to data buffer
 955 
  * @brief  Receive an amount of data in blocking mode.
956 
  * @param  Size amount of data to be received
 956 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
957 
  * @param  Timeout Timeout duration
 957 
  *               the configuration information for SPI module.
958 
  * @retval HAL status
 958 
  * @param  pData pointer to data buffer
959 
  */
 959 
  * @param  Size amount of data to be received
960 
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 960 
  * @param  Timeout Timeout duration
961 
{
 961 
  * @retval HAL status
962 
#if (USE_SPI_CRC != 0U)
 962 
  */
963 
  __IO uint32_t tmpreg = 0U;
 963 
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
964 
#endif /* USE_SPI_CRC */
 964 
{
965 
  uint32_t tickstart;
 965 
#if (USE_SPI_CRC != 0U)
966 
  HAL_StatusTypeDef errorcode = HAL_OK;
 966 
  __IO uint32_t tmpreg = 0U;
967 
 
 967 
#endif /* USE_SPI_CRC */
968 
  if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
 968 
  uint32_t tickstart;
969 
  {
 969 
  HAL_StatusTypeDef errorcode = HAL_OK;
970 
    hspi->State = HAL_SPI_STATE_BUSY_RX;
 970 
 
971 
    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
 971 
  if (hspi->State != HAL_SPI_STATE_READY)
972 
    return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
 972 
  {
973 
  }
 973 
    errorcode = HAL_BUSY;
974 
 
 974 
    goto error;
975 
  /* Process Locked */
 975 
  }
976 
  __HAL_LOCK(hspi);
 976 
 
977 
 
 977 
  if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
978 
  /* Init tickstart for timeout management*/
 978 
  {
979 
  tickstart = HAL_GetTick();
 979 
    hspi->State = HAL_SPI_STATE_BUSY_RX;
980 
 
 980 
    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
981 
  if (hspi->State != HAL_SPI_STATE_READY)
 981 
    return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
982 
  {
 982 
  }
983 
    errorcode = HAL_BUSY;
 983 
 
984 
    goto error;
 984 
  /* Process Locked */
985 
  }
 985 
  __HAL_LOCK(hspi);
986 
 
 986 
 
987 
  if ((pData == NULL) || (Size == 0U))
 987 
  /* Init tickstart for timeout management*/
988 
  {
 988 
  tickstart = HAL_GetTick();
989 
    errorcode = HAL_ERROR;
 989 
 
990 
    goto error;
 990 
  if ((pData == NULL) || (Size == 0U))
991 
  }
 991 
  {
992 
 
 992 
    errorcode = HAL_ERROR;
993 
  /* Set the transaction information */
 993 
    goto error;
994 
  hspi->State       = HAL_SPI_STATE_BUSY_RX;
 994 
  }
995 
  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
 995 
 
996 
  hspi->pRxBuffPtr  = (uint8_t *)pData;
 996 
  /* Set the transaction information */
997 
  hspi->RxXferSize  = Size;
 997 
  hspi->State       = HAL_SPI_STATE_BUSY_RX;
998 
  hspi->RxXferCount = Size;
 998 
  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
999 
 
 999 
  hspi->pRxBuffPtr  = (uint8_t *)pData;
1000 
  /*Init field not used in handle to zero */
 1000 
  hspi->RxXferSize  = Size;
1001 
  hspi->pTxBuffPtr  = (uint8_t *)NULL;
 1001 
  hspi->RxXferCount = Size;
1002 
  hspi->TxXferSize  = 0U;
 1002 
 
1003 
  hspi->TxXferCount = 0U;
 1003 
  /*Init field not used in handle to zero */
1004 
  hspi->RxISR       = NULL;
 1004 
  hspi->pTxBuffPtr  = (uint8_t *)NULL;
1005 
  hspi->TxISR       = NULL;
 1005 
  hspi->TxXferSize  = 0U;
1006 
 
 1006 
  hspi->TxXferCount = 0U;
1007 
#if (USE_SPI_CRC != 0U)
 1007 
  hspi->RxISR       = NULL;
1008 
  /* Reset CRC Calculation */
 1008 
  hspi->TxISR       = NULL;
1009 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 1009 
 
1010 
  {
 1010 
#if (USE_SPI_CRC != 0U)
1011 
    SPI_RESET_CRC(hspi);
 1011 
  /* Reset CRC Calculation */
1012 
    /* this is done to handle the CRCNEXT before the latest data */
 1012 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1013 
    hspi->RxXferCount--;
 1013 
  {
1014 
  }
 1014 
    SPI_RESET_CRC(hspi);
1015 
#endif /* USE_SPI_CRC */
 1015 
    /* this is done to handle the CRCNEXT before the latest data */
1016 
 
 1016 
    hspi->RxXferCount--;
1017 
  /* Configure communication direction: 1Line */
 1017 
  }
1018 
  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
 1018 
#endif /* USE_SPI_CRC */
1019 
  {
 1019 
 
1020 
    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
 1020 
  /* Configure communication direction: 1Line */
1021 
    __HAL_SPI_DISABLE(hspi);
 1021 
  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1022 
    SPI_1LINE_RX(hspi);
 1022 
  {
1023 
  }
 1023 
    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1024 
 
 1024 
    __HAL_SPI_DISABLE(hspi);
1025 
  /* Check if the SPI is already enabled */
 1025 
    SPI_1LINE_RX(hspi);
1026 
  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
 1026 
  }
1027 
  {
 1027 
 
1028 
    /* Enable SPI peripheral */
 1028 
  /* Check if the SPI is already enabled */
1029 
    __HAL_SPI_ENABLE(hspi);
 1029 
  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1030 
  }
 1030 
  {
1031 
 
 1031 
    /* Enable SPI peripheral */
1032 
  /* Receive data in 8 Bit mode */
 1032 
    __HAL_SPI_ENABLE(hspi);
1033 
  if (hspi->Init.DataSize == SPI_DATASIZE_8BIT)
 1033 
  }
1034 
  {
 1034 
 
1035 
    /* Transfer loop */
 1035 
  /* Receive data in 8 Bit mode */
1036 
    while (hspi->RxXferCount > 0U)
 1036 
  if (hspi->Init.DataSize == SPI_DATASIZE_8BIT)
1037 
    {
 1037 
  {
1038 
      /* Check the RXNE flag */
 1038 
    /* Transfer loop */
1039 
      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
 1039 
    while (hspi->RxXferCount > 0U)
1040 
      {
 1040 
    {
1041 
        /* read the received data */
 1041 
      /* Check the RXNE flag */
1042 
        (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
 1042 
      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
1043 
        hspi->pRxBuffPtr += sizeof(uint8_t);
 1043 
      {
1044 
        hspi->RxXferCount--;
 1044 
        /* read the received data */
1045 
      }
 1045 
        (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1046 
      else
 1046 
        hspi->pRxBuffPtr += sizeof(uint8_t);
1047 
      {
 1047 
        hspi->RxXferCount--;
1048 
        /* Timeout management */
 1048 
      }
1049 
        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
 1049 
      else
1050 
        {
 1050 
      {
1051 
          errorcode = HAL_TIMEOUT;
 1051 
        /* Timeout management */
1052 
          goto error;
 1052 
        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1053 
        }
 1053 
        {
1054 
      }
 1054 
          errorcode = HAL_TIMEOUT;
1055 
    }
 1055 
          hspi->State = HAL_SPI_STATE_READY;
1056 
  }
 1056 
          goto error;
1057 
  else
 1057 
        }
1058 
  {
 1058 
      }
1059 
    /* Transfer loop */
 1059 
    }
1060 
    while (hspi->RxXferCount > 0U)
 1060 
  }
1061 
    {
 1061 
  else
1062 
      /* Check the RXNE flag */
 1062 
  {
1063 
      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
 1063 
    /* Transfer loop */
1064 
      {
 1064 
    while (hspi->RxXferCount > 0U)
1065 
        *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
 1065 
    {
1066 
        hspi->pRxBuffPtr += sizeof(uint16_t);
 1066 
      /* Check the RXNE flag */
1067 
        hspi->RxXferCount--;
 1067 
      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
1068 
      }
 1068 
      {
1069 
      else
 1069 
        *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1070 
      {
 1070 
        hspi->pRxBuffPtr += sizeof(uint16_t);
1071 
        /* Timeout management */
 1071 
        hspi->RxXferCount--;
1072 
        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
 1072 
      }
1073 
        {
 1073 
      else
1074 
          errorcode = HAL_TIMEOUT;
 1074 
      {
1075 
          goto error;
 1075 
        /* Timeout management */
1076 
        }
 1076 
        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1077 
      }
 1077 
        {
1078 
    }
 1078 
          errorcode = HAL_TIMEOUT;
1079 
  }
 1079 
          hspi->State = HAL_SPI_STATE_READY;
1080 
 
 1080 
          goto error;
1081 
#if (USE_SPI_CRC != 0U)
 1081 
        }
1082 
  /* Handle the CRC Transmission */
 1082 
      }
1083 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 1083 
    }
1084 
  {
 1084 
  }
1085 
    /* freeze the CRC before the latest data */
 1085 
 
1086 
    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
 1086 
#if (USE_SPI_CRC != 0U)
1087 
 
 1087 
  /* Handle the CRC Transmission */
1088 
    /* Check if CRCNEXT is well reseted by hardware */
 1088 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1089 
    if (READ_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT))
 1089 
  {
1090 
    {
 1090 
    /* freeze the CRC before the latest data */
1091 
      /* Workaround to force CRCNEXT bit to zero in case of CRCNEXT is not reset automatically by hardware */
 1091 
    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1092 
      CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
 1092 
 
1093 
    }
 1093 
    /* Check if CRCNEXT is well reset by hardware */
1094 
    /* Read the latest data */
 1094 
    if (READ_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT))
1095 
    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
 1095 
    {
1096 
    {
 1096 
      /* Workaround to force CRCNEXT bit to zero in case of CRCNEXT is not reset automatically by hardware */
1097 
      /* the latest data has not been received */
 1097 
      CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1098 
      errorcode = HAL_TIMEOUT;
 1098 
    }
1099 
      goto error;
 1099 
    /* Read the latest data */
1100 
    }
 1100 
    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1101 
 
 1101 
    {
1102 
    /* Receive last data in 16 Bit mode */
 1102 
      /* the latest data has not been received */
1103 
    if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
 1103 
      errorcode = HAL_TIMEOUT;
1104 
    {
 1104 
      goto error;
1105 
      *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
 1105 
    }
1106 
    }
 1106 
 
1107 
    /* Receive last data in 8 Bit mode */
 1107 
    /* Receive last data in 16 Bit mode */
1108 
    else
 1108 
    if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
1109 
    {
 1109 
    {
1110 
      (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
 1110 
      *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1111 
    }
 1111 
    }
1112 
 
 1112 
    /* Receive last data in 8 Bit mode */
1113 
    /* Wait the CRC data */
 1113 
    else
1114 
    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
 1114 
    {
1115 
    {
 1115 
      (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1116 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
 1116 
    }
1117 
      errorcode = HAL_TIMEOUT;
 1117 
 
1118 
      goto error;
 1118 
    /* Wait the CRC data */
1119 
    }
 1119 
    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1120 
 
 1120 
    {
1121 
    /* Read CRC to Flush DR and RXNE flag */
 1121 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1122 
    tmpreg = READ_REG(hspi->Instance->DR);
 1122 
      errorcode = HAL_TIMEOUT;
1123 
    /* To avoid GCC warning */
 1123 
      goto error;
1124 
    UNUSED(tmpreg);
 1124 
    }
1125 
  }
 1125 
 
1126 
#endif /* USE_SPI_CRC */
 1126 
    /* Read CRC to Flush DR and RXNE flag */
1127 
 
 1127 
    tmpreg = READ_REG(hspi->Instance->DR);
1128 
  /* Check the end of the transaction */
 1128 
    /* To avoid GCC warning */
1129 
  if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
 1129 
    UNUSED(tmpreg);
1130 
  {
 1130 
  }
1131 
    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
 1131 
#endif /* USE_SPI_CRC */
1132 
  }
 1132 
 
1133 
 
 1133 
  /* Check the end of the transaction */
1134 
#if (USE_SPI_CRC != 0U)
 1134 
  if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
1135 
  /* Check if CRC error occurred */
 1135 
  {
1136 
  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
 1136 
    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
1137 
  {
 1137 
  }
1138 
    /* Check if CRC error is valid or not (workaround to be applied or not) */
 1138 
 
1139 
    if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
 1139 
#if (USE_SPI_CRC != 0U)
1140 
    {
 1140 
  /* Check if CRC error occurred */
1141 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
 1141 
  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
1142 
 
 1142 
  {
1143 
      /* Reset CRC Calculation */
 1143 
    /* Check if CRC error is valid or not (workaround to be applied or not) */
1144 
      SPI_RESET_CRC(hspi);
 1144 
    if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
1145 
    }
 1145 
    {
1146 
    else
 1146 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1147 
    {
 1147 
 
1148 
      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
 1148 
      /* Reset CRC Calculation */
1149 
    }
 1149 
      SPI_RESET_CRC(hspi);
1150 
  }
 1150 
    }
1151 
#endif /* USE_SPI_CRC */
 1151 
    else
1152 
 
 1152 
    {
1153 
  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
 1153 
      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
1154 
  {
 1154 
    }
1155 
    errorcode = HAL_ERROR;
 1155 
  }
1156 
  }
 1156 
#endif /* USE_SPI_CRC */
1157 
 
 1157 
 
1158 
error :
 1158 
  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
1159 
  hspi->State = HAL_SPI_STATE_READY;
 1159 
  {
1160 
  __HAL_UNLOCK(hspi);
 1160 
    errorcode = HAL_ERROR;
1161 
  return errorcode;
 1161 
  }
1162 
}
 1162 
  else
1163 
 
 1163 
  {
1164 
/**
 1164 
    hspi->State = HAL_SPI_STATE_READY;
1165 
  * @brief  Transmit and Receive an amount of data in blocking mode.
 1165 
  }
1166 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 1166 
 
1167 
  *               the configuration information for SPI module.
 1167 
error :
1168 
  * @param  pTxData pointer to transmission data buffer
 1168 
  __HAL_UNLOCK(hspi);
1169 
  * @param  pRxData pointer to reception data buffer
 1169 
  return errorcode;
1170 
  * @param  Size amount of data to be sent and received
 1170 
}
1171 
  * @param  Timeout Timeout duration
 1171 
 
1172 
  * @retval HAL status
 1172 
/**
1173 
  */
 1173 
  * @brief  Transmit and Receive an amount of data in blocking mode.
1174 
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
 1174 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
1175 
                                          uint32_t Timeout)
 1175 
  *               the configuration information for SPI module.
1176 
{
 1176 
  * @param  pTxData pointer to transmission data buffer
1177 
  uint16_t             initial_TxXferCount;
 1177 
  * @param  pRxData pointer to reception data buffer
1178 
  uint32_t             tmp_mode;
 1178 
  * @param  Size amount of data to be sent and received
1179 
  HAL_SPI_StateTypeDef tmp_state;
 1179 
  * @param  Timeout Timeout duration
1180 
  uint32_t             tickstart;
 1180 
  * @retval HAL status
1181 
#if (USE_SPI_CRC != 0U)
 1181 
  */
1182 
  __IO uint32_t tmpreg = 0U;
 1182 
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
1183 
#endif /* USE_SPI_CRC */
 1183 
                                          uint32_t Timeout)
1184 
 
 1184 
{
1185 
  /* Variable used to alternate Rx and Tx during transfer */
 1185 
  uint16_t             initial_TxXferCount;
1186 
  uint32_t             txallowed = 1U;
 1186 
  uint32_t             tmp_mode;
1187 
  HAL_StatusTypeDef    errorcode = HAL_OK;
 1187 
  HAL_SPI_StateTypeDef tmp_state;
1188 
 
 1188 
  uint32_t             tickstart;
1189 
  /* Check Direction parameter */
 1189 
#if (USE_SPI_CRC != 0U)
1190 
  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
 1190 
  __IO uint32_t tmpreg = 0U;
1191 
 
 1191 
#endif /* USE_SPI_CRC */
1192 
  /* Process Locked */
 1192 
 
1193 
  __HAL_LOCK(hspi);
 1193 
  /* Variable used to alternate Rx and Tx during transfer */
1194 
 
 1194 
  uint32_t             txallowed = 1U;
1195 
  /* Init tickstart for timeout management*/
 1195 
  HAL_StatusTypeDef    errorcode = HAL_OK;
1196 
  tickstart = HAL_GetTick();
 1196 
 
1197 
 
 1197 
  /* Check Direction parameter */
1198 
  /* Init temporary variables */
 1198 
  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1199 
  tmp_state           = hspi->State;
 1199 
 
1200 
  tmp_mode            = hspi->Init.Mode;
 1200 
  /* Process Locked */
1201 
  initial_TxXferCount = Size;
 1201 
  __HAL_LOCK(hspi);
1202 
 
 1202 
 
1203 
  if (!((tmp_state == HAL_SPI_STATE_READY) || \
 1203 
  /* Init tickstart for timeout management*/
1204 
        ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
 1204 
  tickstart = HAL_GetTick();
1205 
  {
 1205 
 
1206 
    errorcode = HAL_BUSY;
 1206 
  /* Init temporary variables */
1207 
    goto error;
 1207 
  tmp_state           = hspi->State;
1208 
  }
 1208 
  tmp_mode            = hspi->Init.Mode;
1209 
 
 1209 
  initial_TxXferCount = Size;
1210 
  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
 1210 
 
1211 
  {
 1211 
  if (!((tmp_state == HAL_SPI_STATE_READY) || \
1212 
    errorcode = HAL_ERROR;
 1212 
        ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
1213 
    goto error;
 1213 
  {
1214 
  }
 1214 
    errorcode = HAL_BUSY;
1215 
 
 1215 
    goto error;
1216 
  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
 1216 
  }
1217 
  if (hspi->State != HAL_SPI_STATE_BUSY_RX)
 1217 
 
1218 
  {
 1218 
  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1219 
    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
 1219 
  {
1220 
  }
 1220 
    errorcode = HAL_ERROR;
1221 
 
 1221 
    goto error;
1222 
  /* Set the transaction information */
 1222 
  }
1223 
  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
 1223 
 
1224 
  hspi->pRxBuffPtr  = (uint8_t *)pRxData;
 1224 
  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1225 
  hspi->RxXferCount = Size;
 1225 
  if (hspi->State != HAL_SPI_STATE_BUSY_RX)
1226 
  hspi->RxXferSize  = Size;
 1226 
  {
1227 
  hspi->pTxBuffPtr  = (uint8_t *)pTxData;
 1227 
    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1228 
  hspi->TxXferCount = Size;
 1228 
  }
1229 
  hspi->TxXferSize  = Size;
 1229 
 
1230 
 
 1230 
  /* Set the transaction information */
1231 
  /*Init field not used in handle to zero */
 1231 
  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
1232 
  hspi->RxISR       = NULL;
 1232 
  hspi->pRxBuffPtr  = (uint8_t *)pRxData;
1233 
  hspi->TxISR       = NULL;
 1233 
  hspi->RxXferCount = Size;
1234 
 
 1234 
  hspi->RxXferSize  = Size;
1235 
#if (USE_SPI_CRC != 0U)
 1235 
  hspi->pTxBuffPtr  = (uint8_t *)pTxData;
1236 
  /* Reset CRC Calculation */
 1236 
  hspi->TxXferCount = Size;
1237 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 1237 
  hspi->TxXferSize  = Size;
1238 
  {
 1238 
 
1239 
    SPI_RESET_CRC(hspi);
 1239 
  /*Init field not used in handle to zero */
1240 
  }
 1240 
  hspi->RxISR       = NULL;
1241 
#endif /* USE_SPI_CRC */
 1241 
  hspi->TxISR       = NULL;
1242 
 
 1242 
 
1243 
  /* Check if the SPI is already enabled */
 1243 
#if (USE_SPI_CRC != 0U)
1244 
  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
 1244 
  /* Reset CRC Calculation */
1245 
  {
 1245 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1246 
    /* Enable SPI peripheral */
 1246 
  {
1247 
    __HAL_SPI_ENABLE(hspi);
 1247 
    SPI_RESET_CRC(hspi);
1248 
  }
 1248 
  }
1249 
 
 1249 
#endif /* USE_SPI_CRC */
1250 
  /* Transmit and Receive data in 16 Bit mode */
 1250 
 
1251 
  if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
 1251 
  /* Check if the SPI is already enabled */
1252 
  {
 1252 
  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1253 
    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
 1253 
  {
1254 
    {
 1254 
    /* Enable SPI peripheral */
1255 
      hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
 1255 
    __HAL_SPI_ENABLE(hspi);
1256 
      hspi->pTxBuffPtr += sizeof(uint16_t);
 1256 
  }
1257 
      hspi->TxXferCount--;
 1257 
 
1258 
    }
 1258 
  /* Transmit and Receive data in 16 Bit mode */
1259 
    while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
 1259 
  if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
1260 
    {
 1260 
  {
1261 
      /* Check TXE flag */
 1261 
    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
1262 
      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
 1262 
    {
1263 
      {
 1263 
      hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1264 
        hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
 1264 
      hspi->pTxBuffPtr += sizeof(uint16_t);
1265 
        hspi->pTxBuffPtr += sizeof(uint16_t);
 1265 
      hspi->TxXferCount--;
1266 
        hspi->TxXferCount--;
 1266 
    }
1267 
        /* Next Data is a reception (Rx). Tx not allowed */
 1267 
    while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
1268 
        txallowed = 0U;
 1268 
    {
1269 
 
 1269 
      /* Check TXE flag */
1270 
#if (USE_SPI_CRC != 0U)
 1270 
      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
1271 
        /* Enable CRC Transmission */
 1271 
      {
1272 
        if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
 1272 
        hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1273 
        {
 1273 
        hspi->pTxBuffPtr += sizeof(uint16_t);
1274 
          SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
 1274 
        hspi->TxXferCount--;
1275 
        }
 1275 
        /* Next Data is a reception (Rx). Tx not allowed */
1276 
#endif /* USE_SPI_CRC */
 1276 
        txallowed = 0U;
1277 
      }
 1277 
 
1278 
 
 1278 
#if (USE_SPI_CRC != 0U)
1279 
      /* Check RXNE flag */
 1279 
        /* Enable CRC Transmission */
1280 
      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
 1280 
        if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
1281 
      {
 1281 
        {
1282 
        *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
 1282 
          SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1283 
        hspi->pRxBuffPtr += sizeof(uint16_t);
 1283 
        }
1284 
        hspi->RxXferCount--;
 1284 
#endif /* USE_SPI_CRC */
1285 
        /* Next Data is a Transmission (Tx). Tx is allowed */
 1285 
      }
1286 
        txallowed = 1U;
 1286 
 
1287 
      }
 1287 
      /* Check RXNE flag */
1288 
      if (((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY))
 1288 
      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
1289 
      {
 1289 
      {
1290 
        errorcode = HAL_TIMEOUT;
 1290 
        *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1291 
        goto error;
 1291 
        hspi->pRxBuffPtr += sizeof(uint16_t);
1292 
      }
 1292 
        hspi->RxXferCount--;
1293 
    }
 1293 
        /* Next Data is a Transmission (Tx). Tx is allowed */
1294 
  }
 1294 
        txallowed = 1U;
1295 
  /* Transmit and Receive data in 8 Bit mode */
 1295 
      }
1296 
  else
 1296 
      if (((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY))
1297 
  {
 1297 
      {
1298 
    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
 1298 
        errorcode = HAL_TIMEOUT;
1299 
    {
 1299 
        hspi->State = HAL_SPI_STATE_READY;
1300 
      *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
 1300 
        goto error;
1301 
      hspi->pTxBuffPtr += sizeof(uint8_t);
 1301 
      }
1302 
      hspi->TxXferCount--;
 1302 
    }
1303 
    }
 1303 
  }
1304 
    while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
 1304 
  /* Transmit and Receive data in 8 Bit mode */
1305 
    {
 1305 
  else
1306 
      /* Check TXE flag */
 1306 
  {
1307 
      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
 1307 
    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
1308 
      {
 1308 
    {
1309 
        *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
 1309 
      *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
1310 
        hspi->pTxBuffPtr++;
 1310 
      hspi->pTxBuffPtr += sizeof(uint8_t);
1311 
        hspi->TxXferCount--;
 1311 
      hspi->TxXferCount--;
1312 
        /* Next Data is a reception (Rx). Tx not allowed */
 1312 
    }
1313 
        txallowed = 0U;
 1313 
    while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
1314 
 
 1314 
    {
1315 
#if (USE_SPI_CRC != 0U)
 1315 
      /* Check TXE flag */
1316 
        /* Enable CRC Transmission */
 1316 
      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
1317 
        if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
 1317 
      {
1318 
        {
 1318 
        *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
1319 
          SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
 1319 
        hspi->pTxBuffPtr++;
1320 
        }
 1320 
        hspi->TxXferCount--;
1321 
#endif /* USE_SPI_CRC */
 1321 
        /* Next Data is a reception (Rx). Tx not allowed */
1322 
      }
 1322 
        txallowed = 0U;
1323 
 
 1323 
 
1324 
      /* Wait until RXNE flag is reset */
 1324 
#if (USE_SPI_CRC != 0U)
1325 
      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
 1325 
        /* Enable CRC Transmission */
1326 
      {
 1326 
        if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
1327 
        (*(uint8_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
 1327 
        {
1328 
        hspi->pRxBuffPtr++;
 1328 
          SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1329 
        hspi->RxXferCount--;
 1329 
        }
1330 
        /* Next Data is a Transmission (Tx). Tx is allowed */
 1330 
#endif /* USE_SPI_CRC */
1331 
        txallowed = 1U;
 1331 
      }
1332 
      }
 1332 
 
1333 
      if ((((HAL_GetTick() - tickstart) >=  Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
 1333 
      /* Wait until RXNE flag is reset */
1334 
      {
 1334 
      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
1335 
        errorcode = HAL_TIMEOUT;
 1335 
      {
1336 
        goto error;
 1336 
        (*(uint8_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
1337 
      }
 1337 
        hspi->pRxBuffPtr++;
1338 
    }
 1338 
        hspi->RxXferCount--;
1339 
  }
 1339 
        /* Next Data is a Transmission (Tx). Tx is allowed */
1340 
 
 1340 
        txallowed = 1U;
1341 
#if (USE_SPI_CRC != 0U)
 1341 
      }
1342 
  /* Read CRC from DR to close CRC calculation process */
 1342 
      if ((((HAL_GetTick() - tickstart) >=  Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
1343 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 1343 
      {
1344 
  {
 1344 
        errorcode = HAL_TIMEOUT;
1345 
    /* Wait until TXE flag */
 1345 
        hspi->State = HAL_SPI_STATE_READY;
1346 
    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
 1346 
        goto error;
1347 
    {
 1347 
      }
1348 
      /* Error on the CRC reception */
 1348 
    }
1349 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
 1349 
  }
1350 
      errorcode = HAL_TIMEOUT;
 1350 
 
1351 
      goto error;
 1351 
#if (USE_SPI_CRC != 0U)
1352 
    }
 1352 
  /* Read CRC from DR to close CRC calculation process */
1353 
    /* Read CRC */
 1353 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1354 
    tmpreg = READ_REG(hspi->Instance->DR);
 1354 
  {
1355 
    /* To avoid GCC warning */
 1355 
    /* Wait until TXE flag */
1356 
    UNUSED(tmpreg);
 1356 
    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1357 
  }
 1357 
    {
1358 
 
 1358 
      /* Error on the CRC reception */
1359 
  /* Check if CRC error occurred */
 1359 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1360 
  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
 1360 
      errorcode = HAL_TIMEOUT;
1361 
  {
 1361 
      goto error;
1362 
    /* Check if CRC error is valid or not (workaround to be applied or not) */
 1362 
    }
1363 
    if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
 1363 
    /* Read CRC */
1364 
    {
 1364 
    tmpreg = READ_REG(hspi->Instance->DR);
1365 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
 1365 
    /* To avoid GCC warning */
1366 
 
 1366 
    UNUSED(tmpreg);
1367 
      /* Reset CRC Calculation */
 1367 
  }
1368 
      SPI_RESET_CRC(hspi);
 1368 
 
1369 
 
 1369 
  /* Check if CRC error occurred */
1370 
      errorcode = HAL_ERROR;
 1370 
  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
1371 
    }
 1371 
  {
1372 
    else
 1372 
    /* Check if CRC error is valid or not (workaround to be applied or not) */
1373 
    {
 1373 
    if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
1374 
      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
 1374 
    {
1375 
    }
 1375 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1376 
  }
 1376 
 
1377 
#endif /* USE_SPI_CRC */
 1377 
      /* Reset CRC Calculation */
1378 
 
 1378 
      SPI_RESET_CRC(hspi);
1379 
  /* Check the end of the transaction */
 1379 
 
1380 
  if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
 1380 
      errorcode = HAL_ERROR;
1381 
  {
 1381 
    }
1382 
    errorcode = HAL_ERROR;
 1382 
    else
1383 
    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
 1383 
    {
1384 
    goto error;
 1384 
      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
1385 
  }
 1385 
    }
1386 
 
 1386 
  }
1387 
  /* Clear overrun flag in 2 Lines communication mode because received is not read */
 1387 
#endif /* USE_SPI_CRC */
1388 
  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
 1388 
 
1389 
  {
 1389 
  /* Check the end of the transaction */
1390 
    __HAL_SPI_CLEAR_OVRFLAG(hspi);
 1390 
  if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
1391 
  }
 1391 
  {
1392 
 
 1392 
    errorcode = HAL_ERROR;
1393 
error :
 1393 
    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
1394 
  hspi->State = HAL_SPI_STATE_READY;
 1394 
    goto error;
1395 
  __HAL_UNLOCK(hspi);
 1395 
  }
1396 
  return errorcode;
 1396 
 
1397 
}
 1397 
  /* Clear overrun flag in 2 Lines communication mode because received is not read */
1398 
 
 1398 
  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
1399 
/**
 1399 
  {
1400 
  * @brief  Transmit an amount of data in non-blocking mode with Interrupt.
 1400 
    __HAL_SPI_CLEAR_OVRFLAG(hspi);
1401 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 1401 
  }
1402 
  *               the configuration information for SPI module.
 1402 
 
1403 
  * @param  pData pointer to data buffer
 1403 
  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
1404 
  * @param  Size amount of data to be sent
 1404 
  {
1405 
  * @retval HAL status
 1405 
    errorcode = HAL_ERROR;
1406 
  */
 1406 
  }
1407 
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
 1407 
  else
1408 
{
 1408 
  {
1409 
  HAL_StatusTypeDef errorcode = HAL_OK;
 1409 
    hspi->State = HAL_SPI_STATE_READY;
1410 
 
 1410 
  }
1411 
  /* Check Direction parameter */
 1411 
 
1412 
  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
 1412 
error :
1413 
 
 1413 
  __HAL_UNLOCK(hspi);
1414 
  /* Process Locked */
 1414 
  return errorcode;
1415 
  __HAL_LOCK(hspi);
 1415 
}
1416 
 
 1416 
 
1417 
  if ((pData == NULL) || (Size == 0U))
 1417 
/**
1418 
  {
 1418 
  * @brief  Transmit an amount of data in non-blocking mode with Interrupt.
1419 
    errorcode = HAL_ERROR;
 1419 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
1420 
    goto error;
 1420 
  *               the configuration information for SPI module.
1421 
  }
 1421 
  * @param  pData pointer to data buffer
1422 
 
 1422 
  * @param  Size amount of data to be sent
1423 
  if (hspi->State != HAL_SPI_STATE_READY)
 1423 
  * @retval HAL status
1424 
  {
 1424 
  */
1425 
    errorcode = HAL_BUSY;
 1425 
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1426 
    goto error;
 1426 
{
1427 
  }
 1427 
  HAL_StatusTypeDef errorcode = HAL_OK;
1428 
 
 1428 
 
1429 
  /* Set the transaction information */
 1429 
  /* Check Direction parameter */
1430 
  hspi->State       = HAL_SPI_STATE_BUSY_TX;
 1430 
  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
1431 
  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
 1431 
 
1432 
  hspi->pTxBuffPtr  = (uint8_t *)pData;
 1432 
  /* Process Locked */
1433 
  hspi->TxXferSize  = Size;
 1433 
  __HAL_LOCK(hspi);
1434 
  hspi->TxXferCount = Size;
 1434 
 
1435 
 
 1435 
  if ((pData == NULL) || (Size == 0U))
1436 
  /* Init field not used in handle to zero */
 1436 
  {
1437 
  hspi->pRxBuffPtr  = (uint8_t *)NULL;
 1437 
    errorcode = HAL_ERROR;
1438 
  hspi->RxXferSize  = 0U;
 1438 
    goto error;
1439 
  hspi->RxXferCount = 0U;
 1439 
  }
1440 
  hspi->RxISR       = NULL;
 1440 
 
1441 
 
 1441 
  if (hspi->State != HAL_SPI_STATE_READY)
1442 
  /* Set the function for IT treatment */
 1442 
  {
1443 
  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
 1443 
    errorcode = HAL_BUSY;
1444 
  {
 1444 
    goto error;
1445 
    hspi->TxISR = SPI_TxISR_16BIT;
 1445 
  }
1446 
  }
 1446 
 
1447 
  else
 1447 
  /* Set the transaction information */
1448 
  {
 1448 
  hspi->State       = HAL_SPI_STATE_BUSY_TX;
1449 
    hspi->TxISR = SPI_TxISR_8BIT;
 1449 
  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
1450 
  }
 1450 
  hspi->pTxBuffPtr  = (uint8_t *)pData;
1451 
 
 1451 
  hspi->TxXferSize  = Size;
1452 
  /* Configure communication direction : 1Line */
 1452 
  hspi->TxXferCount = Size;
1453 
  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
 1453 
 
1454 
  {
 1454 
  /* Init field not used in handle to zero */
1455 
    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
 1455 
  hspi->pRxBuffPtr  = (uint8_t *)NULL;
1456 
    __HAL_SPI_DISABLE(hspi);
 1456 
  hspi->RxXferSize  = 0U;
1457 
    SPI_1LINE_TX(hspi);
 1457 
  hspi->RxXferCount = 0U;
1458 
  }
 1458 
  hspi->RxISR       = NULL;
1459 
 
 1459 
 
1460 
#if (USE_SPI_CRC != 0U)
 1460 
  /* Set the function for IT treatment */
1461 
  /* Reset CRC Calculation */
 1461 
  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1462 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 1462 
  {
1463 
  {
 1463 
    hspi->TxISR = SPI_TxISR_16BIT;
1464 
    SPI_RESET_CRC(hspi);
 1464 
  }
1465 
  }
 1465 
  else
1466 
#endif /* USE_SPI_CRC */
 1466 
  {
1467 
 
 1467 
    hspi->TxISR = SPI_TxISR_8BIT;
1468 
  /* Enable TXE and ERR interrupt */
 1468 
  }
1469 
  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
 1469 
 
1470 
 
 1470 
  /* Configure communication direction : 1Line */
1471 
 
 1471 
  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1472 
  /* Check if the SPI is already enabled */
 1472 
  {
1473 
  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
 1473 
    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1474 
  {
 1474 
    __HAL_SPI_DISABLE(hspi);
1475 
    /* Enable SPI peripheral */
 1475 
    SPI_1LINE_TX(hspi);
1476 
    __HAL_SPI_ENABLE(hspi);
 1476 
  }
1477 
  }
 1477 
 
1478 
 
 1478 
#if (USE_SPI_CRC != 0U)
1479 
error :
 1479 
  /* Reset CRC Calculation */
1480 
  __HAL_UNLOCK(hspi);
 1480 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1481 
  return errorcode;
 1481 
  {
1482 
}
 1482 
    SPI_RESET_CRC(hspi);
1483 
 
 1483 
  }
1484 
/**
 1484 
#endif /* USE_SPI_CRC */
1485 
  * @brief  Receive an amount of data in non-blocking mode with Interrupt.
 1485 
 
1486 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 1486 
  /* Enable TXE and ERR interrupt */
1487 
  *               the configuration information for SPI module.
 1487 
  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
1488 
  * @param  pData pointer to data buffer
 1488 
 
1489 
  * @param  Size amount of data to be sent
 1489 
 
1490 
  * @retval HAL status
 1490 
  /* Check if the SPI is already enabled */
1491 
  */
 1491 
  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1492 
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
 1492 
  {
1493 
{
 1493 
    /* Enable SPI peripheral */
1494 
  HAL_StatusTypeDef errorcode = HAL_OK;
 1494 
    __HAL_SPI_ENABLE(hspi);
1495 
 
 1495 
  }
1496 
  if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
 1496 
 
1497 
  {
 1497 
error :
1498 
    hspi->State = HAL_SPI_STATE_BUSY_RX;
 1498 
  __HAL_UNLOCK(hspi);
1499 
    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
 1499 
  return errorcode;
1500 
    return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
 1500 
}
1501 
  }
 1501 
 
1502 
 
 1502 
/**
1503 
  /* Process Locked */
 1503 
  * @brief  Receive an amount of data in non-blocking mode with Interrupt.
1504 
  __HAL_LOCK(hspi);
 1504 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
1505 
 
 1505 
  *               the configuration information for SPI module.
1506 
  if (hspi->State != HAL_SPI_STATE_READY)
 1506 
  * @param  pData pointer to data buffer
1507 
  {
 1507 
  * @param  Size amount of data to be sent
1508 
    errorcode = HAL_BUSY;
 1508 
  * @retval HAL status
1509 
    goto error;
 1509 
  */
1510 
  }
 1510 
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1511 
 
 1511 
{
1512 
  if ((pData == NULL) || (Size == 0U))
 1512 
  HAL_StatusTypeDef errorcode = HAL_OK;
1513 
  {
 1513 
 
1514 
    errorcode = HAL_ERROR;
 1514 
 
1515 
    goto error;
 1515 
  if (hspi->State != HAL_SPI_STATE_READY)
1516 
  }
 1516 
  {
1517 
 
 1517 
    errorcode = HAL_BUSY;
1518 
  /* Set the transaction information */
 1518 
    goto error;
1519 
  hspi->State       = HAL_SPI_STATE_BUSY_RX;
 1519 
  }
1520 
  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
 1520 
 
1521 
  hspi->pRxBuffPtr  = (uint8_t *)pData;
 1521 
  if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
1522 
  hspi->RxXferSize  = Size;
 1522 
  {
1523 
  hspi->RxXferCount = Size;
 1523 
    hspi->State = HAL_SPI_STATE_BUSY_RX;
1524 
 
 1524 
    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1525 
  /* Init field not used in handle to zero */
 1525 
    return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
1526 
  hspi->pTxBuffPtr  = (uint8_t *)NULL;
 1526 
  }
1527 
  hspi->TxXferSize  = 0U;
 1527 
 
1528 
  hspi->TxXferCount = 0U;
 1528 
  /* Process Locked */
1529 
  hspi->TxISR       = NULL;
 1529 
  __HAL_LOCK(hspi);
1530 
 
 1530 
 
1531 
  /* Set the function for IT treatment */
 1531 
  if ((pData == NULL) || (Size == 0U))
1532 
  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
 1532 
  {
1533 
  {
 1533 
    errorcode = HAL_ERROR;
1534 
    hspi->RxISR = SPI_RxISR_16BIT;
 1534 
    goto error;
1535 
  }
 1535 
  }
1536 
  else
 1536 
 
1537 
  {
 1537 
  /* Set the transaction information */
1538 
    hspi->RxISR = SPI_RxISR_8BIT;
 1538 
  hspi->State       = HAL_SPI_STATE_BUSY_RX;
1539 
  }
 1539 
  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
1540 
 
 1540 
  hspi->pRxBuffPtr  = (uint8_t *)pData;
1541 
  /* Configure communication direction : 1Line */
 1541 
  hspi->RxXferSize  = Size;
1542 
  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
 1542 
  hspi->RxXferCount = Size;
1543 
  {
 1543 
 
1544 
    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
 1544 
  /* Init field not used in handle to zero */
1545 
    __HAL_SPI_DISABLE(hspi);
 1545 
  hspi->pTxBuffPtr  = (uint8_t *)NULL;
1546 
    SPI_1LINE_RX(hspi);
 1546 
  hspi->TxXferSize  = 0U;
1547 
  }
 1547 
  hspi->TxXferCount = 0U;
1548 
 
 1548 
  hspi->TxISR       = NULL;
1549 
#if (USE_SPI_CRC != 0U)
 1549 
 
1550 
  /* Reset CRC Calculation */
 1550 
  /* Set the function for IT treatment */
1551 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 1551 
  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1552 
  {
 1552 
  {
1553 
    SPI_RESET_CRC(hspi);
 1553 
    hspi->RxISR = SPI_RxISR_16BIT;
1554 
  }
 1554 
  }
1555 
#endif /* USE_SPI_CRC */
 1555 
  else
1556 
 
 1556 
  {
1557 
  /* Enable TXE and ERR interrupt */
 1557 
    hspi->RxISR = SPI_RxISR_8BIT;
1558 
  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
 1558 
  }
1559 
 
 1559 
 
1560 
  /* Note : The SPI must be enabled after unlocking current process
 1560 
  /* Configure communication direction : 1Line */
1561 
            to avoid the risk of SPI interrupt handle execution before current
 1561 
  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1562 
            process unlock */
 1562 
  {
1563 
 
 1563 
    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1564 
  /* Check if the SPI is already enabled */
 1564 
    __HAL_SPI_DISABLE(hspi);
1565 
  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
 1565 
    SPI_1LINE_RX(hspi);
1566 
  {
 1566 
  }
1567 
    /* Enable SPI peripheral */
 1567 
 
1568 
    __HAL_SPI_ENABLE(hspi);
 1568 
#if (USE_SPI_CRC != 0U)
1569 
  }
 1569 
  /* Reset CRC Calculation */
1570 
 
 1570 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1571 
error :
 1571 
  {
1572 
  /* Process Unlocked */
 1572 
    SPI_RESET_CRC(hspi);
1573 
  __HAL_UNLOCK(hspi);
 1573 
  }
1574 
  return errorcode;
 1574 
#endif /* USE_SPI_CRC */
1575 
}
 1575 
 
1576 
 
 1576 
  /* Enable TXE and ERR interrupt */
1577 
/**
 1577 
  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
1578 
  * @brief  Transmit and Receive an amount of data in non-blocking mode with Interrupt.
 1578 
 
1579 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 1579 
  /* Note : The SPI must be enabled after unlocking current process
1580 
  *               the configuration information for SPI module.
 1580 
            to avoid the risk of SPI interrupt handle execution before current
1581 
  * @param  pTxData pointer to transmission data buffer
 1581 
            process unlock */
1582 
  * @param  pRxData pointer to reception data buffer
 1582 
 
1583 
  * @param  Size amount of data to be sent and received
 1583 
  /* Check if the SPI is already enabled */
1584 
  * @retval HAL status
 1584 
  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1585 
  */
 1585 
  {
1586 
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
 1586 
    /* Enable SPI peripheral */
1587 
{
 1587 
    __HAL_SPI_ENABLE(hspi);
1588 
  uint32_t             tmp_mode;
 1588 
  }
1589 
  HAL_SPI_StateTypeDef tmp_state;
 1589 
 
1590 
  HAL_StatusTypeDef    errorcode = HAL_OK;
 1590 
error :
1591 
 
 1591 
  /* Process Unlocked */
1592 
  /* Check Direction parameter */
 1592 
  __HAL_UNLOCK(hspi);
1593 
  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
 1593 
  return errorcode;
1594 
 
 1594 
}
1595 
  /* Process locked */
 1595 
 
1596 
  __HAL_LOCK(hspi);
 1596 
/**
1597 
 
 1597 
  * @brief  Transmit and Receive an amount of data in non-blocking mode with Interrupt.
1598 
  /* Init temporary variables */
 1598 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
1599 
  tmp_state           = hspi->State;
 1599 
  *               the configuration information for SPI module.
1600 
  tmp_mode            = hspi->Init.Mode;
 1600 
  * @param  pTxData pointer to transmission data buffer
1601 
 
 1601 
  * @param  pRxData pointer to reception data buffer
1602 
  if (!((tmp_state == HAL_SPI_STATE_READY) || \
 1602 
  * @param  Size amount of data to be sent and received
1603 
        ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
 1603 
  * @retval HAL status
1604 
  {
 1604 
  */
1605 
    errorcode = HAL_BUSY;
 1605 
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
1606 
    goto error;
 1606 
{
1607 
  }
 1607 
  uint32_t             tmp_mode;
1608 
 
 1608 
  HAL_SPI_StateTypeDef tmp_state;
1609 
  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
 1609 
  HAL_StatusTypeDef    errorcode = HAL_OK;
1610 
  {
 1610 
 
1611 
    errorcode = HAL_ERROR;
 1611 
  /* Check Direction parameter */
1612 
    goto error;
 1612 
  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1613 
  }
 1613 
 
1614 
 
 1614 
  /* Process locked */
1615 
  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
 1615 
  __HAL_LOCK(hspi);
1616 
  if (hspi->State != HAL_SPI_STATE_BUSY_RX)
 1616 
 
1617 
  {
 1617 
  /* Init temporary variables */
1618 
    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
 1618 
  tmp_state           = hspi->State;
1619 
  }
 1619 
  tmp_mode            = hspi->Init.Mode;
1620 
 
 1620 
 
1621 
  /* Set the transaction information */
 1621 
  if (!((tmp_state == HAL_SPI_STATE_READY) || \
1622 
  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
 1622 
        ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
1623 
  hspi->pTxBuffPtr  = (uint8_t *)pTxData;
 1623 
  {
1624 
  hspi->TxXferSize  = Size;
 1624 
    errorcode = HAL_BUSY;
1625 
  hspi->TxXferCount = Size;
 1625 
    goto error;
1626 
  hspi->pRxBuffPtr  = (uint8_t *)pRxData;
 1626 
  }
1627 
  hspi->RxXferSize  = Size;
 1627 
 
1628 
  hspi->RxXferCount = Size;
 1628 
  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1629 
 
 1629 
  {
1630 
  /* Set the function for IT treatment */
 1630 
    errorcode = HAL_ERROR;
1631 
  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
 1631 
    goto error;
1632 
  {
 1632 
  }
1633 
    hspi->RxISR     = SPI_2linesRxISR_16BIT;
 1633 
 
1634 
    hspi->TxISR     = SPI_2linesTxISR_16BIT;
 1634 
  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1635 
  }
 1635 
  if (hspi->State != HAL_SPI_STATE_BUSY_RX)
1636 
  else
 1636 
  {
1637 
  {
 1637 
    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1638 
    hspi->RxISR     = SPI_2linesRxISR_8BIT;
 1638 
  }
1639 
    hspi->TxISR     = SPI_2linesTxISR_8BIT;
 1639 
 
1640 
  }
 1640 
  /* Set the transaction information */
1641 
 
 1641 
  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
1642 
#if (USE_SPI_CRC != 0U)
 1642 
  hspi->pTxBuffPtr  = (uint8_t *)pTxData;
1643 
  /* Reset CRC Calculation */
 1643 
  hspi->TxXferSize  = Size;
1644 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 1644 
  hspi->TxXferCount = Size;
1645 
  {
 1645 
  hspi->pRxBuffPtr  = (uint8_t *)pRxData;
1646 
    SPI_RESET_CRC(hspi);
 1646 
  hspi->RxXferSize  = Size;
1647 
  }
 1647 
  hspi->RxXferCount = Size;
1648 
#endif /* USE_SPI_CRC */
 1648 
 
1649 
 
 1649 
  /* Set the function for IT treatment */
1650 
  /* Enable TXE, RXNE and ERR interrupt */
 1650 
  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1651 
  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
 1651 
  {
1652 
 
 1652 
    hspi->RxISR     = SPI_2linesRxISR_16BIT;
1653 
  /* Check if the SPI is already enabled */
 1653 
    hspi->TxISR     = SPI_2linesTxISR_16BIT;
1654 
  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
 1654 
  }
1655 
  {
 1655 
  else
1656 
    /* Enable SPI peripheral */
 1656 
  {
1657 
    __HAL_SPI_ENABLE(hspi);
 1657 
    hspi->RxISR     = SPI_2linesRxISR_8BIT;
1658 
  }
 1658 
    hspi->TxISR     = SPI_2linesTxISR_8BIT;
1659 
 
 1659 
  }
1660 
error :
 1660 
 
1661 
  /* Process Unlocked */
 1661 
#if (USE_SPI_CRC != 0U)
1662 
  __HAL_UNLOCK(hspi);
 1662 
  /* Reset CRC Calculation */
1663 
  return errorcode;
 1663 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1664 
}
 1664 
  {
1665 
 
 1665 
    SPI_RESET_CRC(hspi);
1666 
/**
 1666 
  }
1667 
  * @brief  Transmit an amount of data in non-blocking mode with DMA.
 1667 
#endif /* USE_SPI_CRC */
1668 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 1668 
 
1669 
  *               the configuration information for SPI module.
 1669 
  /* Enable TXE, RXNE and ERR interrupt */
1670 
  * @param  pData pointer to data buffer
 1670 
  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
1671 
  * @param  Size amount of data to be sent
 1671 
 
1672 
  * @retval HAL status
 1672 
  /* Check if the SPI is already enabled */
1673 
  */
 1673 
  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1674 
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
 1674 
  {
1675 
{
 1675 
    /* Enable SPI peripheral */
1676 
  HAL_StatusTypeDef errorcode = HAL_OK;
 1676 
    __HAL_SPI_ENABLE(hspi);
1677 
 
 1677 
  }
1678 
  /* Check tx dma handle */
 1678 
 
1679 
  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
 1679 
error :
1680 
 
 1680 
  /* Process Unlocked */
1681 
  /* Check Direction parameter */
 1681 
  __HAL_UNLOCK(hspi);
1682 
  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
 1682 
  return errorcode;
1683 
 
 1683 
}
1684 
  /* Process Locked */
 1684 
 
1685 
  __HAL_LOCK(hspi);
 1685 
/**
1686 
 
 1686 
  * @brief  Transmit an amount of data in non-blocking mode with DMA.
1687 
  if (hspi->State != HAL_SPI_STATE_READY)
 1687 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
1688 
  {
 1688 
  *               the configuration information for SPI module.
1689 
    errorcode = HAL_BUSY;
 1689 
  * @param  pData pointer to data buffer
1690 
    goto error;
 1690 
  * @param  Size amount of data to be sent
1691 
  }
 1691 
  * @retval HAL status
1692 
 
 1692 
  */
1693 
  if ((pData == NULL) || (Size == 0U))
 1693 
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1694 
  {
 1694 
{
1695 
    errorcode = HAL_ERROR;
 1695 
  HAL_StatusTypeDef errorcode = HAL_OK;
1696 
    goto error;
 1696 
 
1697 
  }
 1697 
  /* Check tx dma handle */
1698 
 
 1698 
  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
1699 
  /* Set the transaction information */
 1699 
 
1700 
  hspi->State       = HAL_SPI_STATE_BUSY_TX;
 1700 
  /* Check Direction parameter */
1701 
  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
 1701 
  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
1702 
  hspi->pTxBuffPtr  = (uint8_t *)pData;
 1702 
 
1703 
  hspi->TxXferSize  = Size;
 1703 
  /* Process Locked */
1704 
  hspi->TxXferCount = Size;
 1704 
  __HAL_LOCK(hspi);
1705 
 
 1705 
 
1706 
  /* Init field not used in handle to zero */
 1706 
  if (hspi->State != HAL_SPI_STATE_READY)
1707 
  hspi->pRxBuffPtr  = (uint8_t *)NULL;
 1707 
  {
1708 
  hspi->TxISR       = NULL;
 1708 
    errorcode = HAL_BUSY;
1709 
  hspi->RxISR       = NULL;
 1709 
    goto error;
1710 
  hspi->RxXferSize  = 0U;
 1710 
  }
1711 
  hspi->RxXferCount = 0U;
 1711 
 
1712 
 
 1712 
  if ((pData == NULL) || (Size == 0U))
1713 
  /* Configure communication direction : 1Line */
 1713 
  {
1714 
  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
 1714 
    errorcode = HAL_ERROR;
1715 
  {
 1715 
    goto error;
1716 
    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
 1716 
  }
1717 
    __HAL_SPI_DISABLE(hspi);
 1717 
 
1718 
    SPI_1LINE_TX(hspi);
 1718 
  /* Set the transaction information */
1719 
  }
 1719 
  hspi->State       = HAL_SPI_STATE_BUSY_TX;
1720 
 
 1720 
  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
1721 
#if (USE_SPI_CRC != 0U)
 1721 
  hspi->pTxBuffPtr  = (uint8_t *)pData;
1722 
  /* Reset CRC Calculation */
 1722 
  hspi->TxXferSize  = Size;
1723 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 1723 
  hspi->TxXferCount = Size;
1724 
  {
 1724 
 
1725 
    SPI_RESET_CRC(hspi);
 1725 
  /* Init field not used in handle to zero */
1726 
  }
 1726 
  hspi->pRxBuffPtr  = (uint8_t *)NULL;
1727 
#endif /* USE_SPI_CRC */
 1727 
  hspi->TxISR       = NULL;
1728 
 
 1728 
  hspi->RxISR       = NULL;
1729 
  /* Set the SPI TxDMA Half transfer complete callback */
 1729 
  hspi->RxXferSize  = 0U;
1730 
  hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
 1730 
  hspi->RxXferCount = 0U;
1731 
 
 1731 
 
1732 
  /* Set the SPI TxDMA transfer complete callback */
 1732 
  /* Configure communication direction : 1Line */
1733 
  hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
 1733 
  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1734 
 
 1734 
  {
1735 
  /* Set the DMA error callback */
 1735 
    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1736 
  hspi->hdmatx->XferErrorCallback = SPI_DMAError;
 1736 
    __HAL_SPI_DISABLE(hspi);
1737 
 
 1737 
    SPI_1LINE_TX(hspi);
1738 
  /* Set the DMA AbortCpltCallback */
 1738 
  }
1739 
  hspi->hdmatx->XferAbortCallback = NULL;
 1739 
 
1740 
 
 1740 
#if (USE_SPI_CRC != 0U)
1741 
  /* Enable the Tx DMA Stream/Channel */
 1741 
  /* Reset CRC Calculation */
1742 
  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
 1742 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1743 
                                 hspi->TxXferCount))
 1743 
  {
1744 
  {
 1744 
    SPI_RESET_CRC(hspi);
1745 
    /* Update SPI error code */
 1745 
  }
1746 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
 1746 
#endif /* USE_SPI_CRC */
1747 
    errorcode = HAL_ERROR;
 1747 
 
1748 
 
 1748 
  /* Set the SPI TxDMA Half transfer complete callback */
1749 
    hspi->State = HAL_SPI_STATE_READY;
 1749 
  hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
1750 
    goto error;
 1750 
 
1751 
  }
 1751 
  /* Set the SPI TxDMA transfer complete callback */
1752 
 
 1752 
  hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
1753 
  /* Check if the SPI is already enabled */
 1753 
 
1754 
  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
 1754 
  /* Set the DMA error callback */
1755 
  {
 1755 
  hspi->hdmatx->XferErrorCallback = SPI_DMAError;
1756 
    /* Enable SPI peripheral */
 1756 
 
1757 
    __HAL_SPI_ENABLE(hspi);
 1757 
  /* Set the DMA AbortCpltCallback */
1758 
  }
 1758 
  hspi->hdmatx->XferAbortCallback = NULL;
1759 
 
 1759 
 
1760 
  /* Enable the SPI Error Interrupt Bit */
 1760 
  /* Enable the Tx DMA Stream/Channel */
1761 
  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
 1761 
  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
1762 
 
 1762 
                                 hspi->TxXferCount))
1763 
  /* Enable Tx DMA Request */
 1763 
  {
1764 
  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
 1764 
    /* Update SPI error code */
1765 
 
 1765 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
1766 
error :
 1766 
    errorcode = HAL_ERROR;
1767 
  /* Process Unlocked */
 1767 
 
1768 
  __HAL_UNLOCK(hspi);
 1768 
    goto error;
1769 
  return errorcode;
 1769 
  }
1770 
}
 1770 
 
1771 
 
 1771 
  /* Check if the SPI is already enabled */
1772 
/**
 1772 
  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1773 
  * @brief  Receive an amount of data in non-blocking mode with DMA.
 1773 
  {
1774 
  * @note   In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
 1774 
    /* Enable SPI peripheral */
1775 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 1775 
    __HAL_SPI_ENABLE(hspi);
1776 
  *               the configuration information for SPI module.
 1776 
  }
1777 
  * @param  pData pointer to data buffer
 1777 
 
1778 
  * @note   When the CRC feature is enabled the pData Length must be Size + 1.
 1778 
  /* Enable the SPI Error Interrupt Bit */
1779 
  * @param  Size amount of data to be sent
 1779 
  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
1780 
  * @retval HAL status
 1780 
 
1781 
  */
 1781 
  /* Enable Tx DMA Request */
1782 
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
 1782 
  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
1783 
{
 1783 
 
1784 
  HAL_StatusTypeDef errorcode = HAL_OK;
 1784 
error :
1785 
 
 1785 
  /* Process Unlocked */
1786 
  /* Check rx dma handle */
 1786 
  __HAL_UNLOCK(hspi);
1787 
  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
 1787 
  return errorcode;
1788 
 
 1788 
}
1789 
  if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
 1789 
 
1790 
  {
 1790 
/**
1791 
    hspi->State = HAL_SPI_STATE_BUSY_RX;
 1791 
  * @brief  Receive an amount of data in non-blocking mode with DMA.
1792 
 
 1792 
  * @note   In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
1793 
    /* Check tx dma handle */
 1793 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
1794 
    assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
 1794 
  *               the configuration information for SPI module.
1795 
 
 1795 
  * @param  pData pointer to data buffer
1796 
    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
 1796 
  * @note   When the CRC feature is enabled the pData Length must be Size + 1.
1797 
    return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
 1797 
  * @param  Size amount of data to be sent
1798 
  }
 1798 
  * @retval HAL status
1799 
 
 1799 
  */
1800 
  /* Process Locked */
 1800 
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1801 
  __HAL_LOCK(hspi);
 1801 
{
1802 
 
 1802 
  HAL_StatusTypeDef errorcode = HAL_OK;
1803 
  if (hspi->State != HAL_SPI_STATE_READY)
 1803 
 
1804 
  {
 1804 
  /* Check rx dma handle */
1805 
    errorcode = HAL_BUSY;
 1805 
  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
1806 
    goto error;
 1806 
 
1807 
  }
 1807 
  if (hspi->State != HAL_SPI_STATE_READY)
1808 
 
 1808 
  {
1809 
  if ((pData == NULL) || (Size == 0U))
 1809 
    errorcode = HAL_BUSY;
1810 
  {
 1810 
    goto error;
1811 
    errorcode = HAL_ERROR;
 1811 
  }
1812 
    goto error;
 1812 
 
1813 
  }
 1813 
  if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
1814 
 
 1814 
  {
1815 
  /* Set the transaction information */
 1815 
    hspi->State = HAL_SPI_STATE_BUSY_RX;
1816 
  hspi->State       = HAL_SPI_STATE_BUSY_RX;
 1816 
 
1817 
  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
 1817 
    /* Check tx dma handle */
1818 
  hspi->pRxBuffPtr  = (uint8_t *)pData;
 1818 
    assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
1819 
  hspi->RxXferSize  = Size;
 1819 
 
1820 
  hspi->RxXferCount = Size;
 1820 
    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1821 
 
 1821 
    return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
1822 
  /*Init field not used in handle to zero */
 1822 
  }
1823 
  hspi->RxISR       = NULL;
 1823 
 
1824 
  hspi->TxISR       = NULL;
 1824 
  /* Process Locked */
1825 
  hspi->TxXferSize  = 0U;
 1825 
  __HAL_LOCK(hspi);
1826 
  hspi->TxXferCount = 0U;
 1826 
 
1827 
 
 1827 
  if ((pData == NULL) || (Size == 0U))
1828 
  /* Configure communication direction : 1Line */
 1828 
  {
1829 
  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
 1829 
    errorcode = HAL_ERROR;
1830 
  {
 1830 
    goto error;
1831 
    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
 1831 
  }
1832 
    __HAL_SPI_DISABLE(hspi);
 1832 
 
1833 
    SPI_1LINE_RX(hspi);
 1833 
  /* Set the transaction information */
1834 
  }
 1834 
  hspi->State       = HAL_SPI_STATE_BUSY_RX;
1835 
 
 1835 
  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
1836 
#if (USE_SPI_CRC != 0U)
 1836 
  hspi->pRxBuffPtr  = (uint8_t *)pData;
1837 
  /* Reset CRC Calculation */
 1837 
  hspi->RxXferSize  = Size;
1838 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 1838 
  hspi->RxXferCount = Size;
1839 
  {
 1839 
 
1840 
    SPI_RESET_CRC(hspi);
 1840 
  /*Init field not used in handle to zero */
1841 
  }
 1841 
  hspi->RxISR       = NULL;
1842 
#endif /* USE_SPI_CRC */
 1842 
  hspi->TxISR       = NULL;
1843 
 
 1843 
  hspi->TxXferSize  = 0U;
1844 
  /* Set the SPI RxDMA Half transfer complete callback */
 1844 
  hspi->TxXferCount = 0U;
1845 
  hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
 1845 
 
1846 
 
 1846 
  /* Configure communication direction : 1Line */
1847 
  /* Set the SPI Rx DMA transfer complete callback */
 1847 
  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1848 
  hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
 1848 
  {
1849 
 
 1849 
    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1850 
  /* Set the DMA error callback */
 1850 
    __HAL_SPI_DISABLE(hspi);
1851 
  hspi->hdmarx->XferErrorCallback = SPI_DMAError;
 1851 
    SPI_1LINE_RX(hspi);
1852 
 
 1852 
  }
1853 
  /* Set the DMA AbortCpltCallback */
 1853 
 
1854 
  hspi->hdmarx->XferAbortCallback = NULL;
 1854 
#if (USE_SPI_CRC != 0U)
1855 
 
 1855 
  /* Reset CRC Calculation */
1856 
  /* Enable the Rx DMA Stream/Channel  */
 1856 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1857 
  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
 1857 
  {
1858 
                                 hspi->RxXferCount))
 1858 
    SPI_RESET_CRC(hspi);
1859 
  {
 1859 
  }
1860 
    /* Update SPI error code */
 1860 
#endif /* USE_SPI_CRC */
1861 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
 1861 
 
1862 
    errorcode = HAL_ERROR;
 1862 
  /* Set the SPI RxDMA Half transfer complete callback */
1863 
 
 1863 
  hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
1864 
    hspi->State = HAL_SPI_STATE_READY;
 1864 
 
1865 
    goto error;
 1865 
  /* Set the SPI Rx DMA transfer complete callback */
1866 
  }
 1866 
  hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
1867 
 
 1867 
 
1868 
  /* Check if the SPI is already enabled */
 1868 
  /* Set the DMA error callback */
1869 
  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
 1869 
  hspi->hdmarx->XferErrorCallback = SPI_DMAError;
1870 
  {
 1870 
 
1871 
    /* Enable SPI peripheral */
 1871 
  /* Set the DMA AbortCpltCallback */
1872 
    __HAL_SPI_ENABLE(hspi);
 1872 
  hspi->hdmarx->XferAbortCallback = NULL;
1873 
  }
 1873 
 
1874 
 
 1874 
  /* Enable the Rx DMA Stream/Channel  */
1875 
  /* Enable the SPI Error Interrupt Bit */
 1875 
  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
1876 
  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
 1876 
                                 hspi->RxXferCount))
1877 
 
 1877 
  {
1878 
  /* Enable Rx DMA Request */
 1878 
    /* Update SPI error code */
1879 
  SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
 1879 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
1880 
 
 1880 
    errorcode = HAL_ERROR;
1881 
error:
 1881 
 
1882 
  /* Process Unlocked */
 1882 
    goto error;
1883 
  __HAL_UNLOCK(hspi);
 1883 
  }
1884 
  return errorcode;
 1884 
 
1885 
}
 1885 
  /* Check if the SPI is already enabled */
1886 
 
 1886 
  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1887 
/**
 1887 
  {
1888 
  * @brief  Transmit and Receive an amount of data in non-blocking mode with DMA.
 1888 
    /* Enable SPI peripheral */
1889 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 1889 
    __HAL_SPI_ENABLE(hspi);
1890 
  *               the configuration information for SPI module.
 1890 
  }
1891 
  * @param  pTxData pointer to transmission data buffer
 1891 
 
1892 
  * @param  pRxData pointer to reception data buffer
 1892 
  /* Enable the SPI Error Interrupt Bit */
1893 
  * @note   When the CRC feature is enabled the pRxData Length must be Size + 1
 1893 
  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
1894 
  * @param  Size amount of data to be sent
 1894 
 
1895 
  * @retval HAL status
 1895 
  /* Enable Rx DMA Request */
1896 
  */
 1896 
  SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
1897 
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
 1897 
 
1898 
                                              uint16_t Size)
 1898 
error:
1899 
{
 1899 
  /* Process Unlocked */
1900 
  uint32_t             tmp_mode;
 1900 
  __HAL_UNLOCK(hspi);
1901 
  HAL_SPI_StateTypeDef tmp_state;
 1901 
  return errorcode;
1902 
  HAL_StatusTypeDef errorcode = HAL_OK;
 1902 
}
1903 
 
 1903 
 
1904 
  /* Check rx & tx dma handles */
 1904 
/**
1905 
  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
 1905 
  * @brief  Transmit and Receive an amount of data in non-blocking mode with DMA.
1906 
  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
 1906 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
1907 
 
 1907 
  *               the configuration information for SPI module.
1908 
  /* Check Direction parameter */
 1908 
  * @param  pTxData pointer to transmission data buffer
1909 
  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
 1909 
  * @param  pRxData pointer to reception data buffer
1910 
 
 1910 
  * @note   When the CRC feature is enabled the pRxData Length must be Size + 1
1911 
  /* Process locked */
 1911 
  * @param  Size amount of data to be sent
1912 
  __HAL_LOCK(hspi);
 1912 
  * @retval HAL status
1913 
 
 1913 
  */
1914 
  /* Init temporary variables */
 1914 
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
1915 
  tmp_state           = hspi->State;
 1915 
                                              uint16_t Size)
1916 
  tmp_mode            = hspi->Init.Mode;
 1916 
{
1917 
 
 1917 
  uint32_t             tmp_mode;
1918 
  if (!((tmp_state == HAL_SPI_STATE_READY) ||
 1918 
  HAL_SPI_StateTypeDef tmp_state;
1919 
        ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
 1919 
  HAL_StatusTypeDef errorcode = HAL_OK;
1920 
  {
 1920 
 
1921 
    errorcode = HAL_BUSY;
 1921 
  /* Check rx & tx dma handles */
1922 
    goto error;
 1922 
  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
1923 
  }
 1923 
  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
1924 
 
 1924 
 
1925 
  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
 1925 
  /* Check Direction parameter */
1926 
  {
 1926 
  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1927 
    errorcode = HAL_ERROR;
 1927 
 
1928 
    goto error;
 1928 
  /* Process locked */
1929 
  }
 1929 
  __HAL_LOCK(hspi);
1930 
 
 1930 
 
1931 
  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
 1931 
  /* Init temporary variables */
1932 
  if (hspi->State != HAL_SPI_STATE_BUSY_RX)
 1932 
  tmp_state           = hspi->State;
1933 
  {
 1933 
  tmp_mode            = hspi->Init.Mode;
1934 
    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
 1934 
 
1935 
  }
 1935 
  if (!((tmp_state == HAL_SPI_STATE_READY) ||
1936 
 
 1936 
        ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
1937 
  /* Set the transaction information */
 1937 
  {
1938 
  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
 1938 
    errorcode = HAL_BUSY;
1939 
  hspi->pTxBuffPtr  = (uint8_t *)pTxData;
 1939 
    goto error;
1940 
  hspi->TxXferSize  = Size;
 1940 
  }
1941 
  hspi->TxXferCount = Size;
 1941 
 
1942 
  hspi->pRxBuffPtr  = (uint8_t *)pRxData;
 1942 
  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1943 
  hspi->RxXferSize  = Size;
 1943 
  {
1944 
  hspi->RxXferCount = Size;
 1944 
    errorcode = HAL_ERROR;
1945 
 
 1945 
    goto error;
1946 
  /* Init field not used in handle to zero */
 1946 
  }
1947 
  hspi->RxISR       = NULL;
 1947 
 
1948 
  hspi->TxISR       = NULL;
 1948 
  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1949 
 
 1949 
  if (hspi->State != HAL_SPI_STATE_BUSY_RX)
1950 
#if (USE_SPI_CRC != 0U)
 1950 
  {
1951 
  /* Reset CRC Calculation */
 1951 
    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1952 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 1952 
  }
1953 
  {
 1953 
 
1954 
    SPI_RESET_CRC(hspi);
 1954 
  /* Set the transaction information */
1955 
  }
 1955 
  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
1956 
#endif /* USE_SPI_CRC */
 1956 
  hspi->pTxBuffPtr  = (uint8_t *)pTxData;
1957 
 
 1957 
  hspi->TxXferSize  = Size;
1958 
  /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
 1958 
  hspi->TxXferCount = Size;
1959 
  if (hspi->State == HAL_SPI_STATE_BUSY_RX)
 1959 
  hspi->pRxBuffPtr  = (uint8_t *)pRxData;
1960 
  {
 1960 
  hspi->RxXferSize  = Size;
1961 
    /* Set the SPI Rx DMA Half transfer complete callback */
 1961 
  hspi->RxXferCount = Size;
1962 
    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
 1962 
 
1963 
    hspi->hdmarx->XferCpltCallback     = SPI_DMAReceiveCplt;
 1963 
  /* Init field not used in handle to zero */
1964 
  }
 1964 
  hspi->RxISR       = NULL;
1965 
  else
 1965 
  hspi->TxISR       = NULL;
1966 
  {
 1966 
 
1967 
    /* Set the SPI Tx/Rx DMA Half transfer complete callback */
 1967 
#if (USE_SPI_CRC != 0U)
1968 
    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
 1968 
  /* Reset CRC Calculation */
1969 
    hspi->hdmarx->XferCpltCallback     = SPI_DMATransmitReceiveCplt;
 1969 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1970 
  }
 1970 
  {
1971 
 
 1971 
    SPI_RESET_CRC(hspi);
1972 
  /* Set the DMA error callback */
 1972 
  }
1973 
  hspi->hdmarx->XferErrorCallback = SPI_DMAError;
 1973 
#endif /* USE_SPI_CRC */
1974 
 
 1974 
 
1975 
  /* Set the DMA AbortCpltCallback */
 1975 
  /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
1976 
  hspi->hdmarx->XferAbortCallback = NULL;
 1976 
  if (hspi->State == HAL_SPI_STATE_BUSY_RX)
1977 
 
 1977 
  {
1978 
  /* Enable the Rx DMA Stream/Channel  */
 1978 
    /* Set the SPI Rx DMA Half transfer complete callback */
1979 
  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
 1979 
    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
1980 
                                 hspi->RxXferCount))
 1980 
    hspi->hdmarx->XferCpltCallback     = SPI_DMAReceiveCplt;
1981 
  {
 1981 
  }
1982 
    /* Update SPI error code */
 1982 
  else
1983 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
 1983 
  {
1984 
    errorcode = HAL_ERROR;
 1984 
    /* Set the SPI Tx/Rx DMA Half transfer complete callback */
1985 
 
 1985 
    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
1986 
    hspi->State = HAL_SPI_STATE_READY;
 1986 
    hspi->hdmarx->XferCpltCallback     = SPI_DMATransmitReceiveCplt;
1987 
    goto error;
 1987 
  }
1988 
  }
 1988 
 
1989 
 
 1989 
  /* Set the DMA error callback */
1990 
  /* Enable Rx DMA Request */
 1990 
  hspi->hdmarx->XferErrorCallback = SPI_DMAError;
1991 
  SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
 1991 
 
1992 
 
 1992 
  /* Set the DMA AbortCpltCallback */
1993 
  /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
 1993 
  hspi->hdmarx->XferAbortCallback = NULL;
1994 
  is performed in DMA reception complete callback  */
 1994 
 
1995 
  hspi->hdmatx->XferHalfCpltCallback = NULL;
 1995 
  /* Enable the Rx DMA Stream/Channel  */
1996 
  hspi->hdmatx->XferCpltCallback     = NULL;
 1996 
  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
1997 
  hspi->hdmatx->XferErrorCallback    = NULL;
 1997 
                                 hspi->RxXferCount))
1998 
  hspi->hdmatx->XferAbortCallback    = NULL;
 1998 
  {
1999 
 
 1999 
    /* Update SPI error code */
2000 
  /* Enable the Tx DMA Stream/Channel  */
 2000 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2001 
  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
 2001 
    errorcode = HAL_ERROR;
2002 
                                 hspi->TxXferCount))
 2002 
 
2003 
  {
 2003 
    goto error;
2004 
    /* Update SPI error code */
 2004 
  }
2005 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
 2005 
 
2006 
    errorcode = HAL_ERROR;
 2006 
  /* Enable Rx DMA Request */
2007 
 
 2007 
  SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
2008 
    hspi->State = HAL_SPI_STATE_READY;
 2008 
 
2009 
    goto error;
 2009 
  /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
2010 
  }
 2010 
  is performed in DMA reception complete callback  */
2011 
 
 2011 
  hspi->hdmatx->XferHalfCpltCallback = NULL;
2012 
  /* Check if the SPI is already enabled */
 2012 
  hspi->hdmatx->XferCpltCallback     = NULL;
2013 
  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
 2013 
  hspi->hdmatx->XferErrorCallback    = NULL;
2014 
  {
 2014 
  hspi->hdmatx->XferAbortCallback    = NULL;
2015 
    /* Enable SPI peripheral */
 2015 
 
2016 
    __HAL_SPI_ENABLE(hspi);
 2016 
  /* Enable the Tx DMA Stream/Channel  */
2017 
  }
 2017 
  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
2018 
  /* Enable the SPI Error Interrupt Bit */
 2018 
                                 hspi->TxXferCount))
2019 
  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
 2019 
  {
2020 
 
 2020 
    /* Update SPI error code */
2021 
  /* Enable Tx DMA Request */
 2021 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2022 
  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
 2022 
    errorcode = HAL_ERROR;
2023 
 
 2023 
 
2024 
error :
 2024 
    goto error;
2025 
  /* Process Unlocked */
 2025 
  }
2026 
  __HAL_UNLOCK(hspi);
 2026 
 
2027 
  return errorcode;
 2027 
  /* Check if the SPI is already enabled */
2028 
}
 2028 
  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
2029 
 
 2029 
  {
2030 
/**
 2030 
    /* Enable SPI peripheral */
2031 
  * @brief  Abort ongoing transfer (blocking mode).
 2031 
    __HAL_SPI_ENABLE(hspi);
2032 
  * @param  hspi SPI handle.
 2032 
  }
2033 
  * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),
 2033 
  /* Enable the SPI Error Interrupt Bit */
2034 
  *         started in Interrupt or DMA mode.
 2034 
  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
2035 
  *         This procedure performs following operations :
 2035 
 
2036 
  *           - Disable SPI Interrupts (depending of transfer direction)
 2036 
  /* Enable Tx DMA Request */
2037 
  *           - Disable the DMA transfer in the peripheral register (if enabled)
 2037 
  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
2038 
  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
 2038 
 
2039 
  *           - Set handle State to READY
 2039 
error :
2040 
  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
 2040 
  /* Process Unlocked */
2041 
  * @retval HAL status
 2041 
  __HAL_UNLOCK(hspi);
2042 
  */
 2042 
  return errorcode;
2043 
HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
 2043 
}
2044 
{
 2044 
 
2045 
  HAL_StatusTypeDef errorcode;
 2045 
/**
2046 
  __IO uint32_t count;
 2046 
  * @brief  Abort ongoing transfer (blocking mode).
2047 
  __IO uint32_t resetcount;
 2047 
  * @param  hspi SPI handle.
2048 
 
 2048 
  * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),
2049 
  /* Initialized local variable  */
 2049 
  *         started in Interrupt or DMA mode.
2050 
  errorcode = HAL_OK;
 2050 
  *         This procedure performs following operations :
2051 
  resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
 2051 
  *           - Disable SPI Interrupts (depending of transfer direction)
2052 
  count = resetcount;
 2052 
  *           - Disable the DMA transfer in the peripheral register (if enabled)
2053 
 
 2053 
  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
2054 
  /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
 2054 
  *           - Set handle State to READY
2055 
  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
 2055 
  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
2056 
 
 2056 
  * @retval HAL status
2057 
  /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
 2057 
  */
2058 
  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
 2058 
HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
2059 
  {
 2059 
{
2060 
    hspi->TxISR = SPI_AbortTx_ISR;
 2060 
  HAL_StatusTypeDef errorcode;
2061 
    /* Wait HAL_SPI_STATE_ABORT state */
 2061 
  __IO uint32_t count;
2062 
    do
 2062 
  __IO uint32_t resetcount;
2063 
    {
 2063 
 
2064 
      if (count == 0U)
 2064 
  /* Initialized local variable  */
2065 
      {
 2065 
  errorcode = HAL_OK;
2066 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
 2066 
  resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
2067 
        break;
 2067 
  count = resetcount;
2068 
      }
 2068 
 
2069 
      count--;
 2069 
  /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
2070 
    } while (hspi->State != HAL_SPI_STATE_ABORT);
 2070 
  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
2071 
    /* Reset Timeout Counter */
 2071 
 
2072 
    count = resetcount;
 2072 
  /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
2073 
  }
 2073 
  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
2074 
 
 2074 
  {
2075 
  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
 2075 
    hspi->TxISR = SPI_AbortTx_ISR;
2076 
  {
 2076 
    /* Wait HAL_SPI_STATE_ABORT state */
2077 
    hspi->RxISR = SPI_AbortRx_ISR;
 2077 
    do
2078 
    /* Wait HAL_SPI_STATE_ABORT state */
 2078 
    {
2079 
    do
 2079 
      if (count == 0U)
2080 
    {
 2080 
      {
2081 
      if (count == 0U)
 2081 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2082 
      {
 2082 
        break;
2083 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
 2083 
      }
2084 
        break;
 2084 
      count--;
2085 
      }
 2085 
    } while (hspi->State != HAL_SPI_STATE_ABORT);
2086 
      count--;
 2086 
    /* Reset Timeout Counter */
2087 
    } while (hspi->State != HAL_SPI_STATE_ABORT);
 2087 
    count = resetcount;
2088 
    /* Reset Timeout Counter */
 2088 
  }
2089 
    count = resetcount;
 2089 
 
2090 
  }
 2090 
  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
2091 
 
 2091 
  {
2092 
  /* Disable the SPI DMA Tx request if enabled */
 2092 
    hspi->RxISR = SPI_AbortRx_ISR;
2093 
  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
 2093 
    /* Wait HAL_SPI_STATE_ABORT state */
2094 
  {
 2094 
    do
2095 
    /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
 2095 
    {
2096 
    if (hspi->hdmatx != NULL)
 2096 
      if (count == 0U)
2097 
    {
 2097 
      {
2098 
      /* Set the SPI DMA Abort callback :
 2098 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2099 
      will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
 2099 
        break;
2100 
      hspi->hdmatx->XferAbortCallback = NULL;
 2100 
      }
2101 
 
 2101 
      count--;
2102 
      /* Abort DMA Tx Handle linked to SPI Peripheral */
 2102 
    } while (hspi->State != HAL_SPI_STATE_ABORT);
2103 
      if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
 2103 
    /* Reset Timeout Counter */
2104 
      {
 2104 
    count = resetcount;
2105 
        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
 2105 
  }
2106 
      }
 2106 
 
2107 
 
 2107 
  /* Disable the SPI DMA Tx request if enabled */
2108 
      /* Disable Tx DMA Request */
 2108 
  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2109 
      CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
 2109 
  {
2110 
 
 2110 
    /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
2111 
      /* Wait until TXE flag is set */
 2111 
    if (hspi->hdmatx != NULL)
2112 
      do
 2112 
    {
2113 
      {
 2113 
      /* Set the SPI DMA Abort callback :
2114 
        if (count == 0U)
 2114 
      will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
2115 
        {
 2115 
      hspi->hdmatx->XferAbortCallback = NULL;
2116 
          SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
 2116 
 
2117 
          break;
 2117 
      /* Abort DMA Tx Handle linked to SPI Peripheral */
2118 
        }
 2118 
      if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
2119 
        count--;
 2119 
      {
2120 
      } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
 2120 
        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2121 
    }
 2121 
      }
2122 
  }
 2122 
 
2123 
 
 2123 
      /* Disable Tx DMA Request */
2124 
  /* Disable the SPI DMA Rx request if enabled */
 2124 
      CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
2125 
  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
 2125 
 
2126 
  {
 2126 
      /* Wait until TXE flag is set */
2127 
    /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
 2127 
      do
2128 
    if (hspi->hdmarx != NULL)
 2128 
      {
2129 
    {
 2129 
        if (count == 0U)
2130 
      /* Set the SPI DMA Abort callback :
 2130 
        {
2131 
      will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
 2131 
          SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2132 
      hspi->hdmarx->XferAbortCallback = NULL;
 2132 
          break;
2133 
 
 2133 
        }
2134 
      /* Abort DMA Rx Handle linked to SPI Peripheral */
 2134 
        count--;
2135 
      if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
 2135 
      } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
2136 
      {
 2136 
    }
2137 
        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
 2137 
  }
2138 
      }
 2138 
 
2139 
 
 2139 
  /* Disable the SPI DMA Rx request if enabled */
2140 
      /* Disable peripheral */
 2140 
  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2141 
      __HAL_SPI_DISABLE(hspi);
 2141 
  {
2142 
 
 2142 
    /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
2143 
      /* Disable Rx DMA Request */
 2143 
    if (hspi->hdmarx != NULL)
2144 
      CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
 2144 
    {
2145 
    }
 2145 
      /* Set the SPI DMA Abort callback :
2146 
  }
 2146 
      will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
2147 
  /* Reset Tx and Rx transfer counters */
 2147 
      hspi->hdmarx->XferAbortCallback = NULL;
2148 
  hspi->RxXferCount = 0U;
 2148 
 
2149 
  hspi->TxXferCount = 0U;
 2149 
      /* Abort DMA Rx Handle linked to SPI Peripheral */
2150 
 
 2150 
      if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
2151 
  /* Check error during Abort procedure */
 2151 
      {
2152 
  if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
 2152 
        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2153 
  {
 2153 
      }
2154 
    /* return HAL_Error in case of error during Abort procedure */
 2154 
 
2155 
    errorcode = HAL_ERROR;
 2155 
      /* Disable peripheral */
2156 
  }
 2156 
      __HAL_SPI_DISABLE(hspi);
2157 
  else
 2157 
 
2158 
  {
 2158 
      /* Disable Rx DMA Request */
2159 
    /* Reset errorCode */
 2159 
      CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
2160 
    hspi->ErrorCode = HAL_SPI_ERROR_NONE;
 2160 
    }
2161 
  }
 2161 
  }
2162 
 
 2162 
  /* Reset Tx and Rx transfer counters */
2163 
  /* Clear the Error flags in the SR register */
 2163 
  hspi->RxXferCount = 0U;
2164 
  __HAL_SPI_CLEAR_OVRFLAG(hspi);
 2164 
  hspi->TxXferCount = 0U;
2165 
 
 2165 
 
2166 
  /* Restore hspi->state to ready */
 2166 
  /* Check error during Abort procedure */
2167 
  hspi->State = HAL_SPI_STATE_READY;
 2167 
  if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
2168 
 
 2168 
  {
2169 
  return errorcode;
 2169 
    /* return HAL_Error in case of error during Abort procedure */
2170 
}
 2170 
    errorcode = HAL_ERROR;
2171 
 
 2171 
  }
2172 
/**
 2172 
  else
2173 
  * @brief  Abort ongoing transfer (Interrupt mode).
 2173 
  {
2174 
  * @param  hspi SPI handle.
 2174 
    /* Reset errorCode */
2175 
  * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),
 2175 
    hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2176 
  *         started in Interrupt or DMA mode.
 2176 
  }
2177 
  *         This procedure performs following operations :
 2177 
 
2178 
  *           - Disable SPI Interrupts (depending of transfer direction)
 2178 
  /* Clear the Error flags in the SR register */
2179 
  *           - Disable the DMA transfer in the peripheral register (if enabled)
 2179 
  __HAL_SPI_CLEAR_OVRFLAG(hspi);
2180 
  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
 2180 
 
2181 
  *           - Set handle State to READY
 2181 
  /* Restore hspi->state to ready */
2182 
  *           - At abort completion, call user abort complete callback
 2182 
  hspi->State = HAL_SPI_STATE_READY;
2183 
  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
 2183 
 
2184 
  *         considered as completed only when user abort complete callback is executed (not when exiting function).
 2184 
  return errorcode;
2185 
  * @retval HAL status
 2185 
}
2186 
  */
 2186 
 
2187 
HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
 2187 
/**
2188 
{
 2188 
  * @brief  Abort ongoing transfer (Interrupt mode).
2189 
  HAL_StatusTypeDef errorcode;
 2189 
  * @param  hspi SPI handle.
2190 
  uint32_t abortcplt ;
 2190 
  * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),
2191 
  __IO uint32_t count;
 2191 
  *         started in Interrupt or DMA mode.
2192 
  __IO uint32_t resetcount;
 2192 
  *         This procedure performs following operations :
2193 
 
 2193 
  *           - Disable SPI Interrupts (depending of transfer direction)
2194 
  /* Initialized local variable  */
 2194 
  *           - Disable the DMA transfer in the peripheral register (if enabled)
2195 
  errorcode = HAL_OK;
 2195 
  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
2196 
  abortcplt = 1U;
 2196 
  *           - Set handle State to READY
2197 
  resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
 2197 
  *           - At abort completion, call user abort complete callback
2198 
  count = resetcount;
 2198 
  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
2199 
 
 2199 
  *         considered as completed only when user abort complete callback is executed (not when exiting function).
2200 
  /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
 2200 
  * @retval HAL status
2201 
  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
 2201 
  */
2202 
 
 2202 
HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
2203 
  /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
 2203 
{
2204 
  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
 2204 
  HAL_StatusTypeDef errorcode;
2205 
  {
 2205 
  uint32_t abortcplt ;
2206 
    hspi->TxISR = SPI_AbortTx_ISR;
 2206 
  __IO uint32_t count;
2207 
    /* Wait HAL_SPI_STATE_ABORT state */
 2207 
  __IO uint32_t resetcount;
2208 
    do
 2208 
 
2209 
    {
 2209 
  /* Initialized local variable  */
2210 
      if (count == 0U)
 2210 
  errorcode = HAL_OK;
2211 
      {
 2211 
  abortcplt = 1U;
2212 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
 2212 
  resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
2213 
        break;
 2213 
  count = resetcount;
2214 
      }
 2214 
 
2215 
      count--;
 2215 
  /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
2216 
    } while (hspi->State != HAL_SPI_STATE_ABORT);
 2216 
  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
2217 
    /* Reset Timeout Counter */
 2217 
 
2218 
    count = resetcount;
 2218 
  /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
2219 
  }
 2219 
  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
2220 
 
 2220 
  {
2221 
  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
 2221 
    hspi->TxISR = SPI_AbortTx_ISR;
2222 
  {
 2222 
    /* Wait HAL_SPI_STATE_ABORT state */
2223 
    hspi->RxISR = SPI_AbortRx_ISR;
 2223 
    do
2224 
    /* Wait HAL_SPI_STATE_ABORT state */
 2224 
    {
2225 
    do
 2225 
      if (count == 0U)
2226 
    {
 2226 
      {
2227 
      if (count == 0U)
 2227 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2228 
      {
 2228 
        break;
2229 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
 2229 
      }
2230 
        break;
 2230 
      count--;
2231 
      }
 2231 
    } while (hspi->State != HAL_SPI_STATE_ABORT);
2232 
      count--;
 2232 
    /* Reset Timeout Counter */
2233 
    } while (hspi->State != HAL_SPI_STATE_ABORT);
 2233 
    count = resetcount;
2234 
    /* Reset Timeout Counter */
 2234 
  }
2235 
    count = resetcount;
 2235 
 
2236 
  }
 2236 
  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
2237 
 
 2237 
  {
2238 
  /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
 2238 
    hspi->RxISR = SPI_AbortRx_ISR;
2239 
     before any call to DMA Abort functions */
 2239 
    /* Wait HAL_SPI_STATE_ABORT state */
2240 
  /* DMA Tx Handle is valid */
 2240 
    do
2241 
  if (hspi->hdmatx != NULL)
 2241 
    {
2242 
  {
 2242 
      if (count == 0U)
2243 
    /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
 2243 
      {
2244 
       Otherwise, set it to NULL */
 2244 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2245 
    if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
 2245 
        break;
2246 
    {
 2246 
      }
2247 
      hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
 2247 
      count--;
2248 
    }
 2248 
    } while (hspi->State != HAL_SPI_STATE_ABORT);
2249 
    else
 2249 
    /* Reset Timeout Counter */
2250 
    {
 2250 
    count = resetcount;
2251 
      hspi->hdmatx->XferAbortCallback = NULL;
 2251 
  }
2252 
    }
 2252 
 
2253 
  }
 2253 
  /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
2254 
  /* DMA Rx Handle is valid */
 2254 
     before any call to DMA Abort functions */
2255 
  if (hspi->hdmarx != NULL)
 2255 
  /* DMA Tx Handle is valid */
2256 
  {
 2256 
  if (hspi->hdmatx != NULL)
2257 
    /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
 2257 
  {
2258 
       Otherwise, set it to NULL */
 2258 
    /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
2259 
    if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
 2259 
       Otherwise, set it to NULL */
2260 
    {
 2260 
    if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2261 
      hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
 2261 
    {
2262 
    }
 2262 
      hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
2263 
    else
 2263 
    }
2264 
    {
 2264 
    else
2265 
      hspi->hdmarx->XferAbortCallback = NULL;
 2265 
    {
2266 
    }
 2266 
      hspi->hdmatx->XferAbortCallback = NULL;
2267 
  }
 2267 
    }
2268 
 
 2268 
  }
2269 
  /* Disable the SPI DMA Tx request if enabled */
 2269 
  /* DMA Rx Handle is valid */
2270 
  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
 2270 
  if (hspi->hdmarx != NULL)
2271 
  {
 2271 
  {
2272 
    /* Abort the SPI DMA Tx Stream/Channel */
 2272 
    /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
2273 
    if (hspi->hdmatx != NULL)
 2273 
       Otherwise, set it to NULL */
2274 
    {
 2274 
    if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2275 
      /* Abort DMA Tx Handle linked to SPI Peripheral */
 2275 
    {
2276 
      if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
 2276 
      hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
2277 
      {
 2277 
    }
2278 
        hspi->hdmatx->XferAbortCallback = NULL;
 2278 
    else
2279 
        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
 2279 
    {
2280 
      }
 2280 
      hspi->hdmarx->XferAbortCallback = NULL;
2281 
      else
 2281 
    }
2282 
      {
 2282 
  }
2283 
        abortcplt = 0U;
 2283 
 
2284 
      }
 2284 
  /* Disable the SPI DMA Tx request if enabled */
2285 
    }
 2285 
  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2286 
  }
 2286 
  {
2287 
  /* Disable the SPI DMA Rx request if enabled */
 2287 
    /* Abort the SPI DMA Tx Stream/Channel */
2288 
  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
 2288 
    if (hspi->hdmatx != NULL)
2289 
  {
 2289 
    {
2290 
    /* Abort the SPI DMA Rx Stream/Channel */
 2290 
      /* Abort DMA Tx Handle linked to SPI Peripheral */
2291 
    if (hspi->hdmarx != NULL)
 2291 
      if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
2292 
    {
 2292 
      {
2293 
      /* Abort DMA Rx Handle linked to SPI Peripheral */
 2293 
        hspi->hdmatx->XferAbortCallback = NULL;
2294 
      if (HAL_DMA_Abort_IT(hspi->hdmarx) !=  HAL_OK)
 2294 
        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2295 
      {
 2295 
      }
2296 
        hspi->hdmarx->XferAbortCallback = NULL;
 2296 
      else
2297 
        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
 2297 
      {
2298 
      }
 2298 
        abortcplt = 0U;
2299 
      else
 2299 
      }
2300 
      {
 2300 
    }
2301 
        abortcplt = 0U;
 2301 
  }
2302 
      }
 2302 
  /* Disable the SPI DMA Rx request if enabled */
2303 
    }
 2303 
  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2304 
  }
 2304 
  {
2305 
 
 2305 
    /* Abort the SPI DMA Rx Stream/Channel */
2306 
  if (abortcplt == 1U)
 2306 
    if (hspi->hdmarx != NULL)
2307 
  {
 2307 
    {
2308 
    /* Reset Tx and Rx transfer counters */
 2308 
      /* Abort DMA Rx Handle linked to SPI Peripheral */
2309 
    hspi->RxXferCount = 0U;
 2309 
      if (HAL_DMA_Abort_IT(hspi->hdmarx) !=  HAL_OK)
2310 
    hspi->TxXferCount = 0U;
 2310 
      {
2311 
 
 2311 
        hspi->hdmarx->XferAbortCallback = NULL;
2312 
    /* Check error during Abort procedure */
 2312 
        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2313 
    if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
 2313 
      }
2314 
    {
 2314 
      else
2315 
      /* return HAL_Error in case of error during Abort procedure */
 2315 
      {
2316 
      errorcode = HAL_ERROR;
 2316 
        abortcplt = 0U;
2317 
    }
 2317 
      }
2318 
    else
 2318 
    }
2319 
    {
 2319 
  }
2320 
      /* Reset errorCode */
 2320 
 
2321 
      hspi->ErrorCode = HAL_SPI_ERROR_NONE;
 2321 
  if (abortcplt == 1U)
2322 
    }
 2322 
  {
2323 
 
 2323 
    /* Reset Tx and Rx transfer counters */
2324 
    /* Clear the Error flags in the SR register */
 2324 
    hspi->RxXferCount = 0U;
2325 
    __HAL_SPI_CLEAR_OVRFLAG(hspi);
 2325 
    hspi->TxXferCount = 0U;
2326 
 
 2326 
 
2327 
    /* Restore hspi->State to Ready */
 2327 
    /* Check error during Abort procedure */
2328 
    hspi->State = HAL_SPI_STATE_READY;
 2328 
    if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
2329 
 
 2329 
    {
2330 
    /* As no DMA to be aborted, call directly user Abort complete callback */
 2330 
      /* return HAL_Error in case of error during Abort procedure */
2331 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 2331 
      errorcode = HAL_ERROR;
2332 
    hspi->AbortCpltCallback(hspi);
 2332 
    }
2333 
#else
 2333 
    else
2334 
    HAL_SPI_AbortCpltCallback(hspi);
 2334 
    {
2335 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 2335 
      /* Reset errorCode */
2336 
  }
 2336 
      hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2337 
 
 2337 
    }
2338 
  return errorcode;
 2338 
 
2339 
}
 2339 
    /* Clear the Error flags in the SR register */
2340 
 
 2340 
    __HAL_SPI_CLEAR_OVRFLAG(hspi);
2341 
/**
 2341 
 
2342 
  * @brief  Pause the DMA Transfer.
 2342 
    /* Restore hspi->State to Ready */
2343 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 2343 
    hspi->State = HAL_SPI_STATE_READY;
2344 
  *               the configuration information for the specified SPI module.
 2344 
 
2345 
  * @retval HAL status
 2345 
    /* As no DMA to be aborted, call directly user Abort complete callback */
2346 
  */
 2346 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2347 
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
 2347 
    hspi->AbortCpltCallback(hspi);
2348 
{
 2348 
#else
2349 
  /* Process Locked */
 2349 
    HAL_SPI_AbortCpltCallback(hspi);
2350 
  __HAL_LOCK(hspi);
 2350 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2351 
 
 2351 
  }
2352 
  /* Disable the SPI DMA Tx & Rx requests */
 2352 
 
2353 
  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
 2353 
  return errorcode;
2354 
 
 2354 
}
2355 
  /* Process Unlocked */
 2355 
 
2356 
  __HAL_UNLOCK(hspi);
 2356 
/**
2357 
 
 2357 
  * @brief  Pause the DMA Transfer.
2358 
  return HAL_OK;
 2358 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
2359 
}
 2359 
  *               the configuration information for the specified SPI module.
2360 
 
 2360 
  * @retval HAL status
2361 
/**
 2361 
  */
2362 
  * @brief  Resume the DMA Transfer.
 2362 
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
2363 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 2363 
{
2364 
  *               the configuration information for the specified SPI module.
 2364 
  /* Process Locked */
2365 
  * @retval HAL status
 2365 
  __HAL_LOCK(hspi);
2366 
  */
 2366 
 
2367 
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
 2367 
  /* Disable the SPI DMA Tx & Rx requests */
2368 
{
 2368 
  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2369 
  /* Process Locked */
 2369 
 
2370 
  __HAL_LOCK(hspi);
 2370 
  /* Process Unlocked */
2371 
 
 2371 
  __HAL_UNLOCK(hspi);
2372 
  /* Enable the SPI DMA Tx & Rx requests */
 2372 
 
2373 
  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
 2373 
  return HAL_OK;
2374 
 
 2374 
}
2375 
  /* Process Unlocked */
 2375 
 
2376 
  __HAL_UNLOCK(hspi);
 2376 
/**
2377 
 
 2377 
  * @brief  Resume the DMA Transfer.
2378 
  return HAL_OK;
 2378 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
2379 
}
 2379 
  *               the configuration information for the specified SPI module.
2380 
 
 2380 
  * @retval HAL status
2381 
/**
 2381 
  */
2382 
  * @brief  Stop the DMA Transfer.
 2382 
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
2383 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 2383 
{
2384 
  *               the configuration information for the specified SPI module.
 2384 
  /* Process Locked */
2385 
  * @retval HAL status
 2385 
  __HAL_LOCK(hspi);
2386 
  */
 2386 
 
2387 
HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
 2387 
  /* Enable the SPI DMA Tx & Rx requests */
2388 
{
 2388 
  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2389 
  HAL_StatusTypeDef errorcode = HAL_OK;
 2389 
 
2390 
  /* The Lock is not implemented on this API to allow the user application
 2390 
  /* Process Unlocked */
2391 
     to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
 2391 
  __HAL_UNLOCK(hspi);
2392 
     when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
 2392 
 
2393 
     and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
 2393 
  return HAL_OK;
2394 
     */
 2394 
}
2395 
 
 2395 
 
2396 
  /* Abort the SPI DMA tx Stream/Channel  */
 2396 
/**
2397 
  if (hspi->hdmatx != NULL)
 2397 
  * @brief  Stop the DMA Transfer.
2398 
  {
 2398 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
2399 
    if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx))
 2399 
  *               the configuration information for the specified SPI module.
2400 
    {
 2400 
  * @retval HAL status
2401 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
 2401 
  */
2402 
      errorcode = HAL_ERROR;
 2402 
HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
2403 
    }
 2403 
{
2404 
  }
 2404 
  HAL_StatusTypeDef errorcode = HAL_OK;
2405 
  /* Abort the SPI DMA rx Stream/Channel  */
 2405 
  /* The Lock is not implemented on this API to allow the user application
2406 
  if (hspi->hdmarx != NULL)
 2406 
     to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
2407 
  {
 2407 
     when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
2408 
    if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx))
 2408 
     and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
2409 
    {
 2409 
     */
2410 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
 2410 
 
2411 
      errorcode = HAL_ERROR;
 2411 
  /* Abort the SPI DMA tx Stream/Channel  */
2412 
    }
 2412 
  if (hspi->hdmatx != NULL)
2413 
  }
 2413 
  {
2414 
 
 2414 
    if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx))
2415 
  /* Disable the SPI DMA Tx & Rx requests */
 2415 
    {
2416 
  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
 2416 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2417 
  hspi->State = HAL_SPI_STATE_READY;
 2417 
      errorcode = HAL_ERROR;
2418 
  return errorcode;
 2418 
    }
2419 
}
 2419 
  }
2420 
 
 2420 
  /* Abort the SPI DMA rx Stream/Channel  */
2421 
/**
 2421 
  if (hspi->hdmarx != NULL)
2422 
  * @brief  Handle SPI interrupt request.
 2422 
  {
2423 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 2423 
    if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx))
2424 
  *               the configuration information for the specified SPI module.
 2424 
    {
2425 
  * @retval None
 2425 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2426 
  */
 2426 
      errorcode = HAL_ERROR;
2427 
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
 2427 
    }
2428 
{
 2428 
  }
2429 
  uint32_t itsource = hspi->Instance->CR2;
 2429 
 
2430 
  uint32_t itflag   = hspi->Instance->SR;
 2430 
  /* Disable the SPI DMA Tx & Rx requests */
2431 
 
 2431 
  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2432 
  /* SPI in mode Receiver ----------------------------------------------------*/
 2432 
  hspi->State = HAL_SPI_STATE_READY;
2433 
  if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
 2433 
  return errorcode;
2434 
      (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
 2434 
}
2435 
  {
 2435 
 
2436 
    hspi->RxISR(hspi);
 2436 
/**
2437 
    return;
 2437 
  * @brief  Handle SPI interrupt request.
2438 
  }
 2438 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
2439 
 
 2439 
  *               the configuration information for the specified SPI module.
2440 
  /* SPI in mode Transmitter -------------------------------------------------*/
 2440 
  * @retval None
2441 
  if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))
 2441 
  */
2442 
  {
 2442 
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
2443 
    hspi->TxISR(hspi);
 2443 
{
2444 
    return;
 2444 
  uint32_t itsource = hspi->Instance->CR2;
2445 
  }
 2445 
  uint32_t itflag   = hspi->Instance->SR;
2446 
 
 2446 
 
2447 
  /* SPI in Error Treatment --------------------------------------------------*/
 2447 
  /* SPI in mode Receiver ----------------------------------------------------*/
2448 
  if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET))
 2448 
  if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
2449 
      && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
 2449 
      (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
2450 
  {
 2450 
  {
2451 
    /* SPI Overrun error interrupt occurred ----------------------------------*/
 2451 
    hspi->RxISR(hspi);
2452 
    if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
 2452 
    return;
2453 
    {
 2453 
  }
2454 
      if (hspi->State != HAL_SPI_STATE_BUSY_TX)
 2454 
 
2455 
      {
 2455 
  /* SPI in mode Transmitter -------------------------------------------------*/
2456 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
 2456 
  if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))
2457 
        __HAL_SPI_CLEAR_OVRFLAG(hspi);
 2457 
  {
2458 
      }
 2458 
    hspi->TxISR(hspi);
2459 
      else
 2459 
    return;
2460 
      {
 2460 
  }
2461 
        __HAL_SPI_CLEAR_OVRFLAG(hspi);
 2461 
 
2462 
        return;
 2462 
  /* SPI in Error Treatment --------------------------------------------------*/
2463 
      }
 2463 
  if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET))
2464 
    }
 2464 
      && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
2465 
 
 2465 
  {
2466 
    /* SPI Mode Fault error interrupt occurred -------------------------------*/
 2466 
    /* SPI Overrun error interrupt occurred ----------------------------------*/
2467 
    if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)
 2467 
    if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
2468 
    {
 2468 
    {
2469 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
 2469 
      if (hspi->State != HAL_SPI_STATE_BUSY_TX)
2470 
      __HAL_SPI_CLEAR_MODFFLAG(hspi);
 2470 
      {
2471 
    }
 2471 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
2472 
 
 2472 
        __HAL_SPI_CLEAR_OVRFLAG(hspi);
2473 
    /* SPI Frame error interrupt occurred ------------------------------------*/
 2473 
      }
2474 
 
 2474 
      else
2475 
    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
 2475 
      {
2476 
    {
 2476 
        __HAL_SPI_CLEAR_OVRFLAG(hspi);
2477 
      /* Disable all interrupts */
 2477 
        return;
2478 
      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
 2478 
      }
2479 
 
 2479 
    }
2480 
      hspi->State = HAL_SPI_STATE_READY;
 2480 
 
2481 
      /* Disable the SPI DMA requests if enabled */
 2481 
    /* SPI Mode Fault error interrupt occurred -------------------------------*/
2482 
      if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
 2482 
    if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)
2483 
      {
 2483 
    {
2484 
        CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
 2484 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
2485 
 
 2485 
      __HAL_SPI_CLEAR_MODFFLAG(hspi);
2486 
        /* Abort the SPI DMA Rx channel */
 2486 
    }
2487 
        if (hspi->hdmarx != NULL)
 2487 
 
2488 
        {
 2488 
    /* SPI Frame error interrupt occurred ------------------------------------*/
2489 
          /* Set the SPI DMA Abort callback :
 2489 
 
2490 
          will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
 2490 
    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2491 
          hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
 2491 
    {
2492 
          if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
 2492 
      /* Disable all interrupts */
2493 
          {
 2493 
      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
2494 
            SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
 2494 
 
2495 
          }
 2495 
      hspi->State = HAL_SPI_STATE_READY;
2496 
        }
 2496 
      /* Disable the SPI DMA requests if enabled */
2497 
        /* Abort the SPI DMA Tx channel */
 2497 
      if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
2498 
        if (hspi->hdmatx != NULL)
 2498 
      {
2499 
        {
 2499 
        CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
2500 
          /* Set the SPI DMA Abort callback :
 2500 
 
2501 
          will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
 2501 
        /* Abort the SPI DMA Rx channel */
2502 
          hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
 2502 
        if (hspi->hdmarx != NULL)
2503 
          if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
 2503 
        {
2504 
          {
 2504 
          /* Set the SPI DMA Abort callback :
2505 
            SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
 2505 
          will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
2506 
          }
 2506 
          hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
2507 
        }
 2507 
          if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
2508 
      }
 2508 
          {
2509 
      else
 2509 
            SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2510 
      {
 2510 
          }
2511 
        /* Call user error callback */
 2511 
        }
2512 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 2512 
        /* Abort the SPI DMA Tx channel */
2513 
        hspi->ErrorCallback(hspi);
 2513 
        if (hspi->hdmatx != NULL)
2514 
#else
 2514 
        {
2515 
        HAL_SPI_ErrorCallback(hspi);
 2515 
          /* Set the SPI DMA Abort callback :
2516 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 2516 
          will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
2517 
      }
 2517 
          hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
2518 
    }
 2518 
          if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
2519 
    return;
 2519 
          {
2520 
  }
 2520 
            SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2521 
}
 2521 
          }
2522 
 
 2522 
        }
2523 
/**
 2523 
      }
2524 
  * @brief  Tx Transfer completed callback.
 2524 
      else
2525 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 2525 
      {
2526 
  *               the configuration information for SPI module.
 2526 
        /* Call user error callback */
2527 
  * @retval None
 2527 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2528 
  */
 2528 
        hspi->ErrorCallback(hspi);
2529 
__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
 2529 
#else
2530 
{
 2530 
        HAL_SPI_ErrorCallback(hspi);
2531 
  /* Prevent unused argument(s) compilation warning */
 2531 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2532 
  UNUSED(hspi);
 2532 
      }
2533 
 
 2533 
    }
2534 
  /* NOTE : This function should not be modified, when the callback is needed,
 2534 
    return;
2535 
            the HAL_SPI_TxCpltCallback should be implemented in the user file
 2535 
  }
2536 
   */
 2536 
}
2537 
}
 2537 
 
2538 
 
 2538 
/**
2539 
/**
 2539 
  * @brief  Tx Transfer completed callback.
2540 
  * @brief  Rx Transfer completed callback.
 2540 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
2541 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 2541 
  *               the configuration information for SPI module.
2542 
  *               the configuration information for SPI module.
 2542 
  * @retval None
2543 
  * @retval None
 2543 
  */
2544 
  */
 2544 
__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
2545 
__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
 2545 
{
2546 
{
 2546 
  /* Prevent unused argument(s) compilation warning */
2547 
  /* Prevent unused argument(s) compilation warning */
 2547 
  UNUSED(hspi);
2548 
  UNUSED(hspi);
 2548 
 
2549 
 
 2549 
  /* NOTE : This function should not be modified, when the callback is needed,
2550 
  /* NOTE : This function should not be modified, when the callback is needed,
 2550 
            the HAL_SPI_TxCpltCallback should be implemented in the user file
2551 
            the HAL_SPI_RxCpltCallback should be implemented in the user file
 2551 
   */
2552 
   */
 2552 
}
2553 
}
 2553 
 
2554 
 
 2554 
/**
2555 
/**
 2555 
  * @brief  Rx Transfer completed callback.
2556 
  * @brief  Tx and Rx Transfer completed callback.
 2556 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
2557 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 2557 
  *               the configuration information for SPI module.
2558 
  *               the configuration information for SPI module.
 2558 
  * @retval None
2559 
  * @retval None
 2559 
  */
2560 
  */
 2560 
__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
2561 
__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
 2561 
{
2562 
{
 2562 
  /* Prevent unused argument(s) compilation warning */
2563 
  /* Prevent unused argument(s) compilation warning */
 2563 
  UNUSED(hspi);
2564 
  UNUSED(hspi);
 2564 
 
2565 
 
 2565 
  /* NOTE : This function should not be modified, when the callback is needed,
2566 
  /* NOTE : This function should not be modified, when the callback is needed,
 2566 
            the HAL_SPI_RxCpltCallback should be implemented in the user file
2567 
            the HAL_SPI_TxRxCpltCallback should be implemented in the user file
 2567 
   */
2568 
   */
 2568 
}
2569 
}
 2569 
 
2570 
 
 2570 
/**
2571 
/**
 2571 
  * @brief  Tx and Rx Transfer completed callback.
2572 
  * @brief  Tx Half Transfer completed callback.
 2572 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
2573 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 2573 
  *               the configuration information for SPI module.
2574 
  *               the configuration information for SPI module.
 2574 
  * @retval None
2575 
  * @retval None
 2575 
  */
2576 
  */
 2576 
__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
2577 
__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
 2577 
{
2578 
{
 2578 
  /* Prevent unused argument(s) compilation warning */
2579 
  /* Prevent unused argument(s) compilation warning */
 2579 
  UNUSED(hspi);
2580 
  UNUSED(hspi);
 2580 
 
2581 
 
 2581 
  /* NOTE : This function should not be modified, when the callback is needed,
2582 
  /* NOTE : This function should not be modified, when the callback is needed,
 2582 
            the HAL_SPI_TxRxCpltCallback should be implemented in the user file
2583 
            the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
 2583 
   */
2584 
   */
 2584 
}
2585 
}
 2585 
 
2586 
 
 2586 
/**
2587 
/**
 2587 
  * @brief  Tx Half Transfer completed callback.
2588 
  * @brief  Rx Half Transfer completed callback.
 2588 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
2589 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 2589 
  *               the configuration information for SPI module.
2590 
  *               the configuration information for SPI module.
 2590 
  * @retval None
2591 
  * @retval None
 2591 
  */
2592 
  */
 2592 
__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2593 
__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
 2593 
{
2594 
{
 2594 
  /* Prevent unused argument(s) compilation warning */
2595 
  /* Prevent unused argument(s) compilation warning */
 2595 
  UNUSED(hspi);
2596 
  UNUSED(hspi);
 2596 
 
2597 
 
 2597 
  /* NOTE : This function should not be modified, when the callback is needed,
2598 
  /* NOTE : This function should not be modified, when the callback is needed,
 2598 
            the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
2599 
            the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
 2599 
   */
2600 
   */
 2600 
}
2601 
}
 2601 
 
2602 
 
 2602 
/**
2603 
/**
 2603 
  * @brief  Rx Half Transfer completed callback.
2604 
  * @brief  Tx and Rx Half Transfer callback.
 2604 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
2605 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 2605 
  *               the configuration information for SPI module.
2606 
  *               the configuration information for SPI module.
 2606 
  * @retval None
2607 
  * @retval None
 2607 
  */
2608 
  */
 2608 
__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2609 
__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
 2609 
{
2610 
{
 2610 
  /* Prevent unused argument(s) compilation warning */
2611 
  /* Prevent unused argument(s) compilation warning */
 2611 
  UNUSED(hspi);
2612 
  UNUSED(hspi);
 2612 
 
2613 
 
 2613 
  /* NOTE : This function should not be modified, when the callback is needed,
2614 
  /* NOTE : This function should not be modified, when the callback is needed,
 2614 
            the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
2615 
            the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
 2615 
   */
2616 
   */
 2616 
}
2617 
}
 2617 
 
2618 
 
 2618 
/**
2619 
/**
 2619 
  * @brief  Tx and Rx Half Transfer callback.
2620 
  * @brief  SPI error callback.
 2620 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
2621 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 2621 
  *               the configuration information for SPI module.
2622 
  *               the configuration information for SPI module.
 2622 
  * @retval None
2623 
  * @retval None
 2623 
  */
2624 
  */
 2624 
__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2625 
__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
 2625 
{
2626 
{
 2626 
  /* Prevent unused argument(s) compilation warning */
2627 
  /* Prevent unused argument(s) compilation warning */
 2627 
  UNUSED(hspi);
2628 
  UNUSED(hspi);
 2628 
 
2629 
 
 2629 
  /* NOTE : This function should not be modified, when the callback is needed,
2630 
  /* NOTE : This function should not be modified, when the callback is needed,
 2630 
            the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
2631 
            the HAL_SPI_ErrorCallback should be implemented in the user file
 2631 
   */
2632 
   */
 2632 
}
2633 
  /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
 2633 
 
2634 
            and user can use HAL_SPI_GetError() API to check the latest error occurred
 2634 
/**
2635 
   */
 2635 
  * @brief  SPI error callback.
2636 
}
 2636 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
2637 
 
 2637 
  *               the configuration information for SPI module.
2638 
/**
 2638 
  * @retval None
2639 
  * @brief  SPI Abort Complete callback.
 2639 
  */
2640 
  * @param  hspi SPI handle.
 2640 
__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
2641 
  * @retval None
 2641 
{
2642 
  */
 2642 
  /* Prevent unused argument(s) compilation warning */
2643 
__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
 2643 
  UNUSED(hspi);
2644 
{
 2644 
 
2645 
  /* Prevent unused argument(s) compilation warning */
 2645 
  /* NOTE : This function should not be modified, when the callback is needed,
2646 
  UNUSED(hspi);
 2646 
            the HAL_SPI_ErrorCallback should be implemented in the user file
2647 
 
 2647 
   */
2648 
  /* NOTE : This function should not be modified, when the callback is needed,
 2648 
  /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
2649 
            the HAL_SPI_AbortCpltCallback can be implemented in the user file.
 2649 
            and user can use HAL_SPI_GetError() API to check the latest error occurred
2650 
   */
 2650 
   */
2651 
}
 2651 
}
2652 
 
 2652 
 
2653 
/**
 2653 
/**
2654 
  * @}
 2654 
  * @brief  SPI Abort Complete callback.
2655 
  */
 2655 
  * @param  hspi SPI handle.
2656 
 
 2656 
  * @retval None
2657 
/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
 2657 
  */
2658 
  * @brief   SPI control functions
 2658 
__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
2659 
  *
 2659 
{
2660 
@verbatim
 2660 
  /* Prevent unused argument(s) compilation warning */
2661 
 ===============================================================================
 2661 
  UNUSED(hspi);
2662 
                      ##### Peripheral State and Errors functions #####
 2662 
 
2663 
 ===============================================================================
 2663 
  /* NOTE : This function should not be modified, when the callback is needed,
2664 
    [..]
 2664 
            the HAL_SPI_AbortCpltCallback can be implemented in the user file.
2665 
    This subsection provides a set of functions allowing to control the SPI.
 2665 
   */
2666 
     (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
 2666 
}
2667 
     (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
 2667 
 
2668 
@endverbatim
 2668 
/**
2669 
  * @{
 2669 
  * @}
2670 
  */
 2670 
  */
2671 
 
 2671 
 
2672 
/**
 2672 
/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
2673 
  * @brief  Return the SPI handle state.
 2673 
  * @brief   SPI control functions
2674 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 2674 
  *
2675 
  *               the configuration information for SPI module.
 2675 
@verbatim
2676 
  * @retval SPI state
 2676 
 ===============================================================================
2677 
  */
 2677 
                      ##### Peripheral State and Errors functions #####
2678 
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
 2678 
 ===============================================================================
2679 
{
 2679 
    [..]
2680 
  /* Return SPI handle state */
 2680 
    This subsection provides a set of functions allowing to control the SPI.
2681 
  return hspi->State;
 2681 
     (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
2682 
}
 2682 
     (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
2683 
 
 2683 
@endverbatim
2684 
/**
 2684 
  * @{
2685 
  * @brief  Return the SPI error code.
 2685 
  */
2686 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 2686 
 
2687 
  *               the configuration information for SPI module.
 2687 
/**
2688 
  * @retval SPI error code in bitmap format
 2688 
  * @brief  Return the SPI handle state.
2689 
  */
 2689 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
2690 
uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
 2690 
  *               the configuration information for SPI module.
2691 
{
 2691 
  * @retval SPI state
2692 
  /* Return SPI ErrorCode */
 2692 
  */
2693 
  return hspi->ErrorCode;
 2693 
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
2694 
}
 2694 
{
2695 
 
 2695 
  /* Return SPI handle state */
2696 
/**
 2696 
  return hspi->State;
2697 
  * @}
 2697 
}
2698 
  */
 2698 
 
2699 
 
 2699 
/**
2700 
/**
 2700 
  * @brief  Return the SPI error code.
2701 
  * @}
 2701 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
2702 
  */
 2702 
  *               the configuration information for SPI module.
2703 
 
 2703 
  * @retval SPI error code in bitmap format
2704 
/** @addtogroup SPI_Private_Functions
 2704 
  */
2705 
  * @brief   Private functions
 2705 
uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
2706 
  * @{
 2706 
{
2707 
  */
 2707 
  /* Return SPI ErrorCode */
2708 
 
 2708 
  return hspi->ErrorCode;
2709 
/**
 2709 
}
2710 
  * @brief  DMA SPI transmit process complete callback.
 2710 
 
2711 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
 2711 
/**
2712 
  *               the configuration information for the specified DMA module.
 2712 
  * @}
2713 
  * @retval None
 2713 
  */
2714 
  */
 2714 
 
2715 
static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
 2715 
/**
2716 
{
 2716 
  * @}
2717 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
 2717 
  */
2718 
  uint32_t tickstart;
 2718 
 
2719 
 
 2719 
/** @addtogroup SPI_Private_Functions
2720 
  /* Init tickstart for timeout management*/
 2720 
  * @brief   Private functions
2721 
  tickstart = HAL_GetTick();
 2721 
  * @{
2722 
 
 2722 
  */
2723 
  /* DMA Normal Mode */
 2723 
 
2724 
  if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
 2724 
/**
2725 
  {
 2725 
  * @brief  DMA SPI transmit process complete callback.
2726 
    /* Disable ERR interrupt */
 2726 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
2727 
    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
 2727 
  *               the configuration information for the specified DMA module.
2728 
 
 2728 
  * @retval None
2729 
    /* Disable Tx DMA Request */
 2729 
  */
2730 
    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
 2730 
static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
2731 
 
 2731 
{
2732 
    /* Check the end of the transaction */
 2732 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2733 
    if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
 2733 
  uint32_t tickstart;
2734 
    {
 2734 
 
2735 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
 2735 
  /* Init tickstart for timeout management*/
2736 
    }
 2736 
  tickstart = HAL_GetTick();
2737 
 
 2737 
 
2738 
    /* Clear overrun flag in 2 Lines communication mode because received data is not read */
 2738 
  /* DMA Normal Mode */
2739 
    if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
 2739 
  if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
2740 
    {
 2740 
  {
2741 
      __HAL_SPI_CLEAR_OVRFLAG(hspi);
 2741 
    /* Disable ERR interrupt */
2742 
    }
 2742 
    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
2743 
 
 2743 
 
2744 
    hspi->TxXferCount = 0U;
 2744 
    /* Disable Tx DMA Request */
2745 
    hspi->State = HAL_SPI_STATE_READY;
 2745 
    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
2746 
 
 2746 
 
2747 
    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
 2747 
    /* Check the end of the transaction */
2748 
    {
 2748 
    if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
2749 
      /* Call user error callback */
 2749 
    {
2750 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 2750 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
2751 
      hspi->ErrorCallback(hspi);
 2751 
    }
2752 
#else
 2752 
 
2753 
      HAL_SPI_ErrorCallback(hspi);
 2753 
    /* Clear overrun flag in 2 Lines communication mode because received data is not read */
2754 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 2754 
    if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
2755 
      return;
 2755 
    {
2756 
    }
 2756 
      __HAL_SPI_CLEAR_OVRFLAG(hspi);
2757 
  }
 2757 
    }
2758 
  /* Call user Tx complete callback */
 2758 
 
2759 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 2759 
    hspi->TxXferCount = 0U;
2760 
  hspi->TxCpltCallback(hspi);
 2760 
    hspi->State = HAL_SPI_STATE_READY;
2761 
#else
 2761 
 
2762 
  HAL_SPI_TxCpltCallback(hspi);
 2762 
    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2763 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 2763 
    {
2764 
}
 2764 
      /* Call user error callback */
2765 
 
 2765 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2766 
/**
 2766 
      hspi->ErrorCallback(hspi);
2767 
  * @brief  DMA SPI receive process complete callback.
 2767 
#else
2768 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
 2768 
      HAL_SPI_ErrorCallback(hspi);
2769 
  *               the configuration information for the specified DMA module.
 2769 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2770 
  * @retval None
 2770 
      return;
2771 
  */
 2771 
    }
2772 
static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
 2772 
  }
2773 
{
 2773 
  /* Call user Tx complete callback */
2774 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
 2774 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2775 
  uint32_t tickstart;
 2775 
  hspi->TxCpltCallback(hspi);
2776 
#if (USE_SPI_CRC != 0U)
 2776 
#else
2777 
  __IO uint32_t tmpreg = 0U;
 2777 
  HAL_SPI_TxCpltCallback(hspi);
2778 
#endif /* USE_SPI_CRC */
 2778 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2779 
 
 2779 
}
2780 
  /* Init tickstart for timeout management*/
 2780 
 
2781 
  tickstart = HAL_GetTick();
 2781 
/**
2782 
 
 2782 
  * @brief  DMA SPI receive process complete callback.
2783 
  /* DMA Normal Mode */
 2783 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
2784 
  if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
 2784 
  *               the configuration information for the specified DMA module.
2785 
  {
 2785 
  * @retval None
2786 
    /* Disable ERR interrupt */
 2786 
  */
2787 
    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
 2787 
static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
2788 
 
 2788 
{
2789 
#if (USE_SPI_CRC != 0U)
 2789 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2790 
    /* CRC handling */
 2790 
  uint32_t tickstart;
2791 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 2791 
#if (USE_SPI_CRC != 0U)
2792 
    {
 2792 
  __IO uint32_t tmpreg = 0U;
2793 
      /* Wait until RXNE flag */
 2793 
#endif /* USE_SPI_CRC */
2794 
      if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
 2794 
 
2795 
      {
 2795 
  /* Init tickstart for timeout management*/
2796 
        /* Error on the CRC reception */
 2796 
  tickstart = HAL_GetTick();
2797 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
 2797 
 
2798 
      }
 2798 
  /* DMA Normal Mode */
2799 
      /* Read CRC */
 2799 
  if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
2800 
      tmpreg = READ_REG(hspi->Instance->DR);
 2800 
  {
2801 
      /* To avoid GCC warning */
 2801 
    /* Disable ERR interrupt */
2802 
      UNUSED(tmpreg);
 2802 
    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
2803 
    }
 2803 
 
2804 
#endif /* USE_SPI_CRC */
 2804 
#if (USE_SPI_CRC != 0U)
2805 
 
 2805 
    /* CRC handling */
2806 
    /* Check if we are in Master RX 2 line mode */
 2806 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2807 
    if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
 2807 
    {
2808 
    {
 2808 
      /* Wait until RXNE flag */
2809 
      /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
 2809 
      if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
2810 
      CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
 2810 
      {
2811 
    }
 2811 
        /* Error on the CRC reception */
2812 
    else
 2812 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
2813 
    {
 2813 
      }
2814 
      /* Normal case */
 2814 
      /* Read CRC */
2815 
      CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
 2815 
      tmpreg = READ_REG(hspi->Instance->DR);
2816 
    }
 2816 
      /* To avoid GCC warning */
2817 
 
 2817 
      UNUSED(tmpreg);
2818 
    /* Check the end of the transaction */
 2818 
    }
2819 
    if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
 2819 
#endif /* USE_SPI_CRC */
2820 
    {
 2820 
 
2821 
      hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
 2821 
    /* Check if we are in Master RX 2 line mode */
2822 
    }
 2822 
    if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
2823 
 
 2823 
    {
2824 
    hspi->RxXferCount = 0U;
 2824 
      /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
2825 
    hspi->State = HAL_SPI_STATE_READY;
 2825 
      CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2826 
 
 2826 
    }
2827 
#if (USE_SPI_CRC != 0U)
 2827 
    else
2828 
    /* Check if CRC error occurred */
 2828 
    {
2829 
    if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
 2829 
      /* Normal case */
2830 
    {
 2830 
      CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
2831 
      /* Check if CRC error is valid or not (workaround to be applied or not) */
 2831 
    }
2832 
      if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
 2832 
 
2833 
      {
 2833 
    /* Check the end of the transaction */
2834 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
 2834 
    if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
2835 
 
 2835 
    {
2836 
        /* Reset CRC Calculation */
 2836 
      hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
2837 
        SPI_RESET_CRC(hspi);
 2837 
    }
2838 
      }
 2838 
 
2839 
      else
 2839 
    hspi->RxXferCount = 0U;
2840 
      {
 2840 
    hspi->State = HAL_SPI_STATE_READY;
2841 
        __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
 2841 
 
2842 
      }
 2842 
#if (USE_SPI_CRC != 0U)
2843 
    }
 2843 
    /* Check if CRC error occurred */
2844 
#endif /* USE_SPI_CRC */
 2844 
    if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
2845 
 
 2845 
    {
2846 
    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
 2846 
      /* Check if CRC error is valid or not (workaround to be applied or not) */
2847 
    {
 2847 
      if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
2848 
      /* Call user error callback */
 2848 
      {
2849 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 2849 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
2850 
      hspi->ErrorCallback(hspi);
 2850 
 
2851 
#else
 2851 
        /* Reset CRC Calculation */
2852 
      HAL_SPI_ErrorCallback(hspi);
 2852 
        SPI_RESET_CRC(hspi);
2853 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 2853 
      }
2854 
      return;
 2854 
      else
2855 
    }
 2855 
      {
2856 
  }
 2856 
        __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
2857 
  /* Call user Rx complete callback */
 2857 
      }
2858 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 2858 
    }
2859 
  hspi->RxCpltCallback(hspi);
 2859 
#endif /* USE_SPI_CRC */
2860 
#else
 2860 
 
2861 
  HAL_SPI_RxCpltCallback(hspi);
 2861 
    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2862 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 2862 
    {
2863 
}
 2863 
      /* Call user error callback */
2864 
 
 2864 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2865 
/**
 2865 
      hspi->ErrorCallback(hspi);
2866 
  * @brief  DMA SPI transmit receive process complete callback.
 2866 
#else
2867 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
 2867 
      HAL_SPI_ErrorCallback(hspi);
2868 
  *               the configuration information for the specified DMA module.
 2868 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2869 
  * @retval None
 2869 
      return;
2870 
  */
 2870 
    }
2871 
static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
 2871 
  }
2872 
{
 2872 
  /* Call user Rx complete callback */
2873 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
 2873 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2874 
  uint32_t tickstart;
 2874 
  hspi->RxCpltCallback(hspi);
2875 
#if (USE_SPI_CRC != 0U)
 2875 
#else
2876 
  __IO uint32_t tmpreg = 0U;
 2876 
  HAL_SPI_RxCpltCallback(hspi);
2877 
#endif /* USE_SPI_CRC */
 2877 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2878 
 
 2878 
}
2879 
  /* Init tickstart for timeout management*/
 2879 
 
2880 
  tickstart = HAL_GetTick();
 2880 
/**
2881 
 
 2881 
  * @brief  DMA SPI transmit receive process complete callback.
2882 
  /* DMA Normal Mode */
 2882 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
2883 
  if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
 2883 
  *               the configuration information for the specified DMA module.
2884 
  {
 2884 
  * @retval None
2885 
    /* Disable ERR interrupt */
 2885 
  */
2886 
    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
 2886 
static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
2887 
 
 2887 
{
2888 
#if (USE_SPI_CRC != 0U)
 2888 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2889 
    /* CRC handling */
 2889 
  uint32_t tickstart;
2890 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 2890 
#if (USE_SPI_CRC != 0U)
2891 
    {
 2891 
  __IO uint32_t tmpreg = 0U;
2892 
      /* Wait the CRC data */
 2892 
#endif /* USE_SPI_CRC */
2893 
      if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
 2893 
 
2894 
      {
 2894 
  /* Init tickstart for timeout management*/
2895 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
 2895 
  tickstart = HAL_GetTick();
2896 
      }
 2896 
 
2897 
      /* Read CRC to Flush DR and RXNE flag */
 2897 
  /* DMA Normal Mode */
2898 
      tmpreg = READ_REG(hspi->Instance->DR);
 2898 
  if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
2899 
      /* To avoid GCC warning */
 2899 
  {
2900 
      UNUSED(tmpreg);
 2900 
    /* Disable ERR interrupt */
2901 
    }
 2901 
    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
2902 
#endif /* USE_SPI_CRC */
 2902 
 
2903 
 
 2903 
#if (USE_SPI_CRC != 0U)
2904 
    /* Check the end of the transaction */
 2904 
    /* CRC handling */
2905 
    if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
 2905 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2906 
    {
 2906 
    {
2907 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
 2907 
      /* Wait the CRC data */
2908 
    }
 2908 
      if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
2909 
 
 2909 
      {
2910 
    /* Disable Rx/Tx DMA Request */
 2910 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
2911 
    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
 2911 
      }
2912 
 
 2912 
      /* Read CRC to Flush DR and RXNE flag */
2913 
    hspi->TxXferCount = 0U;
 2913 
      tmpreg = READ_REG(hspi->Instance->DR);
2914 
    hspi->RxXferCount = 0U;
 2914 
      /* To avoid GCC warning */
2915 
    hspi->State = HAL_SPI_STATE_READY;
 2915 
      UNUSED(tmpreg);
2916 
 
 2916 
    }
2917 
#if (USE_SPI_CRC != 0U)
 2917 
#endif /* USE_SPI_CRC */
2918 
    /* Check if CRC error occurred */
 2918 
 
2919 
    if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
 2919 
    /* Check the end of the transaction */
2920 
    {
 2920 
    if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
2921 
      /* Check if CRC error is valid or not (workaround to be applied or not) */
 2921 
    {
2922 
      if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
 2922 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
2923 
      {
 2923 
    }
2924 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
 2924 
 
2925 
 
 2925 
    /* Disable Rx/Tx DMA Request */
2926 
        /* Reset CRC Calculation */
 2926 
    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2927 
        SPI_RESET_CRC(hspi);
 2927 
 
2928 
      }
 2928 
    hspi->TxXferCount = 0U;
2929 
      else
 2929 
    hspi->RxXferCount = 0U;
2930 
      {
 2930 
    hspi->State = HAL_SPI_STATE_READY;
2931 
        __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
 2931 
 
2932 
      }
 2932 
#if (USE_SPI_CRC != 0U)
2933 
    }
 2933 
    /* Check if CRC error occurred */
2934 
#endif /* USE_SPI_CRC */
 2934 
    if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
2935 
 
 2935 
    {
2936 
    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
 2936 
      /* Check if CRC error is valid or not (workaround to be applied or not) */
2937 
    {
 2937 
      if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
2938 
      /* Call user error callback */
 2938 
      {
2939 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 2939 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
2940 
      hspi->ErrorCallback(hspi);
 2940 
 
2941 
#else
 2941 
        /* Reset CRC Calculation */
2942 
      HAL_SPI_ErrorCallback(hspi);
 2942 
        SPI_RESET_CRC(hspi);
2943 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 2943 
      }
2944 
      return;
 2944 
      else
2945 
    }
 2945 
      {
2946 
  }
 2946 
        __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
2947 
  /* Call user TxRx complete callback */
 2947 
      }
2948 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 2948 
    }
2949 
  hspi->TxRxCpltCallback(hspi);
 2949 
#endif /* USE_SPI_CRC */
2950 
#else
 2950 
 
2951 
  HAL_SPI_TxRxCpltCallback(hspi);
 2951 
    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2952 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 2952 
    {
2953 
}
 2953 
      /* Call user error callback */
2954 
 
 2954 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2955 
/**
 2955 
      hspi->ErrorCallback(hspi);
2956 
  * @brief  DMA SPI half transmit process complete callback.
 2956 
#else
2957 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
 2957 
      HAL_SPI_ErrorCallback(hspi);
2958 
  *               the configuration information for the specified DMA module.
 2958 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2959 
  * @retval None
 2959 
      return;
2960 
  */
 2960 
    }
2961 
static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
 2961 
  }
2962 
{
 2962 
  /* Call user TxRx complete callback */
2963 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
 2963 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2964 
 
 2964 
  hspi->TxRxCpltCallback(hspi);
2965 
  /* Call user Tx half complete callback */
 2965 
#else
2966 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 2966 
  HAL_SPI_TxRxCpltCallback(hspi);
2967 
  hspi->TxHalfCpltCallback(hspi);
 2967 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2968 
#else
 2968 
}
2969 
  HAL_SPI_TxHalfCpltCallback(hspi);
 2969 
 
2970 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 2970 
/**
2971 
}
 2971 
  * @brief  DMA SPI half transmit process complete callback.
2972 
 
 2972 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
2973 
/**
 2973 
  *               the configuration information for the specified DMA module.
2974 
  * @brief  DMA SPI half receive process complete callback
 2974 
  * @retval None
2975 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
 2975 
  */
2976 
  *               the configuration information for the specified DMA module.
 2976 
static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
2977 
  * @retval None
 2977 
{
2978 
  */
 2978 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2979 
static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
 2979 
 
2980 
{
 2980 
  /* Call user Tx half complete callback */
2981 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
 2981 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2982 
 
 2982 
  hspi->TxHalfCpltCallback(hspi);
2983 
  /* Call user Rx half complete callback */
 2983 
#else
2984 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 2984 
  HAL_SPI_TxHalfCpltCallback(hspi);
2985 
  hspi->RxHalfCpltCallback(hspi);
 2985 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2986 
#else
 2986 
}
2987 
  HAL_SPI_RxHalfCpltCallback(hspi);
 2987 
 
2988 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 2988 
/**
2989 
}
 2989 
  * @brief  DMA SPI half receive process complete callback
2990 
 
 2990 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
2991 
/**
 2991 
  *               the configuration information for the specified DMA module.
2992 
  * @brief  DMA SPI half transmit receive process complete callback.
 2992 
  * @retval None
2993 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
 2993 
  */
2994 
  *               the configuration information for the specified DMA module.
 2994 
static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
2995 
  * @retval None
 2995 
{
2996 
  */
 2996 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2997 
static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
 2997 
 
2998 
{
 2998 
  /* Call user Rx half complete callback */
2999 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
 2999 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3000 
 
 3000 
  hspi->RxHalfCpltCallback(hspi);
3001 
  /* Call user TxRx half complete callback */
 3001 
#else
3002 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 3002 
  HAL_SPI_RxHalfCpltCallback(hspi);
3003 
  hspi->TxRxHalfCpltCallback(hspi);
 3003 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3004 
#else
 3004 
}
3005 
  HAL_SPI_TxRxHalfCpltCallback(hspi);
 3005 
 
3006 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 3006 
/**
3007 
}
 3007 
  * @brief  DMA SPI half transmit receive process complete callback.
3008 
 
 3008 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
3009 
/**
 3009 
  *               the configuration information for the specified DMA module.
3010 
  * @brief  DMA SPI communication error callback.
 3010 
  * @retval None
3011 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
 3011 
  */
3012 
  *               the configuration information for the specified DMA module.
 3012 
static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
3013 
  * @retval None
 3013 
{
3014 
  */
 3014 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3015 
static void SPI_DMAError(DMA_HandleTypeDef *hdma)
 3015 
 
3016 
{
 3016 
  /* Call user TxRx half complete callback */
3017 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
 3017 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3018 
 
 3018 
  hspi->TxRxHalfCpltCallback(hspi);
3019 
  /* Stop the disable DMA transfer on SPI side */
 3019 
#else
3020 
  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
 3020 
  HAL_SPI_TxRxHalfCpltCallback(hspi);
3021 
 
 3021 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3022 
  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
 3022 
}
3023 
  hspi->State = HAL_SPI_STATE_READY;
 3023 
 
3024 
  /* Call user error callback */
 3024 
/**
3025 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 3025 
  * @brief  DMA SPI communication error callback.
3026 
  hspi->ErrorCallback(hspi);
 3026 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
3027 
#else
 3027 
  *               the configuration information for the specified DMA module.
3028 
  HAL_SPI_ErrorCallback(hspi);
 3028 
  * @retval None
3029 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 3029 
  */
3030 
}
 3030 
static void SPI_DMAError(DMA_HandleTypeDef *hdma)
3031 
 
 3031 
{
3032 
/**
 3032 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3033 
  * @brief  DMA SPI communication abort callback, when initiated by HAL services on Error
 3033 
 
3034 
  *         (To be called at end of DMA Abort procedure following error occurrence).
 3034 
  /* Stop the disable DMA transfer on SPI side */
3035 
  * @param  hdma DMA handle.
 3035 
  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3036 
  * @retval None
 3036 
 
3037 
  */
 3037 
  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
3038 
static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
 3038 
  hspi->State = HAL_SPI_STATE_READY;
3039 
{
 3039 
  /* Call user error callback */
3040 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
 3040 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3041 
  hspi->RxXferCount = 0U;
 3041 
  hspi->ErrorCallback(hspi);
3042 
  hspi->TxXferCount = 0U;
 3042 
#else
3043 
 
 3043 
  HAL_SPI_ErrorCallback(hspi);
3044 
  /* Call user error callback */
 3044 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3045 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 3045 
}
3046 
  hspi->ErrorCallback(hspi);
 3046 
 
3047 
#else
 3047 
/**
3048 
  HAL_SPI_ErrorCallback(hspi);
 3048 
  * @brief  DMA SPI communication abort callback, when initiated by HAL services on Error
3049 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 3049 
  *         (To be called at end of DMA Abort procedure following error occurrence).
3050 
}
 3050 
  * @param  hdma DMA handle.
3051 
 
 3051 
  * @retval None
3052 
/**
 3052 
  */
3053 
  * @brief  DMA SPI Tx communication abort callback, when initiated by user
 3053 
static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
3054 
  *         (To be called at end of DMA Tx Abort procedure following user abort request).
 3054 
{
3055 
  * @note   When this callback is executed, User Abort complete call back is called only if no
 3055 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3056 
  *         Abort still ongoing for Rx DMA Handle.
 3056 
  hspi->RxXferCount = 0U;
3057 
  * @param  hdma DMA handle.
 3057 
  hspi->TxXferCount = 0U;
3058 
  * @retval None
 3058 
 
3059 
  */
 3059 
  /* Call user error callback */
3060 
static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
 3060 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3061 
{
 3061 
  hspi->ErrorCallback(hspi);
3062 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
 3062 
#else
3063 
  __IO uint32_t count;
 3063 
  HAL_SPI_ErrorCallback(hspi);
3064 
 
 3064 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3065 
  hspi->hdmatx->XferAbortCallback = NULL;
 3065 
}
3066 
  count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
 3066 
 
3067 
 
 3067 
/**
3068 
  /* Disable Tx DMA Request */
 3068 
  * @brief  DMA SPI Tx communication abort callback, when initiated by user
3069 
  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
 3069 
  *         (To be called at end of DMA Tx Abort procedure following user abort request).
3070 
 
 3070 
  * @note   When this callback is executed, User Abort complete call back is called only if no
3071 
  /* Wait until TXE flag is set */
 3071 
  *         Abort still ongoing for Rx DMA Handle.
3072 
  do
 3072 
  * @param  hdma DMA handle.
3073 
  {
 3073 
  * @retval None
3074 
    if (count == 0U)
 3074 
  */
3075 
    {
 3075 
static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
3076 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
 3076 
{
3077 
      break;
 3077 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3078 
    }
 3078 
  __IO uint32_t count;
3079 
    count--;
 3079 
 
3080 
  } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
 3080 
  hspi->hdmatx->XferAbortCallback = NULL;
3081 
 
 3081 
  count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
3082 
  /* Check if an Abort process is still ongoing */
 3082 
 
3083 
  if (hspi->hdmarx != NULL)
 3083 
  /* Disable Tx DMA Request */
3084 
  {
 3084 
  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
3085 
    if (hspi->hdmarx->XferAbortCallback != NULL)
 3085 
 
3086 
    {
 3086 
  /* Wait until TXE flag is set */
3087 
      return;
 3087 
  do
3088 
    }
 3088 
  {
3089 
  }
 3089 
    if (count == 0U)
3090 
 
 3090 
    {
3091 
  /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
 3091 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
3092 
  hspi->RxXferCount = 0U;
 3092 
      break;
3093 
  hspi->TxXferCount = 0U;
 3093 
    }
3094 
 
 3094 
    count--;
3095 
  /* Check no error during Abort procedure */
 3095 
  } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
3096 
  if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
 3096 
 
3097 
  {
 3097 
  /* Check if an Abort process is still ongoing */
3098 
    /* Reset errorCode */
 3098 
  if (hspi->hdmarx != NULL)
3099 
    hspi->ErrorCode = HAL_SPI_ERROR_NONE;
 3099 
  {
3100 
  }
 3100 
    if (hspi->hdmarx->XferAbortCallback != NULL)
3101 
 
 3101 
    {
3102 
  /* Clear the Error flags in the SR register */
 3102 
      return;
3103 
  __HAL_SPI_CLEAR_OVRFLAG(hspi);
 3103 
    }
3104 
 
 3104 
  }
3105 
  /* Restore hspi->State to Ready */
 3105 
 
3106 
  hspi->State  = HAL_SPI_STATE_READY;
 3106 
  /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
3107 
 
 3107 
  hspi->RxXferCount = 0U;
3108 
  /* Call user Abort complete callback */
 3108 
  hspi->TxXferCount = 0U;
3109 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 3109 
 
3110 
  hspi->AbortCpltCallback(hspi);
 3110 
  /* Check no error during Abort procedure */
3111 
#else
 3111 
  if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
3112 
  HAL_SPI_AbortCpltCallback(hspi);
 3112 
  {
3113 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 3113 
    /* Reset errorCode */
3114 
}
 3114 
    hspi->ErrorCode = HAL_SPI_ERROR_NONE;
3115 
 
 3115 
  }
3116 
/**
 3116 
 
3117 
  * @brief  DMA SPI Rx communication abort callback, when initiated by user
 3117 
  /* Clear the Error flags in the SR register */
3118 
  *         (To be called at end of DMA Rx Abort procedure following user abort request).
 3118 
  __HAL_SPI_CLEAR_OVRFLAG(hspi);
3119 
  * @note   When this callback is executed, User Abort complete call back is called only if no
 3119 
 
3120 
  *         Abort still ongoing for Tx DMA Handle.
 3120 
  /* Restore hspi->State to Ready */
3121 
  * @param  hdma DMA handle.
 3121 
  hspi->State  = HAL_SPI_STATE_READY;
3122 
  * @retval None
 3122 
 
3123 
  */
 3123 
  /* Call user Abort complete callback */
3124 
static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
 3124 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3125 
{
 3125 
  hspi->AbortCpltCallback(hspi);
3126 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
 3126 
#else
3127 
 
 3127 
  HAL_SPI_AbortCpltCallback(hspi);
3128 
  /* Disable SPI Peripheral */
 3128 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3129 
  __HAL_SPI_DISABLE(hspi);
 3129 
}
3130 
 
 3130 
 
3131 
  hspi->hdmarx->XferAbortCallback = NULL;
 3131 
/**
3132 
 
 3132 
  * @brief  DMA SPI Rx communication abort callback, when initiated by user
3133 
  /* Disable Rx DMA Request */
 3133 
  *         (To be called at end of DMA Rx Abort procedure following user abort request).
3134 
  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
 3134 
  * @note   When this callback is executed, User Abort complete call back is called only if no
3135 
 
 3135 
  *         Abort still ongoing for Tx DMA Handle.
3136 
  /* Check Busy flag */
 3136 
  * @param  hdma DMA handle.
3137 
  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
 3137 
  * @retval None
3138 
  {
 3138 
  */
3139 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
 3139 
static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
3140 
  }
 3140 
{
3141 
 
 3141 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3142 
  /* Check if an Abort process is still ongoing */
 3142 
 
3143 
  if (hspi->hdmatx != NULL)
 3143 
  /* Disable SPI Peripheral */
3144 
  {
 3144 
  __HAL_SPI_DISABLE(hspi);
3145 
    if (hspi->hdmatx->XferAbortCallback != NULL)
 3145 
 
3146 
    {
 3146 
  hspi->hdmarx->XferAbortCallback = NULL;
3147 
      return;
 3147 
 
3148 
    }
 3148 
  /* Disable Rx DMA Request */
3149 
  }
 3149 
  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
3150 
 
 3150 
 
3151 
  /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
 3151 
  /* Check Busy flag */
3152 
  hspi->RxXferCount = 0U;
 3152 
  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3153 
  hspi->TxXferCount = 0U;
 3153 
  {
3154 
 
 3154 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
3155 
  /* Check no error during Abort procedure */
 3155 
  }
3156 
  if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
 3156 
 
3157 
  {
 3157 
  /* Check if an Abort process is still ongoing */
3158 
    /* Reset errorCode */
 3158 
  if (hspi->hdmatx != NULL)
3159 
    hspi->ErrorCode = HAL_SPI_ERROR_NONE;
 3159 
  {
3160 
  }
 3160 
    if (hspi->hdmatx->XferAbortCallback != NULL)
3161 
 
 3161 
    {
3162 
  /* Clear the Error flags in the SR register */
 3162 
      return;
3163 
  __HAL_SPI_CLEAR_OVRFLAG(hspi);
 3163 
    }
3164 
 
 3164 
  }
3165 
  /* Restore hspi->State to Ready */
 3165 
 
3166 
  hspi->State  = HAL_SPI_STATE_READY;
 3166 
  /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
3167 
 
 3167 
  hspi->RxXferCount = 0U;
3168 
  /* Call user Abort complete callback */
 3168 
  hspi->TxXferCount = 0U;
3169 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 3169 
 
3170 
  hspi->AbortCpltCallback(hspi);
 3170 
  /* Check no error during Abort procedure */
3171 
#else
 3171 
  if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
3172 
  HAL_SPI_AbortCpltCallback(hspi);
 3172 
  {
3173 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 3173 
    /* Reset errorCode */
3174 
}
 3174 
    hspi->ErrorCode = HAL_SPI_ERROR_NONE;
3175 
 
 3175 
  }
3176 
/**
 3176 
 
3177 
  * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
 3177 
  /* Clear the Error flags in the SR register */
3178 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 3178 
  __HAL_SPI_CLEAR_OVRFLAG(hspi);
3179 
  *               the configuration information for SPI module.
 3179 
 
3180 
  * @retval None
 3180 
  /* Restore hspi->State to Ready */
3181 
  */
 3181 
  hspi->State  = HAL_SPI_STATE_READY;
3182 
static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
 3182 
 
3183 
{
 3183 
  /* Call user Abort complete callback */
3184 
  /* Receive data in 8bit mode */
 3184 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3185 
  *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR);
 3185 
  hspi->AbortCpltCallback(hspi);
3186 
  hspi->pRxBuffPtr++;
 3186 
#else
3187 
  hspi->RxXferCount--;
 3187 
  HAL_SPI_AbortCpltCallback(hspi);
3188 
 
 3188 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3189 
  /* Check end of the reception */
 3189 
}
3190 
  if (hspi->RxXferCount == 0U)
 3190 
 
3191 
  {
 3191 
/**
3192 
#if (USE_SPI_CRC != 0U)
 3192 
  * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
3193 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 3193 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
3194 
    {
 3194 
  *               the configuration information for SPI module.
3195 
      hspi->RxISR =  SPI_2linesRxISR_8BITCRC;
 3195 
  * @retval None
3196 
      return;
 3196 
  */
3197 
    }
 3197 
static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3198 
#endif /* USE_SPI_CRC */
 3198 
{
3199 
 
 3199 
  /* Receive data in 8bit mode */
3200 
    /* Disable RXNE  and ERR interrupt */
 3200 
  *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR);
3201 
    __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
 3201 
  hspi->pRxBuffPtr++;
3202 
 
 3202 
  hspi->RxXferCount--;
3203 
    if (hspi->TxXferCount == 0U)
 3203 
 
3204 
    {
 3204 
  /* Check end of the reception */
3205 
      SPI_CloseRxTx_ISR(hspi);
 3205 
  if (hspi->RxXferCount == 0U)
3206 
    }
 3206 
  {
3207 
  }
 3207 
#if (USE_SPI_CRC != 0U)
3208 
}
 3208 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3209 
 
 3209 
    {
3210 
#if (USE_SPI_CRC != 0U)
 3210 
      hspi->RxISR =  SPI_2linesRxISR_8BITCRC;
3211 
/**
 3211 
      return;
3212 
  * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
 3212 
    }
3213 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 3213 
#endif /* USE_SPI_CRC */
3214 
  *               the configuration information for SPI module.
 3214 
 
3215 
  * @retval None
 3215 
    /* Disable RXNE  and ERR interrupt */
3216 
  */
 3216 
    __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3217 
static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
 3217 
 
3218 
{
 3218 
    if (hspi->TxXferCount == 0U)
3219 
  __IO uint8_t  * ptmpreg8;
 3219 
    {
3220 
  __IO uint8_t  tmpreg8 = 0;
 3220 
      SPI_CloseRxTx_ISR(hspi);
3221 
 
 3221 
    }
3222 
  /* Initialize the 8bit temporary pointer */
 3222 
  }
3223 
  ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
 3223 
}
3224 
  /* Read 8bit CRC to flush Data Register */
 3224 
 
3225 
  tmpreg8 = *ptmpreg8;
 3225 
#if (USE_SPI_CRC != 0U)
3226 
  /* To avoid GCC warning */
 3226 
/**
3227 
  UNUSED(tmpreg8);
 3227 
  * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
3228 
 
 3228 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
3229 
  /* Disable RXNE and ERR interrupt */
 3229 
  *               the configuration information for SPI module.
3230 
  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
 3230 
  * @retval None
3231 
 
 3231 
  */
3232 
  if (hspi->TxXferCount == 0U)
 3232 
static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
3233 
  {
 3233 
{
3234 
    SPI_CloseRxTx_ISR(hspi);
 3234 
  __IO uint8_t  *ptmpreg8;
3235 
  }
 3235 
  __IO uint8_t  tmpreg8 = 0;
3236 
}
 3236 
 
3237 
#endif /* USE_SPI_CRC */
 3237 
  /* Initialize the 8bit temporary pointer */
3238 
 
 3238 
  ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
3239 
/**
 3239 
  /* Read 8bit CRC to flush Data Register */
3240 
  * @brief  Tx 8-bit handler for Transmit and Receive in Interrupt mode.
 3240 
  tmpreg8 = *ptmpreg8;
3241 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 3241 
  /* To avoid GCC warning */
3242 
  *               the configuration information for SPI module.
 3242 
  UNUSED(tmpreg8);
3243 
  * @retval None
 3243 
 
3244 
  */
 3244 
  /* Disable RXNE and ERR interrupt */
3245 
static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
 3245 
  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3246 
{
 3246 
 
3247 
  *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
 3247 
  if (hspi->TxXferCount == 0U)
3248 
  hspi->pTxBuffPtr++;
 3248 
  {
3249 
  hspi->TxXferCount--;
 3249 
    SPI_CloseRxTx_ISR(hspi);
3250 
 
 3250 
  }
3251 
  /* Check the end of the transmission */
 3251 
}
3252 
  if (hspi->TxXferCount == 0U)
 3252 
#endif /* USE_SPI_CRC */
3253 
  {
 3253 
 
3254 
#if (USE_SPI_CRC != 0U)
 3254 
/**
3255 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 3255 
  * @brief  Tx 8-bit handler for Transmit and Receive in Interrupt mode.
3256 
    {
 3256 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
3257 
      /* Set CRC Next Bit to send CRC */
 3257 
  *               the configuration information for SPI module.
3258 
      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
 3258 
  * @retval None
3259 
      /* Disable TXE interrupt */
 3259 
  */
3260 
      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
 3260 
static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3261 
      return;
 3261 
{
3262 
    }
 3262 
  *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
3263 
#endif /* USE_SPI_CRC */
 3263 
  hspi->pTxBuffPtr++;
3264 
 
 3264 
  hspi->TxXferCount--;
3265 
    /* Disable TXE interrupt */
 3265 
 
3266 
    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
 3266 
  /* Check the end of the transmission */
3267 
 
 3267 
  if (hspi->TxXferCount == 0U)
3268 
    if (hspi->RxXferCount == 0U)
 3268 
  {
3269 
    {
 3269 
#if (USE_SPI_CRC != 0U)
3270 
      SPI_CloseRxTx_ISR(hspi);
 3270 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3271 
    }
 3271 
    {
3272 
  }
 3272 
      /* Set CRC Next Bit to send CRC */
3273 
}
 3273 
      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3274 
 
 3274 
      /* Disable TXE interrupt */
3275 
/**
 3275 
      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3276 
  * @brief  Rx 16-bit handler for Transmit and Receive in Interrupt mode.
 3276 
      return;
3277 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 3277 
    }
3278 
  *               the configuration information for SPI module.
 3278 
#endif /* USE_SPI_CRC */
3279 
  * @retval None
 3279 
 
3280 
  */
 3280 
    /* Disable TXE interrupt */
3281 
static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
 3281 
    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3282 
{
 3282 
 
3283 
  /* Receive data in 16 Bit mode */
 3283 
    if (hspi->RxXferCount == 0U)
3284 
  *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
 3284 
    {
3285 
  hspi->pRxBuffPtr += sizeof(uint16_t);
 3285 
      SPI_CloseRxTx_ISR(hspi);
3286 
  hspi->RxXferCount--;
 3286 
    }
3287 
 
 3287 
  }
3288 
  if (hspi->RxXferCount == 0U)
 3288 
}
3289 
  {
 3289 
 
3290 
#if (USE_SPI_CRC != 0U)
 3290 
/**
3291 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 3291 
  * @brief  Rx 16-bit handler for Transmit and Receive in Interrupt mode.
3292 
    {
 3292 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
3293 
      hspi->RxISR =  SPI_2linesRxISR_16BITCRC;
 3293 
  *               the configuration information for SPI module.
3294 
      return;
 3294 
  * @retval None
3295 
    }
 3295 
  */
3296 
#endif /* USE_SPI_CRC */
 3296 
static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3297 
 
 3297 
{
3298 
    /* Disable RXNE interrupt */
 3298 
  /* Receive data in 16 Bit mode */
3299 
    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
 3299 
  *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3300 
 
 3300 
  hspi->pRxBuffPtr += sizeof(uint16_t);
3301 
    if (hspi->TxXferCount == 0U)
 3301 
  hspi->RxXferCount--;
3302 
    {
 3302 
 
3303 
      SPI_CloseRxTx_ISR(hspi);
 3303 
  if (hspi->RxXferCount == 0U)
3304 
    }
 3304 
  {
3305 
  }
 3305 
#if (USE_SPI_CRC != 0U)
3306 
}
 3306 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3307 
 
 3307 
    {
3308 
#if (USE_SPI_CRC != 0U)
 3308 
      hspi->RxISR =  SPI_2linesRxISR_16BITCRC;
3309 
/**
 3309 
      return;
3310 
  * @brief  Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
 3310 
    }
3311 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 3311 
#endif /* USE_SPI_CRC */
3312 
  *               the configuration information for SPI module.
 3312 
 
3313 
  * @retval None
 3313 
    /* Disable RXNE interrupt */
3314 
  */
 3314 
    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
3315 
static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
 3315 
 
3316 
{
 3316 
    if (hspi->TxXferCount == 0U)
3317 
  __IO uint32_t tmpreg = 0U;
 3317 
    {
3318 
 
 3318 
      SPI_CloseRxTx_ISR(hspi);
3319 
  /* Read 16bit CRC to flush Data Register */
 3319 
    }
3320 
  tmpreg = READ_REG(hspi->Instance->DR);
 3320 
  }
3321 
  /* To avoid GCC warning */
 3321 
}
3322 
  UNUSED(tmpreg);  
 3322 
 
3323 
 
 3323 
#if (USE_SPI_CRC != 0U)
3324 
  /* Disable RXNE interrupt */
 3324 
/**
3325 
  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
 3325 
  * @brief  Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
3326 
 
 3326 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
3327 
  SPI_CloseRxTx_ISR(hspi);
 3327 
  *               the configuration information for SPI module.
3328 
}
 3328 
  * @retval None
3329 
#endif /* USE_SPI_CRC */
 3329 
  */
3330 
 
 3330 
static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
3331 
/**
 3331 
{
3332 
  * @brief  Tx 16-bit handler for Transmit and Receive in Interrupt mode.
 3332 
  __IO uint32_t tmpreg = 0U;
3333 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 3333 
 
3334 
  *               the configuration information for SPI module.
 3334 
  /* Read 16bit CRC to flush Data Register */
3335 
  * @retval None
 3335 
  tmpreg = READ_REG(hspi->Instance->DR);
3336 
  */
 3336 
  /* To avoid GCC warning */
3337 
static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
 3337 
  UNUSED(tmpreg);
3338 
{
 3338 
 
3339 
  /* Transmit data in 16 Bit mode */
 3339 
  /* Disable RXNE interrupt */
3340 
  hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
 3340 
  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
3341 
  hspi->pTxBuffPtr += sizeof(uint16_t);
 3341 
 
3342 
  hspi->TxXferCount--;
 3342 
  SPI_CloseRxTx_ISR(hspi);
3343 
 
 3343 
}
3344 
  /* Enable CRC Transmission */
 3344 
#endif /* USE_SPI_CRC */
3345 
  if (hspi->TxXferCount == 0U)
 3345 
 
3346 
  {
 3346 
/**
3347 
#if (USE_SPI_CRC != 0U)
 3347 
  * @brief  Tx 16-bit handler for Transmit and Receive in Interrupt mode.
3348 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 3348 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
3349 
    {
 3349 
  *               the configuration information for SPI module.
3350 
      /* Set CRC Next Bit to send CRC */
 3350 
  * @retval None
3351 
      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
 3351 
  */
3352 
      /* Disable TXE interrupt */
 3352 
static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3353 
      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
 3353 
{
3354 
      return;
 3354 
  /* Transmit data in 16 Bit mode */
3355 
    }
 3355 
  hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3356 
#endif /* USE_SPI_CRC */
 3356 
  hspi->pTxBuffPtr += sizeof(uint16_t);
3357 
 
 3357 
  hspi->TxXferCount--;
3358 
    /* Disable TXE interrupt */
 3358 
 
3359 
    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
 3359 
  /* Enable CRC Transmission */
3360 
 
 3360 
  if (hspi->TxXferCount == 0U)
3361 
    if (hspi->RxXferCount == 0U)
 3361 
  {
3362 
    {
 3362 
#if (USE_SPI_CRC != 0U)
3363 
      SPI_CloseRxTx_ISR(hspi);
 3363 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3364 
    }
 3364 
    {
3365 
  }
 3365 
      /* Set CRC Next Bit to send CRC */
3366 
}
 3366 
      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3367 
 
 3367 
      /* Disable TXE interrupt */
3368 
#if (USE_SPI_CRC != 0U)
 3368 
      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3369 
/**
 3369 
      return;
3370 
  * @brief  Manage the CRC 8-bit receive in Interrupt context.
 3370 
    }
3371 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 3371 
#endif /* USE_SPI_CRC */
3372 
  *               the configuration information for SPI module.
 3372 
 
3373 
  * @retval None
 3373 
    /* Disable TXE interrupt */
3374 
  */
 3374 
    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3375 
static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
 3375 
 
3376 
{
 3376 
    if (hspi->RxXferCount == 0U)
3377 
  __IO uint8_t  * ptmpreg8;
 3377 
    {
3378 
  __IO uint8_t  tmpreg8 = 0;
 3378 
      SPI_CloseRxTx_ISR(hspi);
3379 
 
 3379 
    }
3380 
  /* Initialize the 8bit temporary pointer */
 3380 
  }
3381 
  ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
 3381 
}
3382 
  /* Read 8bit CRC to flush Data Register */
 3382 
 
3383 
  tmpreg8 = *ptmpreg8;
 3383 
#if (USE_SPI_CRC != 0U)
3384 
  /* To avoid GCC warning */
 3384 
/**
3385 
  UNUSED(tmpreg8);
 3385 
  * @brief  Manage the CRC 8-bit receive in Interrupt context.
3386 
 
 3386 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
3387 
  SPI_CloseRx_ISR(hspi);
 3387 
  *               the configuration information for SPI module.
3388 
}
 3388 
  * @retval None
3389 
#endif /* USE_SPI_CRC */
 3389 
  */
3390 
 
 3390 
static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
3391 
/**
 3391 
{
3392 
  * @brief  Manage the receive 8-bit in Interrupt context.
 3392 
  __IO uint8_t  *ptmpreg8;
3393 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 3393 
  __IO uint8_t  tmpreg8 = 0;
3394 
  *               the configuration information for SPI module.
 3394 
 
3395 
  * @retval None
 3395 
  /* Initialize the 8bit temporary pointer */
3396 
  */
 3396 
  ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
3397 
static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
 3397 
  /* Read 8bit CRC to flush Data Register */
3398 
{
 3398 
  tmpreg8 = *ptmpreg8;
3399 
  *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR);
 3399 
  /* To avoid GCC warning */
3400 
  hspi->pRxBuffPtr++;
 3400 
  UNUSED(tmpreg8);
3401 
  hspi->RxXferCount--;
 3401 
 
3402 
 
 3402 
  SPI_CloseRx_ISR(hspi);
3403 
#if (USE_SPI_CRC != 0U)
 3403 
}
3404 
  /* Enable CRC Transmission */
 3404 
#endif /* USE_SPI_CRC */
3405 
  if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
 3405 
 
3406 
  {
 3406 
/**
3407 
    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
 3407 
  * @brief  Manage the receive 8-bit in Interrupt context.
3408 
  }
 3408 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
3409 
  /* Check if CRCNEXT is well reseted by hardware */
 3409 
  *               the configuration information for SPI module.
3410 
  if (READ_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT))
 3410 
  * @retval None
3411 
  {
 3411 
  */
3412 
    /* Workaround to force CRCNEXT bit to zero in case of CRCNEXT is not reset automatically by hardware */
 3412 
static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3413 
    CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
 3413 
{
3414 
  }
 3414 
  *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR);
3415 
 
 3415 
  hspi->pRxBuffPtr++;
3416 
#endif /* USE_SPI_CRC */
 3416 
  hspi->RxXferCount--;
3417 
 
 3417 
 
3418 
  if (hspi->RxXferCount == 0U)
 3418 
#if (USE_SPI_CRC != 0U)
3419 
  {
 3419 
  /* Enable CRC Transmission */
3420 
#if (USE_SPI_CRC != 0U)
 3420 
  if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
3421 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 3421 
  {
3422 
    {
 3422 
    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3423 
      hspi->RxISR =  SPI_RxISR_8BITCRC;
 3423 
  }
3424 
      return;
 3424 
  /* Check if CRCNEXT is well reset by hardware */
3425 
    }
 3425 
  if (READ_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT))
3426 
#endif /* USE_SPI_CRC */
 3426 
  {
3427 
    SPI_CloseRx_ISR(hspi);
 3427 
    /* Workaround to force CRCNEXT bit to zero in case of CRCNEXT is not reset automatically by hardware */
3428 
  }
 3428 
    CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3429 
}
 3429 
  }
3430 
 
 3430 
 
3431 
#if (USE_SPI_CRC != 0U)
 3431 
#endif /* USE_SPI_CRC */
3432 
/**
 3432 
 
3433 
  * @brief  Manage the CRC 16-bit receive in Interrupt context.
 3433 
  if (hspi->RxXferCount == 0U)
3434 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 3434 
  {
3435 
  *               the configuration information for SPI module.
 3435 
#if (USE_SPI_CRC != 0U)
3436 
  * @retval None
 3436 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3437 
  */
 3437 
    {
3438 
static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
 3438 
      hspi->RxISR =  SPI_RxISR_8BITCRC;
3439 
{
 3439 
      return;
3440 
  __IO uint32_t tmpreg = 0U;
 3440 
    }
3441 
 
 3441 
#endif /* USE_SPI_CRC */
3442 
  /* Read 16bit CRC to flush Data Register */
 3442 
    SPI_CloseRx_ISR(hspi);
3443 
  tmpreg = READ_REG(hspi->Instance->DR);
 3443 
  }
3444 
  /* To avoid GCC warning */
 3444 
}
3445 
  UNUSED(tmpreg);
 3445 
 
3446 
 
 3446 
#if (USE_SPI_CRC != 0U)
3447 
  /* Disable RXNE and ERR interrupt */
 3447 
/**
3448 
  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
 3448 
  * @brief  Manage the CRC 16-bit receive in Interrupt context.
3449 
 
 3449 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
3450 
  SPI_CloseRx_ISR(hspi);
 3450 
  *               the configuration information for SPI module.
3451 
}
 3451 
  * @retval None
3452 
#endif /* USE_SPI_CRC */
 3452 
  */
3453 
 
 3453 
static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
3454 
/**
 3454 
{
3455 
  * @brief  Manage the 16-bit receive in Interrupt context.
 3455 
  __IO uint32_t tmpreg = 0U;
3456 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 3456 
 
3457 
  *               the configuration information for SPI module.
 3457 
  /* Read 16bit CRC to flush Data Register */
3458 
  * @retval None
 3458 
  tmpreg = READ_REG(hspi->Instance->DR);
3459 
  */
 3459 
  /* To avoid GCC warning */
3460 
static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
 3460 
  UNUSED(tmpreg);
3461 
{
 3461 
 
3462 
  *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
 3462 
  /* Disable RXNE and ERR interrupt */
3463 
  hspi->pRxBuffPtr += sizeof(uint16_t);
 3463 
  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3464 
  hspi->RxXferCount--;
 3464 
 
3465 
 
 3465 
  SPI_CloseRx_ISR(hspi);
3466 
#if (USE_SPI_CRC != 0U)
 3466 
}
3467 
  /* Enable CRC Transmission */
 3467 
#endif /* USE_SPI_CRC */
3468 
  if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
 3468 
 
3469 
  {
 3469 
/**
3470 
    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
 3470 
  * @brief  Manage the 16-bit receive in Interrupt context.
3471 
  }
 3471 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
3472 
  /* Check if CRCNEXT is well reseted by hardware */
 3472 
  *               the configuration information for SPI module.
3473 
  if (READ_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT))
 3473 
  * @retval None
3474 
  {
 3474 
  */
3475 
    /* Workaround to force CRCNEXT bit to zero in case of CRCNEXT is not reset automatically by hardware */
 3475 
static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3476 
    CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
 3476 
{
3477 
  }
 3477 
  *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3478 
 
 3478 
  hspi->pRxBuffPtr += sizeof(uint16_t);
3479 
#endif /* USE_SPI_CRC */
 3479 
  hspi->RxXferCount--;
3480 
 
 3480 
 
3481 
  if (hspi->RxXferCount == 0U)
 3481 
#if (USE_SPI_CRC != 0U)
3482 
  {
 3482 
  /* Enable CRC Transmission */
3483 
#if (USE_SPI_CRC != 0U)
 3483 
  if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
3484 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 3484 
  {
3485 
    {
 3485 
    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3486 
      hspi->RxISR = SPI_RxISR_16BITCRC;
 3486 
  }
3487 
      return;
 3487 
  /* Check if CRCNEXT is well reset by hardware */
3488 
    }
 3488 
  if (READ_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT))
3489 
#endif /* USE_SPI_CRC */
 3489 
  {
3490 
    SPI_CloseRx_ISR(hspi);
 3490 
    /* Workaround to force CRCNEXT bit to zero in case of CRCNEXT is not reset automatically by hardware */
3491 
  }
 3491 
    CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3492 
}
 3492 
  }
3493 
 
 3493 
 
3494 
/**
 3494 
#endif /* USE_SPI_CRC */
3495 
  * @brief  Handle the data 8-bit transmit in Interrupt mode.
 3495 
 
3496 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 3496 
  if (hspi->RxXferCount == 0U)
3497 
  *               the configuration information for SPI module.
 3497 
  {
3498 
  * @retval None
 3498 
#if (USE_SPI_CRC != 0U)
3499 
  */
 3499 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3500 
static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
 3500 
    {
3501 
{
 3501 
      hspi->RxISR = SPI_RxISR_16BITCRC;
3502 
  *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
 3502 
      return;
3503 
  hspi->pTxBuffPtr++;
 3503 
    }
3504 
  hspi->TxXferCount--;
 3504 
#endif /* USE_SPI_CRC */
3505 
 
 3505 
    SPI_CloseRx_ISR(hspi);
3506 
  if (hspi->TxXferCount == 0U)
 3506 
  }
3507 
  {
 3507 
}
3508 
#if (USE_SPI_CRC != 0U)
 3508 
 
3509 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 3509 
/**
3510 
    {
 3510 
  * @brief  Handle the data 8-bit transmit in Interrupt mode.
3511 
      /* Enable CRC Transmission */
 3511 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
3512 
      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
 3512 
  *               the configuration information for SPI module.
3513 
    }
 3513 
  * @retval None
3514 
#endif /* USE_SPI_CRC */
 3514 
  */
3515 
    SPI_CloseTx_ISR(hspi);
 3515 
static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3516 
  }
 3516 
{
3517 
}
 3517 
  *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
3518 
 
 3518 
  hspi->pTxBuffPtr++;
3519 
/**
 3519 
  hspi->TxXferCount--;
3520 
  * @brief  Handle the data 16-bit transmit in Interrupt mode.
 3520 
 
3521 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 3521 
  if (hspi->TxXferCount == 0U)
3522 
  *               the configuration information for SPI module.
 3522 
  {
3523 
  * @retval None
 3523 
#if (USE_SPI_CRC != 0U)
3524 
  */
 3524 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3525 
static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
 3525 
    {
3526 
{
 3526 
      /* Enable CRC Transmission */
3527 
  /* Transmit data in 16 Bit mode */
 3527 
      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3528 
  hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
 3528 
    }
3529 
  hspi->pTxBuffPtr += sizeof(uint16_t);
 3529 
#endif /* USE_SPI_CRC */
3530 
  hspi->TxXferCount--;
 3530 
    SPI_CloseTx_ISR(hspi);
3531 
 
 3531 
  }
3532 
  if (hspi->TxXferCount == 0U)
 3532 
}
3533 
  {
 3533 
 
3534 
#if (USE_SPI_CRC != 0U)
 3534 
/**
3535 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 3535 
  * @brief  Handle the data 16-bit transmit in Interrupt mode.
3536 
    {
 3536 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
3537 
      /* Enable CRC Transmission */
 3537 
  *               the configuration information for SPI module.
3538 
      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
 3538 
  * @retval None
3539 
    }
 3539 
  */
3540 
#endif /* USE_SPI_CRC */
 3540 
static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3541 
    SPI_CloseTx_ISR(hspi);
 3541 
{
3542 
  }
 3542 
  /* Transmit data in 16 Bit mode */
3543 
}
 3543 
  hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3544 
 
 3544 
  hspi->pTxBuffPtr += sizeof(uint16_t);
3545 
/**
 3545 
  hspi->TxXferCount--;
3546 
  * @brief  Handle SPI Communication Timeout.
 3546 
 
3547 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 3547 
  if (hspi->TxXferCount == 0U)
3548 
  *              the configuration information for SPI module.
 3548 
  {
3549 
  * @param  Flag SPI flag to check
 3549 
#if (USE_SPI_CRC != 0U)
3550 
  * @param  State flag state to check
 3550 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3551 
  * @param  Timeout Timeout duration
 3551 
    {
3552 
  * @param  Tickstart tick start value
 3552 
      /* Enable CRC Transmission */
3553 
  * @retval HAL status
 3553 
      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3554 
  */
 3554 
    }
3555 
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
 3555 
#endif /* USE_SPI_CRC */
3556 
                                                       uint32_t Timeout, uint32_t Tickstart)
 3556 
    SPI_CloseTx_ISR(hspi);
3557 
{
 3557 
  }
3558 
  __IO uint32_t count;
 3558 
}
3559 
  uint32_t tmp_timeout;
 3559 
 
3560 
  uint32_t tmp_tickstart;
 3560 
/**
3561 
 
 3561 
  * @brief  Handle SPI Communication Timeout.
3562 
  /* Adjust Timeout value  in case of end of transfer */
 3562 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
3563 
  tmp_timeout   = Timeout - (HAL_GetTick() - Tickstart);
 3563 
  *              the configuration information for SPI module.
3564 
  tmp_tickstart = HAL_GetTick();
 3564 
  * @param  Flag SPI flag to check
3565 
 
 3565 
  * @param  State flag state to check
3566 
  /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
 3566 
  * @param  Timeout Timeout duration
3567 
  count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
 3567 
  * @param  Tickstart tick start value
3568 
 
 3568 
  * @retval HAL status
3569 
  while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
 3569 
  */
3570 
  {
 3570 
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
3571 
    if (Timeout != HAL_MAX_DELAY)
 3571 
                                                       uint32_t Timeout, uint32_t Tickstart)
3572 
    {
 3572 
{
3573 
      if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
 3573 
  __IO uint32_t count;
3574 
      {
 3574 
  uint32_t tmp_timeout;
3575 
        /* Disable the SPI and reset the CRC: the CRC value should be cleared
 3575 
  uint32_t tmp_tickstart;
3576 
           on both master and slave sides in order to resynchronize the master
 3576 
 
3577 
           and slave for their respective CRC calculation */
 3577 
  /* Adjust Timeout value  in case of end of transfer */
3578 
 
 3578 
  tmp_timeout   = Timeout - (HAL_GetTick() - Tickstart);
3579 
        /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
 3579 
  tmp_tickstart = HAL_GetTick();
3580 
        __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
 3580 
 
3581 
 
 3581 
  /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
3582 
        if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
 3582 
  count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
3583 
                                                     || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
 3583 
 
3584 
        {
 3584 
  while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
3585 
          /* Disable SPI peripheral */
 3585 
  {
3586 
          __HAL_SPI_DISABLE(hspi);
 3586 
    if (Timeout != HAL_MAX_DELAY)
3587 
        }
 3587 
    {
3588 
 
 3588 
      if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
3589 
        /* Reset CRC Calculation */
 3589 
      {
3590 
        if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 3590 
        /* Disable the SPI and reset the CRC: the CRC value should be cleared
3591 
        {
 3591 
           on both master and slave sides in order to resynchronize the master
3592 
          SPI_RESET_CRC(hspi);
 3592 
           and slave for their respective CRC calculation */
3593 
        }
 3593 
 
3594 
 
 3594 
        /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
3595 
        hspi->State = HAL_SPI_STATE_READY;
 3595 
        __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
3596 
 
 3596 
 
3597 
        /* Process Unlocked */
 3597 
        if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
3598 
        __HAL_UNLOCK(hspi);
 3598 
                                                     || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3599 
 
 3599 
        {
3600 
        return HAL_TIMEOUT;
 3600 
          /* Disable SPI peripheral */
3601 
      }
 3601 
          __HAL_SPI_DISABLE(hspi);
3602 
      /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
 3602 
        }
3603 
      if(count == 0U)
 3603 
 
3604 
      {
 3604 
        /* Reset CRC Calculation */
3605 
        tmp_timeout = 0U;
 3605 
        if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3606 
      }
 3606 
        {
3607 
      count--;
 3607 
          SPI_RESET_CRC(hspi);
3608 
    }
 3608 
        }
3609 
  }
 3609 
 
3610 
 
 3610 
        hspi->State = HAL_SPI_STATE_READY;
3611 
  return HAL_OK;
 3611 
 
3612 
}
 3612 
        /* Process Unlocked */
3613 
 
 3613 
        __HAL_UNLOCK(hspi);
3614 
/**
 3614 
 
3615 
  * @brief  Handle the check of the RX transaction complete.
 3615 
        return HAL_TIMEOUT;
3616 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 3616 
      }
3617 
  *               the configuration information for SPI module.
 3617 
      /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
3618 
  * @param  Timeout Timeout duration
 3618 
      if (count == 0U)
3619 
  * @param  Tickstart tick start value
 3619 
      {
3620 
  * @retval HAL status
 3620 
        tmp_timeout = 0U;
3621 
  */
 3621 
      }
3622 
static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi,  uint32_t Timeout, uint32_t Tickstart)
 3622 
      count--;
3623 
{
 3623 
    }
3624 
  if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
 3624 
  }
3625 
                                               || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
 3625 
 
3626 
  {
 3626 
  return HAL_OK;
3627 
    /* Disable SPI peripheral */
 3627 
}
3628 
    __HAL_SPI_DISABLE(hspi);
 3628 
 
3629 
  }
 3629 
/**
3630 
 
 3630 
  * @brief  Handle the check of the RX transaction complete.
3631 
  if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))
 3631 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
3632 
  {
 3632 
  *               the configuration information for SPI module.
3633 
    /* Wait the RXNE reset */
 3633 
  * @param  Timeout Timeout duration
3634 
    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout, Tickstart) != HAL_OK)
 3634 
  * @param  Tickstart tick start value
3635 
    {
 3635 
  * @retval HAL status
3636 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
 3636 
  */
3637 
      return HAL_TIMEOUT;
 3637 
static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi,  uint32_t Timeout, uint32_t Tickstart)
3638 
    }
 3638 
{
3639 
  }
 3639 
  if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
3640 
  else
 3640 
                                               || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3641 
  {
 3641 
  {
3642 
    /* Control the BSY flag */
 3642 
    /* Disable SPI peripheral */
3643 
    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
 3643 
    __HAL_SPI_DISABLE(hspi);
3644 
    {
 3644 
  }
3645 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
 3645 
 
3646 
      return HAL_TIMEOUT;
 3646 
  if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))
3647 
    }
 3647 
  {
3648 
  }
 3648 
    /* Wait the RXNE reset */
3649 
  return HAL_OK;
 3649 
    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout, Tickstart) != HAL_OK)
3650 
}
 3650 
    {
3651 
 
 3651 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3652 
/**
 3652 
      return HAL_TIMEOUT;
3653 
  * @brief  Handle the check of the RXTX or TX transaction complete.
 3653 
    }
3654 
  * @param  hspi SPI handle
 3654 
  }
3655 
  * @param  Timeout Timeout duration
 3655 
  else
3656 
  * @param  Tickstart tick start value
 3656 
  {
3657 
  * @retval HAL status
 3657 
    /* Control the BSY flag */
3658 
  */
 3658 
    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
3659 
static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
 3659 
    {
3660 
{
 3660 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3661 
  /* Control the BSY flag */
 3661 
      return HAL_TIMEOUT;
3662 
  if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
 3662 
    }
3663 
  {
 3663 
  }
3664 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
 3664 
  return HAL_OK;
3665 
    return HAL_TIMEOUT;
 3665 
}
3666 
  }
 3666 
 
3667 
  return HAL_OK;
 3667 
/**
3668 
}
 3668 
  * @brief  Handle the check of the RXTX or TX transaction complete.
3669 
 
 3669 
  * @param  hspi SPI handle
3670 
/**
 3670 
  * @param  Timeout Timeout duration
3671 
  * @brief  Handle the end of the RXTX transaction.
 3671 
  * @param  Tickstart tick start value
3672 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 3672 
  * @retval HAL status
3673 
  *               the configuration information for SPI module.
 3673 
  */
3674 
  * @retval None
 3674 
static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
3675 
  */
 3675 
{
3676 
static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
 3676 
  /* Control the BSY flag */
3677 
{
 3677 
  if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
3678 
  uint32_t tickstart;
 3678 
  {
3679 
  __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
 3679 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3680 
 
 3680 
    return HAL_TIMEOUT;
3681 
  /* Init tickstart for timeout management */
 3681 
  }
3682 
  tickstart = HAL_GetTick();
 3682 
  return HAL_OK;
3683 
 
 3683 
}
3684 
  /* Disable ERR interrupt */
 3684 
 
3685 
  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
 3685 
/**
3686 
 
 3686 
  * @brief  Handle the end of the RXTX transaction.
3687 
  /* Wait until TXE flag is set */
 3687 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
3688 
  do
 3688 
  *               the configuration information for SPI module.
3689 
  {
 3689 
  * @retval None
3690 
    if (count == 0U)
 3690 
  */
3691 
    {
 3691 
static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
3692 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
 3692 
{
3693 
      break;
 3693 
  uint32_t tickstart;
3694 
    }
 3694 
  __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
3695 
    count--;
 3695 
 
3696 
  } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
 3696 
  /* Init tickstart for timeout management */
3697 
 
 3697 
  tickstart = HAL_GetTick();
3698 
  /* Check the end of the transaction */
 3698 
 
3699 
  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
 3699 
  /* Disable ERR interrupt */
3700 
  {
 3700 
  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3701 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
 3701 
 
3702 
  }
 3702 
  /* Wait until TXE flag is set */
3703 
 
 3703 
  do
3704 
  /* Clear overrun flag in 2 Lines communication mode because received is not read */
 3704 
  {
3705 
  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
 3705 
    if (count == 0U)
3706 
  {
 3706 
    {
3707 
    __HAL_SPI_CLEAR_OVRFLAG(hspi);
 3707 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3708 
  }
 3708 
      break;
3709 
 
 3709 
    }
3710 
#if (USE_SPI_CRC != 0U)
 3710 
    count--;
3711 
  /* Check if CRC error occurred */
 3711 
  } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
3712 
  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
 3712 
 
3713 
  {
 3713 
  /* Check the end of the transaction */
3714 
    /* Check if CRC error is valid or not (workaround to be applied or not) */
 3714 
  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3715 
    if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
 3715 
  {
3716 
    {
 3716 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3717 
      hspi->State = HAL_SPI_STATE_READY;
 3717 
  }
3718 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
 3718 
 
3719 
 
 3719 
  /* Clear overrun flag in 2 Lines communication mode because received is not read */
3720 
      /* Reset CRC Calculation */
 3720 
  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
3721 
      SPI_RESET_CRC(hspi);
 3721 
  {
3722 
 
 3722 
    __HAL_SPI_CLEAR_OVRFLAG(hspi);
3723 
      /* Call user error callback */
 3723 
  }
3724 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 3724 
 
3725 
      hspi->ErrorCallback(hspi);
 3725 
#if (USE_SPI_CRC != 0U)
3726 
#else
 3726 
  /* Check if CRC error occurred */
3727 
      HAL_SPI_ErrorCallback(hspi);
 3727 
  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
3728 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 3728 
  {
3729 
    }
 3729 
    /* Check if CRC error is valid or not (workaround to be applied or not) */
3730 
    else
 3730 
    if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
3731 
    {
 3731 
    {
3732 
      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
 3732 
      hspi->State = HAL_SPI_STATE_READY;
3733 
    }
 3733 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3734 
  }
 3734 
 
3735 
  else
 3735 
      /* Reset CRC Calculation */
3736 
  {
 3736 
      SPI_RESET_CRC(hspi);
3737 
#endif /* USE_SPI_CRC */
 3737 
 
3738 
    if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
 3738 
      /* Call user error callback */
3739 
    {
 3739 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3740 
      if (hspi->State == HAL_SPI_STATE_BUSY_RX)
 3740 
      hspi->ErrorCallback(hspi);
3741 
      {
 3741 
#else
3742 
        hspi->State = HAL_SPI_STATE_READY;
 3742 
      HAL_SPI_ErrorCallback(hspi);
3743 
        /* Call user Rx complete callback */
 3743 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3744 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 3744 
    }
3745 
        hspi->RxCpltCallback(hspi);
 3745 
    else
3746 
#else
 3746 
    {
3747 
        HAL_SPI_RxCpltCallback(hspi);
 3747 
      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3748 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 3748 
    }
3749 
      }
 3749 
  }
3750 
      else
 3750 
  else
3751 
      {
 3751 
  {
3752 
        hspi->State = HAL_SPI_STATE_READY;
 3752 
#endif /* USE_SPI_CRC */
3753 
        /* Call user TxRx complete callback */
 3753 
    if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
3754 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 3754 
    {
3755 
        hspi->TxRxCpltCallback(hspi);
 3755 
      if (hspi->State == HAL_SPI_STATE_BUSY_RX)
3756 
#else
 3756 
      {
3757 
        HAL_SPI_TxRxCpltCallback(hspi);
 3757 
        hspi->State = HAL_SPI_STATE_READY;
3758 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 3758 
        /* Call user Rx complete callback */
3759 
      }
 3759 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3760 
    }
 3760 
        hspi->RxCpltCallback(hspi);
3761 
    else
 3761 
#else
3762 
    {
 3762 
        HAL_SPI_RxCpltCallback(hspi);
3763 
      hspi->State = HAL_SPI_STATE_READY;
 3763 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3764 
      /* Call user error callback */
 3764 
      }
3765 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 3765 
      else
3766 
      hspi->ErrorCallback(hspi);
 3766 
      {
3767 
#else
 3767 
        hspi->State = HAL_SPI_STATE_READY;
3768 
      HAL_SPI_ErrorCallback(hspi);
 3768 
        /* Call user TxRx complete callback */
3769 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 3769 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3770 
    }
 3770 
        hspi->TxRxCpltCallback(hspi);
3771 
#if (USE_SPI_CRC != 0U)
 3771 
#else
3772 
  }
 3772 
        HAL_SPI_TxRxCpltCallback(hspi);
3773 
#endif /* USE_SPI_CRC */
 3773 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3774 
}
 3774 
      }
3775 
 
 3775 
    }
3776 
/**
 3776 
    else
3777 
  * @brief  Handle the end of the RX transaction.
 3777 
    {
3778 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 3778 
      hspi->State = HAL_SPI_STATE_READY;
3779 
  *               the configuration information for SPI module.
 3779 
      /* Call user error callback */
3780 
  * @retval None
 3780 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3781 
  */
 3781 
      hspi->ErrorCallback(hspi);
3782 
static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
 3782 
#else
3783 
{
 3783 
      HAL_SPI_ErrorCallback(hspi);
3784 
  /* Disable RXNE and ERR interrupt */
 3784 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3785 
  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
 3785 
    }
3786 
 
 3786 
#if (USE_SPI_CRC != 0U)
3787 
  /* Check the end of the transaction */
 3787 
  }
3788 
  if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
 3788 
#endif /* USE_SPI_CRC */
3789 
  {
 3789 
}
3790 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
 3790 
 
3791 
  }
 3791 
/**
3792 
 
 3792 
  * @brief  Handle the end of the RX transaction.
3793 
  /* Clear overrun flag in 2 Lines communication mode because received is not read */
 3793 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
3794 
  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
 3794 
  *               the configuration information for SPI module.
3795 
  {
 3795 
  * @retval None
3796 
    __HAL_SPI_CLEAR_OVRFLAG(hspi);
 3796 
  */
3797 
  }
 3797 
static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
3798 
  hspi->State = HAL_SPI_STATE_READY;
 3798 
{
3799 
 
 3799 
  /* Disable RXNE and ERR interrupt */
3800 
#if (USE_SPI_CRC != 0U)
 3800 
  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3801 
  /* Check if CRC error occurred */
 3801 
 
3802 
  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
 3802 
  /* Check the end of the transaction */
3803 
  {
 3803 
  if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3804 
    /* Check if CRC error is valid or not (workaround to be applied or not) */
 3804 
  {
3805 
    if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
 3805 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3806 
    {
 3806 
  }
3807 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
 3807 
 
3808 
 
 3808 
  /* Clear overrun flag in 2 Lines communication mode because received is not read */
3809 
      /* Reset CRC Calculation */
 3809 
  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
3810 
      SPI_RESET_CRC(hspi);
 3810 
  {
3811 
 
 3811 
    __HAL_SPI_CLEAR_OVRFLAG(hspi);
3812 
      /* Call user error callback */
 3812 
  }
3813 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 3813 
  hspi->State = HAL_SPI_STATE_READY;
3814 
      hspi->ErrorCallback(hspi);
 3814 
 
3815 
#else
 3815 
#if (USE_SPI_CRC != 0U)
3816 
      HAL_SPI_ErrorCallback(hspi);
 3816 
  /* Check if CRC error occurred */
3817 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 3817 
  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
3818 
    }
 3818 
  {
3819 
    else
 3819 
    /* Check if CRC error is valid or not (workaround to be applied or not) */
3820 
    {
 3820 
    if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
3821 
      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
 3821 
    {
3822 
    }
 3822 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3823 
  }
 3823 
 
3824 
  else
 3824 
      /* Reset CRC Calculation */
3825 
  {
 3825 
      SPI_RESET_CRC(hspi);
3826 
#endif /* USE_SPI_CRC */
 3826 
 
3827 
    if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
 3827 
      /* Call user error callback */
3828 
    {
 3828 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3829 
      /* Call user Rx complete callback */
 3829 
      hspi->ErrorCallback(hspi);
3830 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 3830 
#else
3831 
      hspi->RxCpltCallback(hspi);
 3831 
      HAL_SPI_ErrorCallback(hspi);
3832 
#else
 3832 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3833 
      HAL_SPI_RxCpltCallback(hspi);
 3833 
    }
3834 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 3834 
    else
3835 
    }
 3835 
    {
3836 
    else
 3836 
      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3837 
    {
 3837 
    }
3838 
      /* Call user error callback */
 3838 
  }
3839 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 3839 
  else
3840 
      hspi->ErrorCallback(hspi);
 3840 
  {
3841 
#else
 3841 
#endif /* USE_SPI_CRC */
3842 
      HAL_SPI_ErrorCallback(hspi);
 3842 
    if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
3843 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 3843 
    {
3844 
    }
 3844 
      /* Call user Rx complete callback */
3845 
#if (USE_SPI_CRC != 0U)
 3845 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3846 
  }
 3846 
      hspi->RxCpltCallback(hspi);
3847 
#endif /* USE_SPI_CRC */
 3847 
#else
3848 
}
 3848 
      HAL_SPI_RxCpltCallback(hspi);
3849 
 
 3849 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3850 
/**
 3850 
    }
3851 
  * @brief  Handle the end of the TX transaction.
 3851 
    else
3852 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 3852 
    {
3853 
  *               the configuration information for SPI module.
 3853 
      /* Call user error callback */
3854 
  * @retval None
 3854 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3855 
  */
 3855 
      hspi->ErrorCallback(hspi);
3856 
static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
 3856 
#else
3857 
{
 3857 
      HAL_SPI_ErrorCallback(hspi);
3858 
  uint32_t tickstart;
 3858 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3859 
  __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
 3859 
    }
3860 
 
 3860 
#if (USE_SPI_CRC != 0U)
3861 
  /* Init tickstart for timeout management*/
 3861 
  }
3862 
  tickstart = HAL_GetTick();
 3862 
#endif /* USE_SPI_CRC */
3863 
 
 3863 
}
3864 
  /* Wait until TXE flag is set */
 3864 
 
3865 
  do
 3865 
/**
3866 
  {
 3866 
  * @brief  Handle the end of the TX transaction.
3867 
    if (count == 0U)
 3867 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
3868 
    {
 3868 
  *               the configuration information for SPI module.
3869 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
 3869 
  * @retval None
3870 
      break;
 3870 
  */
3871 
    }
 3871 
static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
3872 
    count--;
 3872 
{
3873 
  } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
 3873 
  uint32_t tickstart;
3874 
 
 3874 
  __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
3875 
  /* Disable TXE and ERR interrupt */
 3875 
 
3876 
  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
 3876 
  /* Init tickstart for timeout management*/
3877 
 
 3877 
  tickstart = HAL_GetTick();
3878 
  /* Check the end of the transaction */
 3878 
 
3879 
  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
 3879 
  /* Wait until TXE flag is set */
3880 
  {
 3880 
  do
3881 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
 3881 
  {
3882 
  }
 3882 
    if (count == 0U)
3883 
 
 3883 
    {
3884 
  /* Clear overrun flag in 2 Lines communication mode because received is not read */
 3884 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3885 
  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
 3885 
      break;
3886 
  {
 3886 
    }
3887 
    __HAL_SPI_CLEAR_OVRFLAG(hspi);
 3887 
    count--;
3888 
  }
 3888 
  } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
3889 
 
 3889 
 
3890 
  hspi->State = HAL_SPI_STATE_READY;
 3890 
  /* Disable TXE and ERR interrupt */
3891 
  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
 3891 
  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
3892 
  {
 3892 
 
3893 
    /* Call user error callback */
 3893 
  /* Check the end of the transaction */
3894 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 3894 
  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3895 
    hspi->ErrorCallback(hspi);
 3895 
  {
3896 
#else
 3896 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3897 
    HAL_SPI_ErrorCallback(hspi);
 3897 
  }
3898 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 3898 
 
3899 
  }
 3899 
  /* Clear overrun flag in 2 Lines communication mode because received is not read */
3900 
  else
 3900 
  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
3901 
  {
 3901 
  {
3902 
    /* Call user Rx complete callback */
 3902 
    __HAL_SPI_CLEAR_OVRFLAG(hspi);
3903 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 3903 
  }
3904 
    hspi->TxCpltCallback(hspi);
 3904 
 
3905 
#else
 3905 
  hspi->State = HAL_SPI_STATE_READY;
3906 
    HAL_SPI_TxCpltCallback(hspi);
 3906 
  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3907 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 3907 
  {
3908 
  }
 3908 
    /* Call user error callback */
3909 
}
 3909 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3910 
 
 3910 
    hspi->ErrorCallback(hspi);
3911 
/**
 3911 
#else
3912 
  * @brief  Handle abort a Rx transaction.
 3912 
    HAL_SPI_ErrorCallback(hspi);
3913 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 3913 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3914 
  *               the configuration information for SPI module.
 3914 
  }
3915 
  * @retval None
 3915 
  else
3916 
  */
 3916 
  {
3917 
static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
 3917 
    /* Call user Rx complete callback */
3918 
{
 3918 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3919 
  __IO uint32_t tmpreg = 0U;
 3919 
    hspi->TxCpltCallback(hspi);
3920 
  __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
 3920 
#else
3921 
 
 3921 
    HAL_SPI_TxCpltCallback(hspi);
3922 
  /* Wait until TXE flag is set */
 3922 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3923 
  do
 3923 
  }
3924 
  {
 3924 
}
3925 
    if (count == 0U)
 3925 
 
3926 
    {
 3926 
/**
3927 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
 3927 
  * @brief  Handle abort a Rx transaction.
3928 
      break;
 3928 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
3929 
    }
 3929 
  *               the configuration information for SPI module.
3930 
    count--;
 3930 
  * @retval None
3931 
  } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
 3931 
  */
3932 
 
 3932 
static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
3933 
  /* Disable SPI Peripheral */
 3933 
{
3934 
  __HAL_SPI_DISABLE(hspi);
 3934 
  __IO uint32_t tmpreg = 0U;
3935 
 
 3935 
  __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
3936 
  /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
 3936 
 
3937 
  CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
 3937 
  /* Wait until TXE flag is set */
3938 
 
 3938 
  do
3939 
  /* Flush Data Register by a blank read */
 3939 
  {
3940 
  tmpreg = READ_REG(hspi->Instance->DR);
 3940 
    if (count == 0U)
3941 
  /* To avoid GCC warning */
 3941 
    {
3942 
  UNUSED(tmpreg);
 3942 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
3943 
 
 3943 
      break;
3944 
  hspi->State = HAL_SPI_STATE_ABORT;
 3944 
    }
3945 
}
 3945 
    count--;
3946 
 
 3946 
  } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
3947 
/**
 3947 
 
3948 
  * @brief  Handle abort a Tx or Rx/Tx transaction.
 3948 
  /* Disable SPI Peripheral */
3949 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 3949 
  __HAL_SPI_DISABLE(hspi);
3950 
  *               the configuration information for SPI module.
 3950 
 
3951 
  * @retval None
 3951 
  /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
3952 
  */
 3952 
  CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
3953 
static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
 3953 
 
3954 
{
 3954 
  /* Flush Data Register by a blank read */
3955 
  /* Disable TXEIE interrupt */
 3955 
  tmpreg = READ_REG(hspi->Instance->DR);
3956 
  CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));
 3956 
  /* To avoid GCC warning */
3957 
 
 3957 
  UNUSED(tmpreg);
3958 
  /* Disable SPI Peripheral */
 3958 
 
3959 
  __HAL_SPI_DISABLE(hspi);
 3959 
  hspi->State = HAL_SPI_STATE_ABORT;
3960 
 
 3960 
}
3961 
  hspi->State = HAL_SPI_STATE_ABORT;
 3961 
 
3962 
}
 3962 
/**
3963 
 
 3963 
  * @brief  Handle abort a Tx or Rx/Tx transaction.
3964 
#if (USE_SPI_CRC != 0U)
 3964 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
3965 
/**
 3965 
  *               the configuration information for SPI module.
3966 
  * @brief  Checks if encountered CRC error could be corresponding to wrongly detected errors
 3966 
  * @retval None
3967 
  *         according to SPI instance, Device type, and revision ID.
 3967 
  */
3968 
  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
 3968 
static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
3969 
  *               the configuration information for SPI module.
 3969 
{
3970 
  * @retval CRC error validity (SPI_INVALID_CRC_ERROR or SPI_VALID_CRC_ERROR).
 3970 
  /* Disable TXEIE interrupt */
3971 
  */
 3971 
  CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));
3972 
uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi)
 3972 
 
3973 
{
 3973 
  /* Disable SPI Peripheral */
3974 
#if defined(SPI_CRC_ERROR_WORKAROUND_FEATURE) && (USE_SPI_CRC_ERROR_WORKAROUND != 0U)
 3974 
  __HAL_SPI_DISABLE(hspi);
3975 
  /* Check how to handle this CRC error (workaround to be applied or not) */
 3975 
 
3976 
  /* If CRC errors could be wrongly detected (issue 2.15.2 in STM32F10xxC/D/E silicon limitations ES (DocID14732 Rev 13) */
 3976 
  hspi->State = HAL_SPI_STATE_ABORT;
3977 
  if (hspi->Instance == SPI2)
 3977 
}
3978 
  {
 3978 
 
3979 
    if (hspi->Instance->RXCRCR == 0U)
 3979 
#if (USE_SPI_CRC != 0U)
3980 
    {
 3980 
/**
3981 
      return (SPI_INVALID_CRC_ERROR);
 3981 
  * @brief  Checks if encountered CRC error could be corresponding to wrongly detected errors
3982 
    }
 3982 
  *         according to SPI instance, Device type, and revision ID.
3983 
  }
 3983 
  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
3984 
#endif
 3984 
  *               the configuration information for SPI module.
3985 
  /* Prevent unused argument(s) compilation warning */
 3985 
  * @retval CRC error validity (SPI_INVALID_CRC_ERROR or SPI_VALID_CRC_ERROR).
3986 
  UNUSED(hspi);
 3986 
  */
3987 
 
 3987 
uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi)
3988 
  return (SPI_VALID_CRC_ERROR);
 3988 
{
3989 
}
 3989 
#if defined(SPI_CRC_ERROR_WORKAROUND_FEATURE) && (USE_SPI_CRC_ERROR_WORKAROUND != 0U)
3990 
#endif /* USE_SPI_CRC */
 3990 
  /* Check how to handle this CRC error (workaround to be applied or not) */
3991 
/**
 3991 
  /* If CRC errors could be wrongly detected (issue 2.15.2 in STM32F10xxC/D/E silicon limitations ES (DocID14732 Rev 13) */
3992 
  * @}
 3992 
  if (hspi->Instance == SPI2)
3993 
  */
 3993 
  {
3994 
 
 3994 
    if (hspi->Instance->RXCRCR == 0U)
3995 
#endif /* HAL_SPI_MODULE_ENABLED */
 3995 
    {
3996 
 
 3996 
      return (SPI_INVALID_CRC_ERROR);
3997 
/**
 3997 
    }
3998 
  * @}
 3998 
  }
3999 
  */
 3999 
#endif /* USE_SPI_CRC_ERROR_WORKAROUND */
4000 
 
 4000 
  /* Prevent unused argument(s) compilation warning */
4001 
/**
 4001 
  UNUSED(hspi);
4002 
  * @}
 4002 
 
4003 
  */
 4003 
  return (SPI_VALID_CRC_ERROR);
4004 
 
 4004 
}
4005 
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 4005 
#endif /* USE_SPI_CRC */
- 
 
 4006 
/**
- 
 
 4007 
  * @}
- 
 
 4008 
  */
- 
 
 4009 
 
- 
 
 4010 
#endif /* HAL_SPI_MODULE_ENABLED */
- 
 
 4011 
 
- 
 
 4012 
/**
- 
 
 4013 
  * @}
- 
 
 4014 
  */
- 
 
 4015 
 
- 
 
 4016 
/**
- 
 
 4017 
  * @}
- 
 
 4018 
  */
- 
 
 4019