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1 
/**
 1 
/**
2 
  ******************************************************************************
 2 
  ******************************************************************************
3 
  * @file    stm32f1xx_hal_rcc_ex.c
 3 
  * @file    stm32f1xx_hal_rcc_ex.c
4 
  * @author  MCD Application Team
 4 
  * @author  MCD Application Team
5 
  * @brief   Extended RCC HAL module driver.
 5 
  * @brief   Extended RCC HAL module driver.
6 
  *          This file provides firmware functions to manage the following
 6 
  *          This file provides firmware functions to manage the following
7 
  *          functionalities RCC extension peripheral:
 7 
  *          functionalities RCC extension peripheral:
8 
  *           + Extended Peripheral Control functions
 8 
  *           + Extended Peripheral Control functions
9 
  *
 9 
  *
10 
  ******************************************************************************
 10 
  ******************************************************************************
11 
  * @attention
 11 
  * @attention
12 
  *
 12 
  *
13 
  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
 13 
  * Copyright (c) 2016 STMicroelectronics.
14 
  * All rights reserved.</center></h2>
 14 
  * All rights reserved.
15 
  *
 15 
  *
16 
  * This software component is licensed by ST under BSD 3-Clause license,
 16 
  * This software is licensed under terms that can be found in the LICENSE file in
17 
  * the "License"; You may not use this file except in compliance with the
 17 
  * the root directory of this software component.
18 
  * License. You may obtain a copy of the License at:
 18 
  * If no LICENSE file comes with this software, it is provided AS-IS.
19 
  *                        opensource.org/licenses/BSD-3-Clause
 19 
  ******************************************************************************
20 
  *
 20 
  */
21 
  ******************************************************************************
 21 
 
22 
  */
 22 
/* Includes ------------------------------------------------------------------*/
23 
 
 23 
#include "stm32f1xx_hal.h"
24 
/* Includes ------------------------------------------------------------------*/
 24 
 
25 
#include "stm32f1xx_hal.h"
 25 
/** @addtogroup STM32F1xx_HAL_Driver
26 
 
 26 
  * @{
27 
/** @addtogroup STM32F1xx_HAL_Driver
 27 
  */
28 
  * @{
 28 
 
29 
  */
 29 
#ifdef HAL_RCC_MODULE_ENABLED
30 
 
 30 
 
31 
#ifdef HAL_RCC_MODULE_ENABLED
 31 
/** @defgroup RCCEx RCCEx
32 
 
 32 
  * @brief RCC Extension HAL module driver.
33 
/** @defgroup RCCEx RCCEx
 33 
  * @{
34 
  * @brief RCC Extension HAL module driver.
 34 
  */
35 
  * @{
 35 
 
36 
  */
 36 
/* Private typedef -----------------------------------------------------------*/
37 
 
 37 
/* Private define ------------------------------------------------------------*/
38 
/* Private typedef -----------------------------------------------------------*/
 38 
/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
39 
/* Private define ------------------------------------------------------------*/
 39 
  * @{
40 
/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
 40 
  */
41 
  * @{
 41 
/**
42 
  */
 42 
  * @}
43 
/**
 43 
  */
44 
  * @}
 44 
 
45 
  */
 45 
/* Private macro -------------------------------------------------------------*/
46 
 
 46 
/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
47 
/* Private macro -------------------------------------------------------------*/
 47 
  * @{
48 
/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
 48 
  */
49 
  * @{
 49 
/**
50 
  */
 50 
  * @}
51 
/**
 51 
  */
52 
  * @}
 52 
 
53 
  */
 53 
/* Private variables ---------------------------------------------------------*/
54 
 
 54 
/* Private function prototypes -----------------------------------------------*/
55 
/* Private variables ---------------------------------------------------------*/
 55 
/* Private functions ---------------------------------------------------------*/
56 
/* Private function prototypes -----------------------------------------------*/
 56 
 
57 
/* Private functions ---------------------------------------------------------*/
 57 
/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
58 
 
 58 
  * @{
59 
/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
 59 
  */
60 
  * @{
 60 
 
61 
  */
 61 
/** @defgroup RCCEx_Exported_Functions_Group1 Peripheral Control functions
62 
 
 62 
  *  @brief  Extended Peripheral Control functions
63 
/** @defgroup RCCEx_Exported_Functions_Group1 Peripheral Control functions
 63 
  *
64 
  *  @brief  Extended Peripheral Control functions
 64 
@verbatim
65 
  *
 65 
 ===============================================================================
66 
@verbatim
 66 
                ##### Extended Peripheral Control functions  #####
67 
 ===============================================================================
 67 
 ===============================================================================
68 
                ##### Extended Peripheral Control functions  #####
 68 
    [..]
69 
 ===============================================================================
 69 
    This subsection provides a set of functions allowing to control the RCC Clocks
70 
    [..]
 70 
    frequencies.
71 
    This subsection provides a set of functions allowing to control the RCC Clocks
 71 
    [..]
72 
    frequencies.
 72 
    (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
73 
    [..]
 73 
        select the RTC clock source; in this case the Backup domain will be reset in
74 
    (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
 74 
        order to modify the RTC Clock source, as consequence RTC registers (including
75 
        select the RTC clock source; in this case the Backup domain will be reset in
 75 
        the backup registers) are set to their reset values.
76 
        order to modify the RTC Clock source, as consequence RTC registers (including
 76 
 
77 
        the backup registers) are set to their reset values.
 77 
@endverbatim
78 
 
 78 
  * @{
79 
@endverbatim
 79 
  */
80 
  * @{
 80 
 
81 
  */
 81 
/**
82 
 
 82 
  * @brief  Initializes the RCC extended peripherals clocks according to the specified parameters in the
83 
/**
 83 
  *         RCC_PeriphCLKInitTypeDef.
84 
  * @brief  Initializes the RCC extended peripherals clocks according to the specified parameters in the
 84 
  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
85 
  *         RCC_PeriphCLKInitTypeDef.
 85 
  *         contains the configuration information for the Extended Peripherals clocks(RTC clock).
86 
  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
 86 
  *
87 
  *         contains the configuration information for the Extended Peripherals clocks(RTC clock).
 87 
  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
88 
  *
 88 
  *         the RTC clock source; in this case the Backup domain will be reset in
89 
  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
 89 
  *         order to modify the RTC Clock source, as consequence RTC registers (including
90 
  *         the RTC clock source; in this case the Backup domain will be reset in
 90 
  *         the backup registers) are set to their reset values.
91 
  *         order to modify the RTC Clock source, as consequence RTC registers (including
 91 
  *
92 
  *         the backup registers) are set to their reset values.
 92 
  * @note   In case of STM32F105xC or STM32F107xC devices, PLLI2S will be enabled if requested on
93 
  *
 93 
  *         one of 2 I2S interfaces. When PLLI2S is enabled, you need to call HAL_RCCEx_DisablePLLI2S to
94 
  * @note   In case of STM32F105xC or STM32F107xC devices, PLLI2S will be enabled if requested on
 94 
  *         manually disable it.
95 
  *         one of 2 I2S interfaces. When PLLI2S is enabled, you need to call HAL_RCCEx_DisablePLLI2S to
 95 
  *
96 
  *         manually disable it.
 96 
  * @retval HAL status
97 
  *
 97 
  */
98 
  * @retval HAL status
 98 
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
99 
  */
 99 
{
100 
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
 100 
  uint32_t tickstart = 0U, temp_reg = 0U;
101 
{
 101 
#if defined(STM32F105xC) || defined(STM32F107xC)
102 
  uint32_t tickstart = 0U, temp_reg = 0U;
 102 
  uint32_t  pllactive = 0U;
103 
#if defined(STM32F105xC) || defined(STM32F107xC)
 103 
#endif /* STM32F105xC || STM32F107xC */
104 
  uint32_t  pllactive = 0U;
 104 
 
105 
#endif /* STM32F105xC || STM32F107xC */
 105 
  /* Check the parameters */
106 
 
 106 
  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
107 
  /* Check the parameters */
 107 
 
108 
  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
 108 
  /*------------------------------- RTC/LCD Configuration ------------------------*/
109 
 
 109 
  if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
110 
  /*------------------------------- RTC/LCD Configuration ------------------------*/
 110 
  {
111 
  if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
 111 
    FlagStatus pwrclkchanged = RESET;
112 
  {
 112 
 
113 
    FlagStatus pwrclkchanged = RESET;
 113 
    /* check for RTC Parameters used to output RTCCLK */
114 
 
 114 
    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
115 
    /* check for RTC Parameters used to output RTCCLK */
 115 
 
116 
    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
 116 
    /* As soon as function is called to change RTC clock source, activation of the
117 
 
 117 
       power domain is done. */
118 
    /* As soon as function is called to change RTC clock source, activation of the
 118 
    /* Requires to enable write access to Backup Domain of necessary */
119 
       power domain is done. */
 119 
    if (__HAL_RCC_PWR_IS_CLK_DISABLED())
120 
    /* Requires to enable write access to Backup Domain of necessary */
 120 
    {
121 
    if (__HAL_RCC_PWR_IS_CLK_DISABLED())
 121 
      __HAL_RCC_PWR_CLK_ENABLE();
122 
    {
 122 
      pwrclkchanged = SET;
123 
      __HAL_RCC_PWR_CLK_ENABLE();
 123 
    }
124 
      pwrclkchanged = SET;
 124 
 
125 
    }
 125 
    if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
126 
 
 126 
    {
127 
    if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 127 
      /* Enable write access to Backup domain */
128 
    {
 128 
      SET_BIT(PWR->CR, PWR_CR_DBP);
129 
      /* Enable write access to Backup domain */
 129 
 
130 
      SET_BIT(PWR->CR, PWR_CR_DBP);
 130 
      /* Wait for Backup domain Write protection disable */
131 
 
 131 
      tickstart = HAL_GetTick();
132 
      /* Wait for Backup domain Write protection disable */
 132 
 
133 
      tickstart = HAL_GetTick();
 133 
      while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
134 
 
 134 
      {
135 
      while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 135 
        if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
136 
      {
 136 
        {
137 
        if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 137 
          return HAL_TIMEOUT;
138 
        {
 138 
        }
139 
          return HAL_TIMEOUT;
 139 
      }
140 
        }
 140 
    }
141 
      }
 141 
 
142 
    }
 142 
    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
143 
 
 143 
    temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
144 
    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
 144 
    if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
145 
    temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
 145 
    {
146 
    if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
 146 
      /* Store the content of BDCR register before the reset of Backup Domain */
147 
    {
 147 
      temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
148 
      /* Store the content of BDCR register before the reset of Backup Domain */
 148 
      /* RTC Clock selection can be changed only if the Backup Domain is reset */
149 
      temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
 149 
      __HAL_RCC_BACKUPRESET_FORCE();
150 
      /* RTC Clock selection can be changed only if the Backup Domain is reset */
 150 
      __HAL_RCC_BACKUPRESET_RELEASE();
151 
      __HAL_RCC_BACKUPRESET_FORCE();
 151 
      /* Restore the Content of BDCR register */
152 
      __HAL_RCC_BACKUPRESET_RELEASE();
 152 
      RCC->BDCR = temp_reg;
153 
      /* Restore the Content of BDCR register */
 153 
 
154 
      RCC->BDCR = temp_reg;
 154 
      /* Wait for LSERDY if LSE was enabled */
155 
 
 155 
      if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
156 
      /* Wait for LSERDY if LSE was enabled */
 156 
      {
157 
      if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
 157 
        /* Get Start Tick */
158 
      {
 158 
        tickstart = HAL_GetTick();
159 
        /* Get Start Tick */
 159 
 
160 
        tickstart = HAL_GetTick();
 160 
        /* Wait till LSE is ready */
161 
 
 161 
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
162 
        /* Wait till LSE is ready */
 162 
        {
163 
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
 163 
          if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
164 
        {
 164 
          {
165 
          if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 165 
            return HAL_TIMEOUT;
166 
          {
 166 
          }
167 
            return HAL_TIMEOUT;
 167 
        }
168 
          }
 168 
      }
169 
        }
 169 
    }
170 
      }
 170 
    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
171 
    }
 171 
 
172 
    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
 172 
    /* Require to disable power clock if necessary */
173 
 
 173 
    if (pwrclkchanged == SET)
174 
    /* Require to disable power clock if necessary */
 174 
    {
175 
    if (pwrclkchanged == SET)
 175 
      __HAL_RCC_PWR_CLK_DISABLE();
176 
    {
 176 
    }
177 
      __HAL_RCC_PWR_CLK_DISABLE();
 177 
  }
178 
    }
 178 
 
179 
  }
 179 
  /*------------------------------ ADC clock Configuration ------------------*/
180 
 
 180 
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
181 
  /*------------------------------ ADC clock Configuration ------------------*/
 181 
  {
182 
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
 182 
    /* Check the parameters */
183 
  {
 183 
    assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection));
184 
    /* Check the parameters */
 184 
 
185 
    assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection));
 185 
    /* Configure the ADC clock source */
186 
 
 186 
    __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
187 
    /* Configure the ADC clock source */
 187 
  }
188 
    __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
 188 
 
189 
  }
 189 
#if defined(STM32F105xC) || defined(STM32F107xC)
190 
 
 190 
  /*------------------------------ I2S2 Configuration ------------------------*/
191 
#if defined(STM32F105xC) || defined(STM32F107xC)
 191 
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2)
192 
  /*------------------------------ I2S2 Configuration ------------------------*/
 192 
  {
193 
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2)
 193 
    /* Check the parameters */
194 
  {
 194 
    assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection));
195 
    /* Check the parameters */
 195 
 
196 
    assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection));
 196 
    /* Configure the I2S2 clock source */
197 
 
 197 
    __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection);
198 
    /* Configure the I2S2 clock source */
 198 
  }
199 
    __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection);
 199 
 
200 
  }
 200 
  /*------------------------------ I2S3 Configuration ------------------------*/
201 
 
 201 
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3)
202 
  /*------------------------------ I2S3 Configuration ------------------------*/
 202 
  {
203 
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3)
 203 
    /* Check the parameters */
204 
  {
 204 
    assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection));
205 
    /* Check the parameters */
 205 
 
206 
    assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection));
 206 
    /* Configure the I2S3 clock source */
207 
 
 207 
    __HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection);
208 
    /* Configure the I2S3 clock source */
 208 
  }
209 
    __HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection);
 209 
 
210 
  }
 210 
  /*------------------------------ PLL I2S Configuration ----------------------*/
211 
 
 211 
  /* Check that PLLI2S need to be enabled */
212 
  /*------------------------------ PLL I2S Configuration ----------------------*/
 212 
  if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
213 
  /* Check that PLLI2S need to be enabled */
 213 
  {
214 
  if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
 214 
    /* Update flag to indicate that PLL I2S should be active */
215 
  {
 215 
    pllactive = 1;
216 
    /* Update flag to indicate that PLL I2S should be active */
 216 
  }
217 
    pllactive = 1;
 217 
 
218 
  }
 218 
  /* Check if PLL I2S need to be enabled */
219 
 
 219 
  if (pllactive == 1)
220 
  /* Check if PLL I2S need to be enabled */
 220 
  {
221 
  if (pllactive == 1)
 221 
    /* Enable PLL I2S only if not active */
222 
  {
 222 
    if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON))
223 
    /* Enable PLL I2S only if not active */
 223 
    {
224 
    if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON))
 224 
      /* Check the parameters */
225 
    {
 225 
      assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL));
226 
      /* Check the parameters */
 226 
      assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value));
227 
      assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL));
 227 
 
228 
      assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value));
 228 
      /* Prediv2 can be written only when the PLL2 is disabled. */
229 
 
 229 
      /* Return an error only if new value is different from the programmed value */
230 
      /* Prediv2 can be written only when the PLL2 is disabled. */
 230 
      if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \
231 
      /* Return an error only if new value is different from the programmed value */
 231 
          (__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value))
232 
      if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \
 232 
      {
233 
          (__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value))
 233 
        return HAL_ERROR;
234 
      {
 234 
      }
235 
        return HAL_ERROR;
 235 
 
236 
      }
 236 
      /* Configure the HSE prediv2 factor --------------------------------*/
237 
 
 237 
      __HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value);
238 
      /* Configure the HSE prediv2 factor --------------------------------*/
 238 
 
239 
      __HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value);
 239 
      /* Configure the main PLLI2S multiplication factors. */
240 
 
 240 
      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL);
241 
      /* Configure the main PLLI2S multiplication factors. */
 241 
 
242 
      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL);
 242 
      /* Enable the main PLLI2S. */
243 
 
 243 
      __HAL_RCC_PLLI2S_ENABLE();
244 
      /* Enable the main PLLI2S. */
 244 
 
245 
      __HAL_RCC_PLLI2S_ENABLE();
 245 
      /* Get Start Tick*/
246 
 
 246 
      tickstart = HAL_GetTick();
247 
      /* Get Start Tick*/
 247 
 
248 
      tickstart = HAL_GetTick();
 248 
      /* Wait till PLLI2S is ready */
249 
 
 249 
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
250 
      /* Wait till PLLI2S is ready */
 250 
      {
251 
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
 251 
        if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
252 
      {
 252 
        {
253 
        if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
 253 
          return HAL_TIMEOUT;
254 
        {
 254 
        }
255 
          return HAL_TIMEOUT;
 255 
      }
256 
        }
 256 
    }
257 
      }
 257 
    else
258 
    }
 258 
    {
259 
    else
 259 
      /* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */
260 
    {
 260 
      if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL)
261 
      /* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */
 261 
      {
262 
      if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL)
 262 
        return HAL_ERROR;
263 
      {
 263 
      }
264 
        return HAL_ERROR;
 264 
    }
265 
      }
 265 
  }
266 
    }
 266 
#endif /* STM32F105xC || STM32F107xC */
267 
  }
 267 
 
268 
#endif /* STM32F105xC || STM32F107xC */
 268 
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
269 
 
 269 
 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
270 
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
 270 
 || defined(STM32F105xC) || defined(STM32F107xC)
271 
 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
 271 
  /*------------------------------ USB clock Configuration ------------------*/
272 
 || defined(STM32F105xC) || defined(STM32F107xC)
 272 
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
273 
  /*------------------------------ USB clock Configuration ------------------*/
 273 
  {
274 
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
 274 
    /* Check the parameters */
275 
  {
 275 
    assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection));
276 
    /* Check the parameters */
 276 
 
277 
    assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection));
 277 
    /* Configure the USB clock source */
278 
 
 278 
    __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
279 
    /* Configure the USB clock source */
 279 
  }
280 
    __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
 280 
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
281 
  }
 281 
 
282 
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
 282 
  return HAL_OK;
283 
 
 283 
}
284 
  return HAL_OK;
 284 
 
285 
}
 285 
/**
286 
 
 286 
  * @brief  Get the PeriphClkInit according to the internal
287 
/**
 287 
  * RCC configuration registers.
288 
  * @brief  Get the PeriphClkInit according to the internal
 288 
  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
289 
  * RCC configuration registers.
 289 
  *         returns the configuration information for the Extended Peripherals clocks(RTC, I2S, ADC clocks).
290 
  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
 290 
  * @retval None
291 
  *         returns the configuration information for the Extended Peripherals clocks(RTC, I2S, ADC clocks).
 291 
  */
292 
  * @retval None
 292 
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
293 
  */
 293 
{
294 
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
 294 
  uint32_t srcclk = 0U;
295 
{
 295 
 
296 
  uint32_t srcclk = 0U;
 296 
  /* Set all possible values for the extended clock type parameter------------*/
297 
 
 297 
  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC;
298 
  /* Set all possible values for the extended clock type parameter------------*/
 298 
 
299 
  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC;
 299 
  /* Get the RTC configuration -----------------------------------------------*/
300 
 
 300 
  srcclk = __HAL_RCC_GET_RTC_SOURCE();
301 
  /* Get the RTC configuration -----------------------------------------------*/
 301 
  /* Source clock is LSE or LSI*/
302 
  srcclk = __HAL_RCC_GET_RTC_SOURCE();
 302 
  PeriphClkInit->RTCClockSelection = srcclk;
303 
  /* Source clock is LSE or LSI*/
 303 
 
304 
  PeriphClkInit->RTCClockSelection = srcclk;
 304 
  /* Get the ADC clock configuration -----------------------------------------*/
305 
 
 305 
  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC;
306 
  /* Get the ADC clock configuration -----------------------------------------*/
 306 
  PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE();
307 
  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC;
 307 
 
308 
  PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE();
 308 
#if defined(STM32F105xC) || defined(STM32F107xC)
309 
 
 309 
  /* Get the I2S2 clock configuration -----------------------------------------*/
310 
#if defined(STM32F105xC) || defined(STM32F107xC)
 310 
  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2;
311 
  /* Get the I2S2 clock configuration -----------------------------------------*/
 311 
  PeriphClkInit->I2s2ClockSelection = __HAL_RCC_GET_I2S2_SOURCE();
312 
  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2;
 312 
 
313 
  PeriphClkInit->I2s2ClockSelection = __HAL_RCC_GET_I2S2_SOURCE();
 313 
  /* Get the I2S3 clock configuration -----------------------------------------*/
314 
 
 314 
  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3;
315 
  /* Get the I2S3 clock configuration -----------------------------------------*/
 315 
  PeriphClkInit->I2s3ClockSelection = __HAL_RCC_GET_I2S3_SOURCE();
316 
  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3;
 316 
 
317 
  PeriphClkInit->I2s3ClockSelection = __HAL_RCC_GET_I2S3_SOURCE();
 317 
#endif /* STM32F105xC || STM32F107xC */
318 
 
 318 
 
319 
#endif /* STM32F105xC || STM32F107xC */
 319 
#if defined(STM32F103xE) || defined(STM32F103xG)
320 
 
 320 
  /* Get the I2S2 clock configuration -----------------------------------------*/
321 
#if defined(STM32F103xE) || defined(STM32F103xG)
 321 
  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2;
322 
  /* Get the I2S2 clock configuration -----------------------------------------*/
 322 
  PeriphClkInit->I2s2ClockSelection = RCC_I2S2CLKSOURCE_SYSCLK;
323 
  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2;
 323 
 
324 
  PeriphClkInit->I2s2ClockSelection = RCC_I2S2CLKSOURCE_SYSCLK;
 324 
  /* Get the I2S3 clock configuration -----------------------------------------*/
325 
 
 325 
  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3;
326 
  /* Get the I2S3 clock configuration -----------------------------------------*/
 326 
  PeriphClkInit->I2s3ClockSelection = RCC_I2S3CLKSOURCE_SYSCLK;
327 
  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3;
 327 
 
328 
  PeriphClkInit->I2s3ClockSelection = RCC_I2S3CLKSOURCE_SYSCLK;
 328 
#endif /* STM32F103xE || STM32F103xG */
329 
 
 329 
 
330 
#endif /* STM32F103xE || STM32F103xG */
 330 
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
331 
 
 331 
 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
332 
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
 332 
 || defined(STM32F105xC) || defined(STM32F107xC)
333 
 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
 333 
  /* Get the USB clock configuration -----------------------------------------*/
334 
 || defined(STM32F105xC) || defined(STM32F107xC)
 334 
  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;
335 
  /* Get the USB clock configuration -----------------------------------------*/
 335 
  PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
336 
  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;
 336 
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
337 
  PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
 337 
}
338 
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
 338 
 
339 
}
 339 
/**
340 
 
 340 
  * @brief  Returns the peripheral clock frequency
341 
/**
 341 
  * @note   Returns 0 if peripheral clock is unknown
342 
  * @brief  Returns the peripheral clock frequency
 342 
  * @param  PeriphClk Peripheral clock identifier
343 
  * @note   Returns 0 if peripheral clock is unknown
 343 
  *         This parameter can be one of the following values:
344 
  * @param  PeriphClk Peripheral clock identifier
 344 
  *            @arg @ref RCC_PERIPHCLK_RTC  RTC peripheral clock
345 
  *         This parameter can be one of the following values:
 345 
  *            @arg @ref RCC_PERIPHCLK_ADC  ADC peripheral clock
346 
  *            @arg @ref RCC_PERIPHCLK_RTC  RTC peripheral clock
 346 
  @if STM32F103xE
347 
  *            @arg @ref RCC_PERIPHCLK_ADC  ADC peripheral clock
 347 
  *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
348 
  @if STM32F103xE
 348 
  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
349 
  *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
 349 
  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
350 
  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
 350 
  @endif
351 
  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
 351 
  @if STM32F103xG
352 
  @endif
 352 
  *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
353 
  @if STM32F103xG
 353 
  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
354 
  *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
 354 
  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
355 
  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
 355 
  *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
356 
  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
 356 
  @endif
357 
  *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
 357 
  @if STM32F105xC
358 
  @endif
 358 
  *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
359 
  @if STM32F105xC
 359 
  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
360 
  *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
 360 
  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
361 
  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
 361 
  *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
362 
  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
 362 
  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
363 
  *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
 363 
  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
364 
  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
 364 
  *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
365 
  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
 365 
  *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock
366 
  *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
 366 
  @endif
367 
  *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock
 367 
  @if STM32F107xC
368 
  @endif
 368 
  *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
369 
  @if STM32F107xC
 369 
  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
370 
  *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
 370 
  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
371 
  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
 371 
  *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
372 
  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
 372 
  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
373 
  *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
 373 
  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
374 
  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
 374 
  *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
375 
  *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
 375 
  *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock
376 
  *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
 376 
  @endif
377 
  *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock
 377 
  @if STM32F102xx
378 
  @endif
 378 
  *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock
379 
  @if STM32F102xx
 379 
  @endif
380 
  *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock
 380 
  @if STM32F103xx
381 
  @endif
 381 
  *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock
382 
  @if STM32F103xx
 382 
  @endif
383 
  *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock
 383 
  * @retval Frequency in Hz (0: means that no available frequency for the peripheral)
384 
  @endif
 384 
  */
385 
  * @retval Frequency in Hz (0: means that no available frequency for the peripheral)
 385 
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
386 
  */
 386 
{
387 
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
 387 
#if defined(STM32F105xC) || defined(STM32F107xC)
388 
{
 388 
  static const uint8_t aPLLMULFactorTable[14U] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
389 
#if defined(STM32F105xC) || defined(STM32F107xC)
 389 
  static const uint8_t aPredivFactorTable[16U] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
390 
  const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
 390 
 
391 
  const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
 391 
  uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U;
392 
 
 392 
  uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U;
393 
  uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U;
 393 
#endif /* STM32F105xC || STM32F107xC */
394 
  uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U;
 394 
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || \
395 
#endif /* STM32F105xC || STM32F107xC */
 395 
    defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
396 
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || \
 396 
  static const uint8_t aPLLMULFactorTable[16U] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
397 
    defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
 397 
  static const uint8_t aPredivFactorTable[2U] = {1, 2};
398 
  const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
 398 
 
399 
  const uint8_t aPredivFactorTable[2] = {1, 2};
 399 
  uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U;
400 
 
 400 
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
401 
  uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U;
 401 
  uint32_t temp_reg = 0U, frequency = 0U;
402 
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
 402 
 
403 
  uint32_t temp_reg = 0U, frequency = 0U;
 403 
  /* Check the parameters */
404 
 
 404 
  assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
405 
  /* Check the parameters */
 405 
 
406 
  assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
 406 
  switch (PeriphClk)
407 
 
 407 
  {
408 
  switch (PeriphClk)
 408 
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
409 
  {
 409 
 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
410 
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
 410 
 || defined(STM32F105xC) || defined(STM32F107xC)
411 
 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
 411 
    case RCC_PERIPHCLK_USB:
412 
 || defined(STM32F105xC) || defined(STM32F107xC)
 412 
    {
413 
    case RCC_PERIPHCLK_USB:
 413 
      /* Get RCC configuration ------------------------------------------------------*/
414 
    {
 414 
      temp_reg = RCC->CFGR;
415 
      /* Get RCC configuration ------------------------------------------------------*/
 415 
 
416 
      temp_reg = RCC->CFGR;
 416 
      /* Check if PLL is enabled */
417 
 
 417 
      if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLON))
418 
      /* Check if PLL is enabled */
 418 
      {
419 
      if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLON))
 419 
        pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
420 
      {
 420 
        if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
421 
        pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
 421 
        {
422 
        if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
 422 
#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
423 
        {
 423 
 || defined(STM32F100xE)
424 
#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
 424 
          prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
425 
 || defined(STM32F100xE)
 425 
#else
426 
          prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
 426 
          prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
427 
#else
 427 
#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
428 
          prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
 428 
 
429 
#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
 429 
#if defined(STM32F105xC) || defined(STM32F107xC)
430 
 
 430 
          if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC))
431 
#if defined(STM32F105xC) || defined(STM32F107xC)
 431 
          {
432 
          if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC))
 432 
            /* PLL2 selected as Prediv1 source */
433 
          {
 433 
            /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
434 
            /* PLL2 selected as Prediv1 source */
 434 
            prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
435 
            /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
 435 
            pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2;
436 
            prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
 436 
            pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul);
437 
            pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2;
 437 
          }
438 
            pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul);
 438 
          else
439 
          }
 439 
          {
440 
          else
 440 
            /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
441 
          {
 441 
            pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
442 
            /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
 442 
          }
443 
            pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
 443 
 
444 
          }
 444 
          /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
445 
 
 445 
          /* In this case need to divide pllclk by 2 */
446 
          /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
 446 
          if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos])
447 
          /* In this case need to divide pllclk by 2 */
 447 
          {
448 
          if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos])
 448 
            pllclk = pllclk / 2;
449 
          {
 449 
          }
450 
            pllclk = pllclk / 2;
 450 
#else
451 
          }
 451 
          if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
452 
#else
 452 
          {
453 
          if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
 453 
            /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
454 
          {
 454 
            pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
455 
            /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
 455 
          }
456 
            pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
 456 
#endif /* STM32F105xC || STM32F107xC */
457 
          }
 457 
        }
458 
#endif /* STM32F105xC || STM32F107xC */
 458 
        else
459 
        }
 459 
        {
460 
        else
 460 
          /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
461 
        {
 461 
          pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
462 
          /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
 462 
        }
463 
          pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
 463 
 
464 
        }
 464 
        /* Calcul of the USB frequency*/
465 
 
 465 
#if defined(STM32F105xC) || defined(STM32F107xC)
466 
        /* Calcul of the USB frequency*/
 466 
        /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */
467 
#if defined(STM32F105xC) || defined(STM32F107xC)
 467 
        if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2)
468 
        /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */
 468 
        {
469 
        if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2)
 469 
          /* Prescaler of 2 selected for USB */
470 
        {
 470 
          frequency = pllclk;
471 
          /* Prescaler of 2 selected for USB */
 471 
        }
472 
          frequency = pllclk;
 472 
        else
473 
        }
 473 
        {
474 
        else
 474 
          /* Prescaler of 3 selected for USB */
475 
        {
 475 
          frequency = (2 * pllclk) / 3;
476 
          /* Prescaler of 3 selected for USB */
 476 
        }
477 
          frequency = (2 * pllclk) / 3;
 477 
#else
478 
        }
 478 
        /* USBCLK = PLLCLK / USB prescaler */
479 
#else
 479 
        if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL)
480 
        /* USBCLK = PLLCLK / USB prescaler */
 480 
        {
481 
        if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL)
 481 
          /* No prescaler selected for USB */
482 
        {
 482 
          frequency = pllclk;
483 
          /* No prescaler selected for USB */
 483 
        }
484 
          frequency = pllclk;
 484 
        else
485 
        }
 485 
        {
486 
        else
 486 
          /* Prescaler of 1.5 selected for USB */
487 
        {
 487 
          frequency = (pllclk * 2) / 3;
488 
          /* Prescaler of 1.5 selected for USB */
 488 
        }
489 
          frequency = (pllclk * 2) / 3;
 489 
#endif
490 
        }
 490 
      }
491 
#endif
 491 
      break;
492 
      }
 492 
    }
493 
      break;
 493 
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
494 
    }
 494 
#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
495 
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
 495 
    case RCC_PERIPHCLK_I2S2:
496 
#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
 496 
    {
497 
    case RCC_PERIPHCLK_I2S2:
 497 
#if defined(STM32F103xE) || defined(STM32F103xG)
498 
    {
 498 
      /* SYSCLK used as source clock for I2S2 */
499 
#if defined(STM32F103xE) || defined(STM32F103xG)
 499 
      frequency = HAL_RCC_GetSysClockFreq();
500 
      /* SYSCLK used as source clock for I2S2 */
 500 
#else
501 
      frequency = HAL_RCC_GetSysClockFreq();
 501 
      if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK)
502 
#else
 502 
      {
503 
      if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK)
 503 
        /* SYSCLK used as source clock for I2S2 */
504 
      {
 504 
        frequency = HAL_RCC_GetSysClockFreq();
505 
        /* SYSCLK used as source clock for I2S2 */
 505 
      }
506 
        frequency = HAL_RCC_GetSysClockFreq();
 506 
      else
507 
      }
 507 
      {
508 
      else
 508 
        /* Check if PLLI2S is enabled */
509 
      {
 509 
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON))
510 
        /* Check if PLLI2S is enabled */
 510 
        {
511 
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON))
 511 
          /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */
512 
        {
 512 
          prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
513 
          /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */
 513 
          pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2;
514 
          prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
 514 
          frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul));
515 
          pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2;
 515 
        }
516 
          frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul));
 516 
      }
517 
        }
 517 
#endif /* STM32F103xE || STM32F103xG */
518 
      }
 518 
      break;
519 
#endif /* STM32F103xE || STM32F103xG */
 519 
    }
520 
      break;
 520 
    case RCC_PERIPHCLK_I2S3:
521 
    }
 521 
    {
522 
    case RCC_PERIPHCLK_I2S3:
 522 
#if defined(STM32F103xE) || defined(STM32F103xG)
523 
    {
 523 
      /* SYSCLK used as source clock for I2S3 */
524 
#if defined(STM32F103xE) || defined(STM32F103xG)
 524 
      frequency = HAL_RCC_GetSysClockFreq();
525 
      /* SYSCLK used as source clock for I2S3 */
 525 
#else
526 
      frequency = HAL_RCC_GetSysClockFreq();
 526 
      if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK)
527 
#else
 527 
      {
528 
      if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK)
 528 
        /* SYSCLK used as source clock for I2S3 */
529 
      {
 529 
        frequency = HAL_RCC_GetSysClockFreq();
530 
        /* SYSCLK used as source clock for I2S3 */
 530 
      }
531 
        frequency = HAL_RCC_GetSysClockFreq();
 531 
      else
532 
      }
 532 
      {
533 
      else
 533 
        /* Check if PLLI2S is enabled */
534 
      {
 534 
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON))
535 
        /* Check if PLLI2S is enabled */
 535 
        {
536 
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON))
 536 
          /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */
537 
        {
 537 
          prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
538 
          /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */
 538 
          pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2;
539 
          prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
 539 
          frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul));
540 
          pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2;
 540 
        }
541 
          frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul));
 541 
      }
542 
        }
 542 
#endif /* STM32F103xE || STM32F103xG */
543 
      }
 543 
      break;
544 
#endif /* STM32F103xE || STM32F103xG */
 544 
    }
545 
      break;
 545 
#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
546 
    }
 546 
    case RCC_PERIPHCLK_RTC:
547 
#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
 547 
    {
548 
    case RCC_PERIPHCLK_RTC:
 548 
      /* Get RCC BDCR configuration ------------------------------------------------------*/
549 
    {
 549 
      temp_reg = RCC->BDCR;
550 
      /* Get RCC BDCR configuration ------------------------------------------------------*/
 550 
 
551 
      temp_reg = RCC->BDCR;
 551 
      /* Check if LSE is ready if RTC clock selection is LSE */
552 
 
 552 
      if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY)))
553 
      /* Check if LSE is ready if RTC clock selection is LSE */
 553 
      {
554 
      if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY)))
 554 
        frequency = LSE_VALUE;
555 
      {
 555 
      }
556 
        frequency = LSE_VALUE;
 556 
      /* Check if LSI is ready if RTC clock selection is LSI */
557 
      }
 557 
      else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
558 
      /* Check if LSI is ready if RTC clock selection is LSI */
 558 
      {
559 
      else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
 559 
        frequency = LSI_VALUE;
560 
      {
 560 
      }
561 
        frequency = LSI_VALUE;
 561 
      else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
562 
      }
 562 
      {
563 
      else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
 563 
        frequency = HSE_VALUE / 128U;
564 
      {
 564 
      }
565 
        frequency = HSE_VALUE / 128U;
 565 
      /* Clock not enabled for RTC*/
566 
      }
 566 
      else
567 
      /* Clock not enabled for RTC*/
 567 
      {
568 
      else
 568 
        /* nothing to do: frequency already initialized to 0U */
569 
      {
 569 
      }
570 
        /* nothing to do: frequency already initialized to 0U */
 570 
      break;
571 
      }
 571 
    }
572 
      break;
 572 
    case RCC_PERIPHCLK_ADC:
573 
    }
 573 
    {
574 
    case RCC_PERIPHCLK_ADC:
 574 
      frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2);
575 
    {
 575 
      break;
576 
      frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2);
 576 
    }
577 
      break;
 577 
    default:
578 
    }
 578 
    {
579 
    default:
 579 
      break;
580 
    {
 580 
    }
581 
      break;
 581 
  }
582 
    }
 582 
  return (frequency);
583 
  }
 583 
}
584 
  return (frequency);
 584 
 
585 
}
 585 
/**
586 
 
 586 
  * @}
587 
/**
 587 
  */
588 
  * @}
 588 
 
589 
  */
 589 
#if defined(STM32F105xC) || defined(STM32F107xC)
590 
 
 590 
/** @defgroup RCCEx_Exported_Functions_Group2 PLLI2S Management function
591 
#if defined(STM32F105xC) || defined(STM32F107xC)
 591 
  *  @brief  PLLI2S Management functions
592 
/** @defgroup RCCEx_Exported_Functions_Group2 PLLI2S Management function
 592 
  *
593 
  *  @brief  PLLI2S Management functions
 593 
@verbatim
594 
  *
 594 
 ===============================================================================
595 
@verbatim
 595 
                ##### Extended PLLI2S Management functions  #####
596 
 ===============================================================================
 596 
 ===============================================================================
597 
                ##### Extended PLLI2S Management functions  #####
 597 
    [..]
598 
 ===============================================================================
 598 
    This subsection provides a set of functions allowing to control the PLLI2S
599 
    [..]
 599 
    activation or deactivation
600 
    This subsection provides a set of functions allowing to control the PLLI2S
 600 
@endverbatim
601 
    activation or deactivation
 601 
  * @{
602 
@endverbatim
 602 
  */
603 
  * @{
 603 
 
604 
  */
 604 
/**
605 
 
 605 
  * @brief  Enable PLLI2S
606 
/**
 606 
  * @param  PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that
607 
  * @brief  Enable PLLI2S
 607 
  *         contains the configuration information for the PLLI2S
608 
  * @param  PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that
 608 
  * @note   The PLLI2S configuration not modified if used by I2S2 or I2S3 Interface.
609 
  *         contains the configuration information for the PLLI2S
 609 
  * @retval HAL status
610 
  * @note   The PLLI2S configuration not modified if used by I2S2 or I2S3 Interface.
 610 
  */
611 
  * @retval HAL status
 611 
HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef  *PLLI2SInit)
612 
  */
 612 
{
613 
HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef  *PLLI2SInit)
 613 
  uint32_t tickstart = 0U;
614 
{
 614 
 
615 
  uint32_t tickstart = 0U;
 615 
  /* Check that PLL I2S has not been already enabled by I2S2 or I2S3*/
616 
 
 616 
  if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
617 
  /* Check that PLL I2S has not been already enabled by I2S2 or I2S3*/
 617 
  {
618 
  if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
 618 
    /* Check the parameters */
619 
  {
 619 
    assert_param(IS_RCC_PLLI2S_MUL(PLLI2SInit->PLLI2SMUL));
620 
    /* Check the parameters */
 620 
    assert_param(IS_RCC_HSE_PREDIV2(PLLI2SInit->HSEPrediv2Value));
621 
    assert_param(IS_RCC_PLLI2S_MUL(PLLI2SInit->PLLI2SMUL));
 621 
 
622 
    assert_param(IS_RCC_HSE_PREDIV2(PLLI2SInit->HSEPrediv2Value));
 622 
    /* Prediv2 can be written only when the PLL2 is disabled. */
623 
 
 623 
    /* Return an error only if new value is different from the programmed value */
624 
    /* Prediv2 can be written only when the PLL2 is disabled. */
 624 
    if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \
625 
    /* Return an error only if new value is different from the programmed value */
 625 
        (__HAL_RCC_HSE_GET_PREDIV2() != PLLI2SInit->HSEPrediv2Value))
626 
    if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \
 626 
    {
627 
        (__HAL_RCC_HSE_GET_PREDIV2() != PLLI2SInit->HSEPrediv2Value))
 627 
      return HAL_ERROR;
628 
    {
 628 
    }
629 
      return HAL_ERROR;
 629 
 
630 
    }
 630 
    /* Disable the main PLLI2S. */
631 
 
 631 
    __HAL_RCC_PLLI2S_DISABLE();
632 
    /* Disable the main PLLI2S. */
 632 
 
633 
    __HAL_RCC_PLLI2S_DISABLE();
 633 
    /* Get Start Tick*/
634 
 
 634 
    tickstart = HAL_GetTick();
635 
    /* Get Start Tick*/
 635 
 
636 
    tickstart = HAL_GetTick();
 636 
    /* Wait till PLLI2S is ready */
637 
 
 637 
    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
638 
    /* Wait till PLLI2S is ready */
 638 
    {
639 
    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
 639 
      if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
640 
    {
 640 
      {
641 
      if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
 641 
        return HAL_TIMEOUT;
642 
      {
 642 
      }
643 
        return HAL_TIMEOUT;
 643 
    }
644 
      }
 644 
 
645 
    }
 645 
    /* Configure the HSE prediv2 factor --------------------------------*/
646 
 
 646 
    __HAL_RCC_HSE_PREDIV2_CONFIG(PLLI2SInit->HSEPrediv2Value);
647 
    /* Configure the HSE prediv2 factor --------------------------------*/
 647 
 
648 
    __HAL_RCC_HSE_PREDIV2_CONFIG(PLLI2SInit->HSEPrediv2Value);
 648 
 
649 
 
 649 
    /* Configure the main PLLI2S multiplication factors. */
650 
 
 650 
    __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SMUL);
651 
    /* Configure the main PLLI2S multiplication factors. */
 651 
 
652 
    __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SMUL);
 652 
    /* Enable the main PLLI2S. */
653 
 
 653 
    __HAL_RCC_PLLI2S_ENABLE();
654 
    /* Enable the main PLLI2S. */
 654 
 
655 
    __HAL_RCC_PLLI2S_ENABLE();
 655 
    /* Get Start Tick*/
656 
 
 656 
    tickstart = HAL_GetTick();
657 
    /* Get Start Tick*/
 657 
 
658 
    tickstart = HAL_GetTick();
 658 
    /* Wait till PLLI2S is ready */
659 
 
 659 
    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
660 
    /* Wait till PLLI2S is ready */
 660 
    {
661 
    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
 661 
      if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
662 
    {
 662 
      {
663 
      if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
 663 
        return HAL_TIMEOUT;
664 
      {
 664 
      }
665 
        return HAL_TIMEOUT;
 665 
    }
666 
      }
 666 
  }
667 
    }
 667 
  else
668 
  }
 668 
  {
669 
  else
 669 
    /* PLLI2S cannot be modified as already used by I2S2 or I2S3 */
670 
  {
 670 
    return HAL_ERROR;
671 
    /* PLLI2S cannot be modified as already used by I2S2 or I2S3 */
 671 
  }
672 
    return HAL_ERROR;
 672 
 
673 
  }
 673 
  return HAL_OK;
674 
 
 674 
}
675 
  return HAL_OK;
 675 
 
676 
}
 676 
/**
677 
 
 677 
  * @brief  Disable PLLI2S
678 
/**
 678 
  * @note   PLLI2S is not disabled if used by I2S2 or I2S3 Interface.
679 
  * @brief  Disable PLLI2S
 679 
  * @retval HAL status
680 
  * @note   PLLI2S is not disabled if used by I2S2 or I2S3 Interface.
 680 
  */
681 
  * @retval HAL status
 681 
HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void)
682 
  */
 682 
{
683 
HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void)
 683 
  uint32_t tickstart = 0U;
684 
{
 684 
 
685 
  uint32_t tickstart = 0U;
 685 
  /* Disable PLL I2S as not requested by I2S2 or I2S3*/
686 
 
 686 
  if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
687 
  /* Disable PLL I2S as not requested by I2S2 or I2S3*/
 687 
  {
688 
  if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
 688 
    /* Disable the main PLLI2S. */
689 
  {
 689 
    __HAL_RCC_PLLI2S_DISABLE();
690 
    /* Disable the main PLLI2S. */
 690 
 
691 
    __HAL_RCC_PLLI2S_DISABLE();
 691 
    /* Get Start Tick*/
692 
 
 692 
    tickstart = HAL_GetTick();
693 
    /* Get Start Tick*/
 693 
 
694 
    tickstart = HAL_GetTick();
 694 
    /* Wait till PLLI2S is ready */
695 
 
 695 
    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
696 
    /* Wait till PLLI2S is ready */
 696 
    {
697 
    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
 697 
      if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
698 
    {
 698 
      {
699 
      if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
 699 
        return HAL_TIMEOUT;
700 
      {
 700 
      }
701 
        return HAL_TIMEOUT;
 701 
    }
702 
      }
 702 
  }
703 
    }
 703 
  else
704 
  }
 704 
  {
705 
  else
 705 
    /* PLLI2S is currently used by I2S2 or I2S3. Cannot be disabled.*/
706 
  {
 706 
    return HAL_ERROR;
707 
    /* PLLI2S is currently used by I2S2 or I2S3. Cannot be disabled.*/
 707 
  }
708 
    return HAL_ERROR;
 708 
 
709 
  }
 709 
  return HAL_OK;
710 
 
 710 
}
711 
  return HAL_OK;
 711 
 
712 
}
 712 
/**
713 
 
 713 
  * @}
714 
/**
 714 
  */
715 
  * @}
 715 
 
716 
  */
 716 
/** @defgroup RCCEx_Exported_Functions_Group3 PLL2 Management function
717 
 
 717 
  *  @brief  PLL2 Management functions
718 
/** @defgroup RCCEx_Exported_Functions_Group3 PLL2 Management function
 718 
  *
719 
  *  @brief  PLL2 Management functions
 719 
@verbatim
720 
  *
 720 
 ===============================================================================
721 
@verbatim
 721 
                ##### Extended PLL2 Management functions  #####
722 
 ===============================================================================
 722 
 ===============================================================================
723 
                ##### Extended PLL2 Management functions  #####
 723 
    [..]
724 
 ===============================================================================
 724 
    This subsection provides a set of functions allowing to control the PLL2
725 
    [..]
 725 
    activation or deactivation
726 
    This subsection provides a set of functions allowing to control the PLL2
 726 
@endverbatim
727 
    activation or deactivation
 727 
  * @{
728 
@endverbatim
 728 
  */
729 
  * @{
 729 
 
730 
  */
 730 
/**
731 
 
 731 
  * @brief  Enable PLL2
732 
/**
 732 
  * @param  PLL2Init pointer to an RCC_PLL2InitTypeDef structure that
733 
  * @brief  Enable PLL2
 733 
  *         contains the configuration information for the PLL2
734 
  * @param  PLL2Init pointer to an RCC_PLL2InitTypeDef structure that
 734 
  * @note   The PLL2 configuration not modified if used indirectly as system clock.
735 
  *         contains the configuration information for the PLL2
 735 
  * @retval HAL status
736 
  * @note   The PLL2 configuration not modified if used indirectly as system clock.
 736 
  */
737 
  * @retval HAL status
 737 
HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef  *PLL2Init)
738 
  */
 738 
{
739 
HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef  *PLL2Init)
 739 
  uint32_t tickstart = 0U;
740 
{
 740 
 
741 
  uint32_t tickstart = 0U;
 741 
  /* This bit can not be cleared if the PLL2 clock is used indirectly as system
742 
 
 742 
    clock (i.e. it is used as PLL clock entry that is used as system clock). */
743 
  /* This bit can not be cleared if the PLL2 clock is used indirectly as system
 743 
  if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
744 
    clock (i.e. it is used as PLL clock entry that is used as system clock). */
 744 
      (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
745 
  if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
 745 
      ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
746 
      (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
 746 
  {
747 
      ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
 747 
    return HAL_ERROR;
748 
  {
 748 
  }
749 
    return HAL_ERROR;
 749 
  else
750 
  }
 750 
  {
751 
  else
 751 
    /* Check the parameters */
752 
  {
 752 
    assert_param(IS_RCC_PLL2_MUL(PLL2Init->PLL2MUL));
753 
    /* Check the parameters */
 753 
    assert_param(IS_RCC_HSE_PREDIV2(PLL2Init->HSEPrediv2Value));
754 
    assert_param(IS_RCC_PLL2_MUL(PLL2Init->PLL2MUL));
 754 
 
755 
    assert_param(IS_RCC_HSE_PREDIV2(PLL2Init->HSEPrediv2Value));
 755 
    /* Prediv2 can be written only when the PLLI2S is disabled. */
756 
 
 756 
    /* Return an error only if new value is different from the programmed value */
757 
    /* Prediv2 can be written only when the PLLI2S is disabled. */
 757 
    if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \
758 
    /* Return an error only if new value is different from the programmed value */
 758 
        (__HAL_RCC_HSE_GET_PREDIV2() != PLL2Init->HSEPrediv2Value))
759 
    if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \
 759 
    {
760 
        (__HAL_RCC_HSE_GET_PREDIV2() != PLL2Init->HSEPrediv2Value))
 760 
      return HAL_ERROR;
761 
    {
 761 
    }
762 
      return HAL_ERROR;
 762 
 
763 
    }
 763 
    /* Disable the main PLL2. */
764 
 
 764 
    __HAL_RCC_PLL2_DISABLE();
765 
    /* Disable the main PLL2. */
 765 
 
766 
    __HAL_RCC_PLL2_DISABLE();
 766 
    /* Get Start Tick*/
767 
 
 767 
    tickstart = HAL_GetTick();
768 
    /* Get Start Tick*/
 768 
 
769 
    tickstart = HAL_GetTick();
 769 
    /* Wait till PLL2 is disabled */
770 
 
 770 
    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
771 
    /* Wait till PLL2 is disabled */
 771 
    {
772 
    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
 772 
      if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
773 
    {
 773 
      {
774 
      if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
 774 
        return HAL_TIMEOUT;
775 
      {
 775 
      }
776 
        return HAL_TIMEOUT;
 776 
    }
777 
      }
 777 
 
778 
    }
 778 
    /* Configure the HSE prediv2 factor --------------------------------*/
779 
 
 779 
    __HAL_RCC_HSE_PREDIV2_CONFIG(PLL2Init->HSEPrediv2Value);
780 
    /* Configure the HSE prediv2 factor --------------------------------*/
 780 
 
781 
    __HAL_RCC_HSE_PREDIV2_CONFIG(PLL2Init->HSEPrediv2Value);
 781 
    /* Configure the main PLL2 multiplication factors. */
782 
 
 782 
    __HAL_RCC_PLL2_CONFIG(PLL2Init->PLL2MUL);
783 
    /* Configure the main PLL2 multiplication factors. */
 783 
 
784 
    __HAL_RCC_PLL2_CONFIG(PLL2Init->PLL2MUL);
 784 
    /* Enable the main PLL2. */
785 
 
 785 
    __HAL_RCC_PLL2_ENABLE();
786 
    /* Enable the main PLL2. */
 786 
 
787 
    __HAL_RCC_PLL2_ENABLE();
 787 
    /* Get Start Tick*/
788 
 
 788 
    tickstart = HAL_GetTick();
789 
    /* Get Start Tick*/
 789 
 
790 
    tickstart = HAL_GetTick();
 790 
    /* Wait till PLL2 is ready */
791 
 
 791 
    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY)  == RESET)
792 
    /* Wait till PLL2 is ready */
 792 
    {
793 
    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY)  == RESET)
 793 
      if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
794 
    {
 794 
      {
795 
      if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
 795 
        return HAL_TIMEOUT;
796 
      {
 796 
      }
797 
        return HAL_TIMEOUT;
 797 
    }
798 
      }
 798 
  }
799 
    }
 799 
 
800 
  }
 800 
  return HAL_OK;
801 
 
 801 
}
802 
  return HAL_OK;
 802 
 
803 
}
 803 
/**
804 
 
 804 
  * @brief  Disable PLL2
805 
/**
 805 
  * @note   PLL2 is not disabled if used indirectly as system clock.
806 
  * @brief  Disable PLL2
 806 
  * @retval HAL status
807 
  * @note   PLL2 is not disabled if used indirectly as system clock.
 807 
  */
808 
  * @retval HAL status
 808 
HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void)
809 
  */
 809 
{
810 
HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void)
 810 
  uint32_t tickstart = 0U;
811 
{
 811 
 
812 
  uint32_t tickstart = 0U;
 812 
  /* This bit can not be cleared if the PLL2 clock is used indirectly as system
813 
 
 813 
    clock (i.e. it is used as PLL clock entry that is used as system clock). */
814 
  /* This bit can not be cleared if the PLL2 clock is used indirectly as system
 814 
  if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
815 
    clock (i.e. it is used as PLL clock entry that is used as system clock). */
 815 
      (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
816 
  if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
 816 
      ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
817 
      (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
 817 
  {
818 
      ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
 818 
    return HAL_ERROR;
819 
  {
 819 
  }
820 
    return HAL_ERROR;
 820 
  else
821 
  }
 821 
  {
822 
  else
 822 
    /* Disable the main PLL2. */
823 
  {
 823 
    __HAL_RCC_PLL2_DISABLE();
824 
    /* Disable the main PLL2. */
 824 
 
825 
    __HAL_RCC_PLL2_DISABLE();
 825 
    /* Get Start Tick*/
826 
 
 826 
    tickstart = HAL_GetTick();
827 
    /* Get Start Tick*/
 827 
 
828 
    tickstart = HAL_GetTick();
 828 
    /* Wait till PLL2 is disabled */
829 
 
 829 
    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY)  != RESET)
830 
    /* Wait till PLL2 is disabled */
 830 
    {
831 
    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY)  != RESET)
 831 
      if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
832 
    {
 832 
      {
833 
      if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
 833 
        return HAL_TIMEOUT;
834 
      {
 834 
      }
835 
        return HAL_TIMEOUT;
 835 
    }
836 
      }
 836 
  }
837 
    }
 837 
 
838 
  }
 838 
  return HAL_OK;
839 
 
 839 
}
840 
  return HAL_OK;
 840 
 
841 
}
 841 
/**
842 
 
 842 
  * @}
843 
/**
 843 
  */
844 
  * @}
 844 
#endif /* STM32F105xC || STM32F107xC */
845 
  */
 845 
 
846 
#endif /* STM32F105xC || STM32F107xC */
 846 
/**
847 
 
 847 
  * @}
848 
/**
 848 
  */
849 
  * @}
 849 
 
850 
  */
 850 
/**
851 
 
 851 
  * @}
852 
/**
 852 
  */
853 
  * @}
 853 
 
854 
  */
 854 
#endif /* HAL_RCC_MODULE_ENABLED */
855 
 
 855 
 
856 
#endif /* HAL_RCC_MODULE_ENABLED */
 856 
/**
857 
 
 857 
  * @}
858 
/**
 858 
  */
859 
  * @}
 859 
 
860 
  */
 860 
 
861 
 
 - 
 
862 
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 - 
 
863 
 
 -