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Line 12... Line 12...
12 
  ==============================================================================
 12 
  ==============================================================================
13 
                      ##### RCC specific features #####
 13 
                      ##### RCC specific features #####
14 
  ==============================================================================
 14 
  ==============================================================================
15 
    [..]
 15 
    [..]
16 
      After reset the device is running from Internal High Speed oscillator
 16 
      After reset the device is running from Internal High Speed oscillator
17 
      (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled,
 17 
      (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled,
18 
      and all peripherals are off except internal SRAM, Flash and JTAG.
 18 
      and all peripherals are off except internal SRAM, Flash and JTAG.
19 
      (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;
 19 
      (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;
20 
          all peripherals mapped on these buses are running at HSI speed.
 20 
          all peripherals mapped on these buses are running at HSI speed.
21 
      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
 21 
      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
22 
      (+) All GPIOs are in input floating state, except the JTAG pins which
 22 
      (+) All GPIOs are in input floating state, except the JTAG pins which
23 
          are assigned to be used for debug purpose.
 23 
          are assigned to be used for debug purpose.
24 
    [..] Once the device started from reset, the user application has to:
 24 
    [..] Once the device started from reset, the user application has to:
25 
      (+) Configure the clock source to be used to drive the System clock
 25 
      (+) Configure the clock source to be used to drive the System clock
26 
          (if the application needs higher frequency/performance)
 26 
          (if the application needs higher frequency/performance)
27 
      (+) Configure the System clock frequency and Flash settings  
 27 
      (+) Configure the System clock frequency and Flash settings
28 
      (+) Configure the AHB and APB buses prescalers
 28 
      (+) Configure the AHB and APB buses prescalers
29 
      (+) Enable the clock for the peripheral(s) to be used
 29 
      (+) Enable the clock for the peripheral(s) to be used
30 
      (+) Configure the clock source(s) for peripherals whose clocks are not
 30 
      (+) Configure the clock source(s) for peripherals whose clocks are not
31 
          derived from the System clock (I2S, RTC, ADC, USB OTG FS)
 31 
          derived from the System clock (I2S, RTC, ADC, USB OTG FS)
32 
 
 32 
 
33 
                      ##### RCC Limitations #####
 33 
                      ##### RCC Limitations #####
34 
  ==============================================================================
 34 
  ==============================================================================
35 
    [..]
 35 
    [..]
36 
      A delay between an RCC peripheral clock enable and the effective peripheral
 36 
      A delay between an RCC peripheral clock enable and the effective peripheral
37 
      enabling should be taken into account in order to manage the peripheral read/write
 37 
      enabling should be taken into account in order to manage the peripheral read/write
38 
      from/to registers.
 38 
      from/to registers.
39 
      (+) This delay depends on the peripheral mapping.
 39 
      (+) This delay depends on the peripheral mapping.
40 
        (++) AHB & APB peripherals, 1 dummy read is necessary
 40 
        (++) AHB & APB peripherals, 1 dummy read is necessary
41 
 
 41 
 
42 
    [..]  
 42 
    [..]
43 
      Workarounds:
 43 
      Workarounds:
44 
      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
 44 
      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
45 
          inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
 45 
          inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
46 
 
 46 
 
47 
  @endverbatim
 47 
  @endverbatim
48 
  ******************************************************************************
 48 
  ******************************************************************************
49 
  * @attention
 49 
  * @attention
50 
  *
 50 
  *
51 
  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
 51 
  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
52 
  *
 - 
 
53 
  * Redistribution and use in source and binary forms, with or without modification,
 - 
 
54 
  * are permitted provided that the following conditions are met:
 - 
 
55 
  *   1. Redistributions of source code must retain the above copyright notice,
 - 
 
56 
  *      this list of conditions and the following disclaimer.
 - 
 
57 
  *   2. Redistributions in binary form must reproduce the above copyright notice,
 - 
 
58 
  *      this list of conditions and the following disclaimer in the documentation
 - 
 
59 
  *      and/or other materials provided with the distribution.
 - 
 
60 
  *   3. Neither the name of STMicroelectronics nor the names of its contributors
 - 
 
61 
  *      may be used to endorse or promote products derived from this software
 - 
 
62 
  *      without specific prior written permission.
 52 
  * All rights reserved.</center></h2>
63 
  *
 53 
  *
64 
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 54 
  * This software component is licensed by ST under BSD 3-Clause license,
65 
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 - 
 
66 
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 - 
 
67 
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 - 
 
68 
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 - 
 
69 
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 55 
  * the "License"; You may not use this file except in compliance with the
70 
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 56 
  * License. You may obtain a copy of the License at:
71 
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 - 
 
72 
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 - 
 
73 
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 57 
  *                        opensource.org/licenses/BSD-3-Clause
74 
  *
 58 
  *
75 
  ******************************************************************************  
 59 
  ******************************************************************************
76 
*/
 60 
  */
77 
 
 61 
 
78 
/* Includes ------------------------------------------------------------------*/
 62 
/* Includes ------------------------------------------------------------------*/
79 
#include "stm32f1xx_hal.h"
 63 
#include "stm32f1xx_hal.h"
80 
 
 64 
 
81 
/** @addtogroup STM32F1xx_HAL_Driver
 65 
/** @addtogroup STM32F1xx_HAL_Driver
82 
  * @{
 66 
  * @{
Line 125... Line 109...
125 
 
 109 
 
126 
/** @defgroup RCC_Exported_Functions RCC Exported Functions
 110 
/** @defgroup RCC_Exported_Functions RCC Exported Functions
127 
  * @{
 111 
  * @{
128 
  */
 112 
  */
129 
 
 113 
 
130 
/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
 114 
/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
131 
  *  @brief    Initialization and Configuration functions
 115 
  *  @brief    Initialization and Configuration functions
132 
  *
 116 
  *
133 
  @verbatim    
 117 
  @verbatim
134 
  ===============================================================================
 118 
  ===============================================================================
135 
           ##### Initialization and de-initialization functions #####
 119 
           ##### Initialization and de-initialization functions #####
136 
  ===============================================================================
 120 
  ===============================================================================
137 
    [..]
 121 
    [..]
138 
      This section provides functions allowing to configure the internal/external oscillators
 122 
      This section provides functions allowing to configure the internal/external oscillators
Line 153... Line 137...
153 
      (#) PLL (clocked by HSI or HSE), featuring different output clocks:
 137 
      (#) PLL (clocked by HSI or HSE), featuring different output clocks:
154 
        (++) The first output is used to generate the high speed system clock (up to 72 MHz for STM32F10xxx or up to 24 MHz for STM32F100xx)
 138 
        (++) The first output is used to generate the high speed system clock (up to 72 MHz for STM32F10xxx or up to 24 MHz for STM32F100xx)
155 
        (++) The second output is used to generate the clock for the USB OTG FS (48 MHz)
 139 
        (++) The second output is used to generate the clock for the USB OTG FS (48 MHz)
156 
 
 140 
 
157 
      (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
 141 
      (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
158 
          and if a HSE clock failure occurs(HSE used directly or through PLL as System
 142 
          and if a HSE clock failure occurs(HSE used directly or through PLL as System
159 
          clock source), the System clocks automatically switched to HSI and an interrupt
 143 
          clock source), the System clocks automatically switched to HSI and an interrupt
160 
          is generated if enabled. The interrupt is linked to the Cortex-M3 NMI
 144 
          is generated if enabled. The interrupt is linked to the Cortex-M3 NMI
161 
          (Non-Maskable Interrupt) exception vector.
 145 
          (Non-Maskable Interrupt) exception vector.
162 
 
 146 
 
163 
      (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI,
 147 
      (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI,
164 
          HSE or PLL clock (divided by 2) on PA8 pin + PLL2CLK, PLL3CLK/2, PLL3CLK and XTI for STM32F105x/STM32F107x
 148 
          HSE or PLL clock (divided by 2) on PA8 pin + PLL2CLK, PLL3CLK/2, PLL3CLK and XTI for STM32F105x/STM32F107x
165 
 
 149 
 
Line 173... Line 157...
173 
          the peripherals mapped on these buses. You can use
 157 
          the peripherals mapped on these buses. You can use
174 
          "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
 158 
          "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
175 
 
 159 
 
176 
      -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
 160 
      -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
177 
          (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock
 161 
          (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock
178 
              divided by 128.
 162 
              divided by 128.
179 
          (+@) USB OTG FS and RTC: USB OTG FS require a frequency equal to 48 MHz
 163 
          (+@) USB OTG FS and RTC: USB OTG FS require a frequency equal to 48 MHz
180 
              to work correctly. This clock is derived of the main PLL through PLL Multiplier.
 164 
              to work correctly. This clock is derived of the main PLL through PLL Multiplier.
181 
          (+@) I2S interface on STM32F105x/STM32F107x can be derived from PLL3CLK
 165 
          (+@) I2S interface on STM32F105x/STM32F107x can be derived from PLL3CLK
182 
          (+@) IWDG clock which is always the LSI clock.
 166 
          (+@) IWDG clock which is always the LSI clock.
183 
 
 167 
 
184 
      (#) For STM32F10xxx, the maximum frequency of the SYSCLK and HCLK/PCLK2 is 72 MHz, PCLK1 36 MHz.
 168 
      (#) For STM32F10xxx, the maximum frequency of the SYSCLK and HCLK/PCLK2 is 72 MHz, PCLK1 36 MHz.
185 
          For STM32F100xx, the maximum frequency of the SYSCLK and HCLK/PCLK1/PCLK2 is 24 MHz.  
 169 
          For STM32F100xx, the maximum frequency of the SYSCLK and HCLK/PCLK1/PCLK2 is 24 MHz.
186 
          Depending on the SYSCLK frequency, the flash latency should be adapted accordingly.
 170 
          Depending on the SYSCLK frequency, the flash latency should be adapted accordingly.
187 
  @endverbatim
 171 
  @endverbatim
188 
  * @{
 172 
  * @{
189 
  */
 173 
  */
190 
 
 174 
 
191 
/*
 175 
/*
192 
  Additional consideration on the SYSCLK based on Latency settings:
 176 
  Additional consideration on the SYSCLK based on Latency settings:
193 
        +-----------------------------------------------+
 177 
        +-----------------------------------------------+
194 
        | Latency       | SYSCLK clock frequency (MHz)  |
 178 
        | Latency       | SYSCLK clock frequency (MHz)  |
195 
        |---------------|-------------------------------|
 179 
        |---------------|-------------------------------|
Line 254... Line 238...
254 
 
 238 
 
255 
  /* Update the SystemCoreClock global variable */
 239 
  /* Update the SystemCoreClock global variable */
256 
  SystemCoreClock = HSI_VALUE;
 240 
  SystemCoreClock = HSI_VALUE;
257 
 
 241 
 
258 
  /* Adapt Systick interrupt period */
 242 
  /* Adapt Systick interrupt period */
259 
  if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
 243 
  if (HAL_InitTick(uwTickPrio) != HAL_OK)
260 
  {
 244 
  {
261 
    return HAL_ERROR;
 245 
    return HAL_ERROR;
262 
  }
 246 
  }
263 
 
 247 
 
264 
  /* Get Start Tick */
 248 
  /* Get Start Tick */
Line 360... Line 344...
360 
  *         first and then HSE On or HSE Bypass.
 344 
  *         first and then HSE On or HSE Bypass.
361 
  * @retval HAL status
 345 
  * @retval HAL status
362 
  */
 346 
  */
363 
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
 347 
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
364 
{
 348 
{
365 
   uint32_t tickstart = 0U;
 349 
  uint32_t tickstart;
- 
 
 350 
  uint32_t pll_config;
- 
 
 351 
 
- 
 
 352 
  /* Check Null pointer */
- 
 
 353 
  if (RCC_OscInitStruct == NULL)
- 
 
 354 
  {
- 
 
 355 
    return HAL_ERROR;
366 
 
 356 
  }
- 
 
 357 
 
367 
  /* Check the parameters */
 358 
  /* Check the parameters */
368 
  assert_param(RCC_OscInitStruct != NULL);
 - 
 
369 
  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
 359 
  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
370 
 
 360 
 
371 
  /*------------------------------- HSE Configuration ------------------------*/
 361 
  /*------------------------------- HSE Configuration ------------------------*/
372 
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 362 
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
373 
  {
 363 
  {
374 
    /* Check the parameters */
 364 
    /* Check the parameters */
375 
    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
 365 
    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
376 
       
 366 
 
377 
    /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
 367 
    /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
378 
    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
 368 
    if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
379 
       || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
 369 
        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
380 
    {
 370 
    {
381 
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 371 
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
382 
      {
 372 
      {
383 
        return HAL_ERROR;
 373 
        return HAL_ERROR;
384 
      }
 374 
      }
385 
    }
 375 
    }
386 
    else
 376 
    else
387 
    {
 377 
    {
388 
      /* Set the new HSE configuration ---------------------------------------*/
 378 
      /* Set the new HSE configuration ---------------------------------------*/
389 
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 379 
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
390 
     
 - 
 
391 
 
 380 
 
- 
 
 381 
 
392 
       /* Check the HSE State */
 382 
      /* Check the HSE State */
393 
      if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
 383 
      if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
394 
      {
 384 
      {
395 
        /* Get Start Tick */
 385 
        /* Get Start Tick */
396 
        tickstart = HAL_GetTick();
 386 
        tickstart = HAL_GetTick();
397 
       
 387 
 
398 
        /* Wait till HSE is ready */
 388 
        /* Wait till HSE is ready */
399 
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 389 
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
400 
        {
 390 
        {
401 
          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
 391 
          if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
402 
          {
 392 
          {
403 
            return HAL_TIMEOUT;
 393 
            return HAL_TIMEOUT;
404 
          }
 394 
          }
405 
        }
 395 
        }
406 
      }
 396 
      }
407 
      else
 397 
      else
408 
      {
 398 
      {
409 
        /* Get Start Tick */
 399 
        /* Get Start Tick */
410 
        tickstart = HAL_GetTick();
 400 
        tickstart = HAL_GetTick();
411 
       
 401 
 
412 
        /* Wait till HSE is disabled */
 402 
        /* Wait till HSE is disabled */
413 
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
 403 
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
414 
        {
 404 
        {
415 
           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
 405 
          if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
416 
          {
 406 
          {
417 
            return HAL_TIMEOUT;
 407 
            return HAL_TIMEOUT;
418 
          }
 408 
          }
419 
        }
 409 
        }
420 
      }
 410 
      }
421 
    }
 411 
    }
422 
  }
 412 
  }
423 
  /*----------------------------- HSI Configuration --------------------------*/
 413 
  /*----------------------------- HSI Configuration --------------------------*/
424 
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
 414 
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
425 
  {
 415 
  {
426 
    /* Check the parameters */
 416 
    /* Check the parameters */
427 
    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
 417 
    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
428 
    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
 418 
    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
429 
 
 419 
 
430 
    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
 420 
    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
431 
    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
 421 
    if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
432 
       || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
 422 
        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
433 
    {
 423 
    {
434 
      /* When HSI is used as system clock it will not disabled */
 424 
      /* When HSI is used as system clock it will not disabled */
435 
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
 425 
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
436 
      {
 426 
      {
437 
        return HAL_ERROR;
 427 
        return HAL_ERROR;
438 
      }
 428 
      }
439 
      /* Otherwise, just the calibration is allowed */
 429 
      /* Otherwise, just the calibration is allowed */
440 
      else
 430 
      else
Line 444... Line 434...
444 
      }
 434 
      }
445 
    }
 435 
    }
446 
    else
 436 
    else
447 
    {
 437 
    {
448 
      /* Check the HSI State */
 438 
      /* Check the HSI State */
449 
      if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
 439 
      if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
450 
      {
 440 
      {
451 
       /* Enable the Internal High Speed oscillator (HSI). */
 441 
        /* Enable the Internal High Speed oscillator (HSI). */
452 
        __HAL_RCC_HSI_ENABLE();
 442 
        __HAL_RCC_HSI_ENABLE();
453 
 
 443 
 
454 
        /* Get Start Tick */
 444 
        /* Get Start Tick */
455 
        tickstart = HAL_GetTick();
 445 
        tickstart = HAL_GetTick();
456 
 
 446 
 
457 
        /* Wait till HSI is ready */
 447 
        /* Wait till HSI is ready */
458 
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 448 
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
459 
        {
 449 
        {
460 
          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
 450 
          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
461 
          {
 451 
          {
462 
            return HAL_TIMEOUT;
 452 
            return HAL_TIMEOUT;
463 
          }
 453 
          }
464 
        }
 454 
        }
465 
 
 455 
 
Line 473... Line 463...
473 
 
 463 
 
474 
        /* Get Start Tick */
 464 
        /* Get Start Tick */
475 
        tickstart = HAL_GetTick();
 465 
        tickstart = HAL_GetTick();
476 
 
 466 
 
477 
        /* Wait till HSI is disabled */
 467 
        /* Wait till HSI is disabled */
478 
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
 468 
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
479 
        {
 469 
        {
480 
          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
 470 
          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
481 
          {
 471 
          {
482 
            return HAL_TIMEOUT;
 472 
            return HAL_TIMEOUT;
483 
          }
 473 
          }
484 
        }
 474 
        }
485 
      }
 475 
      }
486 
    }
 476 
    }
487 
  }
 477 
  }
488 
  /*------------------------------ LSI Configuration -------------------------*/
 478 
  /*------------------------------ LSI Configuration -------------------------*/
489 
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
 479 
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
490 
  {
 480 
  {
491 
    /* Check the parameters */
 481 
    /* Check the parameters */
492 
    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
 482 
    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
493 
 
 483 
 
494 
    /* Check the LSI State */
 484 
    /* Check the LSI State */
495 
    if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
 485 
    if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
496 
    {
 486 
    {
497 
      /* Enable the Internal Low Speed oscillator (LSI). */
 487 
      /* Enable the Internal Low Speed oscillator (LSI). */
498 
      __HAL_RCC_LSI_ENABLE();
 488 
      __HAL_RCC_LSI_ENABLE();
499 
 
 489 
 
500 
      /* Get Start Tick */
 490 
      /* Get Start Tick */
501 
      tickstart = HAL_GetTick();
 491 
      tickstart = HAL_GetTick();
502 
 
 492 
 
503 
      /* Wait till LSI is ready */  
 493 
      /* Wait till LSI is ready */
504 
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
 494 
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
505 
      {
 495 
      {
506 
        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
 496 
        if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
507 
        {
 497 
        {
508 
          return HAL_TIMEOUT;
 498 
          return HAL_TIMEOUT;
509 
        }
 499 
        }
510 
      }
 500 
      }
511 
      /*  To have a fully stabilized clock in the specified range, a software delay of 1ms
 501 
      /*  To have a fully stabilized clock in the specified range, a software delay of 1ms
512 
          should be added.*/
 502 
          should be added.*/
513 
      RCC_Delay(1);
 503 
      RCC_Delay(1);
514 
    }
 504 
    }
515 
    else
 505 
    else
516 
    {
 506 
    {
Line 518... Line 508...
518 
      __HAL_RCC_LSI_DISABLE();
 508 
      __HAL_RCC_LSI_DISABLE();
519 
 
 509 
 
520 
      /* Get Start Tick */
 510 
      /* Get Start Tick */
521 
      tickstart = HAL_GetTick();
 511 
      tickstart = HAL_GetTick();
522 
 
 512 
 
523 
      /* Wait till LSI is disabled */  
 513 
      /* Wait till LSI is disabled */
524 
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
 514 
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
525 
      {
 515 
      {
526 
        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
 516 
        if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
527 
        {
 517 
        {
528 
          return HAL_TIMEOUT;
 518 
          return HAL_TIMEOUT;
529 
        }
 519 
        }
530 
      }
 520 
      }
531 
    }
 521 
    }
532 
  }
 522 
  }
533 
  /*------------------------------ LSE Configuration -------------------------*/
 523 
  /*------------------------------ LSE Configuration -------------------------*/
534 
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
 524 
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
535 
  {
 525 
  {
536 
    FlagStatus       pwrclkchanged = RESET;
 526 
    FlagStatus       pwrclkchanged = RESET;
537 
 
 527 
 
538 
    /* Check the parameters */
 528 
    /* Check the parameters */
539 
    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
 529 
    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
540 
 
 530 
 
541 
    /* Update LSE configuration in Backup Domain control register    */
 531 
    /* Update LSE configuration in Backup Domain control register    */
542 
    /* Requires to enable write access to Backup Domain of necessary */
 532 
    /* Requires to enable write access to Backup Domain of necessary */
543 
    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
 533 
    if (__HAL_RCC_PWR_IS_CLK_DISABLED())
544 
    {
 534 
    {
545 
      __HAL_RCC_PWR_CLK_ENABLE();
 535 
      __HAL_RCC_PWR_CLK_ENABLE();
546 
      pwrclkchanged = SET;
 536 
      pwrclkchanged = SET;
547 
    }
 537 
    }
548 
 
 538 
 
549 
    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 539 
    if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
550 
    {
 540 
    {
551 
      /* Enable write access to Backup domain */
 541 
      /* Enable write access to Backup domain */
552 
      SET_BIT(PWR->CR, PWR_CR_DBP);
 542 
      SET_BIT(PWR->CR, PWR_CR_DBP);
553 
 
 543 
 
554 
      /* Wait for Backup domain Write protection disable */
 544 
      /* Wait for Backup domain Write protection disable */
555 
      tickstart = HAL_GetTick();
 545 
      tickstart = HAL_GetTick();
556 
 
 546 
 
557 
      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 547 
      while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
558 
      {
 548 
      {
559 
        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 549 
        if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
560 
        {
 550 
        {
561 
          return HAL_TIMEOUT;
 551 
          return HAL_TIMEOUT;
562 
        }
 552 
        }
563 
      }
 553 
      }
564 
    }
 554 
    }
565 
 
 555 
 
566 
    /* Set the new LSE configuration -----------------------------------------*/
 556 
    /* Set the new LSE configuration -----------------------------------------*/
567 
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 557 
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
568 
    /* Check the LSE State */
 558 
    /* Check the LSE State */
569 
    if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
 559 
    if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
570 
    {
 560 
    {
571 
      /* Get Start Tick */
 561 
      /* Get Start Tick */
572 
      tickstart = HAL_GetTick();
 562 
      tickstart = HAL_GetTick();
573 
 
 563 
 
574 
      /* Wait till LSE is ready */  
 564 
      /* Wait till LSE is ready */
575 
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
 565 
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
576 
      {
 566 
      {
577 
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 567 
        if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
578 
        {
 568 
        {
579 
          return HAL_TIMEOUT;
 569 
          return HAL_TIMEOUT;
580 
        }
 570 
        }
581 
      }
 571 
      }
582 
    }
 572 
    }
583 
    else
 573 
    else
584 
    {
 574 
    {
585 
      /* Get Start Tick */
 575 
      /* Get Start Tick */
586 
      tickstart = HAL_GetTick();
 576 
      tickstart = HAL_GetTick();
587 
 
 577 
 
588 
      /* Wait till LSE is disabled */  
 578 
      /* Wait till LSE is disabled */
589 
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
 579 
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
590 
      {
 580 
      {
591 
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 581 
        if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
592 
        {
 582 
        {
593 
          return HAL_TIMEOUT;
 583 
          return HAL_TIMEOUT;
594 
        }
 584 
        }
595 
      }
 585 
      }
596 
    }
 586 
    }
597 
 
 587 
 
598 
    /* Require to disable power clock if necessary */
 588 
    /* Require to disable power clock if necessary */
599 
    if(pwrclkchanged == SET)
 589 
    if (pwrclkchanged == SET)
600 
    {
 590 
    {
601 
      __HAL_RCC_PWR_CLK_DISABLE();
 591 
      __HAL_RCC_PWR_CLK_DISABLE();
602 
    }
 592 
    }
603 
  }
 593 
  }
604 
 
 594 
 
Line 606... Line 596...
606 
  /*-------------------------------- PLL2 Configuration -----------------------*/
 596 
  /*-------------------------------- PLL2 Configuration -----------------------*/
607 
  /* Check the parameters */
 597 
  /* Check the parameters */
608 
  assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State));
 598 
  assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State));
609 
  if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE)
 599 
  if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE)
610 
  {
 600 
  {
611 
    /* This bit can not be cleared if the PLL2 clock is used indirectly as system
 601 
    /* This bit can not be cleared if the PLL2 clock is used indirectly as system
612 
      clock (i.e. it is used as PLL clock entry that is used as system clock). */
 602 
      clock (i.e. it is used as PLL clock entry that is used as system clock). */
613 
    if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
 603 
    if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
614 
        (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
 604 
        (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
615 
        ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
 605 
        ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
616 
    {
 606 
    {
617 
      return HAL_ERROR;
 607 
      return HAL_ERROR;
618 
    }
 608 
    }
619 
    else
 609 
    else
620 
    {
 610 
    {
621 
      if((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON)
 611 
      if ((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON)
622 
      {
 612 
      {
623 
        /* Check the parameters */
 613 
        /* Check the parameters */
624 
        assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL));
 614 
        assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL));
625 
        assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value));
 615 
        assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value));
626 
 
 616 
 
627 
        /* Prediv2 can be written only when the PLLI2S is disabled. */
 617 
        /* Prediv2 can be written only when the PLLI2S is disabled. */
628 
        /* Return an error only if new value is different from the programmed value */
 618 
        /* Return an error only if new value is different from the programmed value */
629 
        if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL3ON) && \
 619 
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \
630 
          (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value))
 620 
            (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value))
631 
        {
 621 
        {
632 
          return HAL_ERROR;
 622 
          return HAL_ERROR;
633 
        }
 623 
        }
634 
       
 624 
 
635 
        /* Disable the main PLL2. */
 625 
        /* Disable the main PLL2. */
636 
        __HAL_RCC_PLL2_DISABLE();
 626 
        __HAL_RCC_PLL2_DISABLE();
637 
       
 627 
 
638 
        /* Get Start Tick */
 628 
        /* Get Start Tick */
639 
        tickstart = HAL_GetTick();
 629 
        tickstart = HAL_GetTick();
640 
       
 630 
 
641 
        /* Wait till PLL2 is disabled */
 631 
        /* Wait till PLL2 is disabled */
642 
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
 632 
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
643 
        {
 633 
        {
644 
          if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
 634 
          if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
645 
          {
 635 
          {
646 
            return HAL_TIMEOUT;
 636 
            return HAL_TIMEOUT;
647 
          }
 637 
          }
648 
        }
 638 
        }
649 
 
 639 
 
Line 658... Line 648...
658 
 
 648 
 
659 
        /* Get Start Tick */
 649 
        /* Get Start Tick */
660 
        tickstart = HAL_GetTick();
 650 
        tickstart = HAL_GetTick();
661 
 
 651 
 
662 
        /* Wait till PLL2 is ready */
 652 
        /* Wait till PLL2 is ready */
663 
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY)  == RESET)
 653 
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY)  == RESET)
664 
        {
 654 
        {
665 
          if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
 655 
          if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
666 
          {
 656 
          {
667 
            return HAL_TIMEOUT;
 657 
            return HAL_TIMEOUT;
668 
          }
 658 
          }
669 
        }
 659 
        }
670 
      }
 660 
      }
671 
      else
 661 
      else
672 
      {
 662 
      {
673 
       /* Set PREDIV1 source to HSE */
 663 
        /* Set PREDIV1 source to HSE */
674 
        CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC);
 664 
        CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC);
675 
 
 665 
 
676 
        /* Disable the main PLL2. */
 666 
        /* Disable the main PLL2. */
677 
        __HAL_RCC_PLL2_DISABLE();
 667 
        __HAL_RCC_PLL2_DISABLE();
678 
 
 668 
 
679 
        /* Get Start Tick */
 669 
        /* Get Start Tick */
680 
        tickstart = HAL_GetTick();
 670 
        tickstart = HAL_GetTick();
681 
 
 671 
 
682 
        /* Wait till PLL2 is disabled */  
 672 
        /* Wait till PLL2 is disabled */
683 
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY)  != RESET)
 673 
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY)  != RESET)
684 
        {
 674 
        {
685 
          if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
 675 
          if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
686 
          {
 676 
          {
687 
            return HAL_TIMEOUT;
 677 
            return HAL_TIMEOUT;
688 
          }
 678 
          }
689 
        }
 679 
        }
690 
      }
 680 
      }
Line 696... Line 686...
696 
  /* Check the parameters */
 686 
  /* Check the parameters */
697 
  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
 687 
  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
698 
  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
 688 
  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
699 
  {
 689 
  {
700 
    /* Check if the PLL is used as system clock or not */
 690 
    /* Check if the PLL is used as system clock or not */
701 
    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
 691 
    if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
702 
    {
 692 
    {
703 
      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
 693 
      if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
704 
      {
 694 
      {
705 
        /* Check the parameters */
 695 
        /* Check the parameters */
706 
        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
 696 
        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
707 
        assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
 697 
        assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
708 
 
 698 
 
Line 711... Line 701...
711 
 
 701 
 
712 
        /* Get Start Tick */
 702 
        /* Get Start Tick */
713 
        tickstart = HAL_GetTick();
 703 
        tickstart = HAL_GetTick();
714 
 
 704 
 
715 
        /* Wait till PLL is disabled */
 705 
        /* Wait till PLL is disabled */
716 
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
 706 
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
717 
        {
 707 
        {
718 
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 708 
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
719 
          {
 709 
          {
720 
            return HAL_TIMEOUT;
 710 
            return HAL_TIMEOUT;
721 
          }
 711 
          }
722 
        }
 712 
        }
723 
 
 713 
 
724 
        /* Configure the HSE prediv factor --------------------------------*/
 714 
        /* Configure the HSE prediv factor --------------------------------*/
725 
        /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
 715 
        /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
726 
        if(RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
 716 
        if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
727 
        {
 717 
        {
728 
          /* Check the parameter */
 718 
          /* Check the parameter */
729 
          assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue));
 719 
          assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue));
730 
#if defined(RCC_CFGR2_PREDIV1SRC)
 720 
#if defined(RCC_CFGR2_PREDIV1SRC)
731 
          assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source));
 721 
          assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source));
Line 746... Line 736...
746 
 
 736 
 
747 
        /* Get Start Tick */
 737 
        /* Get Start Tick */
748 
        tickstart = HAL_GetTick();
 738 
        tickstart = HAL_GetTick();
749 
 
 739 
 
750 
        /* Wait till PLL is ready */
 740 
        /* Wait till PLL is ready */
751 
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  == RESET)
 741 
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  == RESET)
752 
        {
 742 
        {
753 
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 743 
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
754 
          {
 744 
          {
755 
            return HAL_TIMEOUT;
 745 
            return HAL_TIMEOUT;
756 
          }
 746 
          }
757 
        }
 747 
        }
758 
      }
 748 
      }
Line 762... Line 752...
762 
        __HAL_RCC_PLL_DISABLE();
 752 
        __HAL_RCC_PLL_DISABLE();
763 
 
 753 
 
764 
        /* Get Start Tick */
 754 
        /* Get Start Tick */
765 
        tickstart = HAL_GetTick();
 755 
        tickstart = HAL_GetTick();
766 
 
 756 
 
767 
        /* Wait till PLL is disabled */  
 757 
        /* Wait till PLL is disabled */
768 
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
 758 
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
769 
        {
 759 
        {
770 
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 760 
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
771 
          {
 761 
          {
772 
            return HAL_TIMEOUT;
 762 
            return HAL_TIMEOUT;
773 
          }
 763 
          }
774 
        }
 764 
        }
775 
      }
 765 
      }
776 
    }
 766 
    }
777 
    else
 767 
    else
778 
    {
 768 
    {
- 
 
 769 
      /* Check if there is a request to disable the PLL used as System clock source */
- 
 
 770 
      if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
- 
 
 771 
      {
779 
      return HAL_ERROR;
 772 
        return HAL_ERROR;
- 
 
 773 
      }
- 
 
 774 
      else
- 
 
 775 
      {
- 
 
 776 
        /* Do not return HAL_ERROR if request repeats the current configuration */
- 
 
 777 
        pll_config = RCC->CFGR;
- 
 
 778 
        if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
- 
 
 779 
            (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL))
- 
 
 780 
        {
- 
 
 781 
          return HAL_ERROR;
- 
 
 782 
        }
- 
 
 783 
      }
780 
    }
 784 
    }
781 
  }
 785 
  }
782 
 
 786 
 
783 
  return HAL_OK;
 787 
  return HAL_OK;
784 
}
 788 
}
785 
 
 789 
 
786 
/**
 790 
/**
787 
  * @brief  Initializes the CPU, AHB and APB buses clocks according to the specified
 791 
  * @brief  Initializes the CPU, AHB and APB buses clocks according to the specified
788 
  *         parameters in the RCC_ClkInitStruct.
 792 
  *         parameters in the RCC_ClkInitStruct.
789 
  * @param  RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
 793 
  * @param  RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
790 
  *         contains the configuration information for the RCC peripheral.
 794 
  *         contains the configuration information for the RCC peripheral.
791 
  * @param  FLatency FLASH Latency                  
 795 
  * @param  FLatency FLASH Latency
792 
  *          The value of this parameter depend on device used within the same series
 796 
  *          The value of this parameter depend on device used within the same series
793 
  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
 797 
  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
794 
  *         and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function
 798 
  *         and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function
795 
  *
 799 
  *
796 
  * @note   The HSI is used (enabled by hardware) as system clock source after
 800 
  * @note   The HSI is used (enabled by hardware) as system clock source after
797 
  *         start-up from Reset, wake-up from STOP and STANDBY mode, or in case
 801 
  *         start-up from Reset, wake-up from STOP and STANDBY mode, or in case
798 
  *         of failure of the HSE used directly or indirectly as system clock
 802 
  *         of failure of the HSE used directly or indirectly as system clock
799 
  *         (if the Clock Security System CSS is enabled).
 803 
  *         (if the Clock Security System CSS is enabled).
800 
  *          
 804 
  *
801 
  * @note   A switch from one clock source to another occurs only if the target
 805 
  * @note   A switch from one clock source to another occurs only if the target
802 
  *         clock source is ready (clock stable after start-up delay or PLL locked).
 806 
  *         clock source is ready (clock stable after start-up delay or PLL locked).
803 
  *         If a clock source which is not yet ready is selected, the switch will
 807 
  *         If a clock source which is not yet ready is selected, the switch will
804 
  *         occur when the clock source will be ready.
 808 
  *         occur when the clock source will be ready.
805 
  *         You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
 809 
  *         You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
806 
  *         currently used as system clock source.
 810 
  *         currently used as system clock source.
807 
  * @retval HAL status
 811 
  * @retval HAL status
808 
  */
 812 
  */
809 
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
 813 
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
810 
{
 814 
{
811 
  uint32_t tickstart = 0U;
 815 
  uint32_t tickstart;
- 
 
 816 
 
- 
 
 817 
  /* Check Null pointer */
- 
 
 818 
  if (RCC_ClkInitStruct == NULL)
- 
 
 819 
  {
- 
 
 820 
    return HAL_ERROR;
- 
 
 821 
  }
812 
 
 822 
 
813 
  /* Check the parameters */
 823 
  /* Check the parameters */
814 
  assert_param(RCC_ClkInitStruct != NULL);
 - 
 
815 
  assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
 824 
  assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
816 
  assert_param(IS_FLASH_LATENCY(FLatency));
 825 
  assert_param(IS_FLASH_LATENCY(FLatency));
817 
 
 826 
 
818 
  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
 827 
  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
819 
  must be correctly programmed according to the frequency of the CPU clock
 828 
  must be correctly programmed according to the frequency of the CPU clock
820 
    (HCLK) of the device. */
 829 
    (HCLK) of the device. */
821 
 
 830 
 
822 
#if defined(FLASH_ACR_LATENCY)
 831 
#if defined(FLASH_ACR_LATENCY)
823 
  /* Increasing the number of wait states because of higher CPU frequency */
 832 
  /* Increasing the number of wait states because of higher CPU frequency */
824 
  if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
 833 
  if (FLatency > __HAL_FLASH_GET_LATENCY())
825 
  {    
 834 
  {
826 
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
 835 
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
827 
    __HAL_FLASH_SET_LATENCY(FLatency);
 836 
    __HAL_FLASH_SET_LATENCY(FLatency);
828 
 
 837 
 
829 
    /* Check that the new number of wait states is taken into account to access the Flash
 838 
    /* Check that the new number of wait states is taken into account to access the Flash
830 
    memory by reading the FLASH_ACR register */
 839 
    memory by reading the FLASH_ACR register */
831 
    if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
 840 
    if (__HAL_FLASH_GET_LATENCY() != FLatency)
832 
    {
 841 
  {
833 
      return HAL_ERROR;
 842 
    return HAL_ERROR;
834 
    }
 - 
 
835 
  }
 843 
  }
- 
 
 844 
}
836 
 
 845 
 
837 
#endif /* FLASH_ACR_LATENCY */
 846 
#endif /* FLASH_ACR_LATENCY */
838 
  /*-------------------------- HCLK Configuration --------------------------*/
 847 
/*-------------------------- HCLK Configuration --------------------------*/
839 
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
 848 
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
840 
  {
 849 
  {
841 
    /* Set the highest APBx dividers in order to ensure that we do not go through
 850 
    /* Set the highest APBx dividers in order to ensure that we do not go through
842 
    a non-spec phase whatever we decrease or increase HCLK. */
 851 
    a non-spec phase whatever we decrease or increase HCLK. */
843 
    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 852 
    if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
844 
    {
 853 
    {
845 
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
 854 
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
846 
    }
 855 
    }
847 
 
 856 
 
848 
    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 857 
    if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
849 
    {
 858 
    {
850 
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
 859 
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
851 
    }
 860 
    }
852 
 
 861 
 
853 
    /* Set the new HCLK clock divider */
 862 
    /* Set the new HCLK clock divider */
854 
    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
 863 
    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
855 
    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
 864 
    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
856 
  }
 865 
  }
857 
 
 866 
 
858 
  /*------------------------- SYSCLK Configuration ---------------------------*/
 867 
  /*------------------------- SYSCLK Configuration ---------------------------*/
859 
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
 868 
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
860 
  {    
 869 
  {
861 
    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
 870 
    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
862 
 
 871 
 
863 
    /* HSE is selected as System Clock Source */
 872 
    /* HSE is selected as System Clock Source */
864 
    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 873 
    if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
865 
    {
 874 
    {
866 
      /* Check the HSE ready flag */  
 875 
      /* Check the HSE ready flag */
867 
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 876 
      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
868 
      {
 877 
      {
869 
        return HAL_ERROR;
 878 
        return HAL_ERROR;
870 
      }
 879 
      }
871 
    }
 880 
    }
872 
    /* PLL is selected as System Clock Source */
 881 
    /* PLL is selected as System Clock Source */
873 
    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
 882 
    else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
874 
    {
 883 
    {
875 
      /* Check the PLL ready flag */  
 884 
      /* Check the PLL ready flag */
876 
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
 885 
      if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
877 
      {
 886 
      {
878 
        return HAL_ERROR;
 887 
        return HAL_ERROR;
879 
      }
 888 
      }
880 
    }
 889 
    }
881 
    /* HSI is selected as System Clock Source */
 890 
    /* HSI is selected as System Clock Source */
882 
    else
 891 
    else
883 
    {
 892 
    {
884 
      /* Check the HSI ready flag */  
 893 
      /* Check the HSI ready flag */
885 
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 894 
      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
886 
      {
 895 
      {
887 
        return HAL_ERROR;
 896 
        return HAL_ERROR;
888 
      }
 897 
      }
889 
    }
 898 
    }
890 
    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
 899 
    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
891 
 
 900 
 
892 
    /* Get Start Tick */
 901 
    /* Get Start Tick */
893 
    tickstart = HAL_GetTick();
 902 
    tickstart = HAL_GetTick();
894 
 
 903 
 
895 
    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 - 
 
896 
    {
 - 
 
897 
      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
 904 
    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
898 
      {
 - 
 
899 
        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
 - 
 
900 
        {
 - 
 
901 
          return HAL_TIMEOUT;
 - 
 
902 
        }
 - 
 
903 
      }
 - 
 
904 
    }
 - 
 
905 
    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
 - 
 
906 
    {
 905 
    {
907 
      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
 906 
      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
908 
      {
 907 
      {
909 
        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
 - 
 
910 
        {
 - 
 
911 
          return HAL_TIMEOUT;
 908 
        return HAL_TIMEOUT;
912 
        }
 - 
 
913 
      }
 909 
      }
914 
    }
 910 
    }
915 
    else
 - 
 
916 
    {
 911 
  }
917 
      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
 - 
 
918 
      {
 - 
 
919 
        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
 - 
 
920 
        {
 - 
 
921 
          return HAL_TIMEOUT;
 - 
 
922 
        }
 - 
 
923 
      }
 - 
 
924 
    }      
 - 
 
925 
  }    
 912 
 
926 
#if defined(FLASH_ACR_LATENCY)
 913 
#if defined(FLASH_ACR_LATENCY)
927 
  /* Decreasing the number of wait states because of lower CPU frequency */
 914 
  /* Decreasing the number of wait states because of lower CPU frequency */
928 
  if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
 915 
  if (FLatency < __HAL_FLASH_GET_LATENCY())
929 
  {    
 916 
  {
930 
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
 917 
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
931 
    __HAL_FLASH_SET_LATENCY(FLatency);
 918 
    __HAL_FLASH_SET_LATENCY(FLatency);
932 
 
 919 
 
933 
    /* Check that the new number of wait states is taken into account to access the Flash
 920 
    /* Check that the new number of wait states is taken into account to access the Flash
934 
    memory by reading the FLASH_ACR register */
 921 
    memory by reading the FLASH_ACR register */
935 
    if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
 922 
    if (__HAL_FLASH_GET_LATENCY() != FLatency)
936 
    {
 923 
  {
937 
      return HAL_ERROR;
 924 
    return HAL_ERROR;
938 
    }
 925 
  }
939 
  }    
 926 
}
940 
#endif /* FLASH_ACR_LATENCY */
 927 
#endif /* FLASH_ACR_LATENCY */
941 
 
 928 
 
942 
  /*-------------------------- PCLK1 Configuration ---------------------------*/
 929 
/*-------------------------- PCLK1 Configuration ---------------------------*/
943 
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 930 
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
944 
  {
 931 
  {
945 
    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
 932 
    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
946 
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
 933 
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
947 
  }
 934 
  }
948 
 
 935 
 
949 
  /*-------------------------- PCLK2 Configuration ---------------------------*/
 936 
  /*-------------------------- PCLK2 Configuration ---------------------------*/
950 
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 937 
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
951 
  {
 938 
  {
952 
    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
 939 
    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
953 
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
 940 
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
954 
  }
 941 
  }
955 
 
 942 
 
956 
  /* Update the SystemCoreClock global variable */
 943 
  /* Update the SystemCoreClock global variable */
957 
  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
 944 
  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
958 
 
 945 
 
959 
  /* Configure the source of time base considering new system clocks settings*/
 946 
  /* Configure the source of time base considering new system clocks settings*/
960 
  HAL_InitTick (TICK_INT_PRIORITY);
 947 
  HAL_InitTick(uwTickPrio);
961 
 
 948 
 
962 
  return HAL_OK;
 949 
  return HAL_OK;
963 
}
 950 
}
964 
 
 951 
 
965 
/**
 952 
/**
966 
  * @}
 953 
  * @}
967 
  */
 954 
  */
968 
 
 955 
 
969 
/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
 956 
/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
970 
  *  @brief   RCC clocks control functions
 957 
  *  @brief   RCC clocks control functions
971 
  *
 958 
  *
972 
  @verbatim  
 959 
  @verbatim
973 
  ===============================================================================
 960 
  ===============================================================================
974 
                  ##### Peripheral Control functions #####
 961 
                  ##### Peripheral Control functions #####
975 
  ===============================================================================  
 962 
  ===============================================================================
976 
    [..]
 963 
    [..]
977 
    This subsection provides a set of functions allowing to control the RCC Clocks
 964 
    This subsection provides a set of functions allowing to control the RCC Clocks
978 
    frequencies.
 965 
    frequencies.
979 
 
 966 
 
980 
  @endverbatim
 967 
  @endverbatim
981 
  * @{
 968 
  * @{
982 
  */
 969 
  */
Line 1043... Line 1030...
1043 
/**
 1030 
/**
1044 
  * @brief  Enables the Clock Security System.
 1031 
  * @brief  Enables the Clock Security System.
1045 
  * @note   If a failure is detected on the HSE oscillator clock, this oscillator
 1032 
  * @note   If a failure is detected on the HSE oscillator clock, this oscillator
1046 
  *         is automatically disabled and an interrupt is generated to inform the
 1033 
  *         is automatically disabled and an interrupt is generated to inform the
1047 
  *         software about the failure (Clock Security System Interrupt, CSSI),
 1034 
  *         software about the failure (Clock Security System Interrupt, CSSI),
1048 
  *         allowing the MCU to perform rescue operations. The CSSI is linked to
 1035 
  *         allowing the MCU to perform rescue operations. The CSSI is linked to
1049 
  *         the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.  
 1036 
  *         the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.
1050 
  * @retval None
 1037 
  * @retval None
1051 
  */
 1038 
  */
1052 
void HAL_RCC_EnableCSS(void)
 1039 
void HAL_RCC_EnableCSS(void)
1053 
{
 1040 
{
1054 
  *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
 1041 
  *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
Line 1062... Line 1049...
1062 
{
 1049 
{
1063 
  *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
 1050 
  *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
1064 
}
 1051 
}
1065 
 
 1052 
 
1066 
/**
 1053 
/**
1067 
  * @brief  Returns the SYSCLK frequency    
 1054 
  * @brief  Returns the SYSCLK frequency
1068 
  * @note   The system frequency computed by this function is not the real
 1055 
  * @note   The system frequency computed by this function is not the real
1069 
  *         frequency in the chip. It is calculated based on the predefined
 1056 
  *         frequency in the chip. It is calculated based on the predefined
1070 
  *         constant and the selected clock source:
 1057 
  *         constant and the selected clock source:
1071 
  * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
 1058 
  * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
1072 
  * @note     If SYSCLK source is HSE, function returns a value based on HSE_VALUE
 1059 
  * @note     If SYSCLK source is HSE, function returns a value based on HSE_VALUE
1073 
  *           divided by PREDIV factor(**)
 1060 
  *           divided by PREDIV factor(**)
1074 
  * @note     If SYSCLK source is PLL, function returns a value based on HSE_VALUE
 1061 
  * @note     If SYSCLK source is PLL, function returns a value based on HSE_VALUE
Line 1078... Line 1065...
1078 
  *               in voltage and temperature.
 1065 
  *               in voltage and temperature.
1079 
  * @note     (**) HSE_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
 1066 
  * @note     (**) HSE_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
1080 
  *                8 MHz), user has to ensure that HSE_VALUE is same as the real
 1067 
  *                8 MHz), user has to ensure that HSE_VALUE is same as the real
1081 
  *                frequency of the crystal used. Otherwise, this function may
 1068 
  *                frequency of the crystal used. Otherwise, this function may
1082 
  *                have wrong result.
 1069 
  *                have wrong result.
1083 
  *                  
 1070 
  *
1084 
  * @note   The result of this function could be not correct when using fractional
 1071 
  * @note   The result of this function could be not correct when using fractional
1085 
  *         value for HSE crystal.
 1072 
  *         value for HSE crystal.
1086 
  *          
 1073 
  *
1087 
  * @note   This function can be used by the user application to compute the
 1074 
  * @note   This function can be used by the user application to compute the
1088 
  *         baud-rate for the communication peripherals or configure other parameters.
 1075 
  *         baud-rate for the communication peripherals or configure other parameters.
1089 
  *          
 1076 
  *
1090 
  * @note   Each time SYSCLK changes, this function must be called to update the
 1077 
  * @note   Each time SYSCLK changes, this function must be called to update the
1091 
  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
 1078 
  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
1092 
  *        
 1079 
  *
1093 
  * @retval SYSCLK frequency
 1080 
  * @retval SYSCLK frequency
1094 
  */
 1081 
  */
1095 
uint32_t HAL_RCC_GetSysClockFreq(void)
 1082 
uint32_t HAL_RCC_GetSysClockFreq(void)
1096 
{
 1083 
{
1097 
#if defined(RCC_CFGR2_PREDIV1SRC)
 1084 
#if defined(RCC_CFGR2_PREDIV1SRC)
Line 1132... Line 1119...
1132 
#else
 1119 
#else
1133 
        prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
 1120 
        prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
1134 
#endif /*RCC_CFGR2_PREDIV1*/
 1121 
#endif /*RCC_CFGR2_PREDIV1*/
1135 
#if defined(RCC_CFGR2_PREDIV1SRC)
 1122 
#if defined(RCC_CFGR2_PREDIV1SRC)
1136 
 
 1123 
 
1137 
        if(HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC))
 1124 
        if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC))
1138 
        {
 1125 
        {
1139 
          /* PLL2 selected as Prediv1 source */
 1126 
          /* PLL2 selected as Prediv1 source */
1140 
          /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
 1127 
          /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
1141 
          prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
 1128 
          prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
1142 
          pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2;
 1129 
          pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2;
Line 1150... Line 1137...
1150 
 
 1137 
 
1151 
        /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
 1138 
        /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
1152 
        /* In this case need to divide pllclk by 2 */
 1139 
        /* In this case need to divide pllclk by 2 */
1153 
        if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos])
 1140 
        if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos])
1154 
        {
 1141 
        {
1155 
            pllclk = pllclk / 2;
 1142 
          pllclk = pllclk / 2;
1156 
        }
 1143 
        }
1157 
#else
 1144 
#else
1158 
        /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
 1145 
        /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
1159 
        pllclk = (uint32_t)((HSE_VALUE  * pllmul) / prediv);
 1146 
        pllclk = (uint32_t)((HSE_VALUE  * pllmul) / prediv);
1160 
#endif /*RCC_CFGR2_PREDIV1SRC*/
 1147 
#endif /*RCC_CFGR2_PREDIV1SRC*/
Line 1176... Line 1163...
1176 
  }
 1163 
  }
1177 
  return sysclockfreq;
 1164 
  return sysclockfreq;
1178 
}
 1165 
}
1179 
 
 1166 
 
1180 
/**
 1167 
/**
1181 
  * @brief  Returns the HCLK frequency    
 1168 
  * @brief  Returns the HCLK frequency
1182 
  * @note   Each time HCLK changes, this function must be called to update the
 1169 
  * @note   Each time HCLK changes, this function must be called to update the
1183 
  *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.
 1170 
  *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.
1184 
  *
 1171 
  *
1185 
  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
 1172 
  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
1186 
  *         and updated within this function
 1173 
  *         and updated within this function
1187 
  * @retval HCLK frequency
 1174 
  * @retval HCLK frequency
1188 
  */
 1175 
  */
1189 
uint32_t HAL_RCC_GetHCLKFreq(void)
 1176 
uint32_t HAL_RCC_GetHCLKFreq(void)
1190 
{
 1177 
{
1191 
  return SystemCoreClock;
 1178 
  return SystemCoreClock;
1192 
}
 1179 
}
1193 
 
 1180 
 
1194 
/**
 1181 
/**
1195 
  * @brief  Returns the PCLK1 frequency    
 1182 
  * @brief  Returns the PCLK1 frequency
1196 
  * @note   Each time PCLK1 changes, this function must be called to update the
 1183 
  * @note   Each time PCLK1 changes, this function must be called to update the
1197 
  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
 1184 
  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
1198 
  * @retval PCLK1 frequency
 1185 
  * @retval PCLK1 frequency
1199 
  */
 1186 
  */
1200 
uint32_t HAL_RCC_GetPCLK1Freq(void)
 1187 
uint32_t HAL_RCC_GetPCLK1Freq(void)
1201 
{
 1188 
{
1202 
  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
 1189 
  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
1203 
  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
 1190 
  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
1204 
}    
 1191 
}
1205 
 
 1192 
 
1206 
/**
 1193 
/**
1207 
  * @brief  Returns the PCLK2 frequency    
 1194 
  * @brief  Returns the PCLK2 frequency
1208 
  * @note   Each time PCLK2 changes, this function must be called to update the
 1195 
  * @note   Each time PCLK2 changes, this function must be called to update the
1209 
  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
 1196 
  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
1210 
  * @retval PCLK2 frequency
 1197 
  * @retval PCLK2 frequency
1211 
  */
 1198 
  */
1212 
uint32_t HAL_RCC_GetPCLK2Freq(void)
 1199 
uint32_t HAL_RCC_GetPCLK2Freq(void)
1213 
{
 1200 
{
1214 
  /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
 1201 
  /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
1215 
  return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
 1202 
  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
1216 
}
 1203 
}
1217 
 
 1204 
 
1218 
/**
 1205 
/**
1219 
  * @brief  Configures the RCC_OscInitStruct according to the internal
 1206 
  * @brief  Configures the RCC_OscInitStruct according to the internal
1220 
  * RCC configuration registers.
 1207 
  * RCC configuration registers.
1221 
  * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
 1208 
  * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
1222 
  * will be configured.
 1209 
  * will be configured.
1223 
  * @retval None
 1210 
  * @retval None
1224 
  */
 1211 
  */
1225 
void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
 1212 
void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
1226 
{
 1213 
{
1227 
  /* Check the parameters */
 1214 
  /* Check the parameters */
1228 
  assert_param(RCC_OscInitStruct != NULL);
 1215 
  assert_param(RCC_OscInitStruct != NULL);
1229 
 
 1216 
 
1230 
  /* Set all possible values for the Oscillator type parameter ---------------*/
 1217 
  /* Set all possible values for the Oscillator type parameter ---------------*/
1231 
  RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI  \
 1218 
  RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI  \
1232 
                  | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
 1219 
                                      | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
1233 
 
 1220 
 
1234 
#if defined(RCC_CFGR2_PREDIV1SRC)
 1221 
#if defined(RCC_CFGR2_PREDIV1SRC)
1235 
  /* Get the Prediv1 source --------------------------------------------------*/
 1222 
  /* Get the Prediv1 source --------------------------------------------------*/
1236 
  RCC_OscInitStruct->Prediv1Source = READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC);
 1223 
  RCC_OscInitStruct->Prediv1Source = READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC);
1237 
#endif /* RCC_CFGR2_PREDIV1SRC */
 1224 
#endif /* RCC_CFGR2_PREDIV1SRC */
1238 
 
 1225 
 
1239 
  /* Get the HSE configuration -----------------------------------------------*/
 1226 
  /* Get the HSE configuration -----------------------------------------------*/
1240 
  if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
 1227 
  if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
1241 
  {
 1228 
  {
1242 
    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
 1229 
    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
1243 
  }
 1230 
  }
1244 
  else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
 1231 
  else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
1245 
  {
 1232 
  {
1246 
    RCC_OscInitStruct->HSEState = RCC_HSE_ON;
 1233 
    RCC_OscInitStruct->HSEState = RCC_HSE_ON;
1247 
  }
 1234 
  }
1248 
  else
 1235 
  else
1249 
  {
 1236 
  {
1250 
    RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
 1237 
    RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
1251 
  }
 1238 
  }
1252 
  RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV();
 1239 
  RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV();
1253 
 
 1240 
 
1254 
  /* Get the HSI configuration -----------------------------------------------*/
 1241 
  /* Get the HSI configuration -----------------------------------------------*/
1255 
  if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
 1242 
  if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
1256 
  {
 1243 
  {
1257 
    RCC_OscInitStruct->HSIState = RCC_HSI_ON;
 1244 
    RCC_OscInitStruct->HSIState = RCC_HSI_ON;
1258 
  }
 1245 
  }
1259 
  else
 1246 
  else
1260 
  {
 1247 
  {
Line 1262... Line 1249...
1262 
  }
 1249 
  }
1263 
 
 1250 
 
1264 
  RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
 1251 
  RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
1265 
 
 1252 
 
1266 
  /* Get the LSE configuration -----------------------------------------------*/
 1253 
  /* Get the LSE configuration -----------------------------------------------*/
1267 
  if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
 1254 
  if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
1268 
  {
 1255 
  {
1269 
    RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
 1256 
    RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
1270 
  }
 1257 
  }
1271 
  else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
 1258 
  else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
1272 
  {
 1259 
  {
1273 
    RCC_OscInitStruct->LSEState = RCC_LSE_ON;
 1260 
    RCC_OscInitStruct->LSEState = RCC_LSE_ON;
1274 
  }
 1261 
  }
1275 
  else
 1262 
  else
1276 
  {
 1263 
  {
1277 
    RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
 1264 
    RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
1278 
  }
 1265 
  }
1279 
 
 1266 
 
1280 
  /* Get the LSI configuration -----------------------------------------------*/
 1267 
  /* Get the LSI configuration -----------------------------------------------*/
1281 
  if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
 1268 
  if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION)
1282 
  {
 1269 
  {
1283 
    RCC_OscInitStruct->LSIState = RCC_LSI_ON;
 1270 
    RCC_OscInitStruct->LSIState = RCC_LSI_ON;
1284 
  }
 1271 
  }
1285 
  else
 1272 
  else
1286 
  {
 1273 
  {
1287 
    RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
 1274 
    RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
1288 
  }
 1275 
  }
1289 
 
 1276 
 
1290 
 
 1277 
 
1291 
  /* Get the PLL configuration -----------------------------------------------*/
 1278 
  /* Get the PLL configuration -----------------------------------------------*/
1292 
  if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
 1279 
  if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON)
1293 
  {
 1280 
  {
1294 
    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
 1281 
    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
1295 
  }
 1282 
  }
1296 
  else
 1283 
  else
1297 
  {
 1284 
  {
Line 1299... Line 1286...
1299 
  }
 1286 
  }
1300 
  RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
 1287 
  RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
1301 
  RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMULL);
 1288 
  RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMULL);
1302 
#if defined(RCC_CR_PLL2ON)
 1289 
#if defined(RCC_CR_PLL2ON)
1303 
  /* Get the PLL2 configuration -----------------------------------------------*/
 1290 
  /* Get the PLL2 configuration -----------------------------------------------*/
1304 
  if((RCC->CR &RCC_CR_PLL2ON) == RCC_CR_PLL2ON)
 1291 
  if ((RCC->CR & RCC_CR_PLL2ON) == RCC_CR_PLL2ON)
1305 
  {
 1292 
  {
1306 
    RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_ON;
 1293 
    RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_ON;
1307 
  }
 1294 
  }
1308 
  else
 1295 
  else
1309 
  {
 1296 
  {
Line 1313... Line 1300...
1313 
  RCC_OscInitStruct->PLL2.PLL2MUL = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PLL2MUL);
 1300 
  RCC_OscInitStruct->PLL2.PLL2MUL = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PLL2MUL);
1314 
#endif /* RCC_CR_PLL2ON */
 1301 
#endif /* RCC_CR_PLL2ON */
1315 
}
 1302 
}
1316 
 
 1303 
 
1317 
/**
 1304 
/**
1318 
  * @brief  Get the RCC_ClkInitStruct according to the internal
 1305 
  * @brief  Get the RCC_ClkInitStruct according to the internal
1319 
  * RCC configuration registers.
 1306 
  * RCC configuration registers.
1320 
  * @param  RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
 1307 
  * @param  RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
1321 
  * contains the current clock configuration.
 1308 
  * contains the current clock configuration.
1322 
  * @param  pFLatency Pointer on the Flash Latency.
 1309 
  * @param  pFLatency Pointer on the Flash Latency.
1323 
  * @retval None
 1310 
  * @retval None
1324 
  */
 1311 
  */
1325 
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
 1312 
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
Line 1328... Line 1315...
1328 
  assert_param(RCC_ClkInitStruct != NULL);
 1315 
  assert_param(RCC_ClkInitStruct != NULL);
1329 
  assert_param(pFLatency != NULL);
 1316 
  assert_param(pFLatency != NULL);
1330 
 
 1317 
 
1331 
  /* Set all possible values for the Clock type parameter --------------------*/
 1318 
  /* Set all possible values for the Clock type parameter --------------------*/
1332 
  RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
 1319 
  RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
1333 
 
 1320 
 
1334 
  /* Get the SYSCLK configuration --------------------------------------------*/
 1321 
  /* Get the SYSCLK configuration --------------------------------------------*/
1335 
  RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
 1322 
  RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
1336 
 
 1323 
 
1337 
  /* Get the HCLK configuration ----------------------------------------------*/
 1324 
  /* Get the HCLK configuration ----------------------------------------------*/
1338 
  RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
 1325 
  RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
1339 
 
 1326 
 
1340 
  /* Get the APB1 configuration ----------------------------------------------*/
 1327 
  /* Get the APB1 configuration ----------------------------------------------*/
1341 
  RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);  
 1328 
  RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
1342 
 
 1329 
 
1343 
  /* Get the APB2 configuration ----------------------------------------------*/
 1330 
  /* Get the APB2 configuration ----------------------------------------------*/
1344 
  RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
 1331 
  RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
1345 
 
 1332 
 
1346 
#if   defined(FLASH_ACR_LATENCY)
 1333 
#if   defined(FLASH_ACR_LATENCY)
1347 
  /* Get the Flash Wait State (Latency) configuration ------------------------*/  
 1334 
  /* Get the Flash Wait State (Latency) configuration ------------------------*/
1348 
  *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
 1335 
  *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
1349 
#else
 1336 
#else
1350 
  /* For VALUE lines devices, only LATENCY_0 can be set*/
 1337 
  /* For VALUE lines devices, only LATENCY_0 can be set*/
1351 
  *pFLatency = (uint32_t)FLASH_LATENCY_0;
 1338 
  *pFLatency = (uint32_t)FLASH_LATENCY_0;
1352 
#endif
 1339 
#endif
1353 
}
 1340 
}
1354 
 
 1341 
 
1355 
/**
 1342 
/**
1356 
  * @brief This function handles the RCC CSS interrupt request.
 1343 
  * @brief This function handles the RCC CSS interrupt request.
Line 1358... Line 1345...
1358 
  * @retval None
 1345 
  * @retval None
1359 
  */
 1346 
  */
1360 
void HAL_RCC_NMI_IRQHandler(void)
 1347 
void HAL_RCC_NMI_IRQHandler(void)
1361 
{
 1348 
{
1362 
  /* Check RCC CSSF flag  */
 1349 
  /* Check RCC CSSF flag  */
1363 
  if(__HAL_RCC_GET_IT(RCC_IT_CSS))
 1350 
  if (__HAL_RCC_GET_IT(RCC_IT_CSS))
1364 
  {
 1351 
  {
1365 
    /* RCC Clock Security System interrupt user callback */
 1352 
    /* RCC Clock Security System interrupt user callback */
1366 
    HAL_RCC_CSSCallback();
 1353 
    HAL_RCC_CSSCallback();
1367 
   
 1354 
 
1368 
    /* Clear RCC CSS pending bit */
 1355 
    /* Clear RCC CSS pending bit */
1369 
    __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
 1356 
    __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
1370 
  }
 1357 
  }
1371 
}
 1358 
}
1372 
 
 1359 
 
Line 1376... Line 1363...
1376 
  * @retval None
 1363 
  * @retval None
1377 
  */
 1364 
  */
1378 
static void RCC_Delay(uint32_t mdelay)
 1365 
static void RCC_Delay(uint32_t mdelay)
1379 
{
 1366 
{
1380 
  __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
 1367 
  __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
1381 
  do
 1368 
  do
1382 
  {
 1369 
  {
1383 
    __NOP();
 1370 
    __NOP();
1384 
  }
 1371 
  }
1385 
  while (Delay --);
 1372 
  while (Delay --);
1386 
}
 1373 
}
1387 
 
 1374 
 
1388 
/**
 1375 
/**
1389 
  * @brief  RCC Clock Security System interrupt callback
 1376 
  * @brief  RCC Clock Security System interrupt callback
Line 1391... Line 1378...
1391 
  */
 1378 
  */
1392 
__weak void HAL_RCC_CSSCallback(void)
 1379 
__weak void HAL_RCC_CSSCallback(void)
1393 
{
 1380 
{
1394 
  /* NOTE : This function Should not be modified, when the callback is needed,
 1381 
  /* NOTE : This function Should not be modified, when the callback is needed,
1395 
    the HAL_RCC_CSSCallback could be implemented in the user file
 1382 
    the HAL_RCC_CSSCallback could be implemented in the user file
1396 
    */
 1383 
    */
1397 
}
 1384 
}
1398 
 
 1385 
 
1399 
/**
 1386 
/**
1400 
  * @}
 1387 
  * @}
1401 
  */
 1388 
  */