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/**
 1 
/**
2 
  ******************************************************************************
 2 
  ******************************************************************************
3 
  * @file    stm32f1xx_hal_rcc.c
 3 
  * @file    stm32f1xx_hal_rcc.c
4 
  * @author  MCD Application Team
 4 
  * @author  MCD Application Team
5 
  * @brief   RCC HAL module driver.
 5 
  * @brief   RCC HAL module driver.
6 
  *          This file provides firmware functions to manage the following
 6 
  *          This file provides firmware functions to manage the following
7 
  *          functionalities of the Reset and Clock Control (RCC) peripheral:
 7 
  *          functionalities of the Reset and Clock Control (RCC) peripheral:
8 
  *           + Initialization and de-initialization functions
 8 
  *           + Initialization and de-initialization functions
9 
  *           + Peripheral Control functions
 9 
  *           + Peripheral Control functions
10 
  *
 10 
  *
11 
  @verbatim
 11 
  @verbatim
12 
  ==============================================================================
 12 
  ==============================================================================
13 
                      ##### RCC specific features #####
 13 
                      ##### RCC specific features #####
14 
  ==============================================================================
 14 
  ==============================================================================
15 
    [..]
 15 
    [..]
16 
      After reset the device is running from Internal High Speed oscillator
 16 
      After reset the device is running from Internal High Speed oscillator
17 
      (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled,
 17 
      (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled,
18 
      and all peripherals are off except internal SRAM, Flash and JTAG.
 18 
      and all peripherals are off except internal SRAM, Flash and JTAG.
19 
      (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;
 19 
      (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;
20 
          all peripherals mapped on these buses are running at HSI speed.
 20 
          all peripherals mapped on these buses are running at HSI speed.
21 
      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
 21 
      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
22 
      (+) All GPIOs are in input floating state, except the JTAG pins which
 22 
      (+) All GPIOs are in input floating state, except the JTAG pins which
23 
          are assigned to be used for debug purpose.
 23 
          are assigned to be used for debug purpose.
24 
    [..] Once the device started from reset, the user application has to:
 24 
    [..] Once the device started from reset, the user application has to:
25 
      (+) Configure the clock source to be used to drive the System clock
 25 
      (+) Configure the clock source to be used to drive the System clock
26 
          (if the application needs higher frequency/performance)
 26 
          (if the application needs higher frequency/performance)
27 
      (+) Configure the System clock frequency and Flash settings
 27 
      (+) Configure the System clock frequency and Flash settings
28 
      (+) Configure the AHB and APB buses prescalers
 28 
      (+) Configure the AHB and APB buses prescalers
29 
      (+) Enable the clock for the peripheral(s) to be used
 29 
      (+) Enable the clock for the peripheral(s) to be used
30 
      (+) Configure the clock source(s) for peripherals whose clocks are not
 30 
      (+) Configure the clock source(s) for peripherals whose clocks are not
31 
          derived from the System clock (I2S, RTC, ADC, USB OTG FS)
 31 
          derived from the System clock (I2S, RTC, ADC, USB OTG FS)
32 
 
 32 
 
33 
                      ##### RCC Limitations #####
 33 
                      ##### RCC Limitations #####
34 
  ==============================================================================
 34 
  ==============================================================================
35 
    [..]
 35 
    [..]
36 
      A delay between an RCC peripheral clock enable and the effective peripheral
 36 
      A delay between an RCC peripheral clock enable and the effective peripheral
37 
      enabling should be taken into account in order to manage the peripheral read/write
 37 
      enabling should be taken into account in order to manage the peripheral read/write
38 
      from/to registers.
 38 
      from/to registers.
39 
      (+) This delay depends on the peripheral mapping.
 39 
      (+) This delay depends on the peripheral mapping.
40 
        (++) AHB & APB peripherals, 1 dummy read is necessary
 40 
        (++) AHB & APB peripherals, 1 dummy read is necessary
41 
 
 41 
 
42 
    [..]
 42 
    [..]
43 
      Workarounds:
 43 
      Workarounds:
44 
      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
 44 
      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
45 
          inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
 45 
          inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
46 
 
 46 
 
47 
  @endverbatim
 47 
  @endverbatim
48 
  ******************************************************************************
 48 
  ******************************************************************************
49 
  * @attention
 49 
  * @attention
50 
  *
 50 
  *
51 
  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
 51 
  * Copyright (c) 2016 STMicroelectronics.
52 
  * All rights reserved.</center></h2>
 52 
  * All rights reserved.
53 
  *
 53 
  *
54 
  * This software component is licensed by ST under BSD 3-Clause license,
 54 
  * This software is licensed under terms that can be found in the LICENSE file in
55 
  * the "License"; You may not use this file except in compliance with the
 55 
  * the root directory of this software component.
56 
  * License. You may obtain a copy of the License at:
 56 
  * If no LICENSE file comes with this software, it is provided AS-IS.
57 
  *                        opensource.org/licenses/BSD-3-Clause
 57 
  ******************************************************************************
58 
  *
 58 
  */
59 
  ******************************************************************************
 59 
 
60 
  */
 60 
/* Includes ------------------------------------------------------------------*/
61 
 
 61 
#include "stm32f1xx_hal.h"
62 
/* Includes ------------------------------------------------------------------*/
 62 
 
63 
#include "stm32f1xx_hal.h"
 63 
/** @addtogroup STM32F1xx_HAL_Driver
64 
 
 64 
  * @{
65 
/** @addtogroup STM32F1xx_HAL_Driver
 65 
  */
66 
  * @{
 66 
 
67 
  */
 67 
/** @defgroup RCC RCC
68 
 
 68 
* @brief RCC HAL module driver
69 
/** @defgroup RCC RCC
 69 
  * @{
70 
* @brief RCC HAL module driver
 70 
  */
71 
  * @{
 71 
 
72 
  */
 72 
#ifdef HAL_RCC_MODULE_ENABLED
73 
 
 73 
 
74 
#ifdef HAL_RCC_MODULE_ENABLED
 74 
/* Private typedef -----------------------------------------------------------*/
75 
 
 75 
/* Private define ------------------------------------------------------------*/
76 
/* Private typedef -----------------------------------------------------------*/
 76 
/** @defgroup RCC_Private_Constants RCC Private Constants
77 
/* Private define ------------------------------------------------------------*/
 77 
 * @{
78 
/** @defgroup RCC_Private_Constants RCC Private Constants
 78 
 */
79 
 * @{
 79 
/**
80 
 */
 80 
  * @}
81 
/**
 81 
  */
82 
  * @}
 82 
/* Private macro -------------------------------------------------------------*/
83 
  */
 83 
/** @defgroup RCC_Private_Macros RCC Private Macros
84 
/* Private macro -------------------------------------------------------------*/
 84 
  * @{
85 
/** @defgroup RCC_Private_Macros RCC Private Macros
 85 
  */
86 
  * @{
 86 
 
87 
  */
 87 
#define MCO1_CLK_ENABLE()     __HAL_RCC_GPIOA_CLK_ENABLE()
88 
 
 88 
#define MCO1_GPIO_PORT        GPIOA
89 
#define MCO1_CLK_ENABLE()     __HAL_RCC_GPIOA_CLK_ENABLE()
 89 
#define MCO1_PIN              GPIO_PIN_8
90 
#define MCO1_GPIO_PORT        GPIOA
 90 
 
91 
#define MCO1_PIN              GPIO_PIN_8
 91 
/**
92 
 
 92 
  * @}
93 
/**
 93 
  */
94 
  * @}
 94 
 
95 
  */
 95 
/* Private variables ---------------------------------------------------------*/
96 
 
 96 
/** @defgroup RCC_Private_Variables RCC Private Variables
97 
/* Private variables ---------------------------------------------------------*/
 97 
  * @{
98 
/** @defgroup RCC_Private_Variables RCC Private Variables
 98 
  */
99 
  * @{
 99 
/**
100 
  */
 100 
  * @}
101 
/**
 101 
  */
102 
  * @}
 102 
 
103 
  */
 103 
/* Private function prototypes -----------------------------------------------*/
104 
 
 104 
static void RCC_Delay(uint32_t mdelay);
105 
/* Private function prototypes -----------------------------------------------*/
 105 
 
106 
static void RCC_Delay(uint32_t mdelay);
 106 
/* Exported functions --------------------------------------------------------*/
107 
 
 107 
 
108 
/* Exported functions --------------------------------------------------------*/
 108 
/** @defgroup RCC_Exported_Functions RCC Exported Functions
109 
 
 109 
  * @{
110 
/** @defgroup RCC_Exported_Functions RCC Exported Functions
 110 
  */
111 
  * @{
 111 
 
112 
  */
 112 
/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
113 
 
 113 
  *  @brief    Initialization and Configuration functions
114 
/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
 114 
  *
115 
  *  @brief    Initialization and Configuration functions
 115 
  @verbatim
116 
  *
 116 
  ===============================================================================
117 
  @verbatim
 117 
           ##### Initialization and de-initialization functions #####
118 
  ===============================================================================
 118 
  ===============================================================================
119 
           ##### Initialization and de-initialization functions #####
 119 
    [..]
120 
  ===============================================================================
 120 
      This section provides functions allowing to configure the internal/external oscillators
121 
    [..]
 121 
      (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
122 
      This section provides functions allowing to configure the internal/external oscillators
 122 
      and APB2).
123 
      (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
 123 
 
124 
      and APB2).
 124 
    [..] Internal/external clock and PLL configuration
125 
 
 125 
      (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through
126 
    [..] Internal/external clock and PLL configuration
 126 
          the PLL as System clock source.
127 
      (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through
 127 
      (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC
128 
          the PLL as System clock source.
 128 
          clock source.
129 
      (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC
 129 
 
130 
          clock source.
 130 
      (#) HSE (high-speed external), 4 to 24 MHz (STM32F100xx) or 4 to 16 MHz (STM32F101x/STM32F102x/STM32F103x) or 3 to 25 MHz (STM32F105x/STM32F107x)  crystal oscillator used directly or
131 
 
 131 
          through the PLL as System clock source. Can be used also as RTC clock source.
132 
      (#) HSE (high-speed external), 4 to 24 MHz (STM32F100xx) or 4 to 16 MHz (STM32F101x/STM32F102x/STM32F103x) or 3 to 25 MHz (STM32F105x/STM32F107x)  crystal oscillator used directly or
 132 
 
133 
          through the PLL as System clock source. Can be used also as RTC clock source.
 133 
      (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
134 
 
 134 
 
135 
      (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
 135 
      (#) PLL (clocked by HSI or HSE), featuring different output clocks:
136 
 
 136 
        (++) The first output is used to generate the high speed system clock (up to 72 MHz for STM32F10xxx or up to 24 MHz for STM32F100xx)
137 
      (#) PLL (clocked by HSI or HSE), featuring different output clocks:
 137 
        (++) The second output is used to generate the clock for the USB OTG FS (48 MHz)
138 
        (++) The first output is used to generate the high speed system clock (up to 72 MHz for STM32F10xxx or up to 24 MHz for STM32F100xx)
 138 
 
139 
        (++) The second output is used to generate the clock for the USB OTG FS (48 MHz)
 139 
      (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
140 
 
 140 
          and if a HSE clock failure occurs(HSE used directly or through PLL as System
141 
      (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
 141 
          clock source), the System clocks automatically switched to HSI and an interrupt
142 
          and if a HSE clock failure occurs(HSE used directly or through PLL as System
 142 
          is generated if enabled. The interrupt is linked to the Cortex-M3 NMI
143 
          clock source), the System clocks automatically switched to HSI and an interrupt
 143 
          (Non-Maskable Interrupt) exception vector.
144 
          is generated if enabled. The interrupt is linked to the Cortex-M3 NMI
 144 
 
145 
          (Non-Maskable Interrupt) exception vector.
 145 
      (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI,
146 
 
 146 
          HSE or PLL clock (divided by 2) on PA8 pin + PLL2CLK, PLL3CLK/2, PLL3CLK and XTI for STM32F105x/STM32F107x
147 
      (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI,
 147 
 
148 
          HSE or PLL clock (divided by 2) on PA8 pin + PLL2CLK, PLL3CLK/2, PLL3CLK and XTI for STM32F105x/STM32F107x
 148 
    [..] System, AHB and APB buses clocks configuration
149 
 
 149 
      (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
150 
    [..] System, AHB and APB buses clocks configuration
 150 
          HSE and PLL.
151 
      (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
 151 
          The AHB clock (HCLK) is derived from System clock through configurable
152 
          HSE and PLL.
 152 
          prescaler and used to clock the CPU, memory and peripherals mapped
153 
          The AHB clock (HCLK) is derived from System clock through configurable
 153 
          on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
154 
          prescaler and used to clock the CPU, memory and peripherals mapped
 154 
          from AHB clock through configurable prescalers and used to clock
155 
          on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
 155 
          the peripherals mapped on these buses. You can use
156 
          from AHB clock through configurable prescalers and used to clock
 156 
          "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
157 
          the peripherals mapped on these buses. You can use
 157 
 
158 
          "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
 158 
      -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
159 
 
 159 
          (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock
160 
      -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
 160 
              divided by 128.
161 
          (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock
 161 
          (+@) USB OTG FS and RTC: USB OTG FS require a frequency equal to 48 MHz
162 
              divided by 128.
 162 
              to work correctly. This clock is derived of the main PLL through PLL Multiplier.
163 
          (+@) USB OTG FS and RTC: USB OTG FS require a frequency equal to 48 MHz
 163 
          (+@) I2S interface on STM32F105x/STM32F107x can be derived from PLL3CLK
164 
              to work correctly. This clock is derived of the main PLL through PLL Multiplier.
 164 
          (+@) IWDG clock which is always the LSI clock.
165 
          (+@) I2S interface on STM32F105x/STM32F107x can be derived from PLL3CLK
 165 
 
166 
          (+@) IWDG clock which is always the LSI clock.
 166 
      (#) For STM32F10xxx, the maximum frequency of the SYSCLK and HCLK/PCLK2 is 72 MHz, PCLK1 36 MHz.
167 
 
 167 
          For STM32F100xx, the maximum frequency of the SYSCLK and HCLK/PCLK1/PCLK2 is 24 MHz.
168 
      (#) For STM32F10xxx, the maximum frequency of the SYSCLK and HCLK/PCLK2 is 72 MHz, PCLK1 36 MHz.
 168 
          Depending on the SYSCLK frequency, the flash latency should be adapted accordingly.
169 
          For STM32F100xx, the maximum frequency of the SYSCLK and HCLK/PCLK1/PCLK2 is 24 MHz.
 169 
  @endverbatim
170 
          Depending on the SYSCLK frequency, the flash latency should be adapted accordingly.
 170 
  * @{
171 
  @endverbatim
 171 
  */
172 
  * @{
 172 
 
173 
  */
 173 
/*
174 
 
 174 
  Additional consideration on the SYSCLK based on Latency settings:
175 
/*
 175 
        +-----------------------------------------------+
176 
  Additional consideration on the SYSCLK based on Latency settings:
 176 
        | Latency       | SYSCLK clock frequency (MHz)  |
177 
        +-----------------------------------------------+
 177 
        |---------------|-------------------------------|
178 
        | Latency       | SYSCLK clock frequency (MHz)  |
 178 
        |0WS(1CPU cycle)|       0 < SYSCLK <= 24        |
179 
        |---------------|-------------------------------|
 179 
        |---------------|-------------------------------|
180 
        |0WS(1CPU cycle)|       0 < SYSCLK <= 24        |
 180 
        |1WS(2CPU cycle)|      24 < SYSCLK <= 48        |
181 
        |---------------|-------------------------------|
 181 
        |---------------|-------------------------------|
182 
        |1WS(2CPU cycle)|      24 < SYSCLK <= 48        |
 182 
        |2WS(3CPU cycle)|      48 < SYSCLK <= 72        |
183 
        |---------------|-------------------------------|
 183 
        +-----------------------------------------------+
184 
        |2WS(3CPU cycle)|      48 < SYSCLK <= 72        |
 184 
  */
185 
        +-----------------------------------------------+
 185 
 
186 
  */
 186 
/**
187 
 
 187 
  * @brief  Resets the RCC clock configuration to the default reset state.
188 
/**
 188 
  * @note   The default reset state of the clock configuration is given below:
189 
  * @brief  Resets the RCC clock configuration to the default reset state.
 189 
  *            - HSI ON and used as system clock source
190 
  * @note   The default reset state of the clock configuration is given below:
 190 
  *            - HSE, PLL, PLL2 and PLL3 are OFF
191 
  *            - HSI ON and used as system clock source
 191 
  *            - AHB, APB1 and APB2 prescaler set to 1.
192 
  *            - HSE, PLL, PLL2 and PLL3 are OFF
 192 
  *            - CSS and MCO1 OFF
193 
  *            - AHB, APB1 and APB2 prescaler set to 1.
 193 
  *            - All interrupts disabled
194 
  *            - CSS and MCO1 OFF
 194 
  *            - All flags are cleared
195 
  *            - All interrupts disabled
 195 
  * @note   This function does not modify the configuration of the
196 
  *            - All flags are cleared
 196 
  *            - Peripheral clocks
197 
  * @note   This function does not modify the configuration of the
 197 
  *            - LSI, LSE and RTC clocks
198 
  *            - Peripheral clocks
 198 
  * @retval HAL_StatusTypeDef
199 
  *            - LSI, LSE and RTC clocks
 199 
  */
200 
  * @retval HAL_StatusTypeDef
 200 
HAL_StatusTypeDef HAL_RCC_DeInit(void)
201 
  */
 201 
{
202 
HAL_StatusTypeDef HAL_RCC_DeInit(void)
 202 
  uint32_t tickstart;
203 
{
 203 
 
204 
  uint32_t tickstart;
 204 
  /* Get Start Tick */
205 
 
 205 
  tickstart = HAL_GetTick();
206 
  /* Get Start Tick */
 206 
 
207 
  tickstart = HAL_GetTick();
 207 
  /* Set HSION bit */
208 
 
 208 
  SET_BIT(RCC->CR, RCC_CR_HSION);
209 
  /* Set HSION bit */
 209 
 
210 
  SET_BIT(RCC->CR, RCC_CR_HSION);
 210 
  /* Wait till HSI is ready */
211 
 
 211 
  while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET)
212 
  /* Wait till HSI is ready */
 212 
  {
213 
  while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET)
 213 
    if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
214 
  {
 214 
    {
215 
    if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
 215 
      return HAL_TIMEOUT;
216 
    {
 216 
    }
217 
      return HAL_TIMEOUT;
 217 
  }
218 
    }
 218 
 
219 
  }
 219 
  /* Set HSITRIM bits to the reset value */
220 
 
 220 
  MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (0x10U << RCC_CR_HSITRIM_Pos));
221 
  /* Set HSITRIM bits to the reset value */
 221 
 
222 
  MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (0x10U << RCC_CR_HSITRIM_Pos));
 222 
  /* Get Start Tick */
223 
 
 223 
  tickstart = HAL_GetTick();
224 
  /* Get Start Tick */
 224 
 
225 
  tickstart = HAL_GetTick();
 225 
  /* Reset CFGR register */
226 
 
 226 
  CLEAR_REG(RCC->CFGR);
227 
  /* Reset CFGR register */
 227 
 
228 
  CLEAR_REG(RCC->CFGR);
 228 
  /* Wait till clock switch is ready */
229 
 
 229 
  while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET)
230 
  /* Wait till clock switch is ready */
 230 
  {
231 
  while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET)
 231 
    if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
232 
  {
 232 
    {
233 
    if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
 233 
      return HAL_TIMEOUT;
234 
    {
 234 
    }
235 
      return HAL_TIMEOUT;
 235 
  }
236 
    }
 236 
 
237 
  }
 237 
  /* Update the SystemCoreClock global variable */
238 
 
 238 
  SystemCoreClock = HSI_VALUE;
239 
  /* Update the SystemCoreClock global variable */
 239 
 
240 
  SystemCoreClock = HSI_VALUE;
 240 
  /* Adapt Systick interrupt period */
241 
 
 241 
  if (HAL_InitTick(uwTickPrio) != HAL_OK)
242 
  /* Adapt Systick interrupt period */
 242 
  {
243 
  if (HAL_InitTick(uwTickPrio) != HAL_OK)
 243 
    return HAL_ERROR;
244 
  {
 244 
  }
245 
    return HAL_ERROR;
 245 
 
246 
  }
 246 
  /* Get Start Tick */
247 
 
 247 
  tickstart = HAL_GetTick();
248 
  /* Get Start Tick */
 248 
 
249 
  tickstart = HAL_GetTick();
 249 
  /* Second step is to clear PLLON bit */
250 
 
 250 
  CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
251 
  /* Second step is to clear PLLON bit */
 251 
 
252 
  CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
 252 
  /* Wait till PLL is disabled */
253 
 
 253 
  while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET)
254 
  /* Wait till PLL is disabled */
 254 
  {
255 
  while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET)
 255 
    if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
256 
  {
 256 
    {
257 
    if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 257 
      return HAL_TIMEOUT;
258 
    {
 258 
    }
259 
      return HAL_TIMEOUT;
 259 
  }
260 
    }
 260 
 
261 
  }
 261 
  /* Ensure to reset PLLSRC and PLLMUL bits */
262 
 
 262 
  CLEAR_REG(RCC->CFGR);
263 
  /* Ensure to reset PLLSRC and PLLMUL bits */
 263 
 
264 
  CLEAR_REG(RCC->CFGR);
 264 
  /* Get Start Tick */
265 
 
 265 
  tickstart = HAL_GetTick();
266 
  /* Get Start Tick */
 266 
 
267 
  tickstart = HAL_GetTick();
 267 
  /* Reset HSEON & CSSON bits */
268 
 
 268 
  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON);
269 
  /* Reset HSEON & CSSON bits */
 269 
 
270 
  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON);
 270 
  /* Wait till HSE is disabled */
271 
 
 271 
  while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET)
272 
  /* Wait till HSE is disabled */
 272 
  {
273 
  while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET)
 273 
    if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
274 
  {
 274 
    {
275 
    if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
 275 
      return HAL_TIMEOUT;
276 
    {
 276 
    }
277 
      return HAL_TIMEOUT;
 277 
  }
278 
    }
 278 
 
279 
  }
 279 
  /* Reset HSEBYP bit */
280 
 
 280 
  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
281 
  /* Reset HSEBYP bit */
 281 
 
282 
  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
 282 
#if defined(RCC_PLL2_SUPPORT)
283 
 
 283 
  /* Get Start Tick */
284 
#if defined(RCC_PLL2_SUPPORT)
 284 
  tickstart = HAL_GetTick();
285 
  /* Get Start Tick */
 285 
 
286 
  tickstart = HAL_GetTick();
 286 
  /* Clear PLL2ON bit */
287 
 
 287 
  CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
288 
  /* Clear PLL2ON bit */
 288 
 
289 
  CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
 289 
  /* Wait till PLL2 is disabled */
290 
 
 290 
  while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != RESET)
291 
  /* Wait till PLL2 is disabled */
 291 
  {
292 
  while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != RESET)
 292 
    if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
293 
  {
 293 
    {
294 
    if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
 294 
      return HAL_TIMEOUT;
295 
    {
 295 
    }
296 
      return HAL_TIMEOUT;
 296 
  }
297 
    }
 297 
#endif /* RCC_PLL2_SUPPORT */
298 
  }
 298 
 
299 
#endif /* RCC_PLL2_SUPPORT */
 299 
#if defined(RCC_PLLI2S_SUPPORT)
300 
 
 300 
  /* Get Start Tick */
301 
#if defined(RCC_PLLI2S_SUPPORT)
 301 
  tickstart = HAL_GetTick();
302 
  /* Get Start Tick */
 302 
 
303 
  tickstart = HAL_GetTick();
 303 
  /* Clear PLL3ON bit */
304 
 
 304 
  CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
305 
  /* Clear PLL3ON bit */
 305 
 
306 
  CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
 306 
  /* Wait till PLL3 is disabled */
307 
 
 307 
  while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != RESET)
308 
  /* Wait till PLL3 is disabled */
 308 
  {
309 
  while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != RESET)
 309 
    if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
310 
  {
 310 
    {
311 
    if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
 311 
      return HAL_TIMEOUT;
312 
    {
 312 
    }
313 
      return HAL_TIMEOUT;
 313 
  }
314 
    }
 314 
#endif /* RCC_PLLI2S_SUPPORT */
315 
  }
 315 
 
316 
#endif /* RCC_PLLI2S_SUPPORT */
 316 
#if defined(RCC_CFGR2_PREDIV1)
317 
 
 317 
  /* Reset CFGR2 register */
318 
#if defined(RCC_CFGR2_PREDIV1)
 318 
  CLEAR_REG(RCC->CFGR2);
319 
  /* Reset CFGR2 register */
 319 
#endif /* RCC_CFGR2_PREDIV1 */
320 
  CLEAR_REG(RCC->CFGR2);
 320 
 
321 
#endif /* RCC_CFGR2_PREDIV1 */
 321 
  /* Reset all CSR flags */
322 
 
 322 
  SET_BIT(RCC->CSR, RCC_CSR_RMVF);
323 
  /* Reset all CSR flags */
 323 
 
324 
  SET_BIT(RCC->CSR, RCC_CSR_RMVF);
 324 
  /* Disable all interrupts */
325 
 
 325 
  CLEAR_REG(RCC->CIR);
326 
  /* Disable all interrupts */
 326 
 
327 
  CLEAR_REG(RCC->CIR);
 327 
  return HAL_OK;
328 
 
 328 
}
329 
  return HAL_OK;
 329 
 
330 
}
 330 
/**
331 
 
 331 
  * @brief  Initializes the RCC Oscillators according to the specified parameters in the
332 
/**
 332 
  *         RCC_OscInitTypeDef.
333 
  * @brief  Initializes the RCC Oscillators according to the specified parameters in the
 333 
  * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
334 
  *         RCC_OscInitTypeDef.
 334 
  *         contains the configuration information for the RCC Oscillators.
335 
  * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
 335 
  * @note   The PLL is not disabled when used as system clock.
336 
  *         contains the configuration information for the RCC Oscillators.
 336 
  * @note   The PLL is not disabled when USB OTG FS clock is enabled (specific to devices with USB FS)
337 
  * @note   The PLL is not disabled when used as system clock.
 337 
  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
338 
  * @note   The PLL is not disabled when USB OTG FS clock is enabled (specific to devices with USB FS)
 338 
  *         supported by this macro. User should request a transition to LSE Off
339 
  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
 339 
  *         first and then LSE On or LSE Bypass.
340 
  *         supported by this macro. User should request a transition to LSE Off
 340 
  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
341 
  *         first and then LSE On or LSE Bypass.
 341 
  *         supported by this macro. User should request a transition to HSE Off
342 
  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
 342 
  *         first and then HSE On or HSE Bypass.
343 
  *         supported by this macro. User should request a transition to HSE Off
 343 
  * @retval HAL status
344 
  *         first and then HSE On or HSE Bypass.
 344 
  */
345 
  * @retval HAL status
 345 
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
346 
  */
 346 
{
347 
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
 347 
  uint32_t tickstart;
348 
{
 348 
  uint32_t pll_config;
349 
  uint32_t tickstart;
 349 
 
350 
  uint32_t pll_config;
 350 
  /* Check Null pointer */
351 
 
 351 
  if (RCC_OscInitStruct == NULL)
352 
  /* Check Null pointer */
 352 
  {
353 
  if (RCC_OscInitStruct == NULL)
 353 
    return HAL_ERROR;
354 
  {
 354 
  }
355 
    return HAL_ERROR;
 355 
 
356 
  }
 356 
  /* Check the parameters */
357 
 
 357 
  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
358 
  /* Check the parameters */
 358 
 
359 
  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
 359 
  /*------------------------------- HSE Configuration ------------------------*/
360 
 
 360 
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
361 
  /*------------------------------- HSE Configuration ------------------------*/
 361 
  {
362 
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 362 
    /* Check the parameters */
363 
  {
 363 
    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
364 
    /* Check the parameters */
 364 
 
365 
    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
 365 
    /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
366 
 
 366 
    if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
367 
    /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
 367 
        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
368 
    if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
 368 
    {
369 
        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
 369 
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
370 
    {
 370 
      {
371 
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 371 
        return HAL_ERROR;
372 
      {
 372 
      }
373 
        return HAL_ERROR;
 373 
    }
374 
      }
 374 
    else
375 
    }
 375 
    {
376 
    else
 376 
      /* Set the new HSE configuration ---------------------------------------*/
377 
    {
 377 
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
378 
      /* Set the new HSE configuration ---------------------------------------*/
 378 
 
379 
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 379 
 
380 
 
 380 
      /* Check the HSE State */
381 
 
 381 
      if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
382 
      /* Check the HSE State */
 382 
      {
383 
      if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
 383 
        /* Get Start Tick */
384 
      {
 384 
        tickstart = HAL_GetTick();
385 
        /* Get Start Tick */
 385 
 
386 
        tickstart = HAL_GetTick();
 386 
        /* Wait till HSE is ready */
387 
 
 387 
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
388 
        /* Wait till HSE is ready */
 388 
        {
389 
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 389 
          if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
390 
        {
 390 
          {
391 
          if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
 391 
            return HAL_TIMEOUT;
392 
          {
 392 
          }
393 
            return HAL_TIMEOUT;
 393 
        }
394 
          }
 394 
      }
395 
        }
 395 
      else
396 
      }
 396 
      {
397 
      else
 397 
        /* Get Start Tick */
398 
      {
 398 
        tickstart = HAL_GetTick();
399 
        /* Get Start Tick */
 399 
 
400 
        tickstart = HAL_GetTick();
 400 
        /* Wait till HSE is disabled */
401 
 
 401 
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
402 
        /* Wait till HSE is disabled */
 402 
        {
403 
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
 403 
          if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
404 
        {
 404 
          {
405 
          if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
 405 
            return HAL_TIMEOUT;
406 
          {
 406 
          }
407 
            return HAL_TIMEOUT;
 407 
        }
408 
          }
 408 
      }
409 
        }
 409 
    }
410 
      }
 410 
  }
411 
    }
 411 
  /*----------------------------- HSI Configuration --------------------------*/
412 
  }
 412 
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
413 
  /*----------------------------- HSI Configuration --------------------------*/
 413 
  {
414 
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
 414 
    /* Check the parameters */
415 
  {
 415 
    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
416 
    /* Check the parameters */
 416 
    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
417 
    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
 417 
 
418 
    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
 418 
    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
419 
 
 419 
    if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
420 
    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
 420 
        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
421 
    if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
 421 
    {
422 
        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
 422 
      /* When HSI is used as system clock it will not disabled */
423 
    {
 423 
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
424 
      /* When HSI is used as system clock it will not disabled */
 424 
      {
425 
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
 425 
        return HAL_ERROR;
426 
      {
 426 
      }
427 
        return HAL_ERROR;
 427 
      /* Otherwise, just the calibration is allowed */
428 
      }
 428 
      else
429 
      /* Otherwise, just the calibration is allowed */
 429 
      {
430 
      else
 430 
        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
431 
      {
 431 
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
432 
        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
 432 
      }
433 
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 433 
    }
434 
      }
 434 
    else
435 
    }
 435 
    {
436 
    else
 436 
      /* Check the HSI State */
437 
    {
 437 
      if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
438 
      /* Check the HSI State */
 438 
      {
439 
      if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
 439 
        /* Enable the Internal High Speed oscillator (HSI). */
440 
      {
 440 
        __HAL_RCC_HSI_ENABLE();
441 
        /* Enable the Internal High Speed oscillator (HSI). */
 441 
 
442 
        __HAL_RCC_HSI_ENABLE();
 442 
        /* Get Start Tick */
443 
 
 443 
        tickstart = HAL_GetTick();
444 
        /* Get Start Tick */
 444 
 
445 
        tickstart = HAL_GetTick();
 445 
        /* Wait till HSI is ready */
446 
 
 446 
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
447 
        /* Wait till HSI is ready */
 447 
        {
448 
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 448 
          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
449 
        {
 449 
          {
450 
          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
 450 
            return HAL_TIMEOUT;
451 
          {
 451 
          }
452 
            return HAL_TIMEOUT;
 452 
        }
453 
          }
 453 
 
454 
        }
 454 
        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
455 
 
 455 
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
456 
        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
 456 
      }
457 
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 457 
      else
458 
      }
 458 
      {
459 
      else
 459 
        /* Disable the Internal High Speed oscillator (HSI). */
460 
      {
 460 
        __HAL_RCC_HSI_DISABLE();
461 
        /* Disable the Internal High Speed oscillator (HSI). */
 461 
 
462 
        __HAL_RCC_HSI_DISABLE();
 462 
        /* Get Start Tick */
463 
 
 463 
        tickstart = HAL_GetTick();
464 
        /* Get Start Tick */
 464 
 
465 
        tickstart = HAL_GetTick();
 465 
        /* Wait till HSI is disabled */
466 
 
 466 
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
467 
        /* Wait till HSI is disabled */
 467 
        {
468 
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
 468 
          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
469 
        {
 469 
          {
470 
          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
 470 
            return HAL_TIMEOUT;
471 
          {
 471 
          }
472 
            return HAL_TIMEOUT;
 472 
        }
473 
          }
 473 
      }
474 
        }
 474 
    }
475 
      }
 475 
  }
476 
    }
 476 
  /*------------------------------ LSI Configuration -------------------------*/
477 
  }
 477 
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
478 
  /*------------------------------ LSI Configuration -------------------------*/
 478 
  {
479 
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
 479 
    /* Check the parameters */
480 
  {
 480 
    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
481 
    /* Check the parameters */
 481 
 
482 
    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
 482 
    /* Check the LSI State */
483 
 
 483 
    if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
484 
    /* Check the LSI State */
 484 
    {
485 
    if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
 485 
      /* Enable the Internal Low Speed oscillator (LSI). */
486 
    {
 486 
      __HAL_RCC_LSI_ENABLE();
487 
      /* Enable the Internal Low Speed oscillator (LSI). */
 487 
 
488 
      __HAL_RCC_LSI_ENABLE();
 488 
      /* Get Start Tick */
489 
 
 489 
      tickstart = HAL_GetTick();
490 
      /* Get Start Tick */
 490 
 
491 
      tickstart = HAL_GetTick();
 491 
      /* Wait till LSI is ready */
492 
 
 492 
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
493 
      /* Wait till LSI is ready */
 493 
      {
494 
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
 494 
        if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
495 
      {
 495 
        {
496 
        if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
 496 
          return HAL_TIMEOUT;
497 
        {
 497 
        }
498 
          return HAL_TIMEOUT;
 498 
      }
499 
        }
 499 
      /*  To have a fully stabilized clock in the specified range, a software delay of 1ms
500 
      }
 500 
          should be added.*/
501 
      /*  To have a fully stabilized clock in the specified range, a software delay of 1ms
 501 
      RCC_Delay(1);
502 
          should be added.*/
 502 
    }
503 
      RCC_Delay(1);
 503 
    else
504 
    }
 504 
    {
505 
    else
 505 
      /* Disable the Internal Low Speed oscillator (LSI). */
506 
    {
 506 
      __HAL_RCC_LSI_DISABLE();
507 
      /* Disable the Internal Low Speed oscillator (LSI). */
 507 
 
508 
      __HAL_RCC_LSI_DISABLE();
 508 
      /* Get Start Tick */
509 
 
 509 
      tickstart = HAL_GetTick();
510 
      /* Get Start Tick */
 510 
 
511 
      tickstart = HAL_GetTick();
 511 
      /* Wait till LSI is disabled */
512 
 
 512 
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
513 
      /* Wait till LSI is disabled */
 513 
      {
514 
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
 514 
        if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
515 
      {
 515 
        {
516 
        if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
 516 
          return HAL_TIMEOUT;
517 
        {
 517 
        }
518 
          return HAL_TIMEOUT;
 518 
      }
519 
        }
 519 
    }
520 
      }
 520 
  }
521 
    }
 521 
  /*------------------------------ LSE Configuration -------------------------*/
522 
  }
 522 
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
523 
  /*------------------------------ LSE Configuration -------------------------*/
 523 
  {
524 
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
 524 
    FlagStatus       pwrclkchanged = RESET;
525 
  {
 525 
 
526 
    FlagStatus       pwrclkchanged = RESET;
 526 
    /* Check the parameters */
527 
 
 527 
    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
528 
    /* Check the parameters */
 528 
 
529 
    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
 529 
    /* Update LSE configuration in Backup Domain control register    */
530 
 
 530 
    /* Requires to enable write access to Backup Domain of necessary */
531 
    /* Update LSE configuration in Backup Domain control register    */
 531 
    if (__HAL_RCC_PWR_IS_CLK_DISABLED())
532 
    /* Requires to enable write access to Backup Domain of necessary */
 532 
    {
533 
    if (__HAL_RCC_PWR_IS_CLK_DISABLED())
 533 
      __HAL_RCC_PWR_CLK_ENABLE();
534 
    {
 534 
      pwrclkchanged = SET;
535 
      __HAL_RCC_PWR_CLK_ENABLE();
 535 
    }
536 
      pwrclkchanged = SET;
 536 
 
537 
    }
 537 
    if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
538 
 
 538 
    {
539 
    if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 539 
      /* Enable write access to Backup domain */
540 
    {
 540 
      SET_BIT(PWR->CR, PWR_CR_DBP);
541 
      /* Enable write access to Backup domain */
 541 
 
542 
      SET_BIT(PWR->CR, PWR_CR_DBP);
 542 
      /* Wait for Backup domain Write protection disable */
543 
 
 543 
      tickstart = HAL_GetTick();
544 
      /* Wait for Backup domain Write protection disable */
 544 
 
545 
      tickstart = HAL_GetTick();
 545 
      while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
546 
 
 546 
      {
547 
      while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 547 
        if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
548 
      {
 548 
        {
549 
        if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 549 
          return HAL_TIMEOUT;
550 
        {
 550 
        }
551 
          return HAL_TIMEOUT;
 551 
      }
552 
        }
 552 
    }
553 
      }
 553 
 
554 
    }
 554 
    /* Set the new LSE configuration -----------------------------------------*/
555 
 
 555 
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
556 
    /* Set the new LSE configuration -----------------------------------------*/
 556 
    /* Check the LSE State */
557 
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 557 
    if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
558 
    /* Check the LSE State */
 558 
    {
559 
    if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
 559 
      /* Get Start Tick */
560 
    {
 560 
      tickstart = HAL_GetTick();
561 
      /* Get Start Tick */
 561 
 
562 
      tickstart = HAL_GetTick();
 562 
      /* Wait till LSE is ready */
563 
 
 563 
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
564 
      /* Wait till LSE is ready */
 564 
      {
565 
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
 565 
        if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
566 
      {
 566 
        {
567 
        if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 567 
          return HAL_TIMEOUT;
568 
        {
 568 
        }
569 
          return HAL_TIMEOUT;
 569 
      }
570 
        }
 570 
    }
571 
      }
 571 
    else
572 
    }
 572 
    {
573 
    else
 573 
      /* Get Start Tick */
574 
    {
 574 
      tickstart = HAL_GetTick();
575 
      /* Get Start Tick */
 575 
 
576 
      tickstart = HAL_GetTick();
 576 
      /* Wait till LSE is disabled */
577 
 
 577 
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
578 
      /* Wait till LSE is disabled */
 578 
      {
579 
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
 579 
        if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
580 
      {
 580 
        {
581 
        if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 581 
          return HAL_TIMEOUT;
582 
        {
 582 
        }
583 
          return HAL_TIMEOUT;
 583 
      }
584 
        }
 584 
    }
585 
      }
 585 
 
586 
    }
 586 
    /* Require to disable power clock if necessary */
587 
 
 587 
    if (pwrclkchanged == SET)
588 
    /* Require to disable power clock if necessary */
 588 
    {
589 
    if (pwrclkchanged == SET)
 589 
      __HAL_RCC_PWR_CLK_DISABLE();
590 
    {
 590 
    }
591 
      __HAL_RCC_PWR_CLK_DISABLE();
 591 
  }
592 
    }
 592 
 
593 
  }
 593 
#if defined(RCC_CR_PLL2ON)
594 
 
 594 
  /*-------------------------------- PLL2 Configuration -----------------------*/
595 
#if defined(RCC_CR_PLL2ON)
 595 
  /* Check the parameters */
596 
  /*-------------------------------- PLL2 Configuration -----------------------*/
 596 
  assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State));
597 
  /* Check the parameters */
 597 
  if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE)
598 
  assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State));
 598 
  {
599 
  if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE)
 599 
    /* This bit can not be cleared if the PLL2 clock is used indirectly as system
600 
  {
 600 
      clock (i.e. it is used as PLL clock entry that is used as system clock). */
601 
    /* This bit can not be cleared if the PLL2 clock is used indirectly as system
 601 
    if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
602 
      clock (i.e. it is used as PLL clock entry that is used as system clock). */
 602 
        (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
603 
    if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
 603 
        ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
604 
        (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
 604 
    {
605 
        ((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
 605 
      return HAL_ERROR;
606 
    {
 606 
    }
607 
      return HAL_ERROR;
 607 
    else
608 
    }
 608 
    {
609 
    else
 609 
      if ((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON)
610 
    {
 610 
      {
611 
      if ((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON)
 611 
        /* Check the parameters */
612 
      {
 612 
        assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL));
613 
        /* Check the parameters */
 613 
        assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value));
614 
        assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL));
 614 
 
615 
        assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value));
 615 
        /* Prediv2 can be written only when the PLLI2S is disabled. */
616 
 
 616 
        /* Return an error only if new value is different from the programmed value */
617 
        /* Prediv2 can be written only when the PLLI2S is disabled. */
 617 
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \
618 
        /* Return an error only if new value is different from the programmed value */
 618 
            (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value))
619 
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \
 619 
        {
620 
            (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value))
 620 
          return HAL_ERROR;
621 
        {
 621 
        }
622 
          return HAL_ERROR;
 622 
 
623 
        }
 623 
        /* Disable the main PLL2. */
624 
 
 624 
        __HAL_RCC_PLL2_DISABLE();
625 
        /* Disable the main PLL2. */
 625 
 
626 
        __HAL_RCC_PLL2_DISABLE();
 626 
        /* Get Start Tick */
627 
 
 627 
        tickstart = HAL_GetTick();
628 
        /* Get Start Tick */
 628 
 
629 
        tickstart = HAL_GetTick();
 629 
        /* Wait till PLL2 is disabled */
630 
 
 630 
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
631 
        /* Wait till PLL2 is disabled */
 631 
        {
632 
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
 632 
          if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
633 
        {
 633 
          {
634 
          if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
 634 
            return HAL_TIMEOUT;
635 
          {
 635 
          }
636 
            return HAL_TIMEOUT;
 636 
        }
637 
          }
 637 
 
638 
        }
 638 
        /* Configure the HSE prediv2 factor --------------------------------*/
639 
 
 639 
        __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value);
640 
        /* Configure the HSE prediv2 factor --------------------------------*/
 640 
 
641 
        __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value);
 641 
        /* Configure the main PLL2 multiplication factors. */
642 
 
 642 
        __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL);
643 
        /* Configure the main PLL2 multiplication factors. */
 643 
 
644 
        __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL);
 644 
        /* Enable the main PLL2. */
645 
 
 645 
        __HAL_RCC_PLL2_ENABLE();
646 
        /* Enable the main PLL2. */
 646 
 
647 
        __HAL_RCC_PLL2_ENABLE();
 647 
        /* Get Start Tick */
648 
 
 648 
        tickstart = HAL_GetTick();
649 
        /* Get Start Tick */
 649 
 
650 
        tickstart = HAL_GetTick();
 650 
        /* Wait till PLL2 is ready */
651 
 
 651 
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY)  == RESET)
652 
        /* Wait till PLL2 is ready */
 652 
        {
653 
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY)  == RESET)
 653 
          if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
654 
        {
 654 
          {
655 
          if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
 655 
            return HAL_TIMEOUT;
656 
          {
 656 
          }
657 
            return HAL_TIMEOUT;
 657 
        }
658 
          }
 658 
      }
659 
        }
 659 
      else
660 
      }
 660 
      {
661 
      else
 661 
        /* Set PREDIV1 source to HSE */
662 
      {
 662 
        CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC);
663 
        /* Set PREDIV1 source to HSE */
 663 
 
664 
        CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC);
 664 
        /* Disable the main PLL2. */
665 
 
 665 
        __HAL_RCC_PLL2_DISABLE();
666 
        /* Disable the main PLL2. */
 666 
 
667 
        __HAL_RCC_PLL2_DISABLE();
 667 
        /* Get Start Tick */
668 
 
 668 
        tickstart = HAL_GetTick();
669 
        /* Get Start Tick */
 669 
 
670 
        tickstart = HAL_GetTick();
 670 
        /* Wait till PLL2 is disabled */
671 
 
 671 
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY)  != RESET)
672 
        /* Wait till PLL2 is disabled */
 672 
        {
673 
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY)  != RESET)
 673 
          if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
674 
        {
 674 
          {
675 
          if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
 675 
            return HAL_TIMEOUT;
676 
          {
 676 
          }
677 
            return HAL_TIMEOUT;
 677 
        }
678 
          }
 678 
      }
679 
        }
 679 
    }
680 
      }
 680 
  }
681 
    }
 681 
 
682 
  }
 682 
#endif /* RCC_CR_PLL2ON */
683 
 
 683 
  /*-------------------------------- PLL Configuration -----------------------*/
684 
#endif /* RCC_CR_PLL2ON */
 684 
  /* Check the parameters */
685 
  /*-------------------------------- PLL Configuration -----------------------*/
 685 
  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
686 
  /* Check the parameters */
 686 
  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
687 
  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
 687 
  {
688 
  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
 688 
    /* Check if the PLL is used as system clock or not */
689 
  {
 689 
    if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
690 
    /* Check if the PLL is used as system clock or not */
 690 
    {
691 
    if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
 691 
      if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
692 
    {
 692 
      {
693 
      if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
 693 
        /* Check the parameters */
694 
      {
 694 
        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
695 
        /* Check the parameters */
 695 
        assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
696 
        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
 696 
 
697 
        assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
 697 
        /* Disable the main PLL. */
698 
 
 698 
        __HAL_RCC_PLL_DISABLE();
699 
        /* Disable the main PLL. */
 699 
 
700 
        __HAL_RCC_PLL_DISABLE();
 700 
        /* Get Start Tick */
701 
 
 701 
        tickstart = HAL_GetTick();
702 
        /* Get Start Tick */
 702 
 
703 
        tickstart = HAL_GetTick();
 703 
        /* Wait till PLL is disabled */
704 
 
 704 
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
705 
        /* Wait till PLL is disabled */
 705 
        {
706 
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
 706 
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
707 
        {
 707 
          {
708 
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 708 
            return HAL_TIMEOUT;
709 
          {
 709 
          }
710 
            return HAL_TIMEOUT;
 710 
        }
711 
          }
 711 
 
712 
        }
 712 
        /* Configure the HSE prediv factor --------------------------------*/
713 
 
 713 
        /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
714 
        /* Configure the HSE prediv factor --------------------------------*/
 714 
        if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
715 
        /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
 715 
        {
716 
        if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
 716 
          /* Check the parameter */
717 
        {
 717 
          assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue));
718 
          /* Check the parameter */
 718 
#if defined(RCC_CFGR2_PREDIV1SRC)
719 
          assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue));
 719 
          assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source));
720 
#if defined(RCC_CFGR2_PREDIV1SRC)
 720 
 
721 
          assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source));
 721 
          /* Set PREDIV1 source */
722 
 
 722 
          SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
723 
          /* Set PREDIV1 source */
 723 
#endif /* RCC_CFGR2_PREDIV1SRC */
724 
          SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
 724 
 
725 
#endif /* RCC_CFGR2_PREDIV1SRC */
 725 
          /* Set PREDIV1 Value */
726 
 
 726 
          __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
727 
          /* Set PREDIV1 Value */
 727 
        }
728 
          __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
 728 
 
729 
        }
 729 
        /* Configure the main PLL clock source and multiplication factors. */
730 
 
 730 
        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
731 
        /* Configure the main PLL clock source and multiplication factors. */
 731 
                             RCC_OscInitStruct->PLL.PLLMUL);
732 
        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
 732 
        /* Enable the main PLL. */
733 
                             RCC_OscInitStruct->PLL.PLLMUL);
 733 
        __HAL_RCC_PLL_ENABLE();
734 
        /* Enable the main PLL. */
 734 
 
735 
        __HAL_RCC_PLL_ENABLE();
 735 
        /* Get Start Tick */
736 
 
 736 
        tickstart = HAL_GetTick();
737 
        /* Get Start Tick */
 737 
 
738 
        tickstart = HAL_GetTick();
 738 
        /* Wait till PLL is ready */
739 
 
 739 
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  == RESET)
740 
        /* Wait till PLL is ready */
 740 
        {
741 
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  == RESET)
 741 
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
742 
        {
 742 
          {
743 
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 743 
            return HAL_TIMEOUT;
744 
          {
 744 
          }
745 
            return HAL_TIMEOUT;
 745 
        }
746 
          }
 746 
      }
747 
        }
 747 
      else
748 
      }
 748 
      {
749 
      else
 749 
        /* Disable the main PLL. */
750 
      {
 750 
        __HAL_RCC_PLL_DISABLE();
751 
        /* Disable the main PLL. */
 751 
 
752 
        __HAL_RCC_PLL_DISABLE();
 752 
        /* Get Start Tick */
753 
 
 753 
        tickstart = HAL_GetTick();
754 
        /* Get Start Tick */
 754 
 
755 
        tickstart = HAL_GetTick();
 755 
        /* Wait till PLL is disabled */
756 
 
 756 
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
757 
        /* Wait till PLL is disabled */
 757 
        {
758 
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
 758 
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
759 
        {
 759 
          {
760 
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 760 
            return HAL_TIMEOUT;
761 
          {
 761 
          }
762 
            return HAL_TIMEOUT;
 762 
        }
763 
          }
 763 
      }
764 
        }
 764 
    }
765 
      }
 765 
    else
766 
    }
 766 
    {
767 
    else
 767 
      /* Check if there is a request to disable the PLL used as System clock source */
768 
    {
 768 
      if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
769 
      /* Check if there is a request to disable the PLL used as System clock source */
 769 
      {
770 
      if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
 770 
        return HAL_ERROR;
771 
      {
 771 
      }
772 
        return HAL_ERROR;
 772 
      else
773 
      }
 773 
      {
774 
      else
 774 
        /* Do not return HAL_ERROR if request repeats the current configuration */
775 
      {
 775 
        pll_config = RCC->CFGR;
776 
        /* Do not return HAL_ERROR if request repeats the current configuration */
 776 
        if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
777 
        pll_config = RCC->CFGR;
 777 
            (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL))
778 
        if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
 778 
        {
779 
            (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL))
 779 
          return HAL_ERROR;
780 
        {
 780 
        }
781 
          return HAL_ERROR;
 781 
      }
782 
        }
 782 
    }
783 
      }
 783 
  }
784 
    }
 784 
 
785 
  }
 785 
  return HAL_OK;
786 
 
 786 
}
787 
  return HAL_OK;
 787 
 
788 
}
 788 
/**
789 
 
 789 
  * @brief  Initializes the CPU, AHB and APB buses clocks according to the specified
790 
/**
 790 
  *         parameters in the RCC_ClkInitStruct.
791 
  * @brief  Initializes the CPU, AHB and APB buses clocks according to the specified
 791 
  * @param  RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
792 
  *         parameters in the RCC_ClkInitStruct.
 792 
  *         contains the configuration information for the RCC peripheral.
793 
  * @param  RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
 793 
  * @param  FLatency FLASH Latency
794 
  *         contains the configuration information for the RCC peripheral.
 794 
  *          The value of this parameter depend on device used within the same series
795 
  * @param  FLatency FLASH Latency
 795 
  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
796 
  *          The value of this parameter depend on device used within the same series
 796 
  *         and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function
797 
  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
 797 
  *
798 
  *         and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function
 798 
  * @note   The HSI is used (enabled by hardware) as system clock source after
799 
  *
 799 
  *         start-up from Reset, wake-up from STOP and STANDBY mode, or in case
800 
  * @note   The HSI is used (enabled by hardware) as system clock source after
 800 
  *         of failure of the HSE used directly or indirectly as system clock
801 
  *         start-up from Reset, wake-up from STOP and STANDBY mode, or in case
 801 
  *         (if the Clock Security System CSS is enabled).
802 
  *         of failure of the HSE used directly or indirectly as system clock
 802 
  *
803 
  *         (if the Clock Security System CSS is enabled).
 803 
  * @note   A switch from one clock source to another occurs only if the target
804 
  *
 804 
  *         clock source is ready (clock stable after start-up delay or PLL locked).
805 
  * @note   A switch from one clock source to another occurs only if the target
 805 
  *         If a clock source which is not yet ready is selected, the switch will
806 
  *         clock source is ready (clock stable after start-up delay or PLL locked).
 806 
  *         occur when the clock source will be ready.
807 
  *         If a clock source which is not yet ready is selected, the switch will
 807 
  *         You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
808 
  *         occur when the clock source will be ready.
 808 
  *         currently used as system clock source.
809 
  *         You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
 809 
  * @retval HAL status
810 
  *         currently used as system clock source.
 810 
  */
811 
  * @retval HAL status
 811 
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
812 
  */
 812 
{
813 
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
 813 
  uint32_t tickstart;
814 
{
 814 
 
815 
  uint32_t tickstart;
 815 
  /* Check Null pointer */
816 
 
 816 
  if (RCC_ClkInitStruct == NULL)
817 
  /* Check Null pointer */
 817 
  {
818 
  if (RCC_ClkInitStruct == NULL)
 818 
    return HAL_ERROR;
819 
  {
 819 
  }
820 
    return HAL_ERROR;
 820 
 
821 
  }
 821 
  /* Check the parameters */
822 
 
 822 
  assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
823 
  /* Check the parameters */
 823 
  assert_param(IS_FLASH_LATENCY(FLatency));
824 
  assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
 824 
 
825 
  assert_param(IS_FLASH_LATENCY(FLatency));
 825 
  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
826 
 
 826 
  must be correctly programmed according to the frequency of the CPU clock
827 
  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
 827 
    (HCLK) of the device. */
828 
  must be correctly programmed according to the frequency of the CPU clock
 828 
 
829 
    (HCLK) of the device. */
 829 
#if defined(FLASH_ACR_LATENCY)
830 
 
 830 
  /* Increasing the number of wait states because of higher CPU frequency */
831 
#if defined(FLASH_ACR_LATENCY)
 831 
  if (FLatency > __HAL_FLASH_GET_LATENCY())
832 
  /* Increasing the number of wait states because of higher CPU frequency */
 832 
  {
833 
  if (FLatency > __HAL_FLASH_GET_LATENCY())
 833 
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
834 
  {
 834 
    __HAL_FLASH_SET_LATENCY(FLatency);
835 
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
 835 
 
836 
    __HAL_FLASH_SET_LATENCY(FLatency);
 836 
    /* Check that the new number of wait states is taken into account to access the Flash
837 
 
 837 
    memory by reading the FLASH_ACR register */
838 
    /* Check that the new number of wait states is taken into account to access the Flash
 838 
    if (__HAL_FLASH_GET_LATENCY() != FLatency)
839 
    memory by reading the FLASH_ACR register */
 839 
  {
840 
    if (__HAL_FLASH_GET_LATENCY() != FLatency)
 840 
    return HAL_ERROR;
841 
  {
 841 
  }
842 
    return HAL_ERROR;
 842 
}
843 
  }
 843 
 
844 
}
 844 
#endif /* FLASH_ACR_LATENCY */
845 
 
 845 
/*-------------------------- HCLK Configuration --------------------------*/
846 
#endif /* FLASH_ACR_LATENCY */
 846 
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
847 
/*-------------------------- HCLK Configuration --------------------------*/
 847 
  {
848 
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
 848 
    /* Set the highest APBx dividers in order to ensure that we do not go through
849 
  {
 849 
    a non-spec phase whatever we decrease or increase HCLK. */
850 
    /* Set the highest APBx dividers in order to ensure that we do not go through
 850 
    if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
851 
    a non-spec phase whatever we decrease or increase HCLK. */
 851 
    {
852 
    if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 852 
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
853 
    {
 853 
    }
854 
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
 854 
 
855 
    }
 855 
    if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
856 
 
 856 
    {
857 
    if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 857 
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
858 
    {
 858 
    }
859 
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
 859 
 
860 
    }
 860 
    /* Set the new HCLK clock divider */
861 
 
 861 
    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
862 
    /* Set the new HCLK clock divider */
 862 
    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
863 
    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
 863 
  }
864 
    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
 864 
 
865 
  }
 865 
  /*------------------------- SYSCLK Configuration ---------------------------*/
866 
 
 866 
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
867 
  /*------------------------- SYSCLK Configuration ---------------------------*/
 867 
  {
868 
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
 868 
    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
869 
  {
 869 
 
870 
    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
 870 
    /* HSE is selected as System Clock Source */
871 
 
 871 
    if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
872 
    /* HSE is selected as System Clock Source */
 872 
    {
873 
    if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 873 
      /* Check the HSE ready flag */
874 
    {
 874 
      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
875 
      /* Check the HSE ready flag */
 875 
      {
876 
      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 876 
        return HAL_ERROR;
877 
      {
 877 
      }
878 
        return HAL_ERROR;
 878 
    }
879 
      }
 879 
    /* PLL is selected as System Clock Source */
880 
    }
 880 
    else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
881 
    /* PLL is selected as System Clock Source */
 881 
    {
882 
    else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
 882 
      /* Check the PLL ready flag */
883 
    {
 883 
      if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
884 
      /* Check the PLL ready flag */
 884 
      {
885 
      if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
 885 
        return HAL_ERROR;
886 
      {
 886 
      }
887 
        return HAL_ERROR;
 887 
    }
888 
      }
 888 
    /* HSI is selected as System Clock Source */
889 
    }
 889 
    else
890 
    /* HSI is selected as System Clock Source */
 890 
    {
891 
    else
 891 
      /* Check the HSI ready flag */
892 
    {
 892 
      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
893 
      /* Check the HSI ready flag */
 893 
      {
894 
      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 894 
        return HAL_ERROR;
895 
      {
 895 
      }
896 
        return HAL_ERROR;
 896 
    }
897 
      }
 897 
    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
898 
    }
 898 
 
899 
    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
 899 
    /* Get Start Tick */
900 
 
 900 
    tickstart = HAL_GetTick();
901 
    /* Get Start Tick */
 901 
 
902 
    tickstart = HAL_GetTick();
 902 
    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
903 
 
 903 
    {
904 
    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
 904 
      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
905 
    {
 905 
      {
906 
      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
 906 
        return HAL_TIMEOUT;
907 
      {
 907 
      }
908 
        return HAL_TIMEOUT;
 908 
    }
909 
      }
 909 
  }
910 
    }
 910 
 
911 
  }
 911 
#if defined(FLASH_ACR_LATENCY)
912 
 
 912 
  /* Decreasing the number of wait states because of lower CPU frequency */
913 
#if defined(FLASH_ACR_LATENCY)
 913 
  if (FLatency < __HAL_FLASH_GET_LATENCY())
914 
  /* Decreasing the number of wait states because of lower CPU frequency */
 914 
  {
915 
  if (FLatency < __HAL_FLASH_GET_LATENCY())
 915 
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
916 
  {
 916 
    __HAL_FLASH_SET_LATENCY(FLatency);
917 
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
 917 
 
918 
    __HAL_FLASH_SET_LATENCY(FLatency);
 918 
    /* Check that the new number of wait states is taken into account to access the Flash
919 
 
 919 
    memory by reading the FLASH_ACR register */
920 
    /* Check that the new number of wait states is taken into account to access the Flash
 920 
    if (__HAL_FLASH_GET_LATENCY() != FLatency)
921 
    memory by reading the FLASH_ACR register */
 921 
  {
922 
    if (__HAL_FLASH_GET_LATENCY() != FLatency)
 922 
    return HAL_ERROR;
923 
  {
 923 
  }
924 
    return HAL_ERROR;
 924 
}
925 
  }
 925 
#endif /* FLASH_ACR_LATENCY */
926 
}
 926 
 
927 
#endif /* FLASH_ACR_LATENCY */
 927 
/*-------------------------- PCLK1 Configuration ---------------------------*/
928 
 
 928 
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
929 
/*-------------------------- PCLK1 Configuration ---------------------------*/
 929 
  {
930 
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 930 
    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
931 
  {
 931 
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
932 
    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
 932 
  }
933 
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
 933 
 
934 
  }
 934 
  /*-------------------------- PCLK2 Configuration ---------------------------*/
935 
 
 935 
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
936 
  /*-------------------------- PCLK2 Configuration ---------------------------*/
 936 
  {
937 
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 937 
    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
938 
  {
 938 
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
939 
    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
 939 
  }
940 
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
 940 
 
941 
  }
 941 
  /* Update the SystemCoreClock global variable */
942 
 
 942 
  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
943 
  /* Update the SystemCoreClock global variable */
 943 
 
944 
  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
 944 
  /* Configure the source of time base considering new system clocks settings*/
945 
 
 945 
  HAL_InitTick(uwTickPrio);
946 
  /* Configure the source of time base considering new system clocks settings*/
 946 
 
947 
  HAL_InitTick(uwTickPrio);
 947 
  return HAL_OK;
948 
 
 948 
}
949 
  return HAL_OK;
 949 
 
950 
}
 950 
/**
951 
 
 951 
  * @}
952 
/**
 952 
  */
953 
  * @}
 953 
 
954 
  */
 954 
/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
955 
 
 955 
  *  @brief   RCC clocks control functions
956 
/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
 956 
  *
957 
  *  @brief   RCC clocks control functions
 957 
  @verbatim
958 
  *
 958 
  ===============================================================================
959 
  @verbatim
 959 
                  ##### Peripheral Control functions #####
960 
  ===============================================================================
 960 
  ===============================================================================
961 
                  ##### Peripheral Control functions #####
 961 
    [..]
962 
  ===============================================================================
 962 
    This subsection provides a set of functions allowing to control the RCC Clocks
963 
    [..]
 963 
    frequencies.
964 
    This subsection provides a set of functions allowing to control the RCC Clocks
 964 
 
965 
    frequencies.
 965 
  @endverbatim
966 
 
 966 
  * @{
967 
  @endverbatim
 967 
  */
968 
  * @{
 968 
 
969 
  */
 969 
/**
970 
 
 970 
  * @brief  Selects the clock source to output on MCO pin.
971 
/**
 971 
  * @note   MCO pin should be configured in alternate function mode.
972 
  * @brief  Selects the clock source to output on MCO pin.
 972 
  * @param  RCC_MCOx specifies the output direction for the clock source.
973 
  * @note   MCO pin should be configured in alternate function mode.
 973 
  *          This parameter can be one of the following values:
974 
  * @param  RCC_MCOx specifies the output direction for the clock source.
 974 
  *            @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
975 
  *          This parameter can be one of the following values:
 975 
  * @param  RCC_MCOSource specifies the clock source to output.
976 
  *            @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
 976 
  *          This parameter can be one of the following values:
977 
  * @param  RCC_MCOSource specifies the clock source to output.
 977 
  *            @arg @ref RCC_MCO1SOURCE_NOCLOCK     No clock selected as MCO clock
978 
  *          This parameter can be one of the following values:
 978 
  *            @arg @ref RCC_MCO1SOURCE_SYSCLK      System clock selected as MCO clock
979 
  *            @arg @ref RCC_MCO1SOURCE_NOCLOCK     No clock selected as MCO clock
 979 
  *            @arg @ref RCC_MCO1SOURCE_HSI         HSI selected as MCO clock
980 
  *            @arg @ref RCC_MCO1SOURCE_SYSCLK      System clock selected as MCO clock
 980 
  *            @arg @ref RCC_MCO1SOURCE_HSE         HSE selected as MCO clock
981 
  *            @arg @ref RCC_MCO1SOURCE_HSI         HSI selected as MCO clock
 981 
  @if STM32F105xC
982 
  *            @arg @ref RCC_MCO1SOURCE_HSE         HSE selected as MCO clock
 982 
  *            @arg @ref RCC_MCO1SOURCE_PLLCLK       PLL clock divided by 2 selected as MCO source
983 
  @if STM32F105xC
 983 
  *            @arg @ref RCC_MCO1SOURCE_PLL2CLK      PLL2 clock selected as MCO source
984 
  *            @arg @ref RCC_MCO1SOURCE_PLLCLK       PLL clock divided by 2 selected as MCO source
 984 
  *            @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source
985 
  *            @arg @ref RCC_MCO1SOURCE_PLL2CLK      PLL2 clock selected as MCO source
 985 
  *            @arg @ref RCC_MCO1SOURCE_EXT_HSE      XT1 external 3-25 MHz oscillator clock selected as MCO source
986 
  *            @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source
 986 
  *            @arg @ref RCC_MCO1SOURCE_PLL3CLK      PLL3 clock selected as MCO source
987 
  *            @arg @ref RCC_MCO1SOURCE_EXT_HSE      XT1 external 3-25 MHz oscillator clock selected as MCO source
 987 
  @endif
988 
  *            @arg @ref RCC_MCO1SOURCE_PLL3CLK      PLL3 clock selected as MCO source
 988 
  @if STM32F107xC
989 
  @endif
 989 
  *            @arg @ref RCC_MCO1SOURCE_PLLCLK       PLL clock divided by 2 selected as MCO source
990 
  @if STM32F107xC
 990 
  *            @arg @ref RCC_MCO1SOURCE_PLL2CLK      PLL2 clock selected as MCO source
991 
  *            @arg @ref RCC_MCO1SOURCE_PLLCLK       PLL clock divided by 2 selected as MCO source
 991 
  *            @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source
992 
  *            @arg @ref RCC_MCO1SOURCE_PLL2CLK      PLL2 clock selected as MCO source
 992 
  *            @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1  external 3-25 MHz oscillator clock selected as MCO source
993 
  *            @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source
 993 
  *            @arg @ref RCC_MCO1SOURCE_PLL3CLK      PLL3 clock selected as MCO source
994 
  *            @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1  external 3-25 MHz oscillator clock selected as MCO source
 994 
  @endif
995 
  *            @arg @ref RCC_MCO1SOURCE_PLL3CLK      PLL3 clock selected as MCO source
 995 
  * @param  RCC_MCODiv specifies the MCO DIV.
996 
  @endif
 996 
  *          This parameter can be one of the following values:
997 
  * @param  RCC_MCODiv specifies the MCO DIV.
 997 
  *            @arg @ref RCC_MCODIV_1 no division applied to MCO clock
998 
  *          This parameter can be one of the following values:
 998 
  * @retval None
999 
  *            @arg @ref RCC_MCODIV_1 no division applied to MCO clock
 999 
  */
1000 
  * @retval None
 1000 
void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
1001 
  */
 1001 
{
1002 
void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
 1002 
  GPIO_InitTypeDef gpio = {0U};
1003 
{
 1003 
 
1004 
  GPIO_InitTypeDef gpio = {0U};
 1004 
  /* Check the parameters */
1005 
 
 1005 
  assert_param(IS_RCC_MCO(RCC_MCOx));
1006 
  /* Check the parameters */
 1006 
  assert_param(IS_RCC_MCODIV(RCC_MCODiv));
1007 
  assert_param(IS_RCC_MCO(RCC_MCOx));
 1007 
  assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
1008 
  assert_param(IS_RCC_MCODIV(RCC_MCODiv));
 1008 
 
1009 
  assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
 1009 
  /* Prevent unused argument(s) compilation warning */
1010 
 
 1010 
  UNUSED(RCC_MCOx);
1011 
  /* Prevent unused argument(s) compilation warning */
 1011 
  UNUSED(RCC_MCODiv);
1012 
  UNUSED(RCC_MCOx);
 1012 
 
1013 
  UNUSED(RCC_MCODiv);
 1013 
  /* Configure the MCO1 pin in alternate function mode */
1014 
 
 1014 
  gpio.Mode      = GPIO_MODE_AF_PP;
1015 
  /* Configure the MCO1 pin in alternate function mode */
 1015 
  gpio.Speed     = GPIO_SPEED_FREQ_HIGH;
1016 
  gpio.Mode      = GPIO_MODE_AF_PP;
 1016 
  gpio.Pull      = GPIO_NOPULL;
1017 
  gpio.Speed     = GPIO_SPEED_FREQ_HIGH;
 1017 
  gpio.Pin       = MCO1_PIN;
1018 
  gpio.Pull      = GPIO_NOPULL;
 1018 
 
1019 
  gpio.Pin       = MCO1_PIN;
 1019 
  /* MCO1 Clock Enable */
1020 
 
 1020 
  MCO1_CLK_ENABLE();
1021 
  /* MCO1 Clock Enable */
 1021 
 
1022 
  MCO1_CLK_ENABLE();
 1022 
  HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio);
1023 
 
 1023 
 
1024 
  HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio);
 1024 
  /* Configure the MCO clock source */
1025 
 
 1025 
  __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv);
1026 
  /* Configure the MCO clock source */
 1026 
}
1027 
  __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv);
 1027 
 
1028 
}
 1028 
/**
1029 
 
 1029 
  * @brief  Enables the Clock Security System.
1030 
/**
 1030 
  * @note   If a failure is detected on the HSE oscillator clock, this oscillator
1031 
  * @brief  Enables the Clock Security System.
 1031 
  *         is automatically disabled and an interrupt is generated to inform the
1032 
  * @note   If a failure is detected on the HSE oscillator clock, this oscillator
 1032 
  *         software about the failure (Clock Security System Interrupt, CSSI),
1033 
  *         is automatically disabled and an interrupt is generated to inform the
 1033 
  *         allowing the MCU to perform rescue operations. The CSSI is linked to
1034 
  *         software about the failure (Clock Security System Interrupt, CSSI),
 1034 
  *         the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.
1035 
  *         allowing the MCU to perform rescue operations. The CSSI is linked to
 1035 
  * @retval None
1036 
  *         the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.
 1036 
  */
1037 
  * @retval None
 1037 
void HAL_RCC_EnableCSS(void)
1038 
  */
 1038 
{
1039 
void HAL_RCC_EnableCSS(void)
 1039 
  *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
1040 
{
 1040 
}
1041 
  *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
 1041 
 
1042 
}
 1042 
/**
1043 
 
 1043 
  * @brief  Disables the Clock Security System.
1044 
/**
 1044 
  * @retval None
1045 
  * @brief  Disables the Clock Security System.
 1045 
  */
1046 
  * @retval None
 1046 
void HAL_RCC_DisableCSS(void)
1047 
  */
 1047 
{
1048 
void HAL_RCC_DisableCSS(void)
 1048 
  *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
1049 
{
 1049 
}
1050 
  *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
 1050 
 
1051 
}
 1051 
/**
1052 
 
 1052 
  * @brief  Returns the SYSCLK frequency
1053 
/**
 1053 
  * @note   The system frequency computed by this function is not the real
1054 
  * @brief  Returns the SYSCLK frequency
 1054 
  *         frequency in the chip. It is calculated based on the predefined
1055 
  * @note   The system frequency computed by this function is not the real
 1055 
  *         constant and the selected clock source:
1056 
  *         frequency in the chip. It is calculated based on the predefined
 1056 
  * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
1057 
  *         constant and the selected clock source:
 1057 
  * @note     If SYSCLK source is HSE, function returns a value based on HSE_VALUE
1058 
  * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
 1058 
  *           divided by PREDIV factor(**)
1059 
  * @note     If SYSCLK source is HSE, function returns a value based on HSE_VALUE
 1059 
  * @note     If SYSCLK source is PLL, function returns a value based on HSE_VALUE
1060 
  *           divided by PREDIV factor(**)
 1060 
  *           divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor.
1061 
  * @note     If SYSCLK source is PLL, function returns a value based on HSE_VALUE
 1061 
  * @note     (*) HSI_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
1062 
  *           divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor.
 1062 
  *               8 MHz) but the real value may vary depending on the variations
1063 
  * @note     (*) HSI_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
 1063 
  *               in voltage and temperature.
1064 
  *               8 MHz) but the real value may vary depending on the variations
 1064 
  * @note     (**) HSE_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
1065 
  *               in voltage and temperature.
 1065 
  *                8 MHz), user has to ensure that HSE_VALUE is same as the real
1066 
  * @note     (**) HSE_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
 1066 
  *                frequency of the crystal used. Otherwise, this function may
1067 
  *                8 MHz), user has to ensure that HSE_VALUE is same as the real
 1067 
  *                have wrong result.
1068 
  *                frequency of the crystal used. Otherwise, this function may
 1068 
  *
1069 
  *                have wrong result.
 1069 
  * @note   The result of this function could be not correct when using fractional
1070 
  *
 1070 
  *         value for HSE crystal.
1071 
  * @note   The result of this function could be not correct when using fractional
 1071 
  *
1072 
  *         value for HSE crystal.
 1072 
  * @note   This function can be used by the user application to compute the
1073 
  *
 1073 
  *         baud-rate for the communication peripherals or configure other parameters.
1074 
  * @note   This function can be used by the user application to compute the
 1074 
  *
1075 
  *         baud-rate for the communication peripherals or configure other parameters.
 1075 
  * @note   Each time SYSCLK changes, this function must be called to update the
1076 
  *
 1076 
  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
1077 
  * @note   Each time SYSCLK changes, this function must be called to update the
 1077 
  *
1078 
  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
 1078 
  * @retval SYSCLK frequency
1079 
  *
 1079 
  */
1080 
  * @retval SYSCLK frequency
 1080 
uint32_t HAL_RCC_GetSysClockFreq(void)
1081 
  */
 1081 
{
1082 
uint32_t HAL_RCC_GetSysClockFreq(void)
 1082 
#if defined(RCC_CFGR2_PREDIV1SRC)
1083 
{
 1083 
  static const uint8_t aPLLMULFactorTable[14U] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
1084 
#if defined(RCC_CFGR2_PREDIV1SRC)
 1084 
  static const uint8_t aPredivFactorTable[16U] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
1085 
  const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
 1085 
#else
1086 
  const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
 1086 
  static const uint8_t aPLLMULFactorTable[16U] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
1087 
#else
 1087 
#if defined(RCC_CFGR2_PREDIV1)
1088 
  const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
 1088 
  static const uint8_t aPredivFactorTable[16U] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
1089 
#if defined(RCC_CFGR2_PREDIV1)
 1089 
#else
1090 
  const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
 1090 
  static const uint8_t aPredivFactorTable[2U] = {1, 2};
1091 
#else
 1091 
#endif /*RCC_CFGR2_PREDIV1*/
1092 
  const uint8_t aPredivFactorTable[2] = {1, 2};
 1092 
 
1093 
#endif /*RCC_CFGR2_PREDIV1*/
 1093 
#endif
1094 
 
 1094 
  uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
1095 
#endif
 1095 
  uint32_t sysclockfreq = 0U;
1096 
  uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
 1096 
#if defined(RCC_CFGR2_PREDIV1SRC)
1097 
  uint32_t sysclockfreq = 0U;
 1097 
  uint32_t prediv2 = 0U, pll2mul = 0U;
1098 
#if defined(RCC_CFGR2_PREDIV1SRC)
 1098 
#endif /*RCC_CFGR2_PREDIV1SRC*/
1099 
  uint32_t prediv2 = 0U, pll2mul = 0U;
 1099 
 
1100 
#endif /*RCC_CFGR2_PREDIV1SRC*/
 1100 
  tmpreg = RCC->CFGR;
1101 
 
 1101 
 
1102 
  tmpreg = RCC->CFGR;
 1102 
  /* Get SYSCLK source -------------------------------------------------------*/
1103 
 
 1103 
  switch (tmpreg & RCC_CFGR_SWS)
1104 
  /* Get SYSCLK source -------------------------------------------------------*/
 1104 
  {
1105 
  switch (tmpreg & RCC_CFGR_SWS)
 1105 
    case RCC_SYSCLKSOURCE_STATUS_HSE:  /* HSE used as system clock */
1106 
  {
 1106 
    {
1107 
    case RCC_SYSCLKSOURCE_STATUS_HSE:  /* HSE used as system clock */
 1107 
      sysclockfreq = HSE_VALUE;
1108 
    {
 1108 
      break;
1109 
      sysclockfreq = HSE_VALUE;
 1109 
    }
1110 
      break;
 1110 
    case RCC_SYSCLKSOURCE_STATUS_PLLCLK:  /* PLL used as system clock */
1111 
    }
 1111 
    {
1112 
    case RCC_SYSCLKSOURCE_STATUS_PLLCLK:  /* PLL used as system clock */
 1112 
      pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
1113 
    {
 1113 
      if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
1114 
      pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
 1114 
      {
1115 
      if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
 1115 
#if defined(RCC_CFGR2_PREDIV1)
1116 
      {
 1116 
        prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
1117 
#if defined(RCC_CFGR2_PREDIV1)
 1117 
#else
1118 
        prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
 1118 
        prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
1119 
#else
 1119 
#endif /*RCC_CFGR2_PREDIV1*/
1120 
        prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
 1120 
#if defined(RCC_CFGR2_PREDIV1SRC)
1121 
#endif /*RCC_CFGR2_PREDIV1*/
 1121 
 
1122 
#if defined(RCC_CFGR2_PREDIV1SRC)
 1122 
        if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC))
1123 
 
 1123 
        {
1124 
        if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC))
 1124 
          /* PLL2 selected as Prediv1 source */
1125 
        {
 1125 
          /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
1126 
          /* PLL2 selected as Prediv1 source */
 1126 
          prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
1127 
          /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
 1127 
          pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2;
1128 
          prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
 1128 
          pllclk = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pll2mul * (uint64_t)pllmul) / ((uint64_t)prediv2 * (uint64_t)prediv));
1129 
          pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2;
 1129 
        }
1130 
          pllclk = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pll2mul * (uint64_t)pllmul) / ((uint64_t)prediv2 * (uint64_t)prediv));
 1130 
        else
1131 
        }
 1131 
        {
1132 
        else
 1132 
          /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
1133 
        {
 1133 
          pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
1134 
          /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
 1134 
        }
1135 
          pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
 1135 
 
1136 
        }
 1136 
        /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
1137 
 
 1137 
        /* In this case need to divide pllclk by 2 */
1138 
        /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
 1138 
        if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos])
1139 
        /* In this case need to divide pllclk by 2 */
 1139 
        {
1140 
        if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos])
 1140 
          pllclk = pllclk / 2;
1141 
        {
 1141 
        }
1142 
          pllclk = pllclk / 2;
 1142 
#else
1143 
        }
 1143 
        /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
1144 
#else
 1144 
        pllclk = (uint32_t)((HSE_VALUE  * pllmul) / prediv);
1145 
        /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
 1145 
#endif /*RCC_CFGR2_PREDIV1SRC*/
1146 
        pllclk = (uint32_t)((HSE_VALUE  * pllmul) / prediv);
 1146 
      }
1147 
#endif /*RCC_CFGR2_PREDIV1SRC*/
 1147 
      else
1148 
      }
 1148 
      {
1149 
      else
 1149 
        /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
1150 
      {
 1150 
        pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
1151 
        /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
 1151 
      }
1152 
        pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
 1152 
      sysclockfreq = pllclk;
1153 
      }
 1153 
      break;
1154 
      sysclockfreq = pllclk;
 1154 
    }
1155 
      break;
 1155 
    case RCC_SYSCLKSOURCE_STATUS_HSI:  /* HSI used as system clock source */
1156 
    }
 1156 
    default: /* HSI used as system clock */
1157 
    case RCC_SYSCLKSOURCE_STATUS_HSI:  /* HSI used as system clock source */
 1157 
    {
1158 
    default: /* HSI used as system clock */
 1158 
      sysclockfreq = HSI_VALUE;
1159 
    {
 1159 
      break;
1160 
      sysclockfreq = HSI_VALUE;
 1160 
    }
1161 
      break;
 1161 
  }
1162 
    }
 1162 
  return sysclockfreq;
1163 
  }
 1163 
}
1164 
  return sysclockfreq;
 1164 
 
1165 
}
 1165 
/**
1166 
 
 1166 
  * @brief  Returns the HCLK frequency
1167 
/**
 1167 
  * @note   Each time HCLK changes, this function must be called to update the
1168 
  * @brief  Returns the HCLK frequency
 1168 
  *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.
1169 
  * @note   Each time HCLK changes, this function must be called to update the
 1169 
  *
1170 
  *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.
 1170 
  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
1171 
  *
 1171 
  *         and updated within this function
1172 
  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
 1172 
  * @retval HCLK frequency
1173 
  *         and updated within this function
 1173 
  */
1174 
  * @retval HCLK frequency
 1174 
uint32_t HAL_RCC_GetHCLKFreq(void)
1175 
  */
 1175 
{
1176 
uint32_t HAL_RCC_GetHCLKFreq(void)
 1176 
  return SystemCoreClock;
1177 
{
 1177 
}
1178 
  return SystemCoreClock;
 1178 
 
1179 
}
 1179 
/**
1180 
 
 1180 
  * @brief  Returns the PCLK1 frequency
1181 
/**
 1181 
  * @note   Each time PCLK1 changes, this function must be called to update the
1182 
  * @brief  Returns the PCLK1 frequency
 1182 
  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
1183 
  * @note   Each time PCLK1 changes, this function must be called to update the
 1183 
  * @retval PCLK1 frequency
1184 
  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
 1184 
  */
1185 
  * @retval PCLK1 frequency
 1185 
uint32_t HAL_RCC_GetPCLK1Freq(void)
1186 
  */
 1186 
{
1187 
uint32_t HAL_RCC_GetPCLK1Freq(void)
 1187 
  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
1188 
{
 1188 
  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
1189 
  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
 1189 
}
1190 
  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
 1190 
 
1191 
}
 1191 
/**
1192 
 
 1192 
  * @brief  Returns the PCLK2 frequency
1193 
/**
 1193 
  * @note   Each time PCLK2 changes, this function must be called to update the
1194 
  * @brief  Returns the PCLK2 frequency
 1194 
  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
1195 
  * @note   Each time PCLK2 changes, this function must be called to update the
 1195 
  * @retval PCLK2 frequency
1196 
  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
 1196 
  */
1197 
  * @retval PCLK2 frequency
 1197 
uint32_t HAL_RCC_GetPCLK2Freq(void)
1198 
  */
 1198 
{
1199 
uint32_t HAL_RCC_GetPCLK2Freq(void)
 1199 
  /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
1200 
{
 1200 
  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
1201 
  /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
 1201 
}
1202 
  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
 1202 
 
1203 
}
 1203 
/**
1204 
 
 1204 
  * @brief  Configures the RCC_OscInitStruct according to the internal
1205 
/**
 1205 
  * RCC configuration registers.
1206 
  * @brief  Configures the RCC_OscInitStruct according to the internal
 1206 
  * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
1207 
  * RCC configuration registers.
 1207 
  * will be configured.
1208 
  * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
 1208 
  * @retval None
1209 
  * will be configured.
 1209 
  */
1210 
  * @retval None
 1210 
void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
1211 
  */
 1211 
{
1212 
void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
 1212 
  /* Check the parameters */
1213 
{
 1213 
  assert_param(RCC_OscInitStruct != NULL);
1214 
  /* Check the parameters */
 1214 
 
1215 
  assert_param(RCC_OscInitStruct != NULL);
 1215 
  /* Set all possible values for the Oscillator type parameter ---------------*/
1216 
 
 1216 
  RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI  \
1217 
  /* Set all possible values for the Oscillator type parameter ---------------*/
 1217 
                                      | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
1218 
  RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI  \
 1218 
 
1219 
                                      | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
 1219 
#if defined(RCC_CFGR2_PREDIV1SRC)
1220 
 
 1220 
  /* Get the Prediv1 source --------------------------------------------------*/
1221 
#if defined(RCC_CFGR2_PREDIV1SRC)
 1221 
  RCC_OscInitStruct->Prediv1Source = READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC);
1222 
  /* Get the Prediv1 source --------------------------------------------------*/
 1222 
#endif /* RCC_CFGR2_PREDIV1SRC */
1223 
  RCC_OscInitStruct->Prediv1Source = READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC);
 1223 
 
1224 
#endif /* RCC_CFGR2_PREDIV1SRC */
 1224 
  /* Get the HSE configuration -----------------------------------------------*/
1225 
 
 1225 
  if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
1226 
  /* Get the HSE configuration -----------------------------------------------*/
 1226 
  {
1227 
  if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
 1227 
    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
1228 
  {
 1228 
  }
1229 
    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
 1229 
  else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
1230 
  }
 1230 
  {
1231 
  else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
 1231 
    RCC_OscInitStruct->HSEState = RCC_HSE_ON;
1232 
  {
 1232 
  }
1233 
    RCC_OscInitStruct->HSEState = RCC_HSE_ON;
 1233 
  else
1234 
  }
 1234 
  {
1235 
  else
 1235 
    RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
1236 
  {
 1236 
  }
1237 
    RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
 1237 
  RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV();
1238 
  }
 1238 
 
1239 
  RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV();
 1239 
  /* Get the HSI configuration -----------------------------------------------*/
1240 
 
 1240 
  if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
1241 
  /* Get the HSI configuration -----------------------------------------------*/
 1241 
  {
1242 
  if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
 1242 
    RCC_OscInitStruct->HSIState = RCC_HSI_ON;
1243 
  {
 1243 
  }
1244 
    RCC_OscInitStruct->HSIState = RCC_HSI_ON;
 1244 
  else
1245 
  }
 1245 
  {
1246 
  else
 1246 
    RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
1247 
  {
 1247 
  }
1248 
    RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
 1248 
 
1249 
  }
 1249 
  RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
1250 
 
 1250 
 
1251 
  RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
 1251 
  /* Get the LSE configuration -----------------------------------------------*/
1252 
 
 1252 
  if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
1253 
  /* Get the LSE configuration -----------------------------------------------*/
 1253 
  {
1254 
  if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
 1254 
    RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
1255 
  {
 1255 
  }
1256 
    RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
 1256 
  else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
1257 
  }
 1257 
  {
1258 
  else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
 1258 
    RCC_OscInitStruct->LSEState = RCC_LSE_ON;
1259 
  {
 1259 
  }
1260 
    RCC_OscInitStruct->LSEState = RCC_LSE_ON;
 1260 
  else
1261 
  }
 1261 
  {
1262 
  else
 1262 
    RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
1263 
  {
 1263 
  }
1264 
    RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
 1264 
 
1265 
  }
 1265 
  /* Get the LSI configuration -----------------------------------------------*/
1266 
 
 1266 
  if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION)
1267 
  /* Get the LSI configuration -----------------------------------------------*/
 1267 
  {
1268 
  if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION)
 1268 
    RCC_OscInitStruct->LSIState = RCC_LSI_ON;
1269 
  {
 1269 
  }
1270 
    RCC_OscInitStruct->LSIState = RCC_LSI_ON;
 1270 
  else
1271 
  }
 1271 
  {
1272 
  else
 1272 
    RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
1273 
  {
 1273 
  }
1274 
    RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
 1274 
 
1275 
  }
 1275 
 
1276 
 
 1276 
  /* Get the PLL configuration -----------------------------------------------*/
1277 
 
 1277 
  if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON)
1278 
  /* Get the PLL configuration -----------------------------------------------*/
 1278 
  {
1279 
  if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON)
 1279 
    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
1280 
  {
 1280 
  }
1281 
    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
 1281 
  else
1282 
  }
 1282 
  {
1283 
  else
 1283 
    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
1284 
  {
 1284 
  }
1285 
    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
 1285 
  RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
1286 
  }
 1286 
  RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMULL);
1287 
  RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
 1287 
#if defined(RCC_CR_PLL2ON)
1288 
  RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMULL);
 1288 
  /* Get the PLL2 configuration -----------------------------------------------*/
1289 
#if defined(RCC_CR_PLL2ON)
 1289 
  if ((RCC->CR & RCC_CR_PLL2ON) == RCC_CR_PLL2ON)
1290 
  /* Get the PLL2 configuration -----------------------------------------------*/
 1290 
  {
1291 
  if ((RCC->CR & RCC_CR_PLL2ON) == RCC_CR_PLL2ON)
 1291 
    RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_ON;
1292 
  {
 1292 
  }
1293 
    RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_ON;
 1293 
  else
1294 
  }
 1294 
  {
1295 
  else
 1295 
    RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_OFF;
1296 
  {
 1296 
  }
1297 
    RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_OFF;
 1297 
  RCC_OscInitStruct->PLL2.HSEPrediv2Value = __HAL_RCC_HSE_GET_PREDIV2();
1298 
  }
 1298 
  RCC_OscInitStruct->PLL2.PLL2MUL = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PLL2MUL);
1299 
  RCC_OscInitStruct->PLL2.HSEPrediv2Value = __HAL_RCC_HSE_GET_PREDIV2();
 1299 
#endif /* RCC_CR_PLL2ON */
1300 
  RCC_OscInitStruct->PLL2.PLL2MUL = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PLL2MUL);
 1300 
}
1301 
#endif /* RCC_CR_PLL2ON */
 1301 
 
1302 
}
 1302 
/**
1303 
 
 1303 
  * @brief  Get the RCC_ClkInitStruct according to the internal
1304 
/**
 1304 
  * RCC configuration registers.
1305 
  * @brief  Get the RCC_ClkInitStruct according to the internal
 1305 
  * @param  RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
1306 
  * RCC configuration registers.
 1306 
  * contains the current clock configuration.
1307 
  * @param  RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
 1307 
  * @param  pFLatency Pointer on the Flash Latency.
1308 
  * contains the current clock configuration.
 1308 
  * @retval None
1309 
  * @param  pFLatency Pointer on the Flash Latency.
 1309 
  */
1310 
  * @retval None
 1310 
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
1311 
  */
 1311 
{
1312 
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
 1312 
  /* Check the parameters */
1313 
{
 1313 
  assert_param(RCC_ClkInitStruct != NULL);
1314 
  /* Check the parameters */
 1314 
  assert_param(pFLatency != NULL);
1315 
  assert_param(RCC_ClkInitStruct != NULL);
 1315 
 
1316 
  assert_param(pFLatency != NULL);
 1316 
  /* Set all possible values for the Clock type parameter --------------------*/
1317 
 
 1317 
  RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
1318 
  /* Set all possible values for the Clock type parameter --------------------*/
 1318 
 
1319 
  RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
 1319 
  /* Get the SYSCLK configuration --------------------------------------------*/
1320 
 
 1320 
  RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
1321 
  /* Get the SYSCLK configuration --------------------------------------------*/
 1321 
 
1322 
  RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
 1322 
  /* Get the HCLK configuration ----------------------------------------------*/
1323 
 
 1323 
  RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
1324 
  /* Get the HCLK configuration ----------------------------------------------*/
 1324 
 
1325 
  RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
 1325 
  /* Get the APB1 configuration ----------------------------------------------*/
1326 
 
 1326 
  RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
1327 
  /* Get the APB1 configuration ----------------------------------------------*/
 1327 
 
1328 
  RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
 1328 
  /* Get the APB2 configuration ----------------------------------------------*/
1329 
 
 1329 
  RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
1330 
  /* Get the APB2 configuration ----------------------------------------------*/
 1330 
 
1331 
  RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
 1331 
#if   defined(FLASH_ACR_LATENCY)
1332 
 
 1332 
  /* Get the Flash Wait State (Latency) configuration ------------------------*/
1333 
#if   defined(FLASH_ACR_LATENCY)
 1333 
  *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
1334 
  /* Get the Flash Wait State (Latency) configuration ------------------------*/
 1334 
#else
1335 
  *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
 1335 
  /* For VALUE lines devices, only LATENCY_0 can be set*/
1336 
#else
 1336 
  *pFLatency = (uint32_t)FLASH_LATENCY_0;
1337 
  /* For VALUE lines devices, only LATENCY_0 can be set*/
 1337 
#endif
1338 
  *pFLatency = (uint32_t)FLASH_LATENCY_0;
 1338 
}
1339 
#endif
 1339 
 
1340 
}
 1340 
/**
1341 
 
 1341 
  * @brief This function handles the RCC CSS interrupt request.
1342 
/**
 1342 
  * @note This API should be called under the NMI_Handler().
1343 
  * @brief This function handles the RCC CSS interrupt request.
 1343 
  * @retval None
1344 
  * @note This API should be called under the NMI_Handler().
 1344 
  */
1345 
  * @retval None
 1345 
void HAL_RCC_NMI_IRQHandler(void)
1346 
  */
 1346 
{
1347 
void HAL_RCC_NMI_IRQHandler(void)
 1347 
  /* Check RCC CSSF flag  */
1348 
{
 1348 
  if (__HAL_RCC_GET_IT(RCC_IT_CSS))
1349 
  /* Check RCC CSSF flag  */
 1349 
  {
1350 
  if (__HAL_RCC_GET_IT(RCC_IT_CSS))
 1350 
    /* RCC Clock Security System interrupt user callback */
1351 
  {
 1351 
    HAL_RCC_CSSCallback();
1352 
    /* RCC Clock Security System interrupt user callback */
 1352 
 
1353 
    HAL_RCC_CSSCallback();
 1353 
    /* Clear RCC CSS pending bit */
1354 
 
 1354 
    __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
1355 
    /* Clear RCC CSS pending bit */
 1355 
  }
1356 
    __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
 1356 
}
1357 
  }
 1357 
 
1358 
}
 1358 
/**
1359 
 
 1359 
  * @brief  This function provides delay (in milliseconds) based on CPU cycles method.
1360 
/**
 1360 
  * @param  mdelay: specifies the delay time length, in milliseconds.
1361 
  * @brief  This function provides delay (in milliseconds) based on CPU cycles method.
 1361 
  * @retval None
1362 
  * @param  mdelay: specifies the delay time length, in milliseconds.
 1362 
  */
1363 
  * @retval None
 1363 
static void RCC_Delay(uint32_t mdelay)
1364 
  */
 1364 
{
1365 
static void RCC_Delay(uint32_t mdelay)
 1365 
  __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
1366 
{
 1366 
  do
1367 
  __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
 1367 
  {
1368 
  do
 1368 
    __NOP();
1369 
  {
 1369 
  }
1370 
    __NOP();
 1370 
  while (Delay --);
1371 
  }
 1371 
}
1372 
  while (Delay --);
 1372 
 
1373 
}
 1373 
/**
1374 
 
 1374 
  * @brief  RCC Clock Security System interrupt callback
1375 
/**
 1375 
  * @retval none
1376 
  * @brief  RCC Clock Security System interrupt callback
 1376 
  */
1377 
  * @retval none
 1377 
__weak void HAL_RCC_CSSCallback(void)
1378 
  */
 1378 
{
1379 
__weak void HAL_RCC_CSSCallback(void)
 1379 
  /* NOTE : This function Should not be modified, when the callback is needed,
1380 
{
 1380 
    the HAL_RCC_CSSCallback could be implemented in the user file
1381 
  /* NOTE : This function Should not be modified, when the callback is needed,
 1381 
    */
1382 
    the HAL_RCC_CSSCallback could be implemented in the user file
 1382 
}
1383 
    */
 1383 
 
1384 
}
 1384 
/**
1385 
 
 1385 
  * @}
1386 
/**
 1386 
  */
1387 
  * @}
 1387 
 
1388 
  */
 1388 
/**
1389 
 
 1389 
  * @}
1390 
/**
 1390 
  */
1391 
  * @}
 1391 
 
1392 
  */
 1392 
#endif /* HAL_RCC_MODULE_ENABLED */
1393 
 
 1393 
/**
1394 
#endif /* HAL_RCC_MODULE_ENABLED */
 1394 
  * @}
1395 
/**
 1395 
  */
1396 
  * @}
 1396 
 
1397 
  */
 1397 
/**
1398 
 
 1398 
  * @}
1399 
/**
 1399 
  */
1400 
  * @}
 1400 
 
1401 
  */
 - 
 
1402 
 
 - 
 
1403 
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 -