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/**
 1 
/**
2 
  ******************************************************************************
 2 
  ******************************************************************************
3 
  * @file    stm32f1xx_hal_nand.c
 3 
  * @file    stm32f1xx_hal_nand.c
4 
  * @author  MCD Application Team
 4 
  * @author  MCD Application Team
5 
  * @brief   NAND HAL module driver.
 5 
  * @brief   NAND HAL module driver.
6 
  *          This file provides a generic firmware to drive NAND memories mounted
 6 
  *          This file provides a generic firmware to drive NAND memories mounted
7 
  *          as external device.
 7 
  *          as external device.
8 
  *        
 8 
  *
9 
  @verbatim
 9 
  @verbatim
10 
  ==============================================================================
 10 
  ==============================================================================
11 
                         ##### How to use this driver #####
 11 
                         ##### How to use this driver #####
12 
  ==============================================================================    
 12 
  ==============================================================================
13 
    [..]
 13 
    [..]
14 
      This driver is a generic layered driver which contains a set of APIs used to
 14 
      This driver is a generic layered driver which contains a set of APIs used to
15 
      control NAND flash memories. It uses the FSMC layer functions to interface
 15 
      control NAND flash memories. It uses the FSMC layer functions to interface
16 
      with NAND devices. This driver is used as follows:
 16 
      with NAND devices. This driver is used as follows:
17 
   
 17 
 
18 
      (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
 18 
      (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
19 
          with control and timing parameters for both common and attribute spaces.
 19 
          with control and timing parameters for both common and attribute spaces.
20 
           
 20 
 
21 
      (+) Read NAND flash memory maker and device IDs using the function
 21 
      (+) Read NAND flash memory maker and device IDs using the function
22 
          HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
 22 
          HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
23 
          structure declared by the function caller.
 23 
          structure declared by the function caller.
24 
       
 24 
 
25 
      (+) Access NAND flash memory by read/write operations using the functions
 25 
      (+) Access NAND flash memory by read/write operations using the functions
26 
          HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(),
 26 
          HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(),
27 
          HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(),
 27 
          HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(),
28 
          HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(),
 28 
          HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(),
29 
          HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b()
 29 
          HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b()
30 
          to read/write page(s)/spare area(s). These functions use specific device
 30 
          to read/write page(s)/spare area(s). These functions use specific device
31 
          information (Block, page size..) predefined by the user in the NAND_DeviceConfigTypeDef
 31 
          information (Block, page size..) predefined by the user in the NAND_DeviceConfigTypeDef
32 
          structure. The read/write address information is contained by the Nand_Address_Typedef
 32 
          structure. The read/write address information is contained by the Nand_Address_Typedef
33 
          structure passed as parameter.
 33 
          structure passed as parameter.
34 
       
 34 
 
35 
      (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
 35 
      (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
36 
       
 36 
 
37 
      (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
 37 
      (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
38 
          The erase block address information is contained in the Nand_Address_Typedef
 38 
          The erase block address information is contained in the Nand_Address_Typedef
39 
          structure passed as parameter.
 39 
          structure passed as parameter.
40 
   
 40 
 
41 
      (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
 41 
      (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
42 
       
 42 
 
43 
      (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
 43 
      (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
44 
          HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
 44 
          HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
45 
          feature or the function HAL_NAND_GetECC() to get the ECC correction code.
 45 
          feature or the function HAL_NAND_GetECC() to get the ECC correction code.
46 
       
 46 
 
47 
      (+) You can monitor the NAND device HAL state by calling the function
 47 
      (+) You can monitor the NAND device HAL state by calling the function
48 
          HAL_NAND_GetState()  
 48 
          HAL_NAND_GetState()
49 
 
 49 
 
50 
    [..]
 50 
    [..]
51 
      (@) This driver is a set of generic APIs which handle standard NAND flash operations.
 51 
      (@) This driver is a set of generic APIs which handle standard NAND flash operations.
52 
          If a NAND flash device contains different operations and/or implementations,
 52 
          If a NAND flash device contains different operations and/or implementations,
53 
          it should be implemented separately.
 53 
          it should be implemented separately.
54 
 
 54 
 
- 
 
 55 
    *** Callback registration ***
- 
 
 56 
    =============================================
- 
 
 57 
    [..]
- 
 
 58 
      The compilation define  USE_HAL_NAND_REGISTER_CALLBACKS when set to 1
- 
 
 59 
      allows the user to configure dynamically the driver callbacks.
- 
 
 60 
 
- 
 
 61 
      Use Functions @ref HAL_NAND_RegisterCallback() to register a user callback,
- 
 
 62 
      it allows to register following callbacks:
- 
 
 63 
        (+) MspInitCallback    : NAND MspInit.
- 
 
 64 
        (+) MspDeInitCallback  : NAND MspDeInit.
- 
 
 65 
      This function takes as parameters the HAL peripheral handle, the Callback ID
- 
 
 66 
      and a pointer to the user callback function.
- 
 
 67 
 
- 
 
 68 
      Use function @ref HAL_NAND_UnRegisterCallback() to reset a callback to the default
- 
 
 69 
      weak (surcharged) function. It allows to reset following callbacks:
- 
 
 70 
        (+) MspInitCallback    : NAND MspInit.
- 
 
 71 
        (+) MspDeInitCallback  : NAND MspDeInit.
- 
 
 72 
      This function) takes as parameters the HAL peripheral handle and the Callback ID.
- 
 
 73 
 
- 
 
 74 
      By default, after the @ref HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET
- 
 
 75 
      all callbacks are reset to the corresponding legacy weak (surcharged) functions.
- 
 
 76 
      Exception done for MspInit and MspDeInit callbacks that are respectively
- 
 
 77 
      reset to the legacy weak (surcharged) functions in the @ref HAL_NAND_Init
- 
 
 78 
      and @ref  HAL_NAND_DeInit only when these callbacks are null (not registered beforehand).
- 
 
 79 
      If not, MspInit or MspDeInit are not null, the @ref HAL_NAND_Init and @ref HAL_NAND_DeInit
- 
 
 80 
      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
- 
 
 81 
 
- 
 
 82 
      Callbacks can be registered/unregistered in READY state only.
- 
 
 83 
      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
- 
 
 84 
      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
- 
 
 85 
      during the Init/DeInit.
- 
 
 86 
      In that case first register the MspInit/MspDeInit user callbacks
- 
 
 87 
      using @ref HAL_NAND_RegisterCallback before calling @ref HAL_NAND_DeInit
- 
 
 88 
      or @ref HAL_NAND_Init function.
- 
 
 89 
 
- 
 
 90 
      When The compilation define USE_HAL_NAND_REGISTER_CALLBACKS is set to 0 or
- 
 
 91 
      not defined, the callback registering feature is not available
- 
 
 92 
      and weak (surcharged) callbacks are used.
- 
 
 93 
 
55 
  @endverbatim
 94 
  @endverbatim
56 
  ******************************************************************************
 95 
  ******************************************************************************
57 
  * @attention
 96 
  * @attention
58 
  *
 97 
  *
59 
  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
 98 
  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
60 
  *
 - 
 
61 
  * Redistribution and use in source and binary forms, with or without modification,
 - 
 
62 
  * are permitted provided that the following conditions are met:
 - 
 
63 
  *   1. Redistributions of source code must retain the above copyright notice,
 - 
 
64 
  *      this list of conditions and the following disclaimer.
 - 
 
65 
  *   2. Redistributions in binary form must reproduce the above copyright notice,
 - 
 
66 
  *      this list of conditions and the following disclaimer in the documentation
 - 
 
67 
  *      and/or other materials provided with the distribution.
 - 
 
68 
  *   3. Neither the name of STMicroelectronics nor the names of its contributors
 - 
 
69 
  *      may be used to endorse or promote products derived from this software
 - 
 
70 
  *      without specific prior written permission.
 99 
  * All rights reserved.</center></h2>
71 
  *
 100 
  *
72 
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 101 
  * This software component is licensed by ST under BSD 3-Clause license,
73 
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 - 
 
74 
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 - 
 
75 
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 - 
 
76 
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 - 
 
77 
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 102 
  * the "License"; You may not use this file except in compliance with the
78 
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 103 
  * License. You may obtain a copy of the License at:
79 
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 - 
 
80 
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 - 
 
81 
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 104 
  *                       opensource.org/licenses/BSD-3-Clause
82 
  *
 105 
  *
83 
  ******************************************************************************
 106 
  ******************************************************************************
84 
  */
 107 
  */
85 
 
 108 
 
86 
/* Includes ------------------------------------------------------------------*/
 109 
/* Includes ------------------------------------------------------------------*/
87 
#include "stm32f1xx_hal.h"
 110 
#include "stm32f1xx_hal.h"
88 
 
 111 
 
- 
 
 112 
#if defined(FSMC_BANK3)
- 
 
 113 
 
89 
/** @addtogroup STM32F1xx_HAL_Driver
 114 
/** @addtogroup STM32F1xx_HAL_Driver
90 
  * @{
 115 
  * @{
91 
  */
 116 
  */
92 
 
 117 
 
93 
#ifdef HAL_NAND_MODULE_ENABLED
 118 
#ifdef HAL_NAND_MODULE_ENABLED
94 
 
 119 
 
95 
#if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
 - 
 
96 
 
 - 
 
97 
/** @defgroup NAND NAND
 120 
/** @defgroup NAND NAND
98 
  * @brief NAND HAL module driver
 121 
  * @brief NAND HAL module driver
99 
  * @{
 122 
  * @{
100 
  */
 123 
  */
101 
 
 124 
 
102 
/* Private typedef -----------------------------------------------------------*/
 125 
/* Private typedef -----------------------------------------------------------*/
103 
/* Private define ------------------------------------------------------------*/
 126 
/* Private Constants ------------------------------------------------------------*/
104 
/** @defgroup NAND_Private_Constants NAND Private Constants
 - 
 
105 
  * @{
 - 
 
106 
  */
 - 
 
107 
 
 - 
 
108 
/**
 - 
 
109 
  * @}
 - 
 
110 
  */
 - 
 
111 
 
 - 
 
112 
/* Private macro -------------------------------------------------------------*/    
 127 
/* Private macro -------------------------------------------------------------*/
113 
/** @defgroup NAND_Private_Macros NAND Private Macros
 - 
 
114 
  * @{
 - 
 
115 
  */
 - 
 
116 
 
 - 
 
117 
/**
 - 
 
118 
  * @}
 - 
 
119 
  */
 - 
 
120 
 
 - 
 
121 
/* Private variables ---------------------------------------------------------*/
 128 
/* Private variables ---------------------------------------------------------*/
122 
/* Private function prototypes -----------------------------------------------*/
 129 
/* Private function prototypes -----------------------------------------------*/
123 
/* Exported functions --------------------------------------------------------*/
 130 
/* Exported functions ---------------------------------------------------------*/
- 
 
 131 
 
124 
/** @defgroup NAND_Exported_Functions NAND Exported Functions
 132 
/** @defgroup NAND_Exported_Functions NAND Exported Functions
125 
  * @{
 133 
  * @{
126 
  */
 134 
  */
127 
   
 135 
 
128 
/** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
 136 
/** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
129 
  * @brief    Initialization and Configuration functions
 137 
  * @brief    Initialization and Configuration functions
130 
  *
 138 
  *
131 
  @verbatim    
 139 
  @verbatim
132 
  ==============================================================================
 140 
  ==============================================================================
133 
            ##### NAND Initialization and de-initialization functions #####
 141 
            ##### NAND Initialization and de-initialization functions #####
134 
  ==============================================================================
 142 
  ==============================================================================
135 
  [..]  
 143 
  [..]
136 
    This section provides functions allowing to initialize/de-initialize
 144 
    This section provides functions allowing to initialize/de-initialize
137 
    the NAND memory
 145 
    the NAND memory
138 
 
 146 
 
139 
@endverbatim
 147 
@endverbatim
140 
  * @{
 148 
  * @{
141 
  */
 149 
  */
142 
   
 150 
 
143 
/**
 151 
/**
144 
  * @brief  Perform NAND memory Initialization sequence
 152 
  * @brief  Perform NAND memory Initialization sequence
145 
  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
 153 
  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
146 
  *                the configuration information for NAND module.
 154 
  *                the configuration information for NAND module.
147 
  * @param  ComSpace_Timing: pointer to Common space timing structure
 155 
  * @param  ComSpace_Timing pointer to Common space timing structure
148 
  * @param  AttSpace_Timing: pointer to Attribute space timing structure
 156 
  * @param  AttSpace_Timing pointer to Attribute space timing structure
149 
  * @retval HAL status
 157 
  * @retval HAL status
150 
  */
 158 
  */
151 
HAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
 159 
HAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing,
- 
 
 160 
                                 FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
152 
{
 161 
{
153 
  /* Check the NAND handle state */
 162 
  /* Check the NAND handle state */
154 
  if(hnand == NULL)
 163 
  if (hnand == NULL)
155 
  {
 164 
  {
156 
     return HAL_ERROR;
 165 
    return HAL_ERROR;
157 
  }
 166 
  }
158 
 
 167 
 
159 
  if(hnand->State == HAL_NAND_STATE_RESET)
 168 
  if (hnand->State == HAL_NAND_STATE_RESET)
160 
  {
 169 
  {
161 
    /* Allocate lock resource and initialize it */
 170 
    /* Allocate lock resource and initialize it */
162 
    hnand->Lock = HAL_UNLOCKED;
 171 
    hnand->Lock = HAL_UNLOCKED;
- 
 
 172 
 
- 
 
 173 
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
- 
 
 174 
    if (hnand->MspInitCallback == NULL)
- 
 
 175 
    {
- 
 
 176 
      hnand->MspInitCallback = HAL_NAND_MspInit;
- 
 
 177 
    }
- 
 
 178 
    hnand->ItCallback = HAL_NAND_ITCallback;
- 
 
 179 
 
- 
 
 180 
    /* Init the low level hardware */
- 
 
 181 
    hnand->MspInitCallback(hnand);
- 
 
 182 
#else
163 
    /* Initialize the low level hardware (MSP) */
 183 
    /* Initialize the low level hardware (MSP) */
164 
    HAL_NAND_MspInit(hnand);
 184 
    HAL_NAND_MspInit(hnand);
- 
 
 185 
#endif
165 
  }
 186 
  }
166 
 
 187 
 
167 
  /* Initialize NAND control Interface */
 188 
  /* Initialize NAND control Interface */
168 
  FSMC_NAND_Init(hnand->Instance, &(hnand->Init));
 189 
  (void)FSMC_NAND_Init(hnand->Instance, &(hnand->Init));
169 
 
 190 
 
170 
  /* Initialize NAND common space timing Interface */  
 191 
  /* Initialize NAND common space timing Interface */
171 
  FSMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
 192 
  (void)FSMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
172 
 
 193 
 
173 
  /* Initialize NAND attribute space timing Interface */  
 194 
  /* Initialize NAND attribute space timing Interface */
174 
  FSMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
 195 
  (void)FSMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
175 
 
 196 
 
176 
  /* Enable the NAND device */
 197 
  /* Enable the NAND device */
177 
  __FSMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
 198 
  __FSMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
178 
 
 199 
 
179 
  /* Update the NAND controller state */
 200 
  /* Update the NAND controller state */
180 
  hnand->State = HAL_NAND_STATE_READY;
 201 
  hnand->State = HAL_NAND_STATE_READY;
181 
 
 202 
 
182 
  return HAL_OK;
 203 
  return HAL_OK;
183 
}
 204 
}
184 
 
 205 
 
185 
/**
 206 
/**
186 
  * @brief  Perform NAND memory De-Initialization sequence
 207 
  * @brief  Perform NAND memory De-Initialization sequence
187 
  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
 208 
  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
188 
  *                the configuration information for NAND module.
 209 
  *                the configuration information for NAND module.
189 
  * @retval HAL status
 210 
  * @retval HAL status
190 
  */
 211 
  */
191 
HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)  
 212 
HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
192 
{
 213 
{
- 
 
 214 
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
- 
 
 215 
  if (hnand->MspDeInitCallback == NULL)
- 
 
 216 
  {
- 
 
 217 
    hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
- 
 
 218 
  }
- 
 
 219 
 
- 
 
 220 
  /* DeInit the low level hardware */
- 
 
 221 
  hnand->MspDeInitCallback(hnand);
- 
 
 222 
#else
193 
  /* Initialize the low level hardware (MSP) */
 223 
  /* Initialize the low level hardware (MSP) */
194 
  HAL_NAND_MspDeInit(hnand);
 224 
  HAL_NAND_MspDeInit(hnand);
- 
 
 225 
#endif
195 
 
 226 
 
196 
  /* Configure the NAND registers with their reset values */
 227 
  /* Configure the NAND registers with their reset values */
197 
  FSMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
 228 
  (void)FSMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
198 
 
 229 
 
199 
  /* Reset the NAND controller state */
 230 
  /* Reset the NAND controller state */
200 
  hnand->State = HAL_NAND_STATE_RESET;
 231 
  hnand->State = HAL_NAND_STATE_RESET;
201 
 
 232 
 
202 
  /* Release Lock */
 233 
  /* Release Lock */
Line 205... Line 236...
205 
  return HAL_OK;
 236 
  return HAL_OK;
206 
}
 237 
}
207 
 
 238 
 
208 
/**
 239 
/**
209 
  * @brief  NAND MSP Init
 240 
  * @brief  NAND MSP Init
210 
  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
 241 
  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
211 
  *                the configuration information for NAND module.
 242 
  *                the configuration information for NAND module.
212 
  * @retval None
 243 
  * @retval None
213 
  */
 244 
  */
214 
__weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
 245 
__weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
215 
{
 246 
{
216 
  /* Prevent unused argument(s) compilation warning */
 247 
  /* Prevent unused argument(s) compilation warning */
217 
  UNUSED(hnand);
 248 
  UNUSED(hnand);
- 
 
 249 
 
218 
  /* NOTE : This function Should not be modified, when the callback is needed,
 250 
  /* NOTE : This function Should not be modified, when the callback is needed,
219 
            the HAL_NAND_MspInit could be implemented in the user file
 251 
            the HAL_NAND_MspInit could be implemented in the user file
220 
   */
 252 
   */
221 
}
 253 
}
222 
 
 254 
 
223 
/**
 255 
/**
224 
  * @brief  NAND MSP DeInit
 256 
  * @brief  NAND MSP DeInit
225 
  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
 257 
  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
226 
  *                the configuration information for NAND module.
 258 
  *                the configuration information for NAND module.
227 
  * @retval None
 259 
  * @retval None
228 
  */
 260 
  */
229 
__weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
 261 
__weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
230 
{
 262 
{
231 
  /* Prevent unused argument(s) compilation warning */
 263 
  /* Prevent unused argument(s) compilation warning */
232 
  UNUSED(hnand);
 264 
  UNUSED(hnand);
- 
 
 265 
 
233 
  /* NOTE : This function Should not be modified, when the callback is needed,
 266 
  /* NOTE : This function Should not be modified, when the callback is needed,
234 
            the HAL_NAND_MspDeInit could be implemented in the user file
 267 
            the HAL_NAND_MspDeInit could be implemented in the user file
235 
   */
 268 
   */
236 
}
 269 
}
237 
 
 270 
 
238 
 
 271 
 
239 
/**
 272 
/**
240 
  * @brief  This function handles NAND device interrupt request.
 273 
  * @brief  This function handles NAND device interrupt request.
241 
  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
 274 
  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
242 
  *                the configuration information for NAND module.
 275 
  *                the configuration information for NAND module.
243 
  * @retval HAL status
 276 
  * @retval HAL status
244 
*/
 277 
  */
245 
void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
 278 
void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
246 
{
 279 
{
247 
  /* Check NAND interrupt Rising edge flag */
 280 
  /* Check NAND interrupt Rising edge flag */
248 
  if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_RISING_EDGE))
 281 
  if (__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_RISING_EDGE))
249 
  {
 282 
  {
250 
    /* NAND interrupt callback*/
 283 
    /* NAND interrupt callback*/
- 
 
 284 
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
- 
 
 285 
    hnand->ItCallback(hnand);
- 
 
 286 
#else
251 
    HAL_NAND_ITCallback(hnand);
 287 
    HAL_NAND_ITCallback(hnand);
- 
 
 288 
#endif
252 
 
 289 
 
253 
    /* Clear NAND interrupt Rising edge pending bit */
 290 
    /* Clear NAND interrupt Rising edge pending bit */
254 
    __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_RISING_EDGE);
 291 
    __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_RISING_EDGE);
255 
  }
 292 
  }
256 
 
 293 
 
257 
  /* Check NAND interrupt Level flag */
 294 
  /* Check NAND interrupt Level flag */
258 
  if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_LEVEL))
 295 
  if (__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_LEVEL))
259 
  {
 296 
  {
260 
    /* NAND interrupt callback*/
 297 
    /* NAND interrupt callback*/
- 
 
 298 
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
- 
 
 299 
    hnand->ItCallback(hnand);
- 
 
 300 
#else
261 
    HAL_NAND_ITCallback(hnand);
 301 
    HAL_NAND_ITCallback(hnand);
- 
 
 302 
#endif
262 
 
 303 
 
263 
    /* Clear NAND interrupt Level pending bit */
 304 
    /* Clear NAND interrupt Level pending bit */
264 
    __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_LEVEL);
 305 
    __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_LEVEL);
265 
  }
 306 
  }
266 
 
 307 
 
267 
  /* Check NAND interrupt Falling edge flag */
 308 
  /* Check NAND interrupt Falling edge flag */
268 
  if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FALLING_EDGE))
 309 
  if (__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FALLING_EDGE))
269 
  {
 310 
  {
270 
    /* NAND interrupt callback*/
 311 
    /* NAND interrupt callback*/
- 
 
 312 
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
- 
 
 313 
    hnand->ItCallback(hnand);
- 
 
 314 
#else
271 
    HAL_NAND_ITCallback(hnand);
 315 
    HAL_NAND_ITCallback(hnand);
- 
 
 316 
#endif
272 
 
 317 
 
273 
    /* Clear NAND interrupt Falling edge pending bit */
 318 
    /* Clear NAND interrupt Falling edge pending bit */
274 
    __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FALLING_EDGE);
 319 
    __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FALLING_EDGE);
275 
  }
 320 
  }
276 
 
 321 
 
277 
  /* Check NAND interrupt FIFO empty flag */
 322 
  /* Check NAND interrupt FIFO empty flag */
278 
  if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FEMPT))
 323 
  if (__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FEMPT))
279 
  {
 324 
  {
280 
    /* NAND interrupt callback*/
 325 
    /* NAND interrupt callback*/
- 
 
 326 
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
- 
 
 327 
    hnand->ItCallback(hnand);
- 
 
 328 
#else
281 
    HAL_NAND_ITCallback(hnand);
 329 
    HAL_NAND_ITCallback(hnand);
- 
 
 330 
#endif
282 
 
 331 
 
283 
    /* Clear NAND interrupt FIFO empty pending bit */
 332 
    /* Clear NAND interrupt FIFO empty pending bit */
284 
    __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FEMPT);
 333 
    __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FEMPT);
285 
  }
 334 
  }
- 
 
 335 
 
286 
}
 336 
}
287 
 
 337 
 
288 
/**
 338 
/**
289 
  * @brief  NAND interrupt feature callback
 339 
  * @brief  NAND interrupt feature callback
290 
  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
 340 
  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
291 
  *                the configuration information for NAND module.
 341 
  *                the configuration information for NAND module.
292 
  * @retval None
 342 
  * @retval None
293 
  */
 343 
  */
294 
__weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
 344 
__weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
295 
{
 345 
{
296 
  /* Prevent unused argument(s) compilation warning */
 346 
  /* Prevent unused argument(s) compilation warning */
297 
  UNUSED(hnand);
 347 
  UNUSED(hnand);
- 
 
 348 
 
298 
  /* NOTE : This function Should not be modified, when the callback is needed,
 349 
  /* NOTE : This function Should not be modified, when the callback is needed,
299 
            the HAL_NAND_ITCallback could be implemented in the user file
 350 
            the HAL_NAND_ITCallback could be implemented in the user file
300 
   */
 351 
   */
301 
}
 352 
}
302 
 
 353 
 
303 
/**
 354 
/**
304 
  * @}
 355 
  * @}
305 
  */
 356 
  */
306 
 
 357 
 
307 
/** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
 358 
/** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
308 
  * @brief    Input Output and memory control functions
 359 
  * @brief    Input Output and memory control functions
309 
  *
 360 
  *
310 
  @verbatim    
 361 
  @verbatim
311 
  ==============================================================================
 362 
  ==============================================================================
312 
                    ##### NAND Input and Output functions #####
 363 
                    ##### NAND Input and Output functions #####
313 
  ==============================================================================
 364 
  ==============================================================================
314 
  [..]  
 365 
  [..]
315 
    This section provides functions allowing to use and control the NAND
 366 
    This section provides functions allowing to use and control the NAND
316 
    memory
 367 
    memory
317 
 
 368 
 
318 
@endverbatim
 369 
@endverbatim
319 
  * @{
 370 
  * @{
320 
  */
 371 
  */
321 
 
 372 
 
322 
/**
 373 
/**
323 
  * @brief  Read the NAND memory electronic signature
 374 
  * @brief  Read the NAND memory electronic signature
324 
  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
 375 
  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
325 
  *                the configuration information for NAND module.
 376 
  *                the configuration information for NAND module.
326 
  * @param  pNAND_ID: NAND ID structure
 377 
  * @param  pNAND_ID NAND ID structure
327 
  * @retval HAL status
 378 
  * @retval HAL status
328 
  */
 379 
  */
329 
HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
 380 
HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
330 
{
 381 
{
331 
  __IO uint32_t data = 0U;
 382 
  __IO uint32_t data = 0;
332 
  __IO uint32_t data1 = 0U;
 383 
  __IO uint32_t data1 = 0;
333 
  uint32_t deviceaddress = 0U;
 384 
  uint32_t deviceaddress;
334 
 
 385 
 
335 
  /* Process Locked */
 - 
 
336 
  __HAL_LOCK(hnand);  
 - 
 
337 
 
 - 
 
338 
  /* Check the NAND controller state */
 386 
  /* Check the NAND controller state */
339 
  if(hnand->State == HAL_NAND_STATE_BUSY)
 387 
  if (hnand->State == HAL_NAND_STATE_BUSY)
340 
  {
 388 
  {
341 
     return HAL_BUSY;
 389 
    return HAL_BUSY;
342 
  }
 390 
  }
343 
 
 - 
 
344 
  /* Identify the device address */
 - 
 
345 
  if(hnand->Init.NandBank == FSMC_NAND_BANK2)
 391 
  else if (hnand->State == HAL_NAND_STATE_READY)
346 
  {
 392 
  {
- 
 
 393 
    /* Process Locked */
- 
 
 394 
    __HAL_LOCK(hnand);
- 
 
 395 
 
- 
 
 396 
    /* Update the NAND controller state */
- 
 
 397 
    hnand->State = HAL_NAND_STATE_BUSY;
- 
 
 398 
 
- 
 
 399 
    /* Identify the device address */
- 
 
 400 
    if (hnand->Init.NandBank == FSMC_NAND_BANK2)
- 
 
 401 
    {
347 
    deviceaddress = NAND_DEVICE1;
 402 
      deviceaddress = NAND_DEVICE1;
348 
  }
 403 
    }
349 
  else
 404 
    else
350 
  {
 405 
    {
351 
    deviceaddress = NAND_DEVICE2;
 406 
      deviceaddress = NAND_DEVICE2;
352 
  }
 407 
    }
353 
 
 - 
 
354 
  /* Update the NAND controller state */
 - 
 
355 
  hnand->State = HAL_NAND_STATE_BUSY;
 - 
 
356 
 
 408 
 
357 
  /* Send Read ID command sequence */  
 409 
    /* Send Read ID command sequence */
358 
  *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA))  = NAND_CMD_READID;
 410 
    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA))  = NAND_CMD_READID;
- 
 
 411 
    __DSB();
359 
  *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 412 
    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- 
 
 413 
    __DSB();
360 
 
 414 
 
361 
  /* Read the electronic signature from NAND flash */
 415 
    /* Read the electronic signature from NAND flash */
362 
  if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8)
 416 
    if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8)
363 
  {
 417 
    {
364 
    data = *(__IO uint32_t *)deviceaddress;
 418 
      data = *(__IO uint32_t *)deviceaddress;
365 
 
 419 
 
366 
    /* Return the data read */
 420 
      /* Return the data read */
367 
    pNAND_ID->Maker_Id   = ADDR_1ST_CYCLE(data);
 421 
      pNAND_ID->Maker_Id   = ADDR_1ST_CYCLE(data);
368 
    pNAND_ID->Device_Id  = ADDR_2ND_CYCLE(data);
 422 
      pNAND_ID->Device_Id  = ADDR_2ND_CYCLE(data);
369 
    pNAND_ID->Third_Id   = ADDR_3RD_CYCLE(data);
 423 
      pNAND_ID->Third_Id   = ADDR_3RD_CYCLE(data);
370 
    pNAND_ID->Fourth_Id  = ADDR_4TH_CYCLE(data);
 424 
      pNAND_ID->Fourth_Id  = ADDR_4TH_CYCLE(data);
- 
 
 425 
    }
- 
 
 426 
    else
- 
 
 427 
    {
- 
 
 428 
      data = *(__IO uint32_t *)deviceaddress;
- 
 
 429 
      data1 = *((__IO uint32_t *)deviceaddress + 4);
- 
 
 430 
 
- 
 
 431 
      /* Return the data read */
- 
 
 432 
      pNAND_ID->Maker_Id   = ADDR_1ST_CYCLE(data);
- 
 
 433 
      pNAND_ID->Device_Id  = ADDR_3RD_CYCLE(data);
- 
 
 434 
      pNAND_ID->Third_Id   = ADDR_1ST_CYCLE(data1);
- 
 
 435 
      pNAND_ID->Fourth_Id  = ADDR_3RD_CYCLE(data1);
- 
 
 436 
    }
- 
 
 437 
 
- 
 
 438 
    /* Update the NAND controller state */
- 
 
 439 
    hnand->State = HAL_NAND_STATE_READY;
- 
 
 440 
 
- 
 
 441 
    /* Process unlocked */
- 
 
 442 
    __HAL_UNLOCK(hnand);
371 
  }
 443 
  }
372 
  else
 444 
  else
373 
  {
 445 
  {
374 
    data = *(__IO uint32_t *)deviceaddress;
 - 
 
375 
    data1 = *((__IO uint32_t *)deviceaddress + 4U);
 - 
 
376 
   
 - 
 
377 
    /* Return the data read */
 446 
    return HAL_ERROR;
378 
    pNAND_ID->Maker_Id   = ADDR_1ST_CYCLE(data);
 - 
 
379 
    pNAND_ID->Device_Id  = ADDR_3RD_CYCLE(data);
 - 
 
380 
    pNAND_ID->Third_Id   = ADDR_1ST_CYCLE(data1);
 - 
 
381 
    pNAND_ID->Fourth_Id  = ADDR_3RD_CYCLE(data1);
 - 
 
382 
  }
 447 
  }
383 
 
 - 
 
384 
  /* Update the NAND controller state */
 - 
 
385 
  hnand->State = HAL_NAND_STATE_READY;
 - 
 
386 
 
 448 
 
387 
  /* Process unlocked */
 - 
 
388 
  __HAL_UNLOCK(hnand);
 - 
 
389 
   
 - 
 
390 
  return HAL_OK;
 449 
  return HAL_OK;
391 
}
 450 
}
392 
 
 451 
 
393 
/**
 452 
/**
394 
  * @brief  NAND memory reset
 453 
  * @brief  NAND memory reset
395 
  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
 454 
  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
396 
  *                the configuration information for NAND module.
 455 
  *                the configuration information for NAND module.
397 
  * @retval HAL status
 456 
  * @retval HAL status
398 
  */
 457 
  */
399 
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
 458 
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
400 
{
 459 
{
401 
  uint32_t deviceaddress = 0U;
 460 
  uint32_t deviceaddress;
402 
 
 - 
 
403 
  /* Process Locked */
 - 
 
404 
  __HAL_LOCK(hnand);
 - 
 
405 
 
 461 
 
406 
  /* Check the NAND controller state */
 462 
  /* Check the NAND controller state */
407 
  if(hnand->State == HAL_NAND_STATE_BUSY)
 463 
  if (hnand->State == HAL_NAND_STATE_BUSY)
408 
  {
 464 
  {
409 
     return HAL_BUSY;
 465 
    return HAL_BUSY;
410 
  }
 466 
  }
411 
 
 - 
 
412 
  /* Identify the device address */
 - 
 
413 
  if(hnand->Init.NandBank == FSMC_NAND_BANK2)
 467 
  else if (hnand->State == HAL_NAND_STATE_READY)
414 
  {
 468 
  {
- 
 
 469 
    /* Process Locked */
- 
 
 470 
    __HAL_LOCK(hnand);
- 
 
 471 
 
- 
 
 472 
    /* Update the NAND controller state */
- 
 
 473 
    hnand->State = HAL_NAND_STATE_BUSY;
- 
 
 474 
 
- 
 
 475 
    /* Identify the device address */
- 
 
 476 
    if (hnand->Init.NandBank == FSMC_NAND_BANK2)
- 
 
 477 
    {
415 
    deviceaddress = NAND_DEVICE1;
 478 
      deviceaddress = NAND_DEVICE1;
- 
 
 479 
    }
- 
 
 480 
    else
- 
 
 481 
    {
- 
 
 482 
      deviceaddress = NAND_DEVICE2;
- 
 
 483 
    }
- 
 
 484 
 
- 
 
 485 
    /* Send NAND reset command */
- 
 
 486 
    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF;
- 
 
 487 
 
- 
 
 488 
    /* Update the NAND controller state */
- 
 
 489 
    hnand->State = HAL_NAND_STATE_READY;
- 
 
 490 
 
- 
 
 491 
    /* Process unlocked */
- 
 
 492 
    __HAL_UNLOCK(hnand);
416 
  }
 493 
  }
417 
  else
 494 
  else
418 
  {
 495 
  {
419 
    deviceaddress = NAND_DEVICE2;
 496 
    return HAL_ERROR;
420 
  }  
 - 
 
421 
 
 - 
 
422 
  /* Update the NAND controller state */
 - 
 
423 
  hnand->State = HAL_NAND_STATE_BUSY;
 - 
 
424 
 
 - 
 
425 
  /* Send NAND reset command */  
 - 
 
426 
  *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF;
 - 
 
427 
 
 - 
 
428 
 
 - 
 
429 
  /* Update the NAND controller state */
 - 
 
430 
  hnand->State = HAL_NAND_STATE_READY;
 - 
 
431 
 
 497 
  }
432 
  /* Process unlocked */
 - 
 
433 
  __HAL_UNLOCK(hnand);
 - 
 
434 
 
 498 
 
435 
  return HAL_OK;
 499 
  return HAL_OK;
436 
 
 500 
 
437 
}
 501 
}
438 
 
 502 
 
439 
/**
 503 
/**
440 
  * @brief  Configure the device: Enter the physical parameters of the device
 504 
  * @brief  Configure the device: Enter the physical parameters of the device
441 
  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
 505 
  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
442 
  *                the configuration information for NAND module.
 506 
  *                the configuration information for NAND module.
443 
  * @param  pDeviceConfig : pointer to NAND_DeviceConfigTypeDef structure
 507 
  * @param  pDeviceConfig  pointer to NAND_DeviceConfigTypeDef structure
444 
  * @retval HAL status
 508 
  * @retval HAL status
445 
  */
 509 
  */
446 
HAL_StatusTypeDef  HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig)
 510 
HAL_StatusTypeDef  HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig)
447 
{
 511 
{
448 
  hnand->Config.PageSize           = pDeviceConfig->PageSize;
 512 
  hnand->Config.PageSize           = pDeviceConfig->PageSize;
Line 450... Line 514...
450 
  hnand->Config.BlockSize          = pDeviceConfig->BlockSize;
 514 
  hnand->Config.BlockSize          = pDeviceConfig->BlockSize;
451 
  hnand->Config.BlockNbr           = pDeviceConfig->BlockNbr;
 515 
  hnand->Config.BlockNbr           = pDeviceConfig->BlockNbr;
452 
  hnand->Config.PlaneSize          = pDeviceConfig->PlaneSize;
 516 
  hnand->Config.PlaneSize          = pDeviceConfig->PlaneSize;
453 
  hnand->Config.PlaneNbr           = pDeviceConfig->PlaneNbr;
 517 
  hnand->Config.PlaneNbr           = pDeviceConfig->PlaneNbr;
454 
  hnand->Config.ExtraCommandEnable = pDeviceConfig->ExtraCommandEnable;
 518 
  hnand->Config.ExtraCommandEnable = pDeviceConfig->ExtraCommandEnable;
455 
 
 519 
 
456 
  return HAL_OK;
 520 
  return HAL_OK;
457 
}
 521 
}
458 
 
 522 
 
459 
/**
 523 
/**
460 
  * @brief  Read Page(s) from NAND memory block (8-bits addressing)
 524 
  * @brief  Read Page(s) from NAND memory block (8-bits addressing)
461 
  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
 525 
  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
462 
  *                the configuration information for NAND module.
 526 
  *                the configuration information for NAND module.
463 
  * @param  pAddress : pointer to NAND address structure
 527 
  * @param  pAddress  pointer to NAND address structure
464 
  * @param  pBuffer : pointer to destination read buffer
 528 
  * @param  pBuffer  pointer to destination read buffer
465 
  * @param  NumPageToRead : number of pages to read from block
 529 
  * @param  NumPageToRead  number of pages to read from block
466 
  * @retval HAL status
 530 
  * @retval HAL status
467 
  */
 531 
  */
468 
HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
 532 
HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
- 
 
 533 
                                        uint32_t NumPageToRead)
469 
{  
 534 
{
470 
  __IO uint32_t index  = 0U;
 535 
  uint32_t index;
471 
  uint32_t tickstart = 0U;
 536 
  uint32_t tickstart;
- 
 
 537 
  uint32_t deviceaddress;
472 
  uint32_t deviceaddress = 0U, size = 0U, numPagesRead = 0U, nandaddress = 0U;
 538 
  uint32_t numpagesread = 0U;
473 
 
 539 
  uint32_t nandaddress;
474 
  /* Process Locked */
 540 
  uint32_t nbpages = NumPageToRead;
475 
  __HAL_LOCK(hnand);
 541 
  uint8_t *buff = pBuffer;
476 
 
 542 
 
477 
  /* Check the NAND controller state */
 543 
  /* Check the NAND controller state */
478 
  if(hnand->State == HAL_NAND_STATE_BUSY)
 544 
  if (hnand->State == HAL_NAND_STATE_BUSY)
479 
  {
 545 
  {
480 
     return HAL_BUSY;
 546 
    return HAL_BUSY;
481 
  }
 547 
  }
482 
 
 - 
 
483 
  /* Identify the device address */
 - 
 
484 
  if(hnand->Init.NandBank == FSMC_NAND_BANK2)
 548 
  else if (hnand->State == HAL_NAND_STATE_READY)
485 
  {
 - 
 
486 
    deviceaddress = NAND_DEVICE1;
 - 
 
487 
  }
 - 
 
488 
  else
 - 
 
489 
  {
 549 
  {
490 
    deviceaddress = NAND_DEVICE2;
 550 
    /* Process Locked */
491 
  }
 551 
    __HAL_LOCK(hnand);
492 
 
 552 
 
493 
  /* Update the NAND controller state */
 553 
    /* Update the NAND controller state */
494 
  hnand->State = HAL_NAND_STATE_BUSY;
 554 
    hnand->State = HAL_NAND_STATE_BUSY;
495 
 
 - 
 
496 
  /* NAND raw address calculation */
 - 
 
497 
  nandaddress = ARRAY_ADDRESS(pAddress, hnand);
 - 
 
498 
 
 555 
 
499 
  /* Page(s) read loop */  
 - 
 
500 
  while((NumPageToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
 - 
 
501 
  {
 - 
 
502 
    /* update the buffer size */
 556 
    /* Identify the device address */
503 
    size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead);
 - 
 
504 
   
 - 
 
505 
    /* Send read page command sequence */
 - 
 
506 
    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
 - 
 
507 
   
 - 
 
508 
    /* Cards with page size <= 512 bytes */
 - 
 
509 
    if((hnand->Config.PageSize) <= 512U)
 557 
    if (hnand->Init.NandBank == FSMC_NAND_BANK2)
510 
    {
 558 
    {
511 
      if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
 559 
      deviceaddress = NAND_DEVICE1;
512 
      {
 560 
    }
513 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 - 
 
514 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 - 
 
515 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 - 
 
516 
      }
 561 
    else
517 
      else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
 - 
 
518 
      {
 562 
    {
519 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 563 
      deviceaddress = NAND_DEVICE2;
520 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 - 
 
521 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 - 
 
522 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
 - 
 
523 
      }
 - 
 
524 
    }
 564 
    }
- 
 
 565 
 
525 
    else /* (hnand->Config.PageSize) > 512 */
 566 
    /* NAND raw address calculation */
- 
 
 567 
    nandaddress = ARRAY_ADDRESS(pAddress, hnand);
- 
 
 568 
 
- 
 
 569 
    /* Page(s) read loop */
- 
 
 570 
    while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
526 
    {
 571 
    {
- 
 
 572 
      /* Send read page command sequence */
- 
 
 573 
      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
- 
 
 574 
      __DSB();
- 
 
 575 
 
- 
 
 576 
      /* Cards with page size <= 512 bytes */
527 
      if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
 577 
      if ((hnand->Config.PageSize) <= 512U)
528 
      {
 578 
      {
- 
 
 579 
        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
- 
 
 580 
        {
529 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 581 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
- 
 
 582 
          __DSB();
- 
 
 583 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- 
 
 584 
          __DSB();
- 
 
 585 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- 
 
 586 
          __DSB();
- 
 
 587 
        }
- 
 
 588 
        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- 
 
 589 
        {
530 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 590 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
- 
 
 591 
          __DSB();
531 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 592 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- 
 
 593 
          __DSB();
532 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 594 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- 
 
 595 
          __DSB();
- 
 
 596 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- 
 
 597 
          __DSB();
- 
 
 598 
        }
533 
      }
 599 
      }
534 
      else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
 600 
      else /* (hnand->Config.PageSize) > 512 */
535 
      {
 601 
      {
- 
 
 602 
        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
- 
 
 603 
        {
536 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 604 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
- 
 
 605 
          __DSB();
- 
 
 606 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
- 
 
 607 
          __DSB();
- 
 
 608 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- 
 
 609 
          __DSB();
- 
 
 610 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- 
 
 611 
          __DSB();
- 
 
 612 
        }
- 
 
 613 
        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- 
 
 614 
        {
- 
 
 615 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
- 
 
 616 
          __DSB();
537 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 617 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
- 
 
 618 
          __DSB();
538 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 619 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- 
 
 620 
          __DSB();
539 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 621 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- 
 
 622 
          __DSB();
540 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
 623 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- 
 
 624 
          __DSB();
- 
 
 625 
        }
541 
      }
 626 
      }
542 
    }
 - 
 
543 
 
 627 
 
544 
    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA))  = NAND_CMD_AREA_TRUE1;
 628 
      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA))  = NAND_CMD_AREA_TRUE1;
545 
   
 629 
      __DSB();
546 
    /* Check if an extra command is needed for reading pages  */
 - 
 
547 
    if(hnand->Config.ExtraCommandEnable == ENABLE)
 - 
 
548 
    {
 630 
 
549 
      /* Get tick */
 - 
 
550 
      tickstart = HAL_GetTick();
 - 
 
551 
     
 631 
 
552 
      /* Read status until NAND is ready */
 - 
 
553 
      while(HAL_NAND_Read_Status(hnand) != NAND_READY)
 632 
      if (hnand->Config.ExtraCommandEnable == ENABLE)
554 
      {
 633 
      {
- 
 
 634 
        /* Get tick */
- 
 
 635 
        tickstart = HAL_GetTick();
- 
 
 636 
 
- 
 
 637 
        /* Read status until NAND is ready */
555 
        if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
 638 
        while (HAL_NAND_Read_Status(hnand) != NAND_READY)
556 
        {
 639 
        {
- 
 
 640 
          if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
- 
 
 641 
          {
- 
 
 642 
            /* Update the NAND controller state */
- 
 
 643 
            hnand->State = HAL_NAND_STATE_ERROR;
- 
 
 644 
 
- 
 
 645 
            /* Process unlocked */
- 
 
 646 
            __HAL_UNLOCK(hnand);
- 
 
 647 
 
557 
          return HAL_TIMEOUT;
 648 
            return HAL_TIMEOUT;
- 
 
 649 
          }
558 
        }
 650 
        }
- 
 
 651 
 
- 
 
 652 
        /* Go back to read mode */
- 
 
 653 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
- 
 
 654 
        __DSB();
559 
      }
 655 
      }
560 
     
 656 
 
561 
      /* Go back to read mode */
 657 
      /* Get Data into Buffer */
562 
      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
 658 
      for (index = 0U; index < hnand->Config.PageSize; index++)
563 
    }
 659 
      {
- 
 
 660 
        *buff = *(uint8_t *)deviceaddress;
- 
 
 661 
        buff++;
564 
   
 662 
      }
- 
 
 663 
 
565 
    /* Get Data into Buffer */    
 664 
      /* Increment read pages number */
- 
 
 665 
      numpagesread++;
- 
 
 666 
 
566 
    for(; index < size; index++)
 667 
      /* Decrement pages to read */
567 
    {
 668 
      nbpages--;
- 
 
 669 
 
- 
 
 670 
      /* Increment the NAND address */
568 
      *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
 671 
      nandaddress = (uint32_t)(nandaddress + 1U);
569 
    }
 672 
    }
570 
   
 673 
 
571 
    /* Increment read pages number */
 674 
    /* Update the NAND controller state */
572 
    numPagesRead++;
 675 
    hnand->State = HAL_NAND_STATE_READY;
573 
   
 676 
 
574 
    /* Decrement pages to read */
 677 
    /* Process unlocked */
575 
    NumPageToRead--;
 678 
    __HAL_UNLOCK(hnand);
576 
   
 679 
  }
577 
    /* Increment the NAND address */
 680 
  else
- 
 
 681 
  {
578 
    nandaddress = (uint32_t)(nandaddress + 1U);
 682 
    return HAL_ERROR;
579 
  }
 683 
  }
580 
 
 - 
 
581 
  /* Update the NAND controller state */
 - 
 
582 
  hnand->State = HAL_NAND_STATE_READY;
 - 
 
583 
 
 - 
 
584 
  /* Process unlocked */
 - 
 
585 
  __HAL_UNLOCK(hnand);
 - 
 
586 
 
 684 
 
587 
  return HAL_OK;
 685 
  return HAL_OK;
588 
}
 686 
}
589 
 
 687 
 
590 
/**
 688 
/**
591 
  * @brief  Read Page(s) from NAND memory block (16-bits addressing)
 689 
  * @brief  Read Page(s) from NAND memory block (16-bits addressing)
592 
  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
 690 
  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
593 
  *                the configuration information for NAND module.
 691 
  *                the configuration information for NAND module.
594 
  * @param  pAddress : pointer to NAND address structure
 692 
  * @param  pAddress  pointer to NAND address structure
595 
  * @param  pBuffer : pointer to destination read buffer. pBuffer should be 16bits aligned
 693 
  * @param  pBuffer  pointer to destination read buffer. pBuffer should be 16bits aligned
596 
  * @param  NumPageToRead : number of pages to read from block
 694 
  * @param  NumPageToRead  number of pages to read from block
597 
  * @retval HAL status
 695 
  * @retval HAL status
598 
  */
 696 
  */
599 
HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead)
 697 
HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
- 
 
 698 
                                         uint32_t NumPageToRead)
600 
{  
 699 
{
601 
  __IO uint32_t index  = 0U;
 700 
  uint32_t index;
602 
  uint32_t tickstart = 0U;
 701 
  uint32_t tickstart;
603 
  uint32_t deviceaddress = 0U, size = 0U, numPagesRead = 0U, nandaddress = 0U;
 702 
  uint32_t deviceaddress;
604 
 
 - 
 
605 
  /* Process Locked */
 703 
  uint32_t numpagesread = 0;
606 
  __HAL_LOCK(hnand);
 704 
  uint32_t nandaddress;
- 
 
 705 
  uint32_t nbpages = NumPageToRead;
- 
 
 706 
  uint16_t *buff = pBuffer;
607 
 
 707 
 
608 
  /* Check the NAND controller state */
 708 
  /* Check the NAND controller state */
609 
  if(hnand->State == HAL_NAND_STATE_BUSY)
 709 
  if (hnand->State == HAL_NAND_STATE_BUSY)
610 
  {
 710 
  {
611 
     return HAL_BUSY;
 711 
    return HAL_BUSY;
612 
  }
 712 
  }
613 
 
 - 
 
614 
  /* Identify the device address */
 - 
 
615 
  if(hnand->Init.NandBank == FSMC_NAND_BANK2)
 713 
  else if (hnand->State == HAL_NAND_STATE_READY)
616 
  {
 714 
  {
617 
    deviceaddress = NAND_DEVICE1;
 715 
    /* Process Locked */
618 
  }
 - 
 
619 
  else
 716 
    __HAL_LOCK(hnand);
620 
  {
 717 
 
- 
 
 718 
    /* Update the NAND controller state */
621 
    deviceaddress = NAND_DEVICE2;
 719 
    hnand->State = HAL_NAND_STATE_BUSY;
622 
  }
 - 
 
623 
 
 720 
 
624 
  /* Update the NAND controller state */
 - 
 
625 
  hnand->State = HAL_NAND_STATE_BUSY;
 - 
 
626 
 
 - 
 
627 
  /* NAND raw address calculation */
 - 
 
628 
  nandaddress = ARRAY_ADDRESS(pAddress, hnand);
 - 
 
629 
 
 - 
 
630 
  /* Page(s) read loop */  
 - 
 
631 
  while((NumPageToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
 - 
 
632 
  {
 - 
 
633 
    /* update the buffer size */
 721 
    /* Identify the device address */
634 
    size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead);
 - 
 
635 
   
 - 
 
636 
    /* Send read page command sequence */
 - 
 
637 
    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;  
 - 
 
638 
   
 - 
 
639 
    /* Cards with page size <= 512 bytes */
 - 
 
640 
    if((hnand->Config.PageSize) <= 512U)
 - 
 
641 
    {
 - 
 
642 
      if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
 - 
 
643 
      {
 - 
 
644 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 - 
 
645 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 - 
 
646 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 - 
 
647 
      }
 - 
 
648 
      else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
 - 
 
649 
      {
 - 
 
650 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 - 
 
651 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 - 
 
652 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 - 
 
653 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
 - 
 
654 
      }
 - 
 
655 
    }
 - 
 
656 
    else /* (hnand->Config.PageSize) > 512 */
 - 
 
657 
    {
 - 
 
658 
      if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
 - 
 
659 
      {
 - 
 
660 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 - 
 
661 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 - 
 
662 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 - 
 
663 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 - 
 
664 
      }
 - 
 
665 
      else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
 - 
 
666 
      {
 - 
 
667 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 - 
 
668 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 - 
 
669 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 - 
 
670 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 - 
 
671 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
 - 
 
672 
      }
 - 
 
673 
    }
 - 
 
674 
 
 - 
 
675 
    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA))  = NAND_CMD_AREA_TRUE1;
 - 
 
676 
   
 - 
 
677 
    if(hnand->Config.ExtraCommandEnable == ENABLE)
 722 
    if (hnand->Init.NandBank == FSMC_NAND_BANK2)
678 
    {
 723 
    {
679 
      /* Get tick */
 724 
      deviceaddress = NAND_DEVICE1;
- 
 
 725 
    }
- 
 
 726 
    else
- 
 
 727 
    {
680 
      tickstart = HAL_GetTick();
 728 
      deviceaddress = NAND_DEVICE2;
681 
     
 729 
    }
- 
 
 730 
 
- 
 
 731 
    /* NAND raw address calculation */
- 
 
 732 
    nandaddress = ARRAY_ADDRESS(pAddress, hnand);
- 
 
 733 
 
- 
 
 734 
    /* Page(s) read loop */
- 
 
 735 
    while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
- 
 
 736 
    {
682 
      /* Read status until NAND is ready */
 737 
      /* Send read page command sequence */
- 
 
 738 
      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
- 
 
 739 
      __DSB();
- 
 
 740 
 
- 
 
 741 
      /* Cards with page size <= 512 bytes */
683 
      while(HAL_NAND_Read_Status(hnand) != NAND_READY)
 742 
      if ((hnand->Config.PageSize) <= 512U)
684 
      {
 743 
      {
- 
 
 744 
        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
- 
 
 745 
        {
685 
        if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
 746 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
- 
 
 747 
          __DSB();
- 
 
 748 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- 
 
 749 
          __DSB();
- 
 
 750 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- 
 
 751 
          __DSB();
- 
 
 752 
        }
- 
 
 753 
        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
686 
        {
 754 
        {
- 
 
 755 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
- 
 
 756 
          __DSB();
- 
 
 757 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
687 
          return HAL_TIMEOUT;
 758 
          __DSB();
- 
 
 759 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- 
 
 760 
          __DSB();
- 
 
 761 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- 
 
 762 
          __DSB();
688 
        }
 763 
        }
689 
      }
 764 
      }
- 
 
 765 
      else /* (hnand->Config.PageSize) > 512 */
690 
     
 766 
      {
- 
 
 767 
        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
- 
 
 768 
        {
- 
 
 769 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
- 
 
 770 
          __DSB();
- 
 
 771 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
- 
 
 772 
          __DSB();
- 
 
 773 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- 
 
 774 
          __DSB();
- 
 
 775 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- 
 
 776 
          __DSB();
- 
 
 777 
        }
- 
 
 778 
        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- 
 
 779 
        {
- 
 
 780 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
- 
 
 781 
          __DSB();
- 
 
 782 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
- 
 
 783 
          __DSB();
- 
 
 784 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- 
 
 785 
          __DSB();
- 
 
 786 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- 
 
 787 
          __DSB();
- 
 
 788 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- 
 
 789 
          __DSB();
- 
 
 790 
        }
- 
 
 791 
      }
- 
 
 792 
 
- 
 
 793 
      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA))  = NAND_CMD_AREA_TRUE1;
- 
 
 794 
      __DSB();
- 
 
 795 
 
- 
 
 796 
      if (hnand->Config.ExtraCommandEnable == ENABLE)
- 
 
 797 
      {
- 
 
 798 
        /* Get tick */
- 
 
 799 
        tickstart = HAL_GetTick();
- 
 
 800 
 
- 
 
 801 
        /* Read status until NAND is ready */
- 
 
 802 
        while (HAL_NAND_Read_Status(hnand) != NAND_READY)
- 
 
 803 
        {
- 
 
 804 
          if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
- 
 
 805 
          {
- 
 
 806 
            /* Update the NAND controller state */
- 
 
 807 
            hnand->State = HAL_NAND_STATE_ERROR;
- 
 
 808 
 
- 
 
 809 
            /* Process unlocked */
- 
 
 810 
            __HAL_UNLOCK(hnand);
- 
 
 811 
 
- 
 
 812 
            return HAL_TIMEOUT;
- 
 
 813 
          }
- 
 
 814 
        }
- 
 
 815 
 
691 
      /* Go back to read mode */
 816 
        /* Go back to read mode */
692 
      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
 817 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
- 
 
 818 
        __DSB();
693 
    }
 819 
      }
694 
   
 820 
 
695 
    /* Get Data into Buffer */    
 821 
      /* Get Data into Buffer */
696 
    for(; index < size; index++)
 822 
      for (index = 0U; index < hnand->Config.PageSize; index++)
697 
    {
 823 
      {
698 
      *(uint16_t *)pBuffer++ = *(uint16_t *)deviceaddress;
 824 
        *buff = *(uint16_t *)deviceaddress;
- 
 
 825 
        buff++;
- 
 
 826 
      }
- 
 
 827 
 
- 
 
 828 
      /* Increment read pages number */
- 
 
 829 
      numpagesread++;
- 
 
 830 
 
- 
 
 831 
      /* Decrement pages to read */
- 
 
 832 
      nbpages--;
- 
 
 833 
 
- 
 
 834 
      /* Increment the NAND address */
- 
 
 835 
      nandaddress = (uint32_t)(nandaddress + 1U);
699 
    }
 836 
    }
700 
   
 837 
 
701 
    /* Increment read pages number */
 838 
    /* Update the NAND controller state */
702 
    numPagesRead++;
 839 
    hnand->State = HAL_NAND_STATE_READY;
703 
   
 840 
 
704 
    /* Decrement pages to read */
 841 
    /* Process unlocked */
705 
    NumPageToRead--;
 842 
    __HAL_UNLOCK(hnand);
706 
   
 - 
 
707 
    /* Increment the NAND address */
 - 
 
708 
    nandaddress = (uint32_t)(nandaddress + 1U);
 - 
 
709 
  }
 843 
  }
710 
 
 844 
  else
711 
  /* Update the NAND controller state */
 - 
 
712 
  hnand->State = HAL_NAND_STATE_READY;
 - 
 
713 
 
 845 
  {
714 
  /* Process unlocked */
 846 
    return HAL_ERROR;
715 
  __HAL_UNLOCK(hnand);  
 - 
 
716 
   
 847 
  }
- 
 
 848 
 
717 
  return HAL_OK;
 849 
  return HAL_OK;
718 
}
 850 
}
719 
 
 851 
 
720 
/**
 852 
/**
721 
  * @brief  Write Page(s) to NAND memory block (8-bits addressing)
 853 
  * @brief  Write Page(s) to NAND memory block (8-bits addressing)
722 
  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
 854 
  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
723 
  *                the configuration information for NAND module.
 855 
  *                the configuration information for NAND module.
724 
  * @param  pAddress : pointer to NAND address structure
 856 
  * @param  pAddress  pointer to NAND address structure
725 
  * @param  pBuffer : pointer to source buffer to write  
 857 
  * @param  pBuffer  pointer to source buffer to write
726 
  * @param  NumPageToWrite  : number of pages to write to block
 858 
  * @param  NumPageToWrite   number of pages to write to block
727 
  * @retval HAL status
 859 
  * @retval HAL status
728 
  */
 860 
  */
729 
HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
 861 
HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
- 
 
 862 
                                         uint32_t NumPageToWrite)
730 
{
 863 
{
731 
  __IO uint32_t index = 0U;
 864 
  uint32_t index;
732 
  uint32_t tickstart = 0U;
 865 
  uint32_t tickstart;
- 
 
 866 
  uint32_t deviceaddress;
733 
  uint32_t deviceaddress = 0U, size = 0U, numPagesWritten = 0U, nandaddress = 0U;
 867 
  uint32_t numpageswritten = 0;
734 
 
 868 
  uint32_t nandaddress;
735 
  /* Process Locked */
 869 
  uint32_t nbpages = NumPageToWrite;
736 
  __HAL_LOCK(hnand);  
 870 
  uint8_t *buff = pBuffer;
737 
 
 871 
 
738 
  /* Check the NAND controller state */
 872 
  /* Check the NAND controller state */
739 
  if(hnand->State == HAL_NAND_STATE_BUSY)
 873 
  if (hnand->State == HAL_NAND_STATE_BUSY)
740 
  {
 874 
  {
741 
     return HAL_BUSY;
 875 
    return HAL_BUSY;
742 
  }
 876 
  }
743 
 
 - 
 
744 
  /* Identify the device address */
 - 
 
745 
  if(hnand->Init.NandBank == FSMC_NAND_BANK2)
 - 
 
746 
  {
 - 
 
747 
    deviceaddress = NAND_DEVICE1;
 - 
 
748 
  }
 - 
 
749 
  else
 - 
 
750 
  {
 - 
 
751 
    deviceaddress = NAND_DEVICE2;
 - 
 
752 
  }
 - 
 
753 
 
 - 
 
754 
  /* Update the NAND controller state */
 - 
 
755 
  hnand->State = HAL_NAND_STATE_BUSY;
 877 
  else if (hnand->State == HAL_NAND_STATE_READY)
756 
 
 - 
 
757 
  /* NAND raw address calculation */
 - 
 
758 
  nandaddress = ARRAY_ADDRESS(pAddress, hnand);
 - 
 
759 
   
 - 
 
760 
  /* Page(s) write loop */
 - 
 
761 
  while((NumPageToWrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
 - 
 
762 
  {
 878 
  {
763 
    /* update the buffer size */
 879 
    /* Process Locked */
764 
    size = hnand->Config.PageSize + ((hnand->Config.PageSize) * numPagesWritten);
 880 
    __HAL_LOCK(hnand);
765 
   
 881 
 
766 
    /* Send write page command sequence */
 882 
    /* Update the NAND controller state */
767 
    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
 - 
 
768 
    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
 883 
    hnand->State = HAL_NAND_STATE_BUSY;
769 
 
 884 
 
770 
    /* Cards with page size <= 512 bytes */
 885 
    /* Identify the device address */
771 
    if((hnand->Config.PageSize) <= 512U)
 886 
    if (hnand->Init.NandBank == FSMC_NAND_BANK2)
772 
    {
 887 
    {
773 
      if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
 888 
      deviceaddress = NAND_DEVICE1;
774 
      {
 889 
    }
775 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 - 
 
776 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 - 
 
777 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 - 
 
778 
      }
 890 
    else
779 
      else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
 - 
 
780 
      {
 891 
    {
781 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 892 
      deviceaddress = NAND_DEVICE2;
782 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 - 
 
783 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 - 
 
784 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
 - 
 
785 
      }
 - 
 
786 
    }
 893 
    }
- 
 
 894 
 
787 
    else /* (hnand->Config.PageSize) > 512 */
 895 
    /* NAND raw address calculation */
- 
 
 896 
    nandaddress = ARRAY_ADDRESS(pAddress, hnand);
- 
 
 897 
 
- 
 
 898 
    /* Page(s) write loop */
- 
 
 899 
    while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
788 
    {
 900 
    {
- 
 
 901 
      /* Send write page command sequence */
- 
 
 902 
      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
- 
 
 903 
      __DSB();
- 
 
 904 
      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
- 
 
 905 
      __DSB();
- 
 
 906 
 
- 
 
 907 
      /* Cards with page size <= 512 bytes */
789 
      if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
 908 
      if ((hnand->Config.PageSize) <= 512U)
790 
      {
 909 
      {
- 
 
 910 
        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
- 
 
 911 
        {
791 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 912 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
- 
 
 913 
          __DSB();
- 
 
 914 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- 
 
 915 
          __DSB();
- 
 
 916 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- 
 
 917 
          __DSB();
- 
 
 918 
        }
- 
 
 919 
        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- 
 
 920 
        {
792 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 921 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
- 
 
 922 
          __DSB();
793 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 923 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- 
 
 924 
          __DSB();
794 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 925 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- 
 
 926 
          __DSB();
- 
 
 927 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- 
 
 928 
          __DSB();
- 
 
 929 
        }
795 
      }
 930 
      }
796 
      else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
 931 
      else /* (hnand->Config.PageSize) > 512 */
797 
      {
 932 
      {
- 
 
 933 
        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
- 
 
 934 
        {
798 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 935 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
- 
 
 936 
          __DSB();
- 
 
 937 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
- 
 
 938 
          __DSB();
- 
 
 939 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- 
 
 940 
          __DSB();
- 
 
 941 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- 
 
 942 
          __DSB();
- 
 
 943 
        }
- 
 
 944 
        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- 
 
 945 
        {
- 
 
 946 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
- 
 
 947 
          __DSB();
799 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 948 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
- 
 
 949 
          __DSB();
800 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 950 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- 
 
 951 
          __DSB();
801 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 952 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- 
 
 953 
          __DSB();
802 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
 954 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- 
 
 955 
          __DSB();
- 
 
 956 
        }
803 
      }
 957 
      }
804 
    }
 - 
 
805 
 
 - 
 
806 
 
 958 
 
807 
    /* Write data to memory */
 959 
      /* Write data to memory */
808 
    for(; index < size; index++)
 960 
      for (index = 0U; index < hnand->Config.PageSize; index++)
809 
    {
 961 
      {
810 
      *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
 962 
        *(__IO uint8_t *)deviceaddress = *buff;
- 
 
 963 
        buff++;
- 
 
 964 
        __DSB();
811 
    }
 965 
      }
812 
   
 966 
 
813 
    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
 967 
      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
814 
   
 968 
      __DSB();
815 
    /* Read status until NAND is ready */
 - 
 
816 
    while(HAL_NAND_Read_Status(hnand) != NAND_READY)
 - 
 
817 
    {
 969 
 
818 
      /* Get tick */
 970 
      /* Get tick */
819 
      tickstart = HAL_GetTick();
 971 
      tickstart = HAL_GetTick();
820 
     
 972 
 
- 
 
 973 
      /* Read status until NAND is ready */
821 
      if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
 974 
      while (HAL_NAND_Read_Status(hnand) != NAND_READY)
822 
      {
 975 
      {
- 
 
 976 
        if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
- 
 
 977 
        {
- 
 
 978 
          /* Update the NAND controller state */
- 
 
 979 
          hnand->State = HAL_NAND_STATE_ERROR;
- 
 
 980 
 
- 
 
 981 
          /* Process unlocked */
- 
 
 982 
          __HAL_UNLOCK(hnand);
- 
 
 983 
 
823 
        return HAL_TIMEOUT;
 984 
          return HAL_TIMEOUT;
- 
 
 985 
        }
824 
      }
 986 
      }
- 
 
 987 
 
- 
 
 988 
      /* Increment written pages number */
- 
 
 989 
      numpageswritten++;
- 
 
 990 
 
- 
 
 991 
      /* Decrement pages to write */
- 
 
 992 
      nbpages--;
- 
 
 993 
 
- 
 
 994 
      /* Increment the NAND address */
- 
 
 995 
      nandaddress = (uint32_t)(nandaddress + 1U);
825 
    }
 996 
    }
826 
 
 997 
 
827 
    /* Increment written pages number */
 998 
    /* Update the NAND controller state */
828 
    numPagesWritten++;
 999 
    hnand->State = HAL_NAND_STATE_READY;
829 
   
 1000 
 
830 
    /* Decrement pages to write */
 1001 
    /* Process unlocked */
831 
    NumPageToWrite--;
 1002 
    __HAL_UNLOCK(hnand);
832 
   
 - 
 
833 
    /* Increment the NAND address */
 - 
 
834 
    nandaddress = (uint32_t)(nandaddress + 1U);
 - 
 
835 
  }
 1003 
  }
836 
 
 1004 
  else
837 
  /* Update the NAND controller state */
 - 
 
838 
  hnand->State = HAL_NAND_STATE_READY;
 - 
 
839 
 
 1005 
  {
840 
  /* Process unlocked */
 1006 
    return HAL_ERROR;
841 
  __HAL_UNLOCK(hnand);
 - 
 
842 
 
 1007 
  }
- 
 
 1008 
 
843 
  return HAL_OK;
 1009 
  return HAL_OK;
844 
}
 1010 
}
845 
 
 1011 
 
846 
/**
 1012 
/**
847 
  * @brief  Write Page(s) to NAND memory block (16-bits addressing)
 1013 
  * @brief  Write Page(s) to NAND memory block (16-bits addressing)
848 
  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
 1014 
  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
849 
  *                the configuration information for NAND module.
 1015 
  *                the configuration information for NAND module.
850 
  * @param  pAddress : pointer to NAND address structure
 1016 
  * @param  pAddress  pointer to NAND address structure
851 
  * @param  pBuffer : pointer to source buffer to write. pBuffer should be 16bits aligned
 1017 
  * @param  pBuffer  pointer to source buffer to write. pBuffer should be 16bits aligned
852 
  * @param  NumPageToWrite  : number of pages to write to block
 1018 
  * @param  NumPageToWrite   number of pages to write to block
853 
  * @retval HAL status
 1019 
  * @retval HAL status
854 
  */
 1020 
  */
855 
HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite)
 1021 
HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
- 
 
 1022 
                                          uint32_t NumPageToWrite)
856 
{
 1023 
{
857 
  __IO uint32_t index = 0U;
 1024 
  uint32_t index;
858 
  uint32_t tickstart = 0U;
 1025 
  uint32_t tickstart;
- 
 
 1026 
  uint32_t deviceaddress;
859 
  uint32_t deviceaddress = 0U, size = 0U, numPagesWritten = 0U, nandaddress = 0U;
 1027 
  uint32_t numpageswritten = 0;
860 
 
 1028 
  uint32_t nandaddress;
861 
  /* Process Locked */
 1029 
  uint32_t nbpages = NumPageToWrite;
862 
  __HAL_LOCK(hnand);  
 1030 
  uint16_t *buff = pBuffer;
863 
 
 1031 
 
864 
  /* Check the NAND controller state */
 1032 
  /* Check the NAND controller state */
865 
  if(hnand->State == HAL_NAND_STATE_BUSY)
 1033 
  if (hnand->State == HAL_NAND_STATE_BUSY)
866 
  {
 1034 
  {
867 
     return HAL_BUSY;
 1035 
    return HAL_BUSY;
868 
  }
 1036 
  }
869 
 
 - 
 
870 
  /* Identify the device address */
 - 
 
871 
  if(hnand->Init.NandBank == FSMC_NAND_BANK2)
 1037 
  else if (hnand->State == HAL_NAND_STATE_READY)
872 
  {
 1038 
  {
873 
    deviceaddress = NAND_DEVICE1;
 1039 
    /* Process Locked */
874 
  }
 - 
 
875 
  else
 - 
 
876 
  {
 - 
 
877 
    deviceaddress = NAND_DEVICE2;
 1040 
    __HAL_LOCK(hnand);
878 
  }
 - 
 
879 
 
 1041 
 
880 
  /* Update the NAND controller state */
 1042 
    /* Update the NAND controller state */
881 
  hnand->State = HAL_NAND_STATE_BUSY;
 1043 
    hnand->State = HAL_NAND_STATE_BUSY;
882 
 
 - 
 
883 
  /* NAND raw address calculation */
 - 
 
884 
  nandaddress = ARRAY_ADDRESS(pAddress, hnand);
 - 
 
885 
 
 - 
 
886 
  /* Page(s) write loop */
 - 
 
887 
  while((NumPageToWrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
 - 
 
888 
  {
 - 
 
889 
    /* update the buffer size */
 - 
 
890 
    size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesWritten);
 - 
 
891 
 
 - 
 
892 
    /* Send write page command sequence */
 - 
 
893 
    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
 - 
 
894 
    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
 - 
 
895 
 
 1044 
 
896 
    /* Cards with page size <= 512 bytes */
 1045 
    /* Identify the device address */
897 
    if((hnand->Config.PageSize) <= 512U)
 1046 
    if (hnand->Init.NandBank == FSMC_NAND_BANK2)
898 
    {
 1047 
    {
899 
      if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
 1048 
      deviceaddress = NAND_DEVICE1;
900 
      {
 1049 
    }
901 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 - 
 
902 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 - 
 
903 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 - 
 
904 
      }
 1050 
    else
905 
      else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
 - 
 
906 
      {
 1051 
    {
907 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 1052 
      deviceaddress = NAND_DEVICE2;
908 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 - 
 
909 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 - 
 
910 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
 - 
 
911 
      }
 - 
 
912 
    }
 1053 
    }
- 
 
 1054 
 
913 
    else /* (hnand->Config.PageSize) > 512 */
 1055 
    /* NAND raw address calculation */
- 
 
 1056 
    nandaddress = ARRAY_ADDRESS(pAddress, hnand);
- 
 
 1057 
 
- 
 
 1058 
    /* Page(s) write loop */
- 
 
 1059 
    while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
914 
    {
 1060 
    {
- 
 
 1061 
      /* Send write page command sequence */
- 
 
 1062 
      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
- 
 
 1063 
      __DSB();
- 
 
 1064 
      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
- 
 
 1065 
      __DSB();
- 
 
 1066 
 
- 
 
 1067 
      /* Cards with page size <= 512 bytes */
915 
      if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
 1068 
      if ((hnand->Config.PageSize) <= 512U)
916 
      {
 1069 
      {
- 
 
 1070 
        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
- 
 
 1071 
        {
917 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 1072 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
- 
 
 1073 
          __DSB();
- 
 
 1074 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- 
 
 1075 
          __DSB();
- 
 
 1076 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- 
 
 1077 
          __DSB();
- 
 
 1078 
        }
- 
 
 1079 
        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- 
 
 1080 
        {
918 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 1081 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
- 
 
 1082 
          __DSB();
919 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 1083 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- 
 
 1084 
          __DSB();
920 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 1085 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- 
 
 1086 
          __DSB();
- 
 
 1087 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- 
 
 1088 
          __DSB();
- 
 
 1089 
        }
921 
      }
 1090 
      }
922 
      else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
 1091 
      else /* (hnand->Config.PageSize) > 512 */
923 
      {
 1092 
      {
- 
 
 1093 
        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
- 
 
 1094 
        {
924 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 1095 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
- 
 
 1096 
          __DSB();
- 
 
 1097 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
- 
 
 1098 
          __DSB();
- 
 
 1099 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- 
 
 1100 
          __DSB();
- 
 
 1101 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- 
 
 1102 
          __DSB();
- 
 
 1103 
        }
- 
 
 1104 
        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- 
 
 1105 
        {
- 
 
 1106 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
- 
 
 1107 
          __DSB();
925 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 1108 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
- 
 
 1109 
          __DSB();
926 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 1110 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- 
 
 1111 
          __DSB();
927 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 1112 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- 
 
 1113 
          __DSB();
928 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
 1114 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- 
 
 1115 
          __DSB();
- 
 
 1116 
        }
929 
      }
 1117 
      }
930 
    }
 - 
 
931 
 
 1118 
 
932 
    /* Write data to memory */
 1119 
      /* Write data to memory */
933 
    for(; index < size; index++)
 1120 
      for (index = 0U; index < hnand->Config.PageSize; index++)
934 
    {
 1121 
      {
935 
      *(__IO uint16_t *)deviceaddress = *(uint16_t *)pBuffer++;
 1122 
        *(__IO uint16_t *)deviceaddress = *buff;
- 
 
 1123 
        buff++;
- 
 
 1124 
        __DSB();
936 
    }
 1125 
      }
937 
   
 1126 
 
938 
    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
 1127 
      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
939 
   
 1128 
      __DSB();
940 
    /* Read status until NAND is ready */
 - 
 
941 
    while(HAL_NAND_Read_Status(hnand) != NAND_READY)
 - 
 
942 
    {
 1129 
 
943 
      /* Get tick */
 1130 
      /* Get tick */
944 
      tickstart = HAL_GetTick();
 1131 
      tickstart = HAL_GetTick();
945 
   
 1132 
 
- 
 
 1133 
      /* Read status until NAND is ready */
946 
      if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
 1134 
      while (HAL_NAND_Read_Status(hnand) != NAND_READY)
947 
      {
 1135 
      {
- 
 
 1136 
        if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
- 
 
 1137 
        {
- 
 
 1138 
          /* Update the NAND controller state */
- 
 
 1139 
          hnand->State = HAL_NAND_STATE_ERROR;
- 
 
 1140 
 
- 
 
 1141 
          /* Process unlocked */
- 
 
 1142 
          __HAL_UNLOCK(hnand);
- 
 
 1143 
 
948 
        return HAL_TIMEOUT;
 1144 
          return HAL_TIMEOUT;
949 
      }
 1145 
        }
950 
    }  
 1146 
      }
951 
 
 1147 
 
952 
    /* Increment written pages number */
 1148 
      /* Increment written pages number */
953 
    numPagesWritten++;
 1149 
      numpageswritten++;
954 
   
 1150 
 
955 
    /* Decrement pages to write */
 1151 
      /* Decrement pages to write */
956 
    NumPageToWrite--;
 1152 
      nbpages--;
957 
   
 1153 
 
958 
    /* Increment the NAND address */
 1154 
      /* Increment the NAND address */
959 
    nandaddress = (uint32_t)(nandaddress + 1U);
 1155 
      nandaddress = (uint32_t)(nandaddress + 1U);
- 
 
 1156 
    }
- 
 
 1157 
 
- 
 
 1158 
    /* Update the NAND controller state */
- 
 
 1159 
    hnand->State = HAL_NAND_STATE_READY;
- 
 
 1160 
 
- 
 
 1161 
    /* Process unlocked */
- 
 
 1162 
    __HAL_UNLOCK(hnand);
960 
  }
 1163 
  }
961 
 
 1164 
  else
962 
  /* Update the NAND controller state */
 - 
 
963 
  hnand->State = HAL_NAND_STATE_READY;
 - 
 
964 
 
 1165 
  {
965 
  /* Process unlocked */
 1166 
    return HAL_ERROR;
966 
  __HAL_UNLOCK(hnand);
 - 
 
967 
 
 1167 
  }
- 
 
 1168 
 
968 
  return HAL_OK;
 1169 
  return HAL_OK;
969 
}
 1170 
}
970 
 
 1171 
 
971 
/**
 1172 
/**
972 
  * @brief  Read Spare area(s) from NAND memory (8-bits addressing)
 1173 
  * @brief  Read Spare area(s) from NAND memory (8-bits addressing)
973 
  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
 1174 
  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
974 
  *                the configuration information for NAND module.
 1175 
  *                the configuration information for NAND module.
975 
  * @param  pAddress : pointer to NAND address structure
 1176 
  * @param  pAddress  pointer to NAND address structure
976 
  * @param  pBuffer: pointer to source buffer to write  
 1177 
  * @param  pBuffer pointer to source buffer to write
977 
  * @param  NumSpareAreaToRead: Number of spare area to read  
 1178 
  * @param  NumSpareAreaToRead Number of spare area to read
978 
  * @retval HAL status
 1179 
  * @retval HAL status
979 
*/
 1180 
  */
980 
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
 1181 
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
- 
 
 1182 
                                             uint32_t NumSpareAreaToRead)
981 
{
 1183 
{
982 
  __IO uint32_t index = 0U;
 1184 
  uint32_t index;
983 
  uint32_t tickstart = 0U;
 1185 
  uint32_t tickstart;
- 
 
 1186 
  uint32_t deviceaddress;
984 
  uint32_t deviceaddress = 0U, size = 0U, numSpareAreaRead = 0U, nandaddress = 0U, columnaddress = 0U;
 1187 
  uint32_t numsparearearead = 0;
985 
 
 1188 
  uint32_t nandaddress;
986 
  /* Process Locked */
 1189 
  uint32_t columnaddress;
- 
 
 1190 
  uint32_t nbspare = NumSpareAreaToRead;
987 
  __HAL_LOCK(hnand);  
 1191 
  uint8_t *buff = pBuffer;
988 
 
 1192 
 
989 
  /* Check the NAND controller state */
 1193 
  /* Check the NAND controller state */
990 
  if(hnand->State == HAL_NAND_STATE_BUSY)
 1194 
  if (hnand->State == HAL_NAND_STATE_BUSY)
991 
  {
 1195 
  {
992 
     return HAL_BUSY;
 1196 
    return HAL_BUSY;
993 
  }
 1197 
  }
994 
 
 - 
 
995 
  /* Identify the device address */
 - 
 
996 
  if(hnand->Init.NandBank == FSMC_NAND_BANK2)
 1198 
  else if (hnand->State == HAL_NAND_STATE_READY)
997 
  {
 1199 
  {
998 
    deviceaddress = NAND_DEVICE1;
 1200 
    /* Process Locked */
999 
  }
 - 
 
1000 
  else
 - 
 
1001 
  {
 - 
 
1002 
    deviceaddress = NAND_DEVICE2;
 1201 
    __HAL_LOCK(hnand);
1003 
  }
 - 
 
1004 
 
 1202 
 
1005 
  /* Update the NAND controller state */
 1203 
    /* Update the NAND controller state */
1006 
  hnand->State = HAL_NAND_STATE_BUSY;
 1204 
    hnand->State = HAL_NAND_STATE_BUSY;
1007 
 
 - 
 
1008 
  /* NAND raw address calculation */
 - 
 
1009 
  nandaddress = ARRAY_ADDRESS(pAddress, hnand);
 - 
 
1010 
 
 - 
 
1011 
  /* Column in page address */
 - 
 
1012 
  columnaddress = COLUMN_ADDRESS(hnand);
 - 
 
1013 
 
 - 
 
1014 
  /* Spare area(s) read loop */
 - 
 
1015 
  while((NumSpareAreaToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
 - 
 
1016 
  {    
 - 
 
1017 
    /* update the buffer size */
 - 
 
1018 
    size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead);
 - 
 
1019 
 
 1205 
 
1020 
    /* Cards with page size <= 512 bytes */
 1206 
    /* Identify the device address */
1021 
    if((hnand->Config.PageSize) <= 512U)
 1207 
    if (hnand->Init.NandBank == FSMC_NAND_BANK2)
1022 
    {
 1208 
    {
1023 
      /* Send read spare area command sequence */    
 - 
 
1024 
      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
 - 
 
1025 
     
 - 
 
1026 
      if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
 - 
 
1027 
      {
 - 
 
1028 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 - 
 
1029 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 - 
 
1030 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 - 
 
1031 
      }
 - 
 
1032 
      else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
 - 
 
1033 
      {
 - 
 
1034 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 1209 
      deviceaddress = NAND_DEVICE1;
1035 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 - 
 
1036 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 - 
 
1037 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
 - 
 
1038 
      }
 - 
 
1039 
    }
 1210 
    }
1040 
    else /* (hnand->Config.PageSize) > 512 */
 1211 
    else
1041 
    {
 1212 
    {
- 
 
 1213 
      deviceaddress = NAND_DEVICE2;
- 
 
 1214 
    }
- 
 
 1215 
 
- 
 
 1216 
    /* NAND raw address calculation */
- 
 
 1217 
    nandaddress = ARRAY_ADDRESS(pAddress, hnand);
- 
 
 1218 
 
- 
 
 1219 
    /* Column in page address */
- 
 
 1220 
    columnaddress = COLUMN_ADDRESS(hnand);
- 
 
 1221 
 
1042 
      /* Send read spare area command sequence */
 1222 
    /* Spare area(s) read loop */
1043 
      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
 1223 
    while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
1044 
     
 1224 
    {
- 
 
 1225 
      /* Cards with page size <= 512 bytes */
1045 
      if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
 1226 
      if ((hnand->Config.PageSize) <= 512U)
1046 
      {
 1227 
      {
- 
 
 1228 
        /* Send read spare area command sequence */
- 
 
 1229 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
- 
 
 1230 
        __DSB();
- 
 
 1231 
 
- 
 
 1232 
        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
- 
 
 1233 
        {
- 
 
 1234 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
- 
 
 1235 
          __DSB();
1047 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
 1236 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- 
 
 1237 
          __DSB();
1048 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
 1238 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- 
 
 1239 
          __DSB();
- 
 
 1240 
        }
- 
 
 1241 
        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- 
 
 1242 
        {
- 
 
 1243 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
- 
 
 1244 
          __DSB();
1049 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 1245 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- 
 
 1246 
          __DSB();
1050 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 1247 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- 
 
 1248 
          __DSB();
- 
 
 1249 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- 
 
 1250 
          __DSB();
- 
 
 1251 
        }
1051 
      }
 1252 
      }
1052 
      else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
 1253 
      else /* (hnand->Config.PageSize) > 512 */
1053 
      {
 1254 
      {
- 
 
 1255 
        /* Send read spare area command sequence */
- 
 
 1256 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
- 
 
 1257 
        __DSB();
- 
 
 1258 
 
- 
 
 1259 
        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
- 
 
 1260 
        {
1054 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
 1261 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
- 
 
 1262 
          __DSB();
- 
 
 1263 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
- 
 
 1264 
          __DSB();
- 
 
 1265 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- 
 
 1266 
          __DSB();
- 
 
 1267 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- 
 
 1268 
          __DSB();
- 
 
 1269 
        }
- 
 
 1270 
        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- 
 
 1271 
        {
- 
 
 1272 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
- 
 
 1273 
          __DSB();
1055 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
 1274 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
- 
 
 1275 
          __DSB();
1056 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 1276 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- 
 
 1277 
          __DSB();
1057 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 1278 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- 
 
 1279 
          __DSB();
1058 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
 1280 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- 
 
 1281 
          __DSB();
- 
 
 1282 
        }
1059 
      }
 1283 
      }
1060 
    }
 - 
 
1061 
 
 1284 
 
1062 
    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
 1285 
      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
1063 
   
 1286 
      __DSB();
- 
 
 1287 
 
1064 
    if(hnand->Config.ExtraCommandEnable == ENABLE)
 1288 
      if (hnand->Config.ExtraCommandEnable == ENABLE)
1065 
    {
 - 
 
1066 
      /* Get tick */
 - 
 
1067 
      tickstart = HAL_GetTick();
 - 
 
1068 
     
 - 
 
1069 
      /* Read status until NAND is ready */
 - 
 
1070 
      while(HAL_NAND_Read_Status(hnand) != NAND_READY)
 - 
 
1071 
      {
 1289 
      {
- 
 
 1290 
        /* Get tick */
- 
 
 1291 
        tickstart = HAL_GetTick();
- 
 
 1292 
 
- 
 
 1293 
        /* Read status until NAND is ready */
1072 
        if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
 1294 
        while (HAL_NAND_Read_Status(hnand) != NAND_READY)
1073 
        {
 1295 
        {
- 
 
 1296 
          if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
- 
 
 1297 
          {
- 
 
 1298 
            /* Update the NAND controller state */
- 
 
 1299 
            hnand->State = HAL_NAND_STATE_ERROR;
- 
 
 1300 
 
- 
 
 1301 
            /* Process unlocked */
- 
 
 1302 
            __HAL_UNLOCK(hnand);
- 
 
 1303 
 
1074 
          return HAL_TIMEOUT;
 1304 
            return HAL_TIMEOUT;
- 
 
 1305 
          }
1075 
        }
 1306 
        }
- 
 
 1307 
 
- 
 
 1308 
        /* Go back to read mode */
- 
 
 1309 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
- 
 
 1310 
        __DSB();
1076 
      }
 1311 
      }
1077 
     
 1312 
 
1078 
      /* Go back to read mode */
 1313 
      /* Get Data into Buffer */
1079 
      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
 1314 
      for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
1080 
    }
 1315 
      {
- 
 
 1316 
        *buff = *(uint8_t *)deviceaddress;
- 
 
 1317 
        buff++;
1081 
   
 1318 
      }
- 
 
 1319 
 
1082 
    /* Get Data into Buffer */
 1320 
      /* Increment read spare areas number */
1083 
    for(; index < size; index++)
 1321 
      numsparearearead++;
- 
 
 1322 
 
- 
 
 1323 
      /* Decrement spare areas to read */
1084 
    {
 1324 
      nbspare--;
- 
 
 1325 
 
- 
 
 1326 
      /* Increment the NAND address */
1085 
      *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
 1327 
      nandaddress = (uint32_t)(nandaddress + 1U);
1086 
    }
 1328 
    }
1087 
   
 1329 
 
1088 
    /* Increment read spare areas number */
 1330 
    /* Update the NAND controller state */
1089 
    numSpareAreaRead++;
 1331 
    hnand->State = HAL_NAND_STATE_READY;
1090 
   
 1332 
 
1091 
    /* Decrement spare areas to read */
 1333 
    /* Process unlocked */
1092 
    NumSpareAreaToRead--;
 1334 
    __HAL_UNLOCK(hnand);
1093 
   
 1335 
  }
1094 
    /* Increment the NAND address */
 1336 
  else
- 
 
 1337 
  {
1095 
    nandaddress = (uint32_t)(nandaddress + 1U);
 1338 
    return HAL_ERROR;
1096 
  }
 1339 
  }
1097 
 
 - 
 
1098 
  /* Update the NAND controller state */
 - 
 
1099 
  hnand->State = HAL_NAND_STATE_READY;
 - 
 
1100 
 
 - 
 
1101 
  /* Process unlocked */
 - 
 
1102 
  __HAL_UNLOCK(hnand);
 - 
 
1103 
 
 1340 
 
1104 
  return HAL_OK;
 1341 
  return HAL_OK;
1105 
}
 1342 
}
1106 
 
 1343 
 
1107 
/**
 1344 
/**
1108 
  * @brief  Read Spare area(s) from NAND memory (16-bits addressing)
 1345 
  * @brief  Read Spare area(s) from NAND memory (16-bits addressing)
1109 
  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
 1346 
  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
1110 
  *                the configuration information for NAND module.
 1347 
  *                the configuration information for NAND module.
1111 
  * @param  pAddress : pointer to NAND address structure
 1348 
  * @param  pAddress  pointer to NAND address structure
1112 
  * @param  pBuffer: pointer to source buffer to write. pBuffer should be 16bits aligned.
 1349 
  * @param  pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned.
1113 
  * @param  NumSpareAreaToRead: Number of spare area to read  
 1350 
  * @param  NumSpareAreaToRead Number of spare area to read
1114 
  * @retval HAL status
 1351 
  * @retval HAL status
1115 
*/
 1352 
  */
1116 
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
 1353 
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
- 
 
 1354 
                                              uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
1117 
{
 1355 
{
1118 
  __IO uint32_t index = 0U;
 1356 
  uint32_t index;
1119 
  uint32_t tickstart = 0U;
 1357 
  uint32_t tickstart;
- 
 
 1358 
  uint32_t deviceaddress;
1120 
  uint32_t deviceaddress = 0U, size = 0U, numSpareAreaRead = 0U, nandaddress = 0U, columnaddress = 0U;
 1359 
  uint32_t numsparearearead = 0;
1121 
 
 - 
 
1122 
  /* Process Locked */
 1360 
  uint32_t nandaddress;
1123 
  __HAL_LOCK(hnand);
 1361 
  uint32_t columnaddress;
- 
 
 1362 
  uint32_t nbspare = NumSpareAreaToRead;
- 
 
 1363 
  uint16_t *buff = pBuffer;
1124 
 
 1364 
 
1125 
  /* Check the NAND controller state */
 1365 
  /* Check the NAND controller state */
1126 
  if(hnand->State == HAL_NAND_STATE_BUSY)
 1366 
  if (hnand->State == HAL_NAND_STATE_BUSY)
1127 
  {
 1367 
  {
1128 
     return HAL_BUSY;
 1368 
    return HAL_BUSY;
1129 
  }
 1369 
  }
1130 
 
 - 
 
1131 
  /* Identify the device address */
 - 
 
1132 
  if(hnand->Init.NandBank == FSMC_NAND_BANK2)
 1370 
  else if (hnand->State == HAL_NAND_STATE_READY)
1133 
  {
 1371 
  {
1134 
    deviceaddress = NAND_DEVICE1;
 1372 
    /* Process Locked */
1135 
  }
 - 
 
1136 
  else
 - 
 
1137 
  {
 - 
 
1138 
    deviceaddress = NAND_DEVICE2;
 1373 
    __HAL_LOCK(hnand);
1139 
  }
 - 
 
1140 
 
 1374 
 
1141 
  /* Update the NAND controller state */
 1375 
    /* Update the NAND controller state */
1142 
  hnand->State = HAL_NAND_STATE_BUSY;
 1376 
    hnand->State = HAL_NAND_STATE_BUSY;
1143 
 
 - 
 
1144 
  /* NAND raw address calculation */
 - 
 
1145 
  nandaddress = ARRAY_ADDRESS(pAddress, hnand);
 - 
 
1146 
 
 - 
 
1147 
  /* Column in page address */
 - 
 
1148 
  columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
 - 
 
1149 
 
 - 
 
1150 
  /* Spare area(s) read loop */
 - 
 
1151 
  while((NumSpareAreaToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
 - 
 
1152 
  {
 - 
 
1153 
    /* update the buffer size */
 - 
 
1154 
    size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead);
 - 
 
1155 
 
 1377 
 
1156 
    /* Cards with page size <= 512 bytes */
 1378 
    /* Identify the device address */
1157 
    if((hnand->Config.PageSize) <= 512U)
 1379 
    if (hnand->Init.NandBank == FSMC_NAND_BANK2)
1158 
    {
 1380 
    {
1159 
      /* Send read spare area command sequence */    
 - 
 
1160 
      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
 - 
 
1161 
     
 - 
 
1162 
      if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
 - 
 
1163 
      {
 - 
 
1164 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 - 
 
1165 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 - 
 
1166 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 - 
 
1167 
      }
 - 
 
1168 
      else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
 - 
 
1169 
      {
 - 
 
1170 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 1381 
      deviceaddress = NAND_DEVICE1;
1171 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 - 
 
1172 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 - 
 
1173 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
 - 
 
1174 
      }
 - 
 
1175 
    }
 1382 
    }
1176 
    else /* (hnand->Config.PageSize) > 512 */
 1383 
    else
1177 
    {
 1384 
    {
- 
 
 1385 
      deviceaddress = NAND_DEVICE2;
- 
 
 1386 
    }
- 
 
 1387 
 
1178 
      /* Send read spare area command sequence */    
 1388 
    /* NAND raw address calculation */
- 
 
 1389 
    nandaddress = ARRAY_ADDRESS(pAddress, hnand);
- 
 
 1390 
 
- 
 
 1391 
    /* Column in page address */
1179 
      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
 1392 
    columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
- 
 
 1393 
 
- 
 
 1394 
    /* Spare area(s) read loop */
- 
 
 1395 
    while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
1180 
     
 1396 
    {
- 
 
 1397 
      /* Cards with page size <= 512 bytes */
1181 
      if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
 1398 
      if ((hnand->Config.PageSize) <= 512U)
1182 
      {
 1399 
      {
- 
 
 1400 
        /* Send read spare area command sequence */
- 
 
 1401 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
- 
 
 1402 
        __DSB();
- 
 
 1403 
 
- 
 
 1404 
        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
- 
 
 1405 
        {
- 
 
 1406 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
- 
 
 1407 
          __DSB();
1183 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
 1408 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- 
 
 1409 
          __DSB();
1184 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
 1410 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- 
 
 1411 
          __DSB();
- 
 
 1412 
        }
- 
 
 1413 
        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- 
 
 1414 
        {
- 
 
 1415 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
- 
 
 1416 
          __DSB();
1185 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 1417 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- 
 
 1418 
          __DSB();
1186 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 1419 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- 
 
 1420 
          __DSB();
- 
 
 1421 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- 
 
 1422 
          __DSB();
- 
 
 1423 
        }
1187 
      }
 1424 
      }
1188 
      else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
 1425 
      else /* (hnand->Config.PageSize) > 512 */
1189 
      {
 1426 
      {
- 
 
 1427 
        /* Send read spare area command sequence */
- 
 
 1428 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
- 
 
 1429 
        __DSB();
- 
 
 1430 
 
- 
 
 1431 
        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
- 
 
 1432 
        {
1190 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
 1433 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
- 
 
 1434 
          __DSB();
- 
 
 1435 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
- 
 
 1436 
          __DSB();
- 
 
 1437 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- 
 
 1438 
          __DSB();
- 
 
 1439 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- 
 
 1440 
          __DSB();
- 
 
 1441 
        }
- 
 
 1442 
        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- 
 
 1443 
        {
- 
 
 1444 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
- 
 
 1445 
          __DSB();
1191 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
 1446 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
- 
 
 1447 
          __DSB();
1192 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 1448 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- 
 
 1449 
          __DSB();
1193 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 1450 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- 
 
 1451 
          __DSB();
1194 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
 1452 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- 
 
 1453 
          __DSB();
- 
 
 1454 
        }
1195 
      }
 1455 
      }
1196 
    }
 - 
 
1197 
 
 1456 
 
1198 
    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
 1457 
      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
- 
 
 1458 
      __DSB();
1199 
 
 1459 
 
1200 
    if(hnand->Config.ExtraCommandEnable == ENABLE)
 1460 
      if (hnand->Config.ExtraCommandEnable == ENABLE)
1201 
    {
 - 
 
1202 
      /* Get tick */
 - 
 
1203 
      tickstart = HAL_GetTick();
 - 
 
1204 
     
 - 
 
1205 
      /* Read status until NAND is ready */
 - 
 
1206 
      while(HAL_NAND_Read_Status(hnand) != NAND_READY)
 - 
 
1207 
      {
 1461 
      {
- 
 
 1462 
        /* Get tick */
- 
 
 1463 
        tickstart = HAL_GetTick();
- 
 
 1464 
 
- 
 
 1465 
        /* Read status until NAND is ready */
1208 
        if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
 1466 
        while (HAL_NAND_Read_Status(hnand) != NAND_READY)
1209 
        {
 1467 
        {
- 
 
 1468 
          if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
- 
 
 1469 
          {
- 
 
 1470 
            /* Update the NAND controller state */
- 
 
 1471 
            hnand->State = HAL_NAND_STATE_ERROR;
- 
 
 1472 
 
- 
 
 1473 
            /* Process unlocked */
- 
 
 1474 
            __HAL_UNLOCK(hnand);
- 
 
 1475 
 
1210 
          return HAL_TIMEOUT;
 1476 
            return HAL_TIMEOUT;
- 
 
 1477 
          }
1211 
        }
 1478 
        }
- 
 
 1479 
 
- 
 
 1480 
        /* Go back to read mode */
- 
 
 1481 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
- 
 
 1482 
        __DSB();
1212 
      }
 1483 
      }
1213 
     
 1484 
 
1214 
      /* Go back to read mode */
 1485 
      /* Get Data into Buffer */
1215 
      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
 1486 
      for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
1216 
    }
 1487 
      {
- 
 
 1488 
        *buff = *(uint16_t *)deviceaddress;
- 
 
 1489 
        buff++;
1217 
   
 1490 
      }
- 
 
 1491 
 
1218 
    /* Get Data into Buffer */
 1492 
      /* Increment read spare areas number */
1219 
    for(; index < size; index++)
 1493 
      numsparearearead++;
- 
 
 1494 
 
- 
 
 1495 
      /* Decrement spare areas to read */
1220 
    {
 1496 
      nbspare--;
- 
 
 1497 
 
- 
 
 1498 
      /* Increment the NAND address */
1221 
      *(uint16_t *)pBuffer++ = *(uint16_t *)deviceaddress;
 1499 
      nandaddress = (uint32_t)(nandaddress + 1U);
1222 
    }
 1500 
    }
1223 
   
 1501 
 
1224 
    /* Increment read spare areas number */
 1502 
    /* Update the NAND controller state */
1225 
    numSpareAreaRead++;
 1503 
    hnand->State = HAL_NAND_STATE_READY;
1226 
   
 1504 
 
1227 
    /* Decrement spare areas to read */
 1505 
    /* Process unlocked */
1228 
    NumSpareAreaToRead--;
 1506 
    __HAL_UNLOCK(hnand);
1229 
   
 1507 
  }
1230 
    /* Increment the NAND address */
 1508 
  else
- 
 
 1509 
  {
1231 
    nandaddress = (uint32_t)(nandaddress + 1U);
 1510 
    return HAL_ERROR;
1232 
  }
 1511 
  }
1233 
 
 - 
 
1234 
  /* Update the NAND controller state */
 - 
 
1235 
  hnand->State = HAL_NAND_STATE_READY;
 - 
 
1236 
 
 - 
 
1237 
  /* Process unlocked */
 - 
 
1238 
  __HAL_UNLOCK(hnand);    
 - 
 
1239 
 
 1512 
 
1240 
  return HAL_OK;  
 1513 
  return HAL_OK;
1241 
}
 1514 
}
1242 
 
 1515 
 
1243 
/**
 1516 
/**
1244 
  * @brief  Write Spare area(s) to NAND memory (8-bits addressing)
 1517 
  * @brief  Write Spare area(s) to NAND memory (8-bits addressing)
1245 
  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
 1518 
  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
1246 
  *                the configuration information for NAND module.
 1519 
  *                the configuration information for NAND module.
1247 
  * @param  pAddress : pointer to NAND address structure
 1520 
  * @param  pAddress  pointer to NAND address structure
1248 
  * @param  pBuffer : pointer to source buffer to write  
 1521 
  * @param  pBuffer  pointer to source buffer to write
1249 
  * @param  NumSpareAreaTowrite  : number of spare areas to write to block
 1522 
  * @param  NumSpareAreaTowrite   number of spare areas to write to block
1250 
  * @retval HAL status
 1523 
  * @retval HAL status
1251 
  */
 1524 
  */
1252 
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
 1525 
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
- 
 
 1526 
                                              uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
1253 
{
 1527 
{
1254 
  __IO uint32_t index = 0U;
 1528 
  uint32_t index;
1255 
  uint32_t tickstart = 0U;
 1529 
  uint32_t tickstart;
- 
 
 1530 
  uint32_t deviceaddress;
1256 
  uint32_t deviceaddress = 0U, size = 0U, numSpareAreaWritten = 0U, nandaddress = 0U, columnaddress = 0U;
 1531 
  uint32_t numspareareawritten = 0;
1257 
 
 - 
 
1258 
  /* Process Locked */
 1532 
  uint32_t nandaddress;
1259 
  __HAL_LOCK(hnand);
 1533 
  uint32_t columnaddress;
- 
 
 1534 
  uint32_t nbspare = NumSpareAreaTowrite;
- 
 
 1535 
  uint8_t *buff = pBuffer;
1260 
 
 1536 
 
1261 
  /* Check the NAND controller state */
 1537 
  /* Check the NAND controller state */
1262 
  if(hnand->State == HAL_NAND_STATE_BUSY)
 1538 
  if (hnand->State == HAL_NAND_STATE_BUSY)
1263 
  {
 - 
 
1264 
     return HAL_BUSY;
 - 
 
1265 
  }
 - 
 
1266 
 
 - 
 
1267 
  /* Identify the device address */
 - 
 
1268 
  if(hnand->Init.NandBank == FSMC_NAND_BANK2)
 - 
 
1269 
  {
 - 
 
1270 
    deviceaddress = NAND_DEVICE1;
 - 
 
1271 
  }
 - 
 
1272 
  else
 - 
 
1273 
  {
 1539 
  {
1274 
    deviceaddress = NAND_DEVICE2;
 1540 
    return HAL_BUSY;
1275 
  }
 1541 
  }
1276 
 
 - 
 
1277 
  /* Update the FSMC_NAND controller state */
 - 
 
1278 
  hnand->State = HAL_NAND_STATE_BUSY;  
 1542 
  else if (hnand->State == HAL_NAND_STATE_READY)
1279 
 
 - 
 
1280 
  /* Page address calculation */
 - 
 
1281 
  nandaddress = ARRAY_ADDRESS(pAddress, hnand);
 - 
 
1282 
 
 - 
 
1283 
  /* Column in page address */
 - 
 
1284 
  columnaddress = COLUMN_ADDRESS(hnand);
 - 
 
1285 
 
 - 
 
1286 
  /* Spare area(s) write loop */
 - 
 
1287 
  while((NumSpareAreaTowrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
 - 
 
1288 
  {
 1543 
  {
1289 
    /* update the buffer size */
 1544 
    /* Process Locked */
1290 
    size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten);
 1545 
    __HAL_LOCK(hnand);
1291 
 
 1546 
 
1292 
    /* Cards with page size <= 512 bytes */
 1547 
    /* Update the NAND controller state */
- 
 
 1548 
    hnand->State = HAL_NAND_STATE_BUSY;
- 
 
 1549 
 
- 
 
 1550 
    /* Identify the device address */
1293 
    if((hnand->Config.PageSize) <= 512U)
 1551 
    if (hnand->Init.NandBank == FSMC_NAND_BANK2)
1294 
    {
 1552 
    {
1295 
      /* Send write Spare area command sequence */
 - 
 
1296 
      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
 - 
 
1297 
      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
 1553 
      deviceaddress = NAND_DEVICE1;
1298 
     
 - 
 
1299 
      if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
 - 
 
1300 
      {
 - 
 
1301 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 - 
 
1302 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 - 
 
1303 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 - 
 
1304 
      }
 - 
 
1305 
      else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
 - 
 
1306 
      {
 - 
 
1307 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 - 
 
1308 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 - 
 
1309 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 - 
 
1310 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
 - 
 
1311 
      }
 - 
 
1312 
    }
 1554 
    }
1313 
    else /* (hnand->Config.PageSize) > 512 */
 1555 
    else
1314 
    {
 1556 
    {
- 
 
 1557 
      deviceaddress = NAND_DEVICE2;
- 
 
 1558 
    }
- 
 
 1559 
 
- 
 
 1560 
    /* Page address calculation */
- 
 
 1561 
    nandaddress = ARRAY_ADDRESS(pAddress, hnand);
- 
 
 1562 
 
- 
 
 1563 
    /* Column in page address */
- 
 
 1564 
    columnaddress = COLUMN_ADDRESS(hnand);
- 
 
 1565 
 
- 
 
 1566 
    /* Spare area(s) write loop */
- 
 
 1567 
    while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
- 
 
 1568 
    {
- 
 
 1569 
      /* Cards with page size <= 512 bytes */
- 
 
 1570 
      if ((hnand->Config.PageSize) <= 512U)
- 
 
 1571 
      {
1315 
      /* Send write Spare area command sequence */
 1572 
        /* Send write Spare area command sequence */
1316 
      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
 1573 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
- 
 
 1574 
        __DSB();
1317 
      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
 1575 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
- 
 
 1576 
        __DSB();
- 
 
 1577 
 
- 
 
 1578 
        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
- 
 
 1579 
        {
- 
 
 1580 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
- 
 
 1581 
          __DSB();
- 
 
 1582 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- 
 
 1583 
          __DSB();
- 
 
 1584 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- 
 
 1585 
          __DSB();
1318 
   
 1586 
        }
1319 
      if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
 1587 
        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- 
 
 1588 
        {
- 
 
 1589 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
- 
 
 1590 
          __DSB();
- 
 
 1591 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- 
 
 1592 
          __DSB();
- 
 
 1593 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- 
 
 1594 
          __DSB();
- 
 
 1595 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- 
 
 1596 
          __DSB();
- 
 
 1597 
        }
- 
 
 1598 
      }
- 
 
 1599 
      else /* (hnand->Config.PageSize) > 512 */
1320 
      {
 1600 
      {
- 
 
 1601 
        /* Send write Spare area command sequence */
- 
 
 1602 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
- 
 
 1603 
        __DSB();
- 
 
 1604 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
- 
 
 1605 
        __DSB();
- 
 
 1606 
 
- 
 
 1607 
        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
- 
 
 1608 
        {
1321 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
 1609 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
- 
 
 1610 
          __DSB();
1322 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
 1611 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
- 
 
 1612 
          __DSB();
- 
 
 1613 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- 
 
 1614 
          __DSB();
- 
 
 1615 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- 
 
 1616 
          __DSB();
- 
 
 1617 
        }
- 
 
 1618 
        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- 
 
 1619 
        {
- 
 
 1620 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
- 
 
 1621 
          __DSB();
- 
 
 1622 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
- 
 
 1623 
          __DSB();
1323 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 1624 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- 
 
 1625 
          __DSB();
1324 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 1626 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- 
 
 1627 
          __DSB();
- 
 
 1628 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- 
 
 1629 
          __DSB();
- 
 
 1630 
        }
1325 
      }
 1631 
      }
- 
 
 1632 
 
- 
 
 1633 
      /* Write data to memory */
1326 
      else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
 1634 
      for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
1327 
      {
 1635 
      {
1328 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
 - 
 
1329 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
 - 
 
1330 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 1636 
        *(__IO uint8_t *)deviceaddress = *buff;
1331 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 1637 
        buff++;
1332 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
 1638 
        __DSB();
1333 
      }
 1639 
      }
1334 
    }
 - 
 
1335 
 
 1640 
 
1336 
    /* Write data to memory */
 - 
 
1337 
    for(; index < size; index++)
 - 
 
1338 
    {
 - 
 
1339 
      *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
 1641 
      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
1340 
    }
 1642 
      __DSB();
1341 
   
 1643 
 
1342 
    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
 - 
 
1343 
   
 - 
 
1344 
    /* Get tick */
 1644 
      /* Get tick */
1345 
    tickstart = HAL_GetTick();
 1645 
      tickstart = HAL_GetTick();
1346 
   
 1646 
 
1347 
    /* Read status until NAND is ready */
 1647 
      /* Read status until NAND is ready */
1348 
    while(HAL_NAND_Read_Status(hnand) != NAND_READY)
 1648 
      while (HAL_NAND_Read_Status(hnand) != NAND_READY)
1349 
    {
 - 
 
1350 
      if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
 - 
 
1351 
      {
 1649 
      {
- 
 
 1650 
        if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
- 
 
 1651 
        {
- 
 
 1652 
          /* Update the NAND controller state */
- 
 
 1653 
          hnand->State = HAL_NAND_STATE_ERROR;
- 
 
 1654 
 
- 
 
 1655 
          /* Process unlocked */
- 
 
 1656 
          __HAL_UNLOCK(hnand);
- 
 
 1657 
 
1352 
        return HAL_TIMEOUT;
 1658 
          return HAL_TIMEOUT;
- 
 
 1659 
        }
1353 
      }
 1660 
      }
- 
 
 1661 
 
- 
 
 1662 
      /* Increment written spare areas number */
- 
 
 1663 
      numspareareawritten++;
- 
 
 1664 
 
- 
 
 1665 
      /* Decrement spare areas to write */
- 
 
 1666 
      nbspare--;
- 
 
 1667 
 
- 
 
 1668 
      /* Increment the NAND address */
- 
 
 1669 
      nandaddress = (uint32_t)(nandaddress + 1U);
1354 
    }
 1670 
    }
1355 
 
 1671 
 
1356 
    /* Increment written spare areas number */
 - 
 
1357 
    numSpareAreaWritten++;
 - 
 
1358 
   
 - 
 
1359 
    /* Decrement spare areas to write */
 - 
 
1360 
    NumSpareAreaTowrite--;
 - 
 
1361 
   
 - 
 
1362 
    /* Increment the NAND address */
 1672 
    /* Update the NAND controller state */
1363 
    nandaddress = (uint32_t)(nandaddress + 1U);
 1673 
    hnand->State = HAL_NAND_STATE_READY;
1364 
  }
 - 
 
1365 
 
 1674 
 
1366 
  /* Update the NAND controller state */
 1675 
    /* Process unlocked */
- 
 
 1676 
    __HAL_UNLOCK(hnand);
- 
 
 1677 
  }
- 
 
 1678 
  else
- 
 
 1679 
  {
1367 
  hnand->State = HAL_NAND_STATE_READY;
 1680 
    return HAL_ERROR;
- 
 
 1681 
  }
1368 
 
 1682 
 
1369 
  /* Process unlocked */
 - 
 
1370 
  __HAL_UNLOCK(hnand);
 - 
 
1371 
   
 - 
 
1372 
  return HAL_OK;
 1683 
  return HAL_OK;
1373 
}
 1684 
}
1374 
 
 1685 
 
1375 
/**
 1686 
/**
1376 
  * @brief  Write Spare area(s) to NAND memory (16-bits addressing)
 1687 
  * @brief  Write Spare area(s) to NAND memory (16-bits addressing)
1377 
  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
 1688 
  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
1378 
  *                the configuration information for NAND module.
 1689 
  *                the configuration information for NAND module.
1379 
  * @param  pAddress : pointer to NAND address structure
 1690 
  * @param  pAddress  pointer to NAND address structure
1380 
  * @param  pBuffer : pointer to source buffer to write. pBuffer should be 16bits aligned.  
 1691 
  * @param  pBuffer  pointer to source buffer to write. pBuffer should be 16bits aligned.
1381 
  * @param  NumSpareAreaTowrite  : number of spare areas to write to block
 1692 
  * @param  NumSpareAreaTowrite   number of spare areas to write to block
1382 
  * @retval HAL status
 1693 
  * @retval HAL status
1383 
  */
 1694 
  */
1384 
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
 1695 
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
- 
 
 1696 
                                               uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
1385 
{
 1697 
{
1386 
  __IO uint32_t index = 0U;
 1698 
  uint32_t index;
1387 
  uint32_t tickstart = 0U;
 1699 
  uint32_t tickstart;
- 
 
 1700 
  uint32_t deviceaddress;
1388 
  uint32_t deviceaddress = 0U, size = 0U, numSpareAreaWritten = 0U, nandaddress = 0U, columnaddress = 0U;
 1701 
  uint32_t numspareareawritten = 0;
1389 
 
 - 
 
1390 
  /* Process Locked */
 1702 
  uint32_t nandaddress;
1391 
  __HAL_LOCK(hnand);
 1703 
  uint32_t columnaddress;
- 
 
 1704 
  uint32_t nbspare = NumSpareAreaTowrite;
- 
 
 1705 
  uint16_t *buff = pBuffer;
1392 
 
 1706 
 
1393 
  /* Check the NAND controller state */
 1707 
  /* Check the NAND controller state */
1394 
  if(hnand->State == HAL_NAND_STATE_BUSY)
 1708 
  if (hnand->State == HAL_NAND_STATE_BUSY)
1395 
  {
 1709 
  {
1396 
     return HAL_BUSY;
 1710 
    return HAL_BUSY;
1397 
  }
 1711 
  }
1398 
 
 - 
 
1399 
  /* Identify the device address */
 - 
 
1400 
  if(hnand->Init.NandBank == FSMC_NAND_BANK2)
 1712 
  else if (hnand->State == HAL_NAND_STATE_READY)
1401 
  {
 1713 
  {
1402 
    deviceaddress = NAND_DEVICE1;
 1714 
    /* Process Locked */
1403 
  }
 - 
 
1404 
  else
 - 
 
1405 
  {
 - 
 
1406 
    deviceaddress = NAND_DEVICE2;
 1715 
    __HAL_LOCK(hnand);
1407 
  }
 - 
 
1408 
 
 1716 
 
1409 
  /* Update the FSMC_NAND controller state */
 1717 
    /* Update the NAND controller state */
1410 
  hnand->State = HAL_NAND_STATE_BUSY;  
 1718 
    hnand->State = HAL_NAND_STATE_BUSY;
1411 
 
 - 
 
1412 
  /* NAND raw address calculation */
 - 
 
1413 
  nandaddress = ARRAY_ADDRESS(pAddress, hnand);
 - 
 
1414 
 
 - 
 
1415 
  /* Column in page address */
 - 
 
1416 
  columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
 - 
 
1417 
 
 - 
 
1418 
  /* Spare area(s) write loop */
 - 
 
1419 
  while((NumSpareAreaTowrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
 - 
 
1420 
  {
 - 
 
1421 
    /* update the buffer size */
 - 
 
1422 
    size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten);
 - 
 
1423 
 
 1719 
 
1424 
    /* Cards with page size <= 512 bytes */
 1720 
    /* Identify the device address */
1425 
    if((hnand->Config.PageSize) <= 512U)
 1721 
    if (hnand->Init.NandBank == FSMC_NAND_BANK2)
1426 
    {
 1722 
    {
- 
 
 1723 
      deviceaddress = NAND_DEVICE1;
- 
 
 1724 
    }
- 
 
 1725 
    else
- 
 
 1726 
    {
- 
 
 1727 
      deviceaddress = NAND_DEVICE2;
- 
 
 1728 
    }
- 
 
 1729 
 
1427 
      /* Send write Spare area command sequence */
 1730 
    /* NAND raw address calculation */
- 
 
 1731 
    nandaddress = ARRAY_ADDRESS(pAddress, hnand);
- 
 
 1732 
 
- 
 
 1733 
    /* Column in page address */
1428 
      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
 1734 
    columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
- 
 
 1735 
 
- 
 
 1736 
    /* Spare area(s) write loop */
1429 
      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
 1737 
    while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
1430 
   
 1738 
    {
- 
 
 1739 
      /* Cards with page size <= 512 bytes */
1431 
      if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
 1740 
      if ((hnand->Config.PageSize) <= 512U)
1432 
      {
 1741 
      {
- 
 
 1742 
        /* Send write Spare area command sequence */
- 
 
 1743 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
- 
 
 1744 
        __DSB();
- 
 
 1745 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
- 
 
 1746 
        __DSB();
- 
 
 1747 
 
- 
 
 1748 
        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
- 
 
 1749 
        {
1433 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 1750 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
- 
 
 1751 
          __DSB();
- 
 
 1752 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- 
 
 1753 
          __DSB();
- 
 
 1754 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- 
 
 1755 
          __DSB();
- 
 
 1756 
        }
- 
 
 1757 
        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- 
 
 1758 
        {
- 
 
 1759 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
- 
 
 1760 
          __DSB();
1434 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 1761 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- 
 
 1762 
          __DSB();
1435 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 1763 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- 
 
 1764 
          __DSB();
- 
 
 1765 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- 
 
 1766 
          __DSB();
- 
 
 1767 
        }
1436 
      }
 1768 
      }
1437 
      else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
 1769 
      else /* (hnand->Config.PageSize) > 512 */
1438 
      {
 1770 
      {
- 
 
 1771 
        /* Send write Spare area command sequence */
- 
 
 1772 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
- 
 
 1773 
        __DSB();
1439 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 1774 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
- 
 
 1775 
        __DSB();
- 
 
 1776 
 
- 
 
 1777 
        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
- 
 
 1778 
        {
- 
 
 1779 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
- 
 
 1780 
          __DSB();
- 
 
 1781 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
- 
 
 1782 
          __DSB();
- 
 
 1783 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- 
 
 1784 
          __DSB();
- 
 
 1785 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- 
 
 1786 
          __DSB();
- 
 
 1787 
        }
- 
 
 1788 
        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
- 
 
 1789 
        {
- 
 
 1790 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
- 
 
 1791 
          __DSB();
- 
 
 1792 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
- 
 
 1793 
          __DSB();
1440 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 1794 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
- 
 
 1795 
          __DSB();
1441 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 1796 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
- 
 
 1797 
          __DSB();
1442 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
 1798 
          *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
- 
 
 1799 
          __DSB();
- 
 
 1800 
        }
1443 
      }
 1801 
      }
1444 
    }
 - 
 
1445 
    else /* (hnand->Config.PageSize) > 512 */
 - 
 
1446 
    {
 1802 
 
1447 
      /* Send write Spare area command sequence */
 1803 
      /* Write data to memory */
1448 
      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
 - 
 
1449 
      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
 - 
 
1450 
   
 - 
 
1451 
      if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
 1804 
      for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
1452 
      {
 1805 
      {
1453 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
 - 
 
1454 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
 - 
 
1455 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 - 
 
1456 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 1806 
        *(__IO uint16_t *)deviceaddress = *buff;
1457 
      }
 1807 
        buff++;
1458 
      else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
 - 
 
1459 
      {
 1808 
        __DSB();
1460 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
 - 
 
1461 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
 - 
 
1462 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
 - 
 
1463 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
 - 
 
1464 
        *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
 - 
 
1465 
      }
 1809 
      }
1466 
    }
 - 
 
1467 
 
 1810 
 
1468 
    /* Write data to memory */
 - 
 
1469 
    for(; index < size; index++)
 - 
 
1470 
    {
 - 
 
1471 
      *(__IO uint16_t *)deviceaddress = *(uint16_t *)pBuffer++;
 - 
 
1472 
    }
 - 
 
1473 
   
 - 
 
1474 
    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
 1811 
      *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
1475 
   
 1812 
      __DSB();
1476 
    /* Read status until NAND is ready */
 - 
 
1477 
    while(HAL_NAND_Read_Status(hnand) != NAND_READY)
 - 
 
1478 
    {
 1813 
 
1479 
      /* Get tick */
 1814 
      /* Get tick */
1480 
      tickstart = HAL_GetTick();
 1815 
      tickstart = HAL_GetTick();
1481 
   
 1816 
 
- 
 
 1817 
      /* Read status until NAND is ready */
1482 
      if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
 1818 
      while (HAL_NAND_Read_Status(hnand) != NAND_READY)
1483 
      {
 1819 
      {
- 
 
 1820 
        if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
- 
 
 1821 
        {
- 
 
 1822 
          /* Update the NAND controller state */
- 
 
 1823 
          hnand->State = HAL_NAND_STATE_ERROR;
- 
 
 1824 
 
- 
 
 1825 
          /* Process unlocked */
- 
 
 1826 
          __HAL_UNLOCK(hnand);
- 
 
 1827 
 
1484 
        return HAL_TIMEOUT;
 1828 
          return HAL_TIMEOUT;
- 
 
 1829 
        }
1485 
      }
 1830 
      }
1486 
    }
 - 
 
1487 
 
 1831 
 
1488 
    /* Increment written spare areas number */
 1832 
      /* Increment written spare areas number */
1489 
    numSpareAreaWritten++;
 1833 
      numspareareawritten++;
1490 
   
 - 
 
1491 
    /* Decrement spare areas to write */
 - 
 
1492 
    NumSpareAreaTowrite--;
 - 
 
1493 
   
 - 
 
1494 
    /* Increment the NAND address */
 - 
 
1495 
    nandaddress = (uint32_t)(nandaddress + 1U);
 - 
 
1496 
  }
 - 
 
1497 
 
 1834 
 
1498 
  /* Update the NAND controller state */
 1835 
      /* Decrement spare areas to write */
1499 
  hnand->State = HAL_NAND_STATE_READY;
 1836 
      nbspare--;
1500 
 
 1837 
 
1501 
  /* Process unlocked */
 1838 
      /* Increment the NAND address */
1502 
  __HAL_UNLOCK(hnand);
 1839 
      nandaddress = (uint32_t)(nandaddress + 1U);
- 
 
 1840 
    }
1503 
 
 1841 
 
- 
 
 1842 
    /* Update the NAND controller state */
1504 
  return HAL_OK;  
 1843 
    hnand->State = HAL_NAND_STATE_READY;
1505 
}
 - 
 
1506 
 
 1844 
 
1507 
/**
 - 
 
1508 
  * @brief  NAND memory Block erase
 - 
 
1509 
  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
 - 
 
1510 
  *                the configuration information for NAND module.
 - 
 
1511 
  * @param  pAddress : pointer to NAND address structure
 - 
 
1512 
  * @retval HAL status
 - 
 
1513 
  */
 - 
 
1514 
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
 - 
 
1515 
{
 - 
 
1516 
  uint32_t deviceaddress = 0U;
 - 
 
1517 
  uint32_t tickstart = 0U;
 - 
 
1518 
 
 - 
 
1519 
  /* Process Locked */
 1845 
    /* Process unlocked */
1520 
  __HAL_LOCK(hnand);
 1846 
    __HAL_UNLOCK(hnand);
1521 
 
 - 
 
1522 
  /* Check the NAND controller state */
 - 
 
1523 
  if(hnand->State == HAL_NAND_STATE_BUSY)
 - 
 
1524 
  {
 - 
 
1525 
     return HAL_BUSY;
 - 
 
1526 
  }
 - 
 
1527 
 
 - 
 
1528 
  /* Identify the device address */
 - 
 
1529 
  if(hnand->Init.NandBank == FSMC_NAND_BANK2)
 - 
 
1530 
  {
 - 
 
1531 
    deviceaddress = NAND_DEVICE1;
 - 
 
1532 
  }
 1847 
  }
1533 
  else
 1848 
  else
1534 
  {
 1849 
  {
1535 
    deviceaddress = NAND_DEVICE2;
 1850 
    return HAL_ERROR;
1536 
  }
 1851 
  }
1537 
 
 - 
 
1538 
  /* Update the NAND controller state */
 - 
 
1539 
  hnand->State = HAL_NAND_STATE_BUSY;  
 - 
 
1540 
 
 - 
 
1541 
  /* Send Erase block command sequence */
 - 
 
1542 
  *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
 - 
 
1543 
 
 1852 
 
1544 
  *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
 - 
 
1545 
  *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
 - 
 
1546 
  *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
 - 
 
1547 
   
 - 
 
1548 
  *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
 - 
 
1549 
 
 - 
 
1550 
  /* Update the NAND controller state */
 - 
 
1551 
  hnand->State = HAL_NAND_STATE_READY;
 - 
 
1552 
 
 - 
 
1553 
  /* Get tick */
 - 
 
1554 
  tickstart = HAL_GetTick();
 - 
 
1555 
 
 - 
 
1556 
  /* Read status until NAND is ready */
 - 
 
1557 
  while(HAL_NAND_Read_Status(hnand) != NAND_READY)
 - 
 
1558 
  {
 - 
 
1559 
    if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
 - 
 
1560 
    {
 - 
 
1561 
      /* Process unlocked */
 - 
 
1562 
      __HAL_UNLOCK(hnand);    
 - 
 
1563 
 
 - 
 
1564 
      return HAL_TIMEOUT;
 - 
 
1565 
    }
 - 
 
1566 
  }    
 - 
 
1567 
 
 - 
 
1568 
  /* Process unlocked */
 - 
 
1569 
  __HAL_UNLOCK(hnand);    
 - 
 
1570 
 
 - 
 
1571 
  return HAL_OK;  
 1853 
  return HAL_OK;
1572 
}
 1854 
}
1573 
 
 1855 
 
1574 
/**
 1856 
/**
1575 
  * @brief  NAND memory read status
 1857 
  * @brief  NAND memory Block erase
1576 
  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
 1858 
  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
1577 
  *                the configuration information for NAND module.
 1859 
  *                the configuration information for NAND module.
- 
 
 1860 
  * @param  pAddress  pointer to NAND address structure
1578 
  * @retval NAND status
 1861 
  * @retval HAL status
1579 
  */
 1862 
  */
1580 
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
 1863 
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
1581 
{
 1864 
{
1582 
  uint32_t data = 0U;
 - 
 
1583 
  uint32_t deviceaddress = 0U;
 1865 
  uint32_t deviceaddress;
1584 
 
 1866 
 
1585 
  /* Identify the device address */
 1867 
  /* Check the NAND controller state */
1586 
  if(hnand->Init.NandBank == FSMC_NAND_BANK2)
 1868 
  if (hnand->State == HAL_NAND_STATE_BUSY)
1587 
  {
 1869 
  {
1588 
    deviceaddress = NAND_DEVICE1;
 1870 
    return HAL_BUSY;
1589 
  }
 1871 
  }
1590 
  else
 1872 
  else if (hnand->State == HAL_NAND_STATE_READY)
1591 
  {
 1873 
  {
1592 
    deviceaddress = NAND_DEVICE2;
 1874 
    /* Process Locked */
1593 
  }
 1875 
    __HAL_LOCK(hnand);
1594 
 
 1876 
 
1595 
  /* Send Read status operation command */
 1877 
    /* Update the NAND controller state */
1596 
  *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;
 - 
 
1597 
 
 - 
 
1598 
  /* Read status register data */
 1878 
    hnand->State = HAL_NAND_STATE_BUSY;
1599 
  data = *(__IO uint8_t *)deviceaddress;
 - 
 
1600 
 
 1879 
 
1601 
  /* Return the status */
 1880 
    /* Identify the device address */
1602 
  if((data & NAND_ERROR) == NAND_ERROR)
 1881 
    if (hnand->Init.NandBank == FSMC_NAND_BANK2)
- 
 
 1882 
    {
- 
 
 1883 
      deviceaddress = NAND_DEVICE1;
- 
 
 1884 
    }
- 
 
 1885 
    else
1603 
  {
 1886 
    {
1604 
    return NAND_ERROR;
 1887 
      deviceaddress = NAND_DEVICE2;
1605 
  }
 1888 
    }
- 
 
 1889 
 
- 
 
 1890 
    /* Send Erase block command sequence */
- 
 
 1891 
    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
- 
 
 1892 
    __DSB();
- 
 
 1893 
    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
- 
 
 1894 
    __DSB();
- 
 
 1895 
    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
- 
 
 1896 
    __DSB();
- 
 
 1897 
    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
- 
 
 1898 
    __DSB();
- 
 
 1899 
 
- 
 
 1900 
    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
- 
 
 1901 
    __DSB();
- 
 
 1902 
 
- 
 
 1903 
    /* Update the NAND controller state */
1606 
  else if((data & NAND_READY) == NAND_READY)
 1904 
    hnand->State = HAL_NAND_STATE_READY;
- 
 
 1905 
 
- 
 
 1906 
    /* Process unlocked */
- 
 
 1907 
    __HAL_UNLOCK(hnand);
- 
 
 1908 
  }
- 
 
 1909 
  else
1607 
  {
 1910 
  {
1608 
    return NAND_READY;
 1911 
    return HAL_ERROR;
1609 
  }
 1912 
  }
1610 
 
 1913 
 
1611 
  return NAND_BUSY;
 1914 
  return HAL_OK;
1612 
}
 1915 
}
1613 
 
 1916 
 
1614 
/**
 1917 
/**
1615 
  * @brief  Increment the NAND memory address
 1918 
  * @brief  Increment the NAND memory address
1616 
  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
 1919 
  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
1617 
  *                the configuration information for NAND module.
 1920 
  *                the configuration information for NAND module.
1618 
  * @param pAddress: pointer to NAND address structure
 1921 
  * @param pAddress pointer to NAND address structure
1619 
  * @retval The new status of the increment address operation. It can be:
 1922 
  * @retval The new status of the increment address operation. It can be:
1620 
  *           - NAND_VALID_ADDRESS: When the new address is valid address
 1923 
  *           - NAND_VALID_ADDRESS: When the new address is valid address
1621 
  *           - NAND_INVALID_ADDRESS: When the new address is invalid address
 1924 
  *           - NAND_INVALID_ADDRESS: When the new address is invalid address
1622 
  */
 1925 
  */
1623 
uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
 1926 
uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
1624 
{
 1927 
{
1625 
  uint32_t status = NAND_VALID_ADDRESS;
 1928 
  uint32_t status = NAND_VALID_ADDRESS;
1626 
 
 1929 
 
1627 
  /* Increment page address */
 1930 
  /* Increment page address */
1628 
  pAddress->Page++;
 1931 
  pAddress->Page++;
1629 
 
 1932 
 
1630 
  /* Check NAND address is valid */
 1933 
  /* Check NAND address is valid */
1631 
  if(pAddress->Page == hnand->Config.BlockSize)
 1934 
  if (pAddress->Page == hnand->Config.BlockSize)
1632 
  {
 1935 
  {
1633 
    pAddress->Page = 0U;
 1936 
    pAddress->Page = 0;
1634 
    pAddress->Block++;
 1937 
    pAddress->Block++;
1635 
   
 1938 
 
1636 
    if(pAddress->Block == hnand->Config.PlaneSize)
 1939 
    if (pAddress->Block == hnand->Config.PlaneSize)
1637 
    {
 1940 
    {
1638 
      pAddress->Block = 0U;
 1941 
      pAddress->Block = 0;
1639 
      pAddress->Plane++;
 1942 
      pAddress->Plane++;
1640 
 
 1943 
 
1641 
      if(pAddress->Plane == (hnand->Config.PlaneNbr))
 1944 
      if (pAddress->Plane == (hnand->Config.PlaneNbr))
1642 
      {
 1945 
      {
1643 
        status = NAND_INVALID_ADDRESS;
 1946 
        status = NAND_INVALID_ADDRESS;
1644 
      }
 1947 
      }
1645 
    }
 1948 
    }
1646 
  }
 1949 
  }
1647 
 
 1950 
 
1648 
  return (status);
 1951 
  return (status);
1649 
}
 1952 
}
- 
 
 1953 
 
- 
 
 1954 
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
- 
 
 1955 
/**
- 
 
 1956 
  * @brief  Register a User NAND Callback
- 
 
 1957 
  *         To be used instead of the weak (surcharged) predefined callback
- 
 
 1958 
  * @param hnand : NAND handle
- 
 
 1959 
  * @param CallbackId : ID of the callback to be registered
- 
 
 1960 
  *        This parameter can be one of the following values:
- 
 
 1961 
  *          @arg @ref HAL_NAND_MSP_INIT_CB_ID       NAND MspInit callback ID
- 
 
 1962 
  *          @arg @ref HAL_NAND_MSP_DEINIT_CB_ID     NAND MspDeInit callback ID
- 
 
 1963 
  *          @arg @ref HAL_NAND_IT_CB_ID             NAND IT callback ID
- 
 
 1964 
  * @param pCallback : pointer to the Callback function
- 
 
 1965 
  * @retval status
- 
 
 1966 
  */
- 
 
 1967 
HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId,
- 
 
 1968 
                                            pNAND_CallbackTypeDef pCallback)
- 
 
 1969 
{
- 
 
 1970 
  HAL_StatusTypeDef status = HAL_OK;
- 
 
 1971 
 
- 
 
 1972 
  if (pCallback == NULL)
- 
 
 1973 
  {
- 
 
 1974 
    return HAL_ERROR;
- 
 
 1975 
  }
- 
 
 1976 
 
- 
 
 1977 
  /* Process locked */
- 
 
 1978 
  __HAL_LOCK(hnand);
- 
 
 1979 
 
- 
 
 1980 
  if (hnand->State == HAL_NAND_STATE_READY)
- 
 
 1981 
  {
- 
 
 1982 
    switch (CallbackId)
- 
 
 1983 
    {
- 
 
 1984 
      case HAL_NAND_MSP_INIT_CB_ID :
- 
 
 1985 
        hnand->MspInitCallback = pCallback;
- 
 
 1986 
        break;
- 
 
 1987 
      case HAL_NAND_MSP_DEINIT_CB_ID :
- 
 
 1988 
        hnand->MspDeInitCallback = pCallback;
- 
 
 1989 
        break;
- 
 
 1990 
      case HAL_NAND_IT_CB_ID :
- 
 
 1991 
        hnand->ItCallback = pCallback;
- 
 
 1992 
        break;
- 
 
 1993 
      default :
- 
 
 1994 
        /* update return status */
- 
 
 1995 
        status =  HAL_ERROR;
- 
 
 1996 
        break;
- 
 
 1997 
    }
- 
 
 1998 
  }
- 
 
 1999 
  else if (hnand->State == HAL_NAND_STATE_RESET)
- 
 
 2000 
  {
- 
 
 2001 
    switch (CallbackId)
- 
 
 2002 
    {
- 
 
 2003 
      case HAL_NAND_MSP_INIT_CB_ID :
- 
 
 2004 
        hnand->MspInitCallback = pCallback;
- 
 
 2005 
        break;
- 
 
 2006 
      case HAL_NAND_MSP_DEINIT_CB_ID :
- 
 
 2007 
        hnand->MspDeInitCallback = pCallback;
- 
 
 2008 
        break;
- 
 
 2009 
      default :
- 
 
 2010 
        /* update return status */
- 
 
 2011 
        status =  HAL_ERROR;
- 
 
 2012 
        break;
- 
 
 2013 
    }
- 
 
 2014 
  }
- 
 
 2015 
  else
- 
 
 2016 
  {
- 
 
 2017 
    /* update return status */
- 
 
 2018 
    status =  HAL_ERROR;
- 
 
 2019 
  }
- 
 
 2020 
 
- 
 
 2021 
  /* Release Lock */
- 
 
 2022 
  __HAL_UNLOCK(hnand);
- 
 
 2023 
  return status;
- 
 
 2024 
}
- 
 
 2025 
 
- 
 
 2026 
/**
- 
 
 2027 
  * @brief  Unregister a User NAND Callback
- 
 
 2028 
  *         NAND Callback is redirected to the weak (surcharged) predefined callback
- 
 
 2029 
  * @param hnand : NAND handle
- 
 
 2030 
  * @param CallbackId : ID of the callback to be unregistered
- 
 
 2031 
  *        This parameter can be one of the following values:
- 
 
 2032 
  *          @arg @ref HAL_NAND_MSP_INIT_CB_ID       NAND MspInit callback ID
- 
 
 2033 
  *          @arg @ref HAL_NAND_MSP_DEINIT_CB_ID     NAND MspDeInit callback ID
- 
 
 2034 
  *          @arg @ref HAL_NAND_IT_CB_ID             NAND IT callback ID
- 
 
 2035 
  * @retval status
- 
 
 2036 
  */
- 
 
 2037 
HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId)
- 
 
 2038 
{
- 
 
 2039 
  HAL_StatusTypeDef status = HAL_OK;
- 
 
 2040 
 
- 
 
 2041 
  /* Process locked */
- 
 
 2042 
  __HAL_LOCK(hnand);
- 
 
 2043 
 
- 
 
 2044 
  if (hnand->State == HAL_NAND_STATE_READY)
- 
 
 2045 
  {
- 
 
 2046 
    switch (CallbackId)
- 
 
 2047 
    {
- 
 
 2048 
      case HAL_NAND_MSP_INIT_CB_ID :
- 
 
 2049 
        hnand->MspInitCallback = HAL_NAND_MspInit;
- 
 
 2050 
        break;
- 
 
 2051 
      case HAL_NAND_MSP_DEINIT_CB_ID :
- 
 
 2052 
        hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
- 
 
 2053 
        break;
- 
 
 2054 
      case HAL_NAND_IT_CB_ID :
- 
 
 2055 
        hnand->ItCallback = HAL_NAND_ITCallback;
- 
 
 2056 
        break;
- 
 
 2057 
      default :
- 
 
 2058 
        /* update return status */
- 
 
 2059 
        status =  HAL_ERROR;
- 
 
 2060 
        break;
- 
 
 2061 
    }
- 
 
 2062 
  }
- 
 
 2063 
  else if (hnand->State == HAL_NAND_STATE_RESET)
- 
 
 2064 
  {
- 
 
 2065 
    switch (CallbackId)
- 
 
 2066 
    {
- 
 
 2067 
      case HAL_NAND_MSP_INIT_CB_ID :
- 
 
 2068 
        hnand->MspInitCallback = HAL_NAND_MspInit;
- 
 
 2069 
        break;
- 
 
 2070 
      case HAL_NAND_MSP_DEINIT_CB_ID :
- 
 
 2071 
        hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
- 
 
 2072 
        break;
- 
 
 2073 
      default :
- 
 
 2074 
        /* update return status */
- 
 
 2075 
        status =  HAL_ERROR;
- 
 
 2076 
        break;
- 
 
 2077 
    }
- 
 
 2078 
  }
- 
 
 2079 
  else
- 
 
 2080 
  {
- 
 
 2081 
    /* update return status */
- 
 
 2082 
    status =  HAL_ERROR;
- 
 
 2083 
  }
- 
 
 2084 
 
- 
 
 2085 
  /* Release Lock */
- 
 
 2086 
  __HAL_UNLOCK(hnand);
- 
 
 2087 
  return status;
- 
 
 2088 
}
- 
 
 2089 
#endif
- 
 
 2090 
 
1650 
/**
 2091 
/**
1651 
  * @}
 2092 
  * @}
1652 
  */
 2093 
  */
1653 
 
 2094 
 
1654 
/** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
 2095 
/** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
1655 
 *  @brief   management functions
 2096 
  *  @brief   management functions
1656 
 *
 2097 
  *
1657 
@verbatim  
 2098 
@verbatim
1658 
  ==============================================================================
 2099 
  ==============================================================================
1659 
                         ##### NAND Control functions #####
 2100 
                         ##### NAND Control functions #####
1660 
  ==============================================================================  
 2101 
  ==============================================================================
1661 
  [..]
 2102 
  [..]
1662 
    This subsection provides a set of functions allowing to control dynamically
 2103 
    This subsection provides a set of functions allowing to control dynamically
1663 
    the NAND interface.
 2104 
    the NAND interface.
1664 
 
 2105 
 
1665 
@endverbatim
 2106 
@endverbatim
1666 
  * @{
 2107 
  * @{
1667 
  */
 2108 
  */
- 
 
 2109 
 
1668 
 
 2110 
 
1669 
   
 - 
 
1670 
/**
 2111 
/**
1671 
  * @brief  Enables dynamically NAND ECC feature.
 2112 
  * @brief  Enables dynamically NAND ECC feature.
1672 
  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
 2113 
  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
1673 
  *                the configuration information for NAND module.
 2114 
  *                the configuration information for NAND module.
1674 
  * @retval HAL status
 2115 
  * @retval HAL status
1675 
  */    
 2116 
  */
1676 
HAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
 2117 
HAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
1677 
{
 2118 
{
1678 
  /* Check the NAND controller state */
 2119 
  /* Check the NAND controller state */
1679 
  if(hnand->State == HAL_NAND_STATE_BUSY)
 2120 
  if (hnand->State == HAL_NAND_STATE_BUSY)
1680 
  {
 2121 
  {
1681 
     return HAL_BUSY;
 2122 
    return HAL_BUSY;
- 
 
 2123 
  }
- 
 
 2124 
  else if (hnand->State == HAL_NAND_STATE_READY)
- 
 
 2125 
  {
- 
 
 2126 
    /* Update the NAND state */
- 
 
 2127 
    hnand->State = HAL_NAND_STATE_BUSY;
- 
 
 2128 
 
- 
 
 2129 
    /* Enable ECC feature */
- 
 
 2130 
    (void)FSMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
- 
 
 2131 
 
- 
 
 2132 
    /* Update the NAND state */
- 
 
 2133 
    hnand->State = HAL_NAND_STATE_READY;
- 
 
 2134 
  }
- 
 
 2135 
  else
- 
 
 2136 
  {
- 
 
 2137 
    return HAL_ERROR;
1682 
  }
 2138 
  }
1683 
 
 2139 
 
1684 
  /* Update the NAND state */
 - 
 
1685 
  hnand->State = HAL_NAND_STATE_BUSY;
 - 
 
1686 
   
 - 
 
1687 
  /* Enable ECC feature */
 - 
 
1688 
  FSMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
 - 
 
1689 
 
 - 
 
1690 
  /* Update the NAND state */
 - 
 
1691 
  hnand->State = HAL_NAND_STATE_READY;
 - 
 
1692 
 
 - 
 
1693 
  return HAL_OK;
 2140 
  return HAL_OK;
1694 
}
 2141 
}
1695 
 
 2142 
 
1696 
/**
 2143 
/**
1697 
  * @brief  Disables dynamically FSMC_NAND ECC feature.
 2144 
  * @brief  Disables dynamically FSMC_NAND ECC feature.
1698 
  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
 2145 
  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
1699 
  *                the configuration information for NAND module.
 2146 
  *                the configuration information for NAND module.
1700 
  * @retval HAL status
 2147 
  * @retval HAL status
1701 
  */  
 2148 
  */
1702 
HAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
 2149 
HAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
1703 
{
 2150 
{
1704 
  /* Check the NAND controller state */
 2151 
  /* Check the NAND controller state */
1705 
  if(hnand->State == HAL_NAND_STATE_BUSY)
 2152 
  if (hnand->State == HAL_NAND_STATE_BUSY)
1706 
  {
 2153 
  {
1707 
     return HAL_BUSY;
 2154 
    return HAL_BUSY;
1708 
  }
 2155 
  }
- 
 
 2156 
  else if (hnand->State == HAL_NAND_STATE_READY)
- 
 
 2157 
  {
- 
 
 2158 
    /* Update the NAND state */
- 
 
 2159 
    hnand->State = HAL_NAND_STATE_BUSY;
1709 
 
 2160 
 
1710 
  /* Update the NAND state */
 - 
 
1711 
  hnand->State = HAL_NAND_STATE_BUSY;
 - 
 
1712 
   
 - 
 
1713 
  /* Disable ECC feature */
 2161 
    /* Disable ECC feature */
1714 
  FSMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
 2162 
    (void)FSMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
1715 
 
 2163 
 
1716 
  /* Update the NAND state */
 2164 
    /* Update the NAND state */
1717 
  hnand->State = HAL_NAND_STATE_READY;
 2165 
    hnand->State = HAL_NAND_STATE_READY;
- 
 
 2166 
  }
- 
 
 2167 
  else
- 
 
 2168 
  {
- 
 
 2169 
    return HAL_ERROR;
1718 
 
 2170 
  }
- 
 
 2171 
 
1719 
  return HAL_OK;  
 2172 
  return HAL_OK;
1720 
}
 2173 
}
1721 
 
 2174 
 
1722 
/**
 2175 
/**
1723 
  * @brief  Disables dynamically NAND ECC feature.
 2176 
  * @brief  Disables dynamically NAND ECC feature.
1724 
  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
 2177 
  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
1725 
  *                the configuration information for NAND module.
 2178 
  *                the configuration information for NAND module.
1726 
  * @param  ECCval: pointer to ECC value
 2179 
  * @param  ECCval pointer to ECC value
1727 
  * @param  Timeout: maximum timeout to wait    
 2180 
  * @param  Timeout maximum timeout to wait
1728 
  * @retval HAL status
 2181 
  * @retval HAL status
1729 
  */
 2182 
  */
1730 
HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
 2183 
HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
1731 
{
 2184 
{
1732 
  HAL_StatusTypeDef status = HAL_OK;
 2185 
  HAL_StatusTypeDef status;
1733 
 
 2186 
 
1734 
  /* Check the NAND controller state */
 2187 
  /* Check the NAND controller state */
1735 
  if(hnand->State == HAL_NAND_STATE_BUSY)
 2188 
  if (hnand->State == HAL_NAND_STATE_BUSY)
1736 
  {
 2189 
  {
1737 
     return HAL_BUSY;
 2190 
    return HAL_BUSY;
1738 
  }
 2191 
  }
- 
 
 2192 
  else if (hnand->State == HAL_NAND_STATE_READY)
1739 
 
 2193 
  {
1740 
  /* Update the NAND state */
 2194 
    /* Update the NAND state */
1741 
  hnand->State = HAL_NAND_STATE_BUSY;  
 2195 
    hnand->State = HAL_NAND_STATE_BUSY;
1742 
   
 2196 
 
1743 
  /* Get NAND ECC value */
 2197 
    /* Get NAND ECC value */
1744 
  status = FSMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
 2198 
    status = FSMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
1745 
 
 - 
 
1746 
  /* Update the NAND state */
 - 
 
1747 
  hnand->State = HAL_NAND_STATE_READY;
 - 
 
1748 
 
 2199 
 
- 
 
 2200 
    /* Update the NAND state */
- 
 
 2201 
    hnand->State = HAL_NAND_STATE_READY;
- 
 
 2202 
  }
- 
 
 2203 
  else
- 
 
 2204 
  {
- 
 
 2205 
    return HAL_ERROR;
- 
 
 2206 
  }
- 
 
 2207 
 
1749 
  return status;  
 2208 
  return status;
1750 
}
 2209 
}
1751 
 
 2210 
 
1752 
/**
 2211 
/**
1753 
  * @}
 2212 
  * @}
1754 
  */
 2213 
  */
1755 
 
 2214 
 
1756 
   
 2215 
 
1757 
/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
 2216 
/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
1758 
 *  @brief   Peripheral State functions
 2217 
  *  @brief   Peripheral State functions
1759 
 *
 2218 
  *
1760 
@verbatim  
 2219 
@verbatim
1761 
  ==============================================================================
 2220 
  ==============================================================================
1762 
                         ##### NAND State functions #####
 2221 
                         ##### NAND State functions #####
1763 
  ==============================================================================  
 2222 
  ==============================================================================
1764 
  [..]
 2223 
  [..]
1765 
    This subsection permits to get in run-time the status of the NAND controller
 2224 
    This subsection permits to get in run-time the status of the NAND controller
1766 
    and the data flow.
 2225 
    and the data flow.
1767 
 
 2226 
 
1768 
@endverbatim
 2227 
@endverbatim
1769 
  * @{
 2228 
  * @{
1770 
  */
 2229 
  */
1771 
 
 2230 
 
1772 
/**
 2231 
/**
1773 
  * @brief  return the NAND state
 2232 
  * @brief  return the NAND state
1774 
  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
 2233 
  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
1775 
  *                the configuration information for NAND module.
 2234 
  *                the configuration information for NAND module.
1776 
  * @retval HAL state
 2235 
  * @retval HAL state
1777 
  */
 2236 
  */
1778 
HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
 2237 
HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
1779 
{
 2238 
{
1780 
  return hnand->State;
 2239 
  return hnand->State;
1781 
}
 2240 
}
1782 
 
 2241 
 
1783 
/**
 2242 
/**
- 
 
 2243 
  * @brief  NAND memory read status
- 
 
 2244 
  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
- 
 
 2245 
  *                the configuration information for NAND module.
- 
 
 2246 
  * @retval NAND status
- 
 
 2247 
  */
- 
 
 2248 
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
- 
 
 2249 
{
- 
 
 2250 
  uint32_t data;
- 
 
 2251 
  uint32_t deviceaddress;
- 
 
 2252 
  UNUSED(hnand);
- 
 
 2253 
 
- 
 
 2254 
  /* Identify the device address */
- 
 
 2255 
  if (hnand->Init.NandBank == FSMC_NAND_BANK2)
- 
 
 2256 
  {
- 
 
 2257 
    deviceaddress = NAND_DEVICE1;
- 
 
 2258 
  }
- 
 
 2259 
  else
- 
 
 2260 
  {
- 
 
 2261 
    deviceaddress = NAND_DEVICE2;
- 
 
 2262 
  }
- 
 
 2263 
 
- 
 
 2264 
  /* Send Read status operation command */
- 
 
 2265 
  *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;
- 
 
 2266 
 
- 
 
 2267 
  /* Read status register data */
- 
 
 2268 
  data = *(__IO uint8_t *)deviceaddress;
- 
 
 2269 
 
- 
 
 2270 
  /* Return the status */
- 
 
 2271 
  if ((data & NAND_ERROR) == NAND_ERROR)
- 
 
 2272 
  {
- 
 
 2273 
    return NAND_ERROR;
- 
 
 2274 
  }
- 
 
 2275 
  else if ((data & NAND_READY) == NAND_READY)
- 
 
 2276 
  {
- 
 
 2277 
    return NAND_READY;
- 
 
 2278 
  }
- 
 
 2279 
  else
- 
 
 2280 
  {
- 
 
 2281 
    return NAND_BUSY;
- 
 
 2282 
  }
- 
 
 2283 
}
- 
 
 2284 
 
- 
 
 2285 
/**
1784 
  * @}
 2286 
  * @}
1785 
  */  
 2287 
  */
1786 
 
 2288 
 
1787 
/**
 2289 
/**
1788 
  * @}
 2290 
  * @}
1789 
  */
 2291 
  */
1790 
 
 2292 
 
1791 
/**
 2293 
/**
1792 
  * @}
 2294 
  * @}
1793 
  */
 2295 
  */
1794 
 
 2296 
 
1795 
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
 - 
 
1796 
#endif /* HAL_NAND_MODULE_ENABLED  */
 2297 
#endif /* HAL_NAND_MODULE_ENABLED  */
1797 
 
 2298 
 
1798 
/**
 2299 
/**
1799 
  * @}
 2300 
  * @}
1800 
  */
 2301 
  */
1801 
 
 2302 
 
- 
 
 2303 
#endif /* FSMC_BANK3 */
- 
 
 2304 
 
1802 
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 2305 
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/