WebSVN – LedShow – Diff – /trunk/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c

   ==============================================================================
   [..]
     (+) The IWDG can be started by either software or hardware (configurable
         through option byte).
-    (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
+    (+) The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays
-        if the main clock fails.
+        active even if the main clock fails.
-    (+) Once the IWDG is started, the LSI is forced ON and both can not be
+    (+) Once the IWDG is started, the LSI is forced ON and both cannot be
         disabled. The counter starts counting down from the reset value (0xFFF).
         When it reaches the end of count value (0x000) a reset signal is
         generated (IWDG reset).
     (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
-        the IWDG_RLR value is reloaded in the counter and the watchdog reset is
+        the IWDG_RLR value is reloaded into the counter and the watchdog reset
-        prevented.
+        is prevented.
     (+) The IWDG is implemented in the VDD voltage domain that is still functional
-        in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
+        in STOP and STANDBY mode (IWDG reset can wake up the CPU from STANDBY).
         IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
         reset occurs.
-    (+) Debug mode : When the microcontroller enters debug mode (core halted),
+    (+) Debug mode: When the microcontroller enters debug mode (core halted),
         the IWDG counter either continues to work normally or stops, depending
         on DBG_IWDG_STOP configuration bit in DBG module, accessible through
-        __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros
+        __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros.
     [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
-         The IWDG timeout may vary due to LSI frequency dispersion. STM32F1xx
+         The IWDG timeout may vary due to LSI clock frequency dispersion.
-         devices provide the capability to measure the LSI frequency (LSI clock
+         STM32F1xx devices provide the capability to measure the LSI clock
-         connected internally to TIM5 CH4 input capture). The measured value
+         frequency (LSI clock is internally connected to TIM5 CH4 input capture).
-         can be used to have an IWDG timeout with an acceptable accuracy.
+         The measured value can be used to have an IWDG timeout with an
+         acceptable accuracy.
+    [..] Default timeout value (necessary for IWDG_SR status register update):
+         Constant LSI_VALUE is defined based on the nominal LSI clock frequency.
+         This frequency being subject to variations as mentioned above, the
+         default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT
+         below) may become too short or too long.
+         In such cases, this default timeout value can be tuned by redefining
+         the constant LSI_VALUE at user-application level (based, for instance,
+         on the measured LSI clock frequency as explained above).
                      ##### How to use this driver #####
   ==============================================================================
   [..]
     (#) Use IWDG using HAL_IWDG_Init() function to :
       (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
-           clock is forced ON and IWDG counter starts downcounting.
+           clock is forced ON and IWDG counter starts counting down.
-      (++) Enable write access to configuration register: IWDG_PR & IWDG_RLR.
+      (++) Enable write access to configuration registers:
+          IWDG_PR and IWDG_RLR.
       (++) Configure the IWDG prescaler and counter reload value. This reload
            value will be loaded in the IWDG counter each time the watchdog is
            reloaded, then the IWDG will start counting down from this value.
-      (++) wait for status flags to be reset"
+      (++) Wait for status flags to be reset.
     (#) Then the application program must refresh the IWDG counter at regular
         intervals during normal operation to prevent an MCU reset, using
         HAL_IWDG_Refresh() function.
   @endverbatim
   ******************************************************************************
   * @attention
+  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
-  * Redistribution and use in source and binary forms, with or without modification,
+  * This software component is licensed by ST under BSD 3-Clause license,
-  * are permitted provided that the following conditions are met:
+  * the "License"; You may not use this file except in compliance with the
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution
+  * License. You may obtain a copy of the License at:
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
+  *                        opensource.org/licenses/BSD-3-Clause
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
   ******************************************************************************
   */
 /* Includes ------------------------------------------------------------------*/
 /** @addtogroup STM32F1xx_HAL_Driver
   * @{
   */
 #ifdef HAL_IWDG_MODULE_ENABLED
-/** @defgroup IWDG IWDG
+/** @addtogroup IWDG
   * @brief IWDG HAL module driver.
   * @{
   */
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
 /** @defgroup IWDG_Private_Defines IWDG Private Defines
   * @{
   */
-/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
+/* Status register needs up to 5 LSI clock periods divided by the clock
-   higher prescaler (256), and according to HSI variation, we need to wait at
+   prescaler to be updated. The number of LSI clock periods is upper-rounded to
-   least 6 cycles so 48 ms. */
+for the timeout value calculation.
+   The timeout value is also calculated using the highest prescaler (256) and
+   the LSI_VALUE constant. The value of this constant can be changed by the user
+   to take into account possible LSI clock period variations.
+   The timeout value is multiplied by 1000 to be converted in milliseconds. */
-#define HAL_IWDG_DEFAULT_TIMEOUT            48U
+#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_VALUE)
 /**
   * @}
   */
 /* Private macro -------------------------------------------------------------*/
   /* Check the parameters */
   assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
   assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
   assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
-  /* Enable IWDG. LSI is turned on automaticaly */
+  /* Enable IWDG. LSI is turned on automatically */
   __HAL_IWDG_START(hiwdg);
-  /* Enable write access to IWDG_PR and IWDG_RLR registers by writing 0x5555 in KR */
+  /* Enable write access to IWDG_PR and IWDG_RLR registers by writing
+x5555 in KR */
   IWDG_ENABLE_WRITE_ACCESS(hiwdg);
   /* Write to IWDG registers the Prescaler & Reload values to work with */
   hiwdg->Instance->PR = hiwdg->Init.Prescaler;
   hiwdg->Instance->RLR = hiwdg->Init.Reload;
   /* Check pending flag, if previous update not done, return timeout */
   tickstart = HAL_GetTick();
   /* Wait for register to be updated */
-  while (hiwdg->Instance->SR != RESET)
+  while (hiwdg->Instance->SR != 0x00u)
+  {
     if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
+    {
       return HAL_TIMEOUT;
+    }
 /**
   * @}
   */
 /** @addtogroup IWDG_Exported_Functions_Group2
   *  @brief   IO operation functions
+  *
 @verbatim
  ===============================================================================
 @endverbatim
   * @{
   */
 /**
   * @brief  Refresh the IWDG.
   * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
   *                the configuration information for the specified IWDG module.
   * @retval HAL status

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(root)/trunk/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c – Rev 2 → 9